US7348610B2 - Multiple layer and crystal plane orientation semiconductor substrate - Google Patents
Multiple layer and crystal plane orientation semiconductor substrate Download PDFInfo
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- US7348610B2 US7348610B2 US10/906,557 US90655705A US7348610B2 US 7348610 B2 US7348610 B2 US 7348610B2 US 90655705 A US90655705 A US 90655705A US 7348610 B2 US7348610 B2 US 7348610B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 239000013078 crystal Substances 0.000 title claims abstract description 94
- 239000000758 substrate Substances 0.000 title claims abstract description 63
- 229910052710 silicon Inorganic materials 0.000 claims description 33
- 239000010703 silicon Substances 0.000 claims description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910005540 GaP Inorganic materials 0.000 claims description 3
- 229910005542 GaSb Inorganic materials 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- 239000000969 carrier Substances 0.000 claims description 3
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 claims 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 239000012212 insulator Substances 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 29
- 235000012431 wafers Nutrition 0.000 description 22
- 229910021419 crystalline silicon Inorganic materials 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 238000003776 cleavage reaction Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000007017 scission Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000009466 transformation Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Definitions
- the present invention relates to the field of semiconductor substrates; more specifically, it relates a method of fabricating a semiconductor substrate having multiple crystalline layers with different crystal plane orientations.
- a semiconductor substrate of the present invention comprises an insulating layer between an upper semiconductor layer and a lower semiconductor layer.
- a first crystal direction in the upper layer is rotationally displaced from a second crystal direction in the lower semiconductor layer.
- the edges of integrated circuit chips formed in the upper semiconductor layer are aligned to the second crystal direction to enhance dicing while some or all of devices formed in the integrated circuit chips have structures aligned to the first crystal direction.
- a first aspect of the present invention is a substrate, comprising: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.
- a second aspect of the present invention is a method of fabricating a substrate, comprising: providing a first crystalline semiconductor substrate, providing a second crystalline semiconductor substrate; aligning a first crystal direction of the first crystalline semiconductor substrate to a second crystal direction of the second crystalline semiconductor substrate, the first crystal direction different from the second crystal direction; and forming an insulating layer between a bottom surface of the first crystalline semiconductor substrate and a top surface of the second crystalline semiconductor substrate, the insulating layer bonding the first crystalline semiconductor substrate to the second crystalline semiconductor substrate.
- a third aspect of the present invention is an integrated circuit chip, comprising: a first crystalline semiconductor layer and a second crystalline semiconductor layer; an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction; a field effect transistor comprising a source region, a drain region and a channel region separating the source and drain regions, the source, drain and a channel regions formed in the first crystalline semiconductor layer, a lengthwise direction of the channel extending between the source and drain regions aligned with both the first and the second directions; and at least one edge of the integrated circuit chip aligned with the second direction.
- a fourth aspect of the present invention is a method of fabricating an integrated circuit chip, comprising: providing a semiconductor-on-insulator substrate comprising a first crystalline semiconductor layer and a second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor substrate aligned relative to a second crystal direction of the second crystalline semiconductor substrate, the first crystal direction different from the second crystal direction, an insulating layer formed between a bottom surface of the first crystalline semiconductor substrate and a top surface of the second crystalline semiconductor substrate, the insulating layer bonding the first crystalline semiconductor substrate to the second crystalline semiconductor; forming a field effect transistor comprising a source region, a drain region and a channel region separating the source and drain regions, the source, drain and a channel regions formed in the first crystalline semiconductor layer, a lengthwise direction of the channel extending between the source and drain regions aligned with both the first and the second directions; and dicing the semiconductor-on-insulator substrate along the second direction to form at least one edge of the integrated circuit chip.
- FIG. 1 is a top view of an exemplary ⁇ 100 ⁇ surfaced semiconductor substrate
- FIG. 2 illustrates an exemplary semiconductor substrate according to the present invention
- FIGS. 3A through 3E are side views of the fabrication of an exemplary semiconductor substrate according to the present invention.
- FIG. 4 is a top view illustrating alignment of integrated circuit chips on the semiconductor substrate of FIG. 2 ;
- FIG. 5 is a top view illustrating alignment of a first type of device to an integrated circuit chip fabricated on a semiconductor substrate according to the present invention.
- wafer should be considered as and exemplary version of the more general term substrate.
- crystalline solids the atoms which make up the solid are spatially arranged in a periodic fashion called a lattice.
- a crystal lattice contains a volume, which is representative of the entire lattice and is regularly repeated throughout the crystal.
- the directions in a lattice are expressed as a set of three integers with the same relationship as the components of a vector in that direction.
- a body diagonal exists along the [ 111 ] direction with the [ ] brackets denoting a specific direction.
- Many directions in a crystal lattice are equivalent by a symmetry transformation, depending upon the arbitrary choice of orientation axes.
- crystal directions in the cubic lattice [100], [010] and [001] are all crystallographically equivalent.
- a direction and all its equivalent directions are denoted by ⁇ > brackets.
- the designation of the ⁇ 100 22 direction includes the equivalent [100], [010] and [001] positive directions as well as the equivalent negative directions [ ⁇ 100], [0-10] and [00-1].
- Planes in a crystal may also be identified with a set of three integers. They are used to define a set of parallel planes and each set of integers enclosed in ( ) parentheses identifies a specific plane. For example the proper designation for a crystal plane perpendicular to the [100] direction is (100). Thus, if either a direction or a plane of a cubic lattice is known, its perpendicular counterpart may be quickly determined without calculation. Many planes in a crystal lattice are equivalent by a symmetry transformation, depending upon the arbitrary choice of orientation axes. For example, the (100), (010) and (001) planes are all crystallographically equivalent. A plane and all its equivalent planes are denoted by ⁇ ⁇ parentheses. Thus, the designation of the ⁇ 100 ⁇ plane includes the equivalent (100), (010) and (001) positive planes as well as the equivalent planes ( ⁇ 100), (0-10) and (00-1).
- FIG. 1 is a top view of an exemplary ⁇ 100 ⁇ surfaced semiconductor substrate.
- a [100] direction of a ⁇ 100 ⁇ silicon substrate 100 is seen to be rotated 45° from a [110] crystal direction.
- a [010] crystal direction is seen to be rotated 90° from the [100] crystal direction and 45° from the [110] crystal direction.
- a [ ⁇ 110] crystal direction is seen to be rotated 90° from the [110] crystal direction.
- a line 105 passing through a notch 110 in the edge of substrate 100 and a center 115 of the substrate marks the [110] direction.
- Inversion carrier flow is affected by the crystal orientation of the channel of a field effect transistor (FET).
- FET field effect transistor
- the mobility of the electrons (inversion carriers) in the channels of NFETs is relatively unaffected by choice of channel direction between the ⁇ 100> crystal directions and the ⁇ 110> crystal directions.
- the mobility of holes (inversion carriers) in the channels of PFETs is highest in ⁇ 100> crystal directions and significantly lower in ⁇ 110> directions.
- a dicing saw is used to scribe a line into the silicon wafer between integrated chips and then the wafer cleaved along these scribed lines. In another method, the dicing saw is used to cut completely through the silicon wafer.
- crystalline silicon wafers have a preferred cleavage planes and are most easily and cleanly broken or cut along ⁇ 110 ⁇ crystal planes.
- FIG. 2 illustrates an exemplary semiconductor substrate 120 according to the present invention.
- a ⁇ 100 ⁇ crystalline silicon layer 100 W 1 is bonded to a ⁇ 100 ⁇ crystalline silicon layer 100 W 2 by an insulating layer 125 .
- a central vertical axis 130 is perpendicular to top surfaces 135 W 1 and 135 W 2 of silicon layers 100 W 1 and 100 W 2 respectively.
- Top surface 135 W 1 is also the top surface of semiconductor substrate 120 .
- Semiconductor devices, such as transistors, are intended to be formed in silicon layer 100 W 1 and/or on top surface 135 W 1 .
- Vertical axis 130 passes through centers 115 W 1 and 115 W 2 of respective silicon layers 100 W 1 and 100 W 2 .
- the [100] and [110] crystal directions of silicon layer 100 W 1 are designated as [100]W 1 and [110]W 1 respectively.
- the [010] and [110] crystal directions of silicon layer 100 W 2 are designated as [100]W 2 and [110]W 2 respectively.
- Crystal direction [100]W 1 is aligned to crystal direction [110]W 2 and crystal direction [110]W 1 is aligned to crystal direction [010]W 2
- Another way of stating the relation ship between the crystal directions of silicon layers 100 W 1 and 100 W 2 is that (a first) crystal direction [100]W 1 is rotated 45° about axis 130 relative to (a second) crystal direction [100]W2.
- crystal plane alignment illustrated in FIG. 2 and described supra should be considered exemplary and many variations are possible.
- the same crystal directions (for example, the [100] and [100] crystal directions) in the two different silicon layers may be rotationally offset from one another by a pre-selected angle of rotation about a vertical axis running through the centers of both wafers.
- different orientation silicon layers may be used.
- silicon layer 100 W 1 may be a ⁇ 111 ⁇ crystalline silicon layer and silicon layer 100 W 2 may be a ⁇ 100 ⁇ crystalline silicon layer.
- one or both of silicon layers 100 W 1 and 100 W 2 may be replaced with a layer comprising a group III-V semiconductor material such as GaAs, GaP, GaSb, InP, In As, InSb
- First silicon layer 100 W 1 has a thickness D 1
- second silicon layer 100 W 2 has a thickness D 2
- insulating layer 125 has a thickness D 3 .
- D 1 is between about 10 nm and about 100 nm
- D 2 is greater than about 700 microns
- D 3 is between about 5 nm and about 1000 nm, preferably between 50 nm and 250 nm.
- insulating layer 125 comprises silicon oxide.
- FIGS. 3A through 3E are side views of the fabrication of an exemplary semiconductor substrate according to the present invention.
- a first silicon wafer 150 has a top surface 155 , a bottom surface 160 and an edge 165 .
- a notch 170 is formed in wafer 150 .
- a silicon dioxide layer 175 having a thickness between about 0.5 nm to about 200 nm is formed on top surface 155 of wafer 150 .
- a hydrogen ion implantation performed to form a hydrogen rich layer 180 in wafer 150 .
- a second silicon wafer 185 has a top surface 190 , a bottom surface 195 and an edge 200 .
- a notch 205 is formed in wafer 185 .
- a silicon dioxide layer 210 having a thickness between about 0.5 nm to about 200 nm is formed on top surface 190 of wafer 185 .
- Oxide layers 175 and 210 are cleaned, edges 165 and 200 are aligned oxide layers 175 and 200 are Drought into contact.
- Notches 170 and 205 serve to locate particular crystal planes in respective wafers 150 and 185 .
- wafers 150 and 185 are heated to a temperature of about 400° C. or greater Hydrogen rich layer 180 (see FIG. 3B ) is brittle and an upper layer of wafer 150 is cleaved off leaving a silicon layer 215 , having a rough top surface 220 .
- a chemical mechanical polishing (CMP) process is performed to form a thin silicon layer 225 having a planer top surface 230 .
- silicon layer 225 has a thickness between about 5 nm to about 100 nm
- wafers 150 and 185 are heated, for example to about 1000° C. in hydrogen in order to merge oxide layers 175 and 210 (see FIG. 3D ) into a silicon dioxide layer 235 which bonds the wafers together.
- silicon dioxide layer 235 has thickness between about 5 nm to about 500 nm.
- the structure illustrated in FIG. 3E is a silicon on insulator (SOI) substrate.
- FIG. 4 is a top view illustrating alignment of integrated circuit chips on semiconductor substrate 120 of FIG. 2 .
- substrate 120 has notches 240 and 245 formed in an edge 250 of the substrate.
- a line passing through central axis 130 and notch 240 locates the [110]W 1 and [010] W 2 crystal directions which are co-aligned.
- a line passing through central axis 130 and notch 245 locates the [100]W 1 and [110]W 2 crystal directions which are co-aligned.
- a multiplicity of integrated circuit chips 255 are formed on top surface 135 W 1 .
- a first set of parallel edges 260 A and 260 B of integrated circuit chips 255 are parallel to crystal direction [ ⁇ 110]W 2
- a second set of parallel edges 265 A and 265 B of integrated circuit chips 255 are parallel to crystal direction [110]W 2 (and crystal direction [100]W 1 ).
- Spaces 270 between integrated circuit chips 255 form a dicing kerf where a dicing saw will cut substrate 120 to separate individual integrated circuit chips.
- the dicing kerf is aligned with lower silicon layer 100 W 2 (see FIG. 2 ) which is the thicker layer of substrate 120 (see description supra) and the preferred cleavage planes of the lower silicon layer, while critical structures of devices formed in integrated circuit chips 255 may be printed aligned to crystal direction [100]W 1 and still be aligned with edges 260 A and 260 B as illustrated in FIG. 5 described infra.
- FIG. 5 is a top view illustrating alignment of a first type of device to an integrated circuit chip fabricated on a semiconductor substrate according to the present invention.
- a complementary metal oxide silicon (CMOS) PFET 300 comprises a silicon channel region 305 and source/drain regions 310 formed in silicon layer 100 W 1 (see FIG. 2 ) and a gate 315 formed over channel region 305 .
- a gate dielectric (not shown) is formed under gate 315 .
- Channel region 305 has a length “L” measured between source/drain regions 310 and a width “W” perpendicular to the channel length.
- Edges 265 A and 265 B are aligned with the [ ⁇ 110]W 2 crystal direction and edges 270 A and 270 B are aligned with the [110]W 2 crystal direction providing improved dicing characteristics.
- the length “L” of channel region 305 is aligned with the [100]W 1 crystal direction, which provides maximum inversion carrier mobility for a PFET as well as with edges 260 A and 260 B. Improved printability of images during fabrication of PFET 300 and maximum device density of devices result as well.
Abstract
Description
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Priority Applications (3)
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US10/906,557 US7348610B2 (en) | 2005-02-24 | 2005-02-24 | Multiple layer and crystal plane orientation semiconductor substrate |
US11/969,279 US20080102566A1 (en) | 2005-02-24 | 2008-01-04 | Multiple layer and crystal plane orientation semiconductor substrate |
US11/969,320 US7521735B2 (en) | 2005-02-24 | 2008-01-04 | Multiple layer and crystal plane orientation semiconductor substrate |
Applications Claiming Priority (1)
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US10/906,557 US7348610B2 (en) | 2005-02-24 | 2005-02-24 | Multiple layer and crystal plane orientation semiconductor substrate |
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US11/969,279 Division US20080102566A1 (en) | 2005-02-24 | 2008-01-04 | Multiple layer and crystal plane orientation semiconductor substrate |
US11/969,320 Division US7521735B2 (en) | 2005-02-24 | 2008-01-04 | Multiple layer and crystal plane orientation semiconductor substrate |
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US20060186416A1 US20060186416A1 (en) | 2006-08-24 |
US7348610B2 true US7348610B2 (en) | 2008-03-25 |
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US11/969,279 Abandoned US20080102566A1 (en) | 2005-02-24 | 2008-01-04 | Multiple layer and crystal plane orientation semiconductor substrate |
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US7482209B2 (en) * | 2006-11-13 | 2009-01-27 | International Business Machines Corporation | Hybrid orientation substrate and method for fabrication of thereof |
US20120132922A1 (en) * | 2009-07-08 | 2012-05-31 | Soitec | Composite substrate with crystalline seed layer and carrier layer with a coincident cleavage plane |
CN103681992A (en) * | 2014-01-07 | 2014-03-26 | 苏州晶湛半导体有限公司 | Semiconductor substrate, semiconductor device and semiconductor substrate manufacturing method |
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Also Published As
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US20080099844A1 (en) | 2008-05-01 |
US20060186416A1 (en) | 2006-08-24 |
US20080102566A1 (en) | 2008-05-01 |
US7521735B2 (en) | 2009-04-21 |
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