|Typ av kungörelse||Beviljande|
|Publiceringsdatum||14 dec 2004|
|Registreringsdatum||17 jun 2003|
|Prioritetsdatum||17 jun 2003|
|Publikationsnummer||10462667, 462667, US 6830998 B1, US 6830998B1, US-B1-6830998, US6830998 B1, US6830998B1|
|Uppfinnare||James Pan, Paul Besser, Christy Mei-Chu Woo, Minh Van Ngo, Jinsong Yin|
|Ursprunglig innehavare||Advanced Micro Devices, Inc.|
|Exportera citat||BiBTeX, EndNote, RefMan|
|Citat från patent (5), Hänvisningar finns i följande patent (60), Klassificeringar (19), Juridiska händelser (8)|
|Externa länkar: USPTO, Överlåtelse av äganderätt till patent som har registrerats av USPTO, Espacenet|
The present invention relates to semiconductor devices comprising transistors with metal gate electrodes and improved gate dielectric layers. The present invention is particularly applicable in fabricaturing high speed semiconductor devices having submicron design features.
The integration of hundreds of millions of circuit elements, such as transistors, on a single integrated circuit necessitates further dramatic scaling down or micro-miniaturization of the physical dimensions of circuit elements, including interconnection structures. Micro-miniaturization has engendered a dramatic increase in transistor engineering complexity, such as the inclusion of graded well-doping, epitaxial wafers, halo implants, tip implants, lightly doped drain structures, multiple implants for source/drain regions, silicidation of gates and source/drains, and multiple sidewall spacers, for example.
The drive for high performance requires high speed operation of microelectronic components requiring high drive currents in addition to low leakage, i.e., low off-state current, to reduce power consumption. Typically, the structural and doping parameters tending to provide a desired increase in drive current adversely impact leakage current.
Recently, metal gate electrodes have evolved for improving the drive current by reducing polysilicon depletion, and reducing processing temperatures subsequent to metal gate formation. In order to implement replacement metal gate process flow, a dummy gate, such as polysilicon, is removed by dry/wet etching, followed by metal deposition.
Polysilicon dry etching is conventionally performed using a plasma. Metal deposition is conventionally performed using physical vapor deposition or sputtering, which also requires a plasma. However, the use of a plasma causes radiation damage to the gate oxide thereby adversely impacting transistor performance.
Accordingly, a need exists for methodology enabling the fabrication of micro-miniaturized semiconductor devices comprising transistors with metal gate electrodes having improved a gate dielectric quality.
An advantage of the present invention is a semiconductor device having a transistor with a metal gate electrode and a gate oxide with improved quality.
Another advantage of the present invention is a method of manufacturing a semiconductor device comprising a transistor with a metal gate electrode and a gate oxide of improved quality.
Additional advantages and other features of the present invention will be set forth in the description which follows and, in part, will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a removable gate over a substrate with a gate dielectric layer therebetween; forming a dielectric layer over the substrate and exposing an upper surface of the removable gate; removing the removable gate leaving an opening in the dielectric layer exposing an upper surface of the gate dielectric layer, wherein the gate dielectric layer is damaged when removing the removable gate; depositing a conductive layer filling the opening and forming an overburden on the dielectric layer; and conducting chemical mechanical polishing (CMP); the method further comprising treating the gate dielectric layer to remedy the damage to the gate dielectric layer.
Embodiments of the present invention include forming a removable polysilicon gate over a gate oxide layer and treating the gate oxide layer at an elevated temperature. Embodiments of the present invention include annealing the gate oxide layer by vacuum annealing after chemical mechanical polishing. Embodiments of the present invention also include annealing after removing the removable gate and wet cleaning before depositing the conductive layer. Annealing before depositing the conductive layer may be conducted in oxygen and argon, ozone, or a forming gas, or by heat soaking in an atmosphere containing silicon, such as heat soaking in silane or disilane. Embodiments of the present invention also comprise forming a composite metal gate electrode comprising a tantalum silicon nitride liner and tantalum nitride filling the opening.
Another advantage of the present invention is a semiconductor device comprising: a substrate; a gate oxide layer on the substrate; a layer of silicon on the gate oxide layer; and a metal gate electrode on the layer of silicon.
A further aspect of the present invention is a semiconductor device having complimentary metal oxide (CMOS) devices including an NMOS transistor with a metal gate electrode and a PMOS transistor with a doped polysilicon gate electrode.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modification in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
FIGS. 1 through 6 schematically illustrate sequential phases of a method in accordance with an embodiment of the present invention, wherein similar features are denoted by similar reference characters.
FIGS. 7a and 7 b are plots of data showing a reduction in gate leakage current and defect density achieved by an embodiment of the present invention.
FIG. 8 is a plot of data showing a reduction in leakage current achieved by another embodiment of the present invention.
The present invention address and solves the problem of gate dielectric degradation attendant upon conventional replacement metal gate processing to replace high resistivity polysilicon gate electrodes. During such conventional replacement metal gate processing, the underlying gate dielectric layer, e.g., gate oxide layer, suffers degradation due to radiation damage during plasma processing, as by dry etching to remove the dummy polysilicon gate and/or during subsequent metal deposition in a plasma. The present invention addresses and solves such gate dielectric degradation during replacement metal gate fabrication by treating the damaged gate dielectric layer to not only cure the damage caused by plasma processing but also to protect the cured gate dielectric layer against future damage during plasma processing.
In accordance with embodiments of the present invention, low temperature vacuum annealing is conducted subsequent to CMP, which is conducted subsequent to metal deposition. Such low temperature annealing may be conducted at a temperature of 300° C. to 600° C., e.g., 600° C., at a pressure of 0.001 mTorr to 1 mTorr, for about 1 to about 10 minutes.
In accordance with another embodiment of the present invention, annealing is conducted after wet cleaning, which is conducted subsequent to removal of the dummy polysilicon by dry etching, and prior to metal deposition. In accordance with this embodiment of the present invention, annealing may be implemented at a relatively low temperature, such as 400° C. to 800° C., in an atmosphere of oxygen and argon, an atmosphere of ozone, an atmosphere comprising a forming gas, typically containing 4 vol % hydrogen and 96 vol % nitrogen, or by heat soaking in an atmosphere of silicon, as by heat soaking in silane or disilane. Embodiments include annealing in oxygen at flow rate of 50 to 100 sccm and argon at a flow rate of 50 to 100 sccm. Such annealing can also be conducted in a silicon-containing environment. Such annealing may be conducted for 0.1 to 2 minutes.
In accordance with embodiments of the present invention, the intermediate structure after removing the polysilicon dummy gate and wet cleaning is heat soaked in silane or disilane. Advantageously, as a result of such heat treatment, a thin layer of silicon is formed on the gate dielectric layer, as any thickness of 5 Å to 20 Å. The presence of silicon at the metal/gate oxide interface reduces the interface trapped density, as to about 6.4×1010 cm−2eV−1, which is comparable to the most advanced polysilicon MOSFET.
Embodiments of the present invention including forming the metal gate as a composite of plural metal layers. For example, the metal gate can be formed by depositing an initial layer of tantalum silicon nitride, as at a thickness of 20 Å to 100 Å, lining the opening, and then depositing a layer of tantalum nitride forming an overburden which is subsequently removed by CMP.
In another embodiment of the present invention, complimentary metal oxide semiconductor (CMOS) transistors are formed wherein only the N-channel MOSFET contains a replacement metal gate electrode, while the P-channel MOSFET contains a conventional dope-polysilicon gate electrode. This objective can be achieved by covering the P-channel MOSFET with a photoresist mask and then implementing the metal gate process flow on the N-channel MOSFET. In accordance with an embodiment of the present invention, replacement metal gate electrode processing is implemented by forming the metal gate electrode after all high temperature cycles are complete, such as source/drain activation annealing.
An embodiment of the present invention is schematically illustrated in FIGS. 1 through 6. Adverting to FIG. 1, a temporary replaceable or dummy gate 11, such as polysilicon, is formed over substrate 10 with a gate dielectric layer 12 therebetween, such as silicon oxide. Embodiments of the present invention also include depositing a high dielectric constant material for the gate dielectric layer 12, such as ZrO2, HfO2, InO2, LaO2 and TaO2. Shallow source/drain extensions of 14 are formed, dielectric sidewall spacers 15, such as silicon oxide, silicon nitride or silicon oxynitride, are then formed on the removable gate 11. Ion implantation is then conducted to form deep source/drain regions 13, followed by silicidation to form metal silicide layer 16 on the exposed surfaces of the source/drain regions 13, such as nickel silicide. The manipulative steps illustrated in FIG. 1 are implemented in a conventional manner.
Adverting to FIG. 2, a layer of dielectric material, such as silicon oxide, e.g., silicon oxide formed from tetraethyl orthosilicate (TEOS), is deposited followed by CMP forming layer 20. It should be understood that shallow source/drain extensions 13 and source/drain regions 14 are activated by high temperature thermal annealing, such as at a temperature of about 900° C. and above, at the stage illustrated in FIG. 1 or alternatively, FIG. 2 or alternatively, even at the stage illustrated in FIG. 3 prior to depositing the replacement metal gate electrode.
As illustrated in FIG. 3, replacement or dummy gate 11 is removed, as by dry etching. During such dry etching to remove dummy gate 11, the underlying gate oxide layer is damaged by radiation due to the plasma employed or generated during dry etching. Radiation damage to the underlying gate oxide layer can also occur during subsequent metal deposition in a plasma. In accordance with embodiments of the present invention, the gate oxide layer may be treated at this point in the process by annealing, as at a temperature of 400° C. to 800° C., in various atmospheres, such as an atmosphere of oxygen and argon, a forming gas or ozone, or by heat soaking in silane or disilane. Heat soaking in silane or disilane results in the formation of a thin layer of silicon on the gate oxide layer, as at a thickness of 5 Å to 10 Å, thereby advantageously reducing interface trap density.
Subsequently, a layer of tantalum silicon nitride 40 is deposited, as illustrated in FIG. 4, as at a thickness of 20 to 100 Å, as by physical vapor deposition. A layer of conductive material 50, such as tantalum nitride is then deposited, as shown in FIG. 5. The present invention is not limited to a conductive material of 50 of tantalum nitride. Other suitable materials can be employed, such as copper (Cu) or a Cu alloy containing minor amounts of tantalum, indium, tin, zinc, manganese, titanium, magnesium, chromium, germanium, strontium, platinum, aluminum or zirconium. Other suitable metals include nickel, ruthenium, cobalt, molybdenum and alloys thereof. The overburden is then removed during planarization by CMP, resulting in the structure illustrated in FIG. 6 containing replacement metal gate electrode in the form of a composite comprising tantalum silicon nitride 400 and tantalum nitride 60.
In another embodiment of the present invention, a low temperature vacuum annealing is conducted subsequent to CMP on the structure shown in FIG. 6. Such low temperature vacuum annealing may be implemented in addition to or in lieu of the low temperature annealing prior to metal deposition.
Comparison testing was conducted with and without such annealing at a temperature of 600° C. and the results reported in FIGS. 7A and 7B. It should be apparent that a low temperature vacuum annealing conducted after CMP in accordance with an embodiment of the present invention reduces the gate leakage current and defect density at the gate oxide/silicon interface. The data were measured from a ALCDD TaN/PVD and Electrode-Plated Cu stacked replacement metal gate and NMOSFET. The on current (Ion), off current (loff), subthreshhold slope (SUB_Vt) and gate leakage current (IG) are all significantly improved.
Further experimental testing was conducted to demonstrate the reduction in leakage current attendant upon gate oxide treatment by heat soaking in silane or disilane. The Ids vs. Vgs plot shown in FIG. 8 demonstrates an advantageous reduction in leakage current. The data generated in FIG. 8 were measured from a TaSiN/Ta 8 replacement metal gate NMOSFET. The presence of silicon at the metal gate/gate oxide interface reduces the Dit (interface trapped density) to 6.4×1010 cm−2eV−1, which is comparable to the best polysilicon MOSFET currently available.
The present invention provides methodology enabling the fabrication of semiconductor devices having transistors with replacement metal gate electrodes and gate dielectric layers with improved integrity. The present invention enables cures radiation damaged gate oxide layers and prevents subsequent damage during plasma processing.
The present invention enjoys industrial applicability in the fabrication of various types of semiconductor devices. The present invention is particularly applicable in fabricating semiconductor devices having submicron features and exhibiting a high drive current and minimized leakage current.
In the previous description, numerous specific details are set forth, such as specific materials, structures, chemicals, processes, etc., to provide a better understanding of the present invention. However, the present invention can be practiced without resorting to the details specifically set forth. In other instances, well known processing and materials have not been described in detail in order not to unnecessarily obscure the present invention.
Only the preferred embodiment of the present invention and but a few examples of its versatility are shown and described in the present application. It is to be understood that the present invention is capable of use in various other combinations and environments, and is capable of changes or modifications within the scope of the inventive concept as expressed herein.
|US6074921 *||30 jun 1997||13 jun 2000||Vlsi Technology, Inc.||Self-aligned processing of semiconductor device features|
|US6358866 *||1 jul 1999||19 mar 2002||Imec Vzw||Method for post-oxidation heating of a structure comprising SiO2|
|US6468926 *||29 jun 1999||22 okt 2002||Fujitsu Limited||Manufacture method and system for semiconductor device with thin gate insulating film of oxynitride|
|US6610614 *||20 jun 2001||26 aug 2003||Texas Instruments Incorporated||Method for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates|
|US6660588 *||16 sep 2002||9 dec 2003||Advanced Micro Devices, Inc.||High density floating gate flash memory and fabrication processes therefor|
|US7425490 *||24 jun 2004||16 sep 2008||Intel Corporation||Reducing reactions between polysilicon gate electrodes and high dielectric constant gate dielectrics|
|US7736956||26 mar 2008||15 jun 2010||Intel Corporation||Lateral undercut of metal gate in SOI device|
|US7781771||4 feb 2008||24 aug 2010||Intel Corporation||Bulk non-planar transistor having strained enhanced mobility and methods of fabrication|
|US7820513||28 okt 2008||26 okt 2010||Intel Corporation||Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication|
|US7858481 *||15 jun 2005||28 dec 2010||Intel Corporation||Method for fabricating transistor with thinned channel|
|US7879675||2 maj 2008||1 feb 2011||Intel Corporation||Field effect transistor with metal source/drain regions|
|US7898041||14 sep 2007||1 mar 2011||Intel Corporation||Block contact architectures for nanoscale channel transistors|
|US7902014||3 jan 2007||8 mar 2011||Intel Corporation||CMOS devices with a single work function gate electrode and method of fabrication|
|US7960794||20 dec 2007||14 jun 2011||Intel Corporation||Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow|
|US7989280||18 dec 2008||2 aug 2011||Intel Corporation||Dielectric interface for group III-V semiconductor device|
|US8067818||24 nov 2010||29 nov 2011||Intel Corporation||Nonplanar device with thinned lower body portion and method of fabrication|
|US8071983||8 maj 2009||6 dec 2011||Intel Corporation||Semiconductor device structures and methods of forming semiconductor structures|
|US8084818||12 jan 2006||27 dec 2011||Intel Corporation||High mobility tri-gate devices and methods of fabrication|
|US8183646||4 feb 2011||22 maj 2012||Intel Corporation||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US8268709||6 aug 2010||18 sep 2012||Intel Corporation||Independently accessed double-gate and tri-gate transistors in same process flow|
|US8273626||29 sep 2010||25 sep 2012||Intel Corporationn||Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication|
|US8294180||1 mar 2011||23 okt 2012||Intel Corporation||CMOS devices with a single work function gate electrode and method of fabrication|
|US8324090 *||18 dec 2008||4 dec 2012||Taiwan Semiconductor Manufacturing Company, Ltd.||Method to improve dielectric quality in high-k metal gate technology|
|US8362566||23 jun 2008||29 jan 2013||Intel Corporation||Stress in trigate devices using complimentary gate fill materials|
|US8368135||23 apr 2012||5 feb 2013||Intel Corporation||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US8399922||14 sep 2012||19 mar 2013||Intel Corporation||Independently accessed double-gate and tri-gate transistors|
|US8405164||26 apr 2010||26 mar 2013||Intel Corporation||Tri-gate transistor device with stress incorporation layer and method of fabrication|
|US8455268 *||31 aug 2007||4 jun 2013||Spansion Llc||Gate replacement with top oxide regrowth for the top oxide improvement|
|US8502351||23 sep 2011||6 aug 2013||Intel Corporation||Nonplanar device with thinned lower body portion and method of fabrication|
|US8581258||20 okt 2011||12 nov 2013||Intel Corporation||Semiconductor device structures and methods of forming semiconductor structures|
|US8609522||11 mar 2011||17 dec 2013||Commissariat ā l'énergie atomique et aux čnergies alternatives||Process for producing a conducting electrode|
|US8617945||3 feb 2012||31 dec 2013||Intel Corporation||Stacking fault and twin blocking barrier for integrating III-V on Si|
|US8664694||28 jan 2013||4 mar 2014||Intel Corporation||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US8741733||25 jan 2013||3 jun 2014||Intel Corporation||Stress in trigate devices using complimentary gate fill materials|
|US8749026||3 jun 2013||10 jun 2014||Intel Corporation||Nonplanar device with thinned lower body portion and method of fabrication|
|US8816394||20 dec 2013||26 aug 2014||Intel Corporation||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US8933458||8 okt 2013||13 jan 2015||Intel Corporation||Semiconductor device structures and methods of forming semiconductor structures|
|US8940589 *||28 maj 2010||27 jan 2015||Taiwan Semiconductor Manufacturing Company, Ltd.||Well implant through dummy gate oxide in gate-last process|
|US9048314||21 aug 2014||2 jun 2015||Intel Corporation||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US9190518||8 maj 2014||17 nov 2015||Intel Corporation||Nonplanar device with thinned lower body portion and method of fabrication|
|US9224754||8 maj 2014||29 dec 2015||Intel Corporation||Stress in trigate devices using complimentary gate fill materials|
|US9337307||18 nov 2010||10 maj 2016||Intel Corporation||Method for fabricating transistor with thinned channel|
|US9362399||20 jan 2015||7 jun 2016||Taiwn Semiconductor Manufacturing Company, Ltd.||Well implant through dummy gate oxide in gate-last process|
|US9368583||1 maj 2015||14 jun 2016||Intel Corporation||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US9385180||18 dec 2014||5 jul 2016||Intel Corporation||Semiconductor device structures and methods of forming semiconductor structures|
|US9450092||11 nov 2015||20 sep 2016||Intel Corporation||Stress in trigate devices using complimentary gate fill materials|
|US9614083||10 jun 2016||4 apr 2017||Intel Corporation||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US9620384 *||3 jul 2014||11 apr 2017||Globalfoundries Inc.||Control of O-ingress into gate stack dielectric layer using oxygen permeable layer|
|US9741577||2 dec 2015||22 aug 2017||International Business Machines Corporation||Metal reflow for middle of line contacts|
|US9741809||16 sep 2015||22 aug 2017||Intel Corporation||Nonplanar device with thinned lower body portion and method of fabrication|
|US9748391||24 feb 2017||29 aug 2017||Intel Corporation||Field effect transistor with narrow bandgap source and drain regions and method of fabrication|
|US9761724||14 jun 2016||12 sep 2017||Intel Corporation||Semiconductor device structures and methods of forming semiconductor structures|
|US9806193||29 aug 2016||31 okt 2017||Intel Corporation||Stress in trigate devices using complimentary gate fill materials|
|US9806195||14 mar 2016||31 okt 2017||Intel Corporation||Method for fabricating transistor with thinned channel|
|US20050287748 *||24 jun 2004||29 dec 2005||Jack Kavalieros||Reducing reactions between polysilicon gate electrodes and high dielectric constant gate dielectrics|
|US20080169512 *||20 dec 2007||17 jul 2008||Doyle Brian S||Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow|
|US20090061572 *||28 okt 2008||5 mar 2009||Intel Corporation||Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication|
|US20090061631 *||31 aug 2007||5 mar 2009||Spansion Llc||Gate replacement with top oxide regrowth for the top oxide improvement|
|US20100052063 *||18 dec 2008||4 mar 2010||Taiwan Semiconductor Manufacturing Company, Ltd.||Method to improve dielectric quality in high-k metal gate technology|
|US20110241127 *||28 maj 2010||6 okt 2011||Taiwan Semiconductor Manufacturing Company, Ltd.||Well implant through dummy gate oxide in gate-last process|
|US20150087144 *||26 sep 2013||26 mar 2015||Taiwan Semiconductor Manufacturing Company Ltd.||Apparatus and method of manufacturing metal gate semiconductor device|
|US20160005620 *||3 jul 2014||7 jan 2016||International Business Machines Corporation||Control of o-ingress into gate stack dielectric layer using oxygen permeable layer|
|CN104051250B *||3 mar 2014||22 dec 2017||Asm Ip 控股有限公司||金属薄膜的硅烷或硼烷处理|
|DE102015114644B3 *||2 sep 2015||5 jan 2017||Taiwan Semiconductor Manufacturing Company, Ltd.||Herstellungsverfahren für eine Halbleiterkomponente und für eine Fin-FET Vorrichtung|
|WO2011114046A1 *||11 mar 2011||22 sep 2011||Commissariat A L'energie Atomique Et Aux Energies Alternatives||Process for producing a conducting electrode|
|USA-klassificering||438/592, 257/E21.444, 438/229, 438/299, 257/E29.16, 257/E21.204, 257/E21.432|
|Internationell klassificering||H01L29/49, H01L21/336, H01L21/28, H01L21/3205|
|Kooperativ klassning||H01L29/66606, H01L21/28088, H01L29/66545, H01L29/4966|
|Europeisk klassificering||H01L29/66M6T6F11C, H01L29/66M6T6F8, H01L21/28E2B6, H01L29/49E|
|17 jun 2003||AS||Assignment|
Owner name: ADVANCED MICRO DEVICES INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PAN, JAMES;BESSER, PAUL;WOO, CHRISTY MEI-CHU;AND OTHERS;REEL/FRAME:014189/0580;SIGNING DATES FROM 20030602 TO 20030613
|3 maj 2005||CC||Certificate of correction|
|15 maj 2008||FPAY||Fee payment|
Year of fee payment: 4
|18 aug 2009||AS||Assignment|
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS
Free format text: AFFIRMATION OF PATENT ASSIGNMENT;ASSIGNOR:ADVANCED MICRO DEVICES, INC.;REEL/FRAME:023119/0083
Effective date: 20090630
|16 maj 2012||FPAY||Fee payment|
Year of fee payment: 8
|22 jul 2016||REMI||Maintenance fee reminder mailed|
|14 dec 2016||LAPS||Lapse for failure to pay maintenance fees|
|31 jan 2017||FP||Expired due to failure to pay maintenance fee|
Effective date: 20161214