US6762068B1 - Transistor with variable electron affinity gate and methods of fabrication and use - Google Patents

Transistor with variable electron affinity gate and methods of fabrication and use Download PDF

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US6762068B1
US6762068B1 US09/652,420 US65242000A US6762068B1 US 6762068 B1 US6762068 B1 US 6762068B1 US 65242000 A US65242000 A US 65242000A US 6762068 B1 US6762068 B1 US 6762068B1
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floating gate
gate
substrate
incident light
exposing
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Leonard Forbes
Kie Y. Ahn
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Micron Technology Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/2807Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being Si or Ge or C and their alloys except Si
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40114Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324Gate electrodes for transistors with a floating gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H01L31/101Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/112Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor
    • H01L31/113Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor being of the conductor-insulator-semiconductor type, e.g. metal-insulator-semiconductor field-effect transistor
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/931Silicon carbide semiconductor

Definitions

  • the present invention relates generally to integrated circuit technology, and particularly to a silicon carbide gate transistor, such as a floating gate transistor, and complementary metal-oxide-semiconductor (CMOS) compatible methods of fabrication, and methods of use in memory and light detection devices.
  • CMOS complementary metal-oxide-semiconductor
  • FETs Field-effect transistors
  • CMOS complementary metal-oxide-semiconductor
  • Resulting FETs typically have gate electrodes composed of n-type conductively doped polycrystalline silicon (polysilicon) material.
  • the intrinsic properties of the polysilicon gate material affects operating characteristics of the FET.
  • Silicon monocrystalline and polycrystalline
  • has intrinsic properties that include a relatively small energy bandgap (E g ), e.g. approximately 1.2 eV, and a corresponding electron affinity ( ⁇ ) that is relatively large, e.g. ⁇ 4.2 eV.
  • E g energy bandgap
  • electron affinity
  • EEPROM memory cells typically use FETs having an electrically isolated (floating) gate that affects conduction between source and drain regions of the FET.
  • a gate dielectric is interposed between the floating gate and an underlying channel region between source and drain regions.
  • a control gate is provided adjacent to the floating gate, separated therefrom by an intergate dielectric.
  • Fowler-Nordheim tunneling is one method that is used to store charge on the polysilicon floating gates during a write operation and to remove charge from the polysilicon floating gate during an erase operation.
  • the relatively large electron affinity of the polysilicon floating gate presents a relatively large tunneling barrier energy at its interface with the underlying gate dielectric.
  • the large tunneling barrier energy provides longer data retention times than realistically needed. For example, a data charge retention time at 85° C. is estimated to be in millions of years for some floating gate memory devices.
  • the large tunneling barrier also increases the time needed to store charge on the polysilicon floating gates during the write operation and the time needed to remove charge from the polysilicon floating gate during the erase operation.
  • flash EEPROMs which have an architecture that allows the simultaneous erasure of many floating gate transistor memory cells. Since more charge must be removed from the many floating gates in a flash EEPROM, even longer erasure times are needed to accomplish this simultaneous erasure. There is a need in the art to obtain floating gate transistors allowing faster storage and erasure, such as millisecond erasure periods in flash EEPROMs.
  • Halvis et al. U.S. Pat. No. 5,369,040 discloses a charge-coupled device (CCD) photodetector which has transparent gate MOS imaging transistors fabricated from polysilicon with the addition of up to 50% carbon, and preferably about 10% carbon, which makes the gate material more transparent to the visible portion of the energy spectrum.
  • the Halvis et al. patent is one example of a class of conventional CCD photodetectors that are directed to improving gate transmissivity to allow a greater portion of incident light in the visible spectrum to penetrate through the gate for absorption in the semiconductor substrate.
  • the absorption of photons in the semiconductor substrate is limited to high energy photons exceeding a bandgap energy of the semiconductor substrate.
  • the present invention includes a transistor having a gate formed of a silicon carbide compound Si 1 ⁇ x C x , wherein x is selected at a predetermined value approximately between 0 and 1.0 to establish a desired value of a barrier energy between the gate and an adjacent insulator.
  • the SiC gate is either electrically isolated (floating) or interconnected.
  • the gate is an electrically isolated floating gate, and the transistor further includes a control gate, separated from the floating gate by an intergate dielectric.
  • Another aspect of the invention provides a method of producing a transistor on a semiconductor substrate.
  • Source and drain regions are formed, thereby defining a channel region between the source and drain regions.
  • An insulating layer is formed on the channel region.
  • a gate is formed on the insulating layer.
  • the gate comprises a silicon carbide compound Si 1 ⁇ x C x .
  • the SiC composition x is selected at a predetermined value approximately between 0 and 1.0. In one embodiment, the value of the SiC composition x is selected to establish the value of a barrier energy between the gate and the insulator.
  • Another aspect of the invention provides light detection.
  • Charge is stored on a floating gate of a transistor.
  • Incident light is received at the floating gate, thereby removing at least a portion of the stored charge from the floating gate by the photoelectric effect.
  • a change in conductance between the transistor source and drain is detected.
  • the method of detecting light includes selecting at least one wavelength of the incident light to which the floating gate transistor is most sensitive.
  • the invention provides a transistor that includes a floating gate separated from a channel region by an insulator.
  • The, floating gate is formed of a silicon carbide compound Si 1 ⁇ x C x .
  • the SiC composition variable x is selected at a predetermined value approximately between 0 and 1.0 to establish the wavelength of incident light absorption to which the floating gate is sensitive.
  • Charge is stored on the floating gate. Incident light is received at the floating gate, thereby removing at least a portion of the stored charge from the floating gate by the photoelectric effect. A change in conductance between the transistor source and drain is detected. Unlike conventional photodetectors, light is absorbed in the floating gate, thereby ejecting previously stored electrons therefrom. Also unlike conventional photodetectors, the light detector according to the present invention is actually more sensitive to lower energy photons as the semiconductor bandgap is increased.
  • the transistor is used in a memory device that includes a plurality of memory cells.
  • Each memory cell includes a transistor having a floating gate separated from the channel region by an insulator.
  • the floating gate is formed of a silicon carbide compound Si 1 ⁇ x C x , wherein x is selected at a predetermined value approximately between 0 and 1.0 to establish a desired value of a barrier energy between the gate and the insulator.
  • the SiC composition x is selected to provide the desired programming and erase voltage and time or data charge retention time.
  • the lower barrier energy and increased tunneling probability of the SiC gate advantageously provides faster programming and erasure times for floating SiC gate transistors in flash EEPROM memories. This is particularly advantageous for “flash” EEPROMs in which many floating gate transistor memory cells must be erased simultaneously. Writing and erasure voltages are also advantageously reduced, minimizing the need for complicated and noisy on-chip charge pump circuits to generate the large erasure voltage.
  • Lower erasure voltages also reduce hole injection into the gate dielectric that can cause erratic overerasure, damage to the gate dielectric, and introduction of trapping states in the gate dielectric. Reducing the erasure voltage also lowers the electric fields, minimizing reliability problems that can lead to device failure, and better accommodating downward scaling of device dimensions.
  • Data charge retention time is decreased. Since conventional data charge retention times are longer than what is realistically needed, a shorter data charge retention time can be accommodated in order to obtain the benefits of a smaller barrier energy.
  • the data charge retention time can be selected between seconds and millions of years by selecting the value of the SiC composition x, such as to obtain different memory functionality.
  • FIG. 1 is a cross-sectional view illustrating generally one embodiment of a FET provided by the invention, which includes an electrically isolated (floating) or interconnected gate including a silicon carbide (SiC) compound.
  • SiC silicon carbide
  • FIG. 2 is a graph illustrating generally barrier energy versus tunneling distance for SiC and conventional polysilicon gates.
  • FIGS. 3A, 3 B, and 3 C illustrate generally electron affinities of various SiC compositions and of silicon dioxide, and the resulting interfacial barrier energy therebetween.
  • FIG. 4 is a cross-sectional view illustrating generally a variable electron affinity floating SiC gate field-effect transistor (FET) provided by the invention.
  • FET field-effect transistor
  • FIG. 5 is a graph that illustrates generally the relationship between retention time and barrier energy, and also the relationship between erase time and barrier energy.
  • FIG. 6 illustrates generally a flash EEPROM memory having memory cells that include an SiC gate transistor according to the present invention.
  • FIG. 7 is a cross-sectional schematic diagram of the floating gate transistor that illustrates generally its application according to the present invention as a light detector or imaging device.
  • FIG. 8 is a cross-sectional schematic diagram that illustrates generally how incident light is detected by the absorption of photons by the floating gate.
  • FIG. 9 is a graph that illustrates generally, by way of example, the SiC absorption coefficient as a function of wavelength and photon energy.
  • FIG. 10 is a graph illustrating generally barrier height versus tunneling distance, and further illustrating the absorption of light energy by the floating gate.
  • FIG. 11 is a graph illustrating generally barrier height versus tunneling distance, and distinguishing photoelectric absorption of incident light in the SiC floating gate from valence-to-conduction band electron transitions.
  • FIGS. 12A, 12 B, 12 C, 12 D, 12 E, 12 F, and 12 G illustrate generally examples of process steps for fabricating n-channel and p-channel SiC gate FETs according to the present invention, including the fabrication of SiC floating gate transistors.
  • wafer and substrate used in the following description include any semiconductor-based structure having an exposed surface with which to form the integrated circuit structure of the invention. Wafer and substrate are used interchangeably to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon.
  • Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art.
  • doped and undoped semiconductors epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art.
  • the following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.
  • the present invention includes a field-effect transistor (FET) having a gate that is formed of at least partially crystalline (e.g., monocrystalline, polycrystalline, microcrystalline, or nanocrystalline) diamond-like silicon carbide (SiC) material, which includes any material that incorporates both silicon and carbon into the gate region of a FET.
  • the SiC gate FET includes characteristics such as, for example, a lower electron affinity than a conventional polycrystalline silicon (polysilicon) gate FET.
  • Another aspect of the invention provides a tailored SiC material composition for use in conjunction with a particular gate dielectric, or for particular applications, such as data storage (memory) and imaging.
  • FIG. 1 is a cross-sectional view illustrating generally, by way of example, one embodiment of a n-channel FET provided by the invention.
  • the invention is understood to also include a p-channel FET embodiment.
  • the n-channel FET includes a source 102 , a drain 104 , and a gate 106 .
  • a gate dielectric such as thin oxide layer 118 or other suitable insulator, is interposed between gate 106 and substrate 108 .
  • source 102 and drain 104 are fabricated by forming highly doped (n+) regions in a lightly doped (p ⁇ ) silicon semiconductor substrate 108 .
  • substrate 108 includes a thin semiconductor surface layer formed on an underlying insulating portion, such as in a semiconductor-on-insulator (SOI) or other thin film transistor technology.
  • Source 102 and drain 104 are separated by a predetermined length in which a channel region 110 is formed.
  • gate 106 is formed of silicon carbide (SiC) material, which includes any material that incorporates both silicon and carbon into gate 106 .
  • the silicon carbide material forming gate 106 is described more generally as Si 1 ⁇ x C x , where x is a composition variable that defines the SiC material composition.
  • the SiC composition x is selected at a predetermined value that establishes the value of a barrier energy (also referred to as a barrier potential, potential barrier, tunneling barrier, interface barrier, or barrier) between gate 106 and thin oxide layer 118 (or other gate dielectric).
  • a barrier energy also referred to as a barrier potential, potential barrier, tunneling barrier, interface barrier, or barrier
  • the SiC composition is approximately stoichiometric, i.e., ⁇ 0.5.
  • the SiC gate material is illustrated by 0.1 ⁇ x ⁇ 0.5.
  • Another example embodiment is illustrated by way of example, but not by way of limitation, by 0.4 ⁇ x ⁇ 0.6.
  • Still another embodiment is illustrated by way of example, but not by way of limitation, by 0.5 ⁇ x ⁇ 1.0.
  • the SiC composition x is selected as a predetermined value in order to tailor the barrier for particular applications.
  • the SiC composition x is uniform over a particular integrated circuit die.
  • the SiC composition x is differently selected at different locations on the integrated circuit die, such as by additional masking or processing steps, to obtain different device characteristics on the same integrated circuit die.
  • an insulating layer such as silicon dioxide (oxide) 114 or other insulating layer, is formed by chemical vapor deposition (CVD).
  • Oxide 114 isolates gate 106 from other layers, such as layer 112 .
  • gate 106 is oxidized to form at least a portion of oxide 114 isolating gate 106 from other layers such as layer 112 .
  • layer 112 is a polysilicon or other control gate in a floating gate transistor.
  • the floating gate transistor is used in an electrically erasable and programmable read-only memory (EEPROM) memory cell, such as a flash EEPROM, or in a floating gate transistor photodetector or imaging device, as described below.
  • EEPROM electrically erasable and programmable read-only memory
  • gate 106 is floating (electrically isolated) for charge storage thereupon.
  • the present invention offers considerable advantages to the known EEPROM techniques used for charge storage on floating gate 106 .
  • layer 112 is a metal or other conductive interconnection line that is located above gate 106 .
  • thin oxide layer 118 is a gate oxide layer that can be approximately 100 angstroms ( ⁇ ) thick, such as for conventional FET operation.
  • thin oxide layer 118 is a tunnel oxide material that can be approximately 50-100 ⁇ thick.
  • the SiC gate 106 has particular advantages over polysilicon gates used in floating gate and conventional FETs fabricated using a conventional complementary metal-oxide-semiconductor (CMOS) process due to different characteristics of the SiC material.
  • CMOS complementary metal-oxide-semiconductor
  • SiC stoichiometric SiC (x ⁇ 0.5) is a wide bandgap semiconductor material with a bandgap energy of about 2.1 eV, in contrast to silicon (monocrystalline or polycrystalline), which has a bandgap energy of about 1.2 eV.
  • Stoichiometric SiC has an electron affinity of about 3.7 to 3.8 eV, while silicon has an electron affinity of about 4.2 eV.
  • the smaller electron affinity of the SiC gate 106 material reduces the barrier energy at the interface between gate 106 and thin oxide layer 118 .
  • thin oxide layer 118 is a tunnel oxide in a floating gate transistor EEPROM memory cell
  • the lower electron affinity of SiC reduces the tunneling distance and increases the tunneling probability. This speeds the write and erase operations of storing and removing charge to and from floating gate 106 .
  • flash EEPROMs in which many floating gate transistor memory cells must be erased simultaneously.
  • the large charge that must be transported by Fowler-Nordheim tunneling during the erasure of a flash EEPROM typically results in relatively long erasure times.
  • the SiC gate 106 reduces erasure times in flash EEPROMs.
  • the exact value of the SiC composition x is selected to obtain the desired barrier potential for the particular application.
  • the predetermined value the SiC composition x establishes the particular electron affinity, ⁇ , such as between that of stoichiometric SiC (about 3.7 to 3.8 eV) and a value ⁇ 0 eV.
  • the particular electron affinity
  • the barrier energy is further decreased from that of stoichiometric SiC by the exact amount desired. This speeds storage and removal of charge to and from the floating gate 106 during write and erase operations.
  • the SiC composition x is selected to establish the particular data charge retention time.
  • the data charge retention time can be selected between seconds and millions of years.
  • FIG. 1 illustrates generally, by way of example, a complementary metal-oxide-semiconductor (CMOS) compatible n-channel FET that includes an SiC gate 106 , which may be floating or electrically interconnected.
  • CMOS complementary metal-oxide-semiconductor
  • the FET can be formed on substrate 108 using an n-well CMOS process for monolithic CMOS fabrication of n-channel and p-channel FETs on a common substrate.
  • the invention includes both n-channel and p-channel FETs that have a polycrystalline or microcrystalline SiC gate 106 .
  • the FET of FIG. 1 can be a p-channel FET.
  • the p-channel and n-channel SiC gate FETs are useful for any application in which conventionally formed polysilicon gate FETs are used, including both electrically driven and floating gate applications.
  • FIG. 2 illustrates generally how the smaller SiC electron affinity provides a smaller barrier energy than a conventional polysilicon gate.
  • the smaller SiC barrier energy reduces the energy to which the electrons must be excited to be stored on the SiC gate 106 by thermionic emission.
  • the smaller barrier energy also reduces the distance that electrons stored on the gate have to traverse, such as by Fowler-Nordheim tunneling, to be stored upon or removed from the SiC gate 106 .
  • the reduced tunneling distance allows easier charge transfer, such as during writing or erasing data in a floating gate transistor in a flash EEPROM memory cell.
  • “do” represents the tunneling distance of a typical polysilicon floating gate transistor due to the barrier height represented by the dashed line “OLD”.
  • the tunneling distance “dn” corresponds to a SiC gate and its smaller barrier height represented by the dashed line “NEW”. Even a small reduction in the tunneling distance results in a large increase in the tunneling probability, because the tunneling probability is an exponential function of the reciprocal of the tunneling distance.
  • the increased tunneling probability of the SiC gate 106 advantageously provides faster programming and erasure times for floating SiC gate transistors in flash EEPROM memories.
  • the smaller bandgap of floating SiC gate transistors have a smaller turn-on threshold voltage magnitude, thereby also allowing operation of such flash EEPROM memories at lower power supply voltages.
  • FIGS. 3A-3C illustrate generally by way of example, but not by way of limitation, different selections of the predetermined value of the SiC composition x. Differently selected values of the SiC composition x provide different resulting barrier energies at the interface between gate 106 and the adjacent thin oxide layer 118 (or other gate or tunneling dielectric).
  • FIGS. 3A-3C illustrate, by way of example, but not by way of limitation, the use of a silicon dioxide gate insulator such as thin oxide layer 118 .
  • the invention includes the use of any other gate insulator materials in combination with the SiC gate 106 .
  • the electron affinities, ⁇ , of each of the thin oxide layer 118 and SiC gate 106 are measured with respect to the vacuum level 300 .
  • the electron affinity, ⁇ is defined by the difference between the oxide conduction band 302 and the vacuum level 300 .
  • the electron affinity, ⁇ is defined by the difference between the semiconductor conduction band edge 305 and the vacuum level 300 .
  • the barrier energy at the interface between thin oxide layer 118 and SiC gate 106 is illustrated by the difference between their respective electron affinities, ⁇ .
  • the SiC composition is selected at x ⁇ 0, which is an extreme limit in which the SiC gate 106 material composition is approximately pure silicon (e.g., polycrystalline or microcrystalline).
  • the resulting electron affinity in the gate 106 material is ⁇ 4.2 eV.
  • the electron affinity in thin oxide layer 118 is ⁇ 0.9 eV.
  • the resulting barrier energy is approximately 3.3 eV.
  • the 3.3 eV barrier energy results in long data charge retention times (estimated in millions of years at a temperature of 85 degrees C.) together with large erasure voltages and long write and erase times.
  • the 3.3 eV barrier energy requires relatively high energy photons (i.e., high frequency and short wavelength) to eject stored electrons from the floating gate 106 .
  • the SiC composition is selected at x ⁇ 0.5, for which the SiC gate 106 material is approximately stoichiometric SiC.
  • the resulting electron affinity in the gate 106 material is ⁇ 3.7 eV.
  • the electron affinity in thin oxide layer 118 is ⁇ 0.9 eV.
  • the resulting barrier energy is approximately 2.8 eV.
  • the 2.8 eV barrier energy results in shorter charge retention times than are obtained than in the case described with respect to FIG. 3A, together with smaller erasure voltages and shorter write and erase times.
  • the 2.8 eV barrier energy needs less photon energy (i.e., lower frequency and longer wavelength) to eject electrons from the floating gate 106 than in the case described with respect to FIG. 3 A.
  • the SiC composition is selected at x ⁇ 1, which is an extreme limit in which the material is substantially pure carbon (i.e., diamond).
  • the resulting electron affinity in the gate material is ⁇ 0.4 eV.
  • the electron affinity in the silicon dioxide insulator 118 is ⁇ 0.9 eV.
  • the resulting barrier energy is approximately ⁇ 1.3 eV. In this case, electrons will not stay in the conduction band of the diamond gate 106 material, but will instead move into the thin oxide layer 118 .
  • the barrier energy at the interface between thin oxide layer 118 and SiC gate 106 is adjusted by tuning the SiC composition x.
  • the SiC gate material compounds can be doped p-type or n-type, either during formation or by a subsequent doping step.
  • the SiC films are quite conductive even when intrinsic. In floating gate applications, the SiC films need not be very conductive since they are not used for interconnection wiring.
  • An SiC floating gate 106 need only allow for redistribution of carriers in the floating gate 106 .
  • Microcrystalline SiC compounds have a smaller electron affinity than polycrystalline SiC compounds.
  • the barrier potential is adjusted by selecting between microcrystalline and polycrystalline SiC compounds for the gate 106 material.
  • FIG. 4 is a cross-sectional view of a transistor, similar to that of FIG. 1, illustrating generally a floating gate transistor embodiment of the invention, such as for use as a nonvolatile memory cell in a flash EEPROM.
  • floating gate 106 is a polycrystalline or microcrystalline SiC compound for which 0.5 ⁇ x ⁇ 1.0.
  • a lower barrier energy is obtained at the interface between gate 106 and thin oxide layer 118 .
  • the exact barrier energy is established by selecting the predetermined value of the SiC composition x.
  • the lower barrier energy provides a larger tunneling probability during write and erase operations.
  • Write and erasure voltages and times are reduced. Secondary problems that are normally associated with erasure of charge stored on polysilicon gates, such as electron trap creation and hole injection, are correspondingly reduced along with the erasure voltage.
  • the exact value of the SiC composition x is selected to establish a barrier energy that is large enough to prevent electrons from being thermally excited over the barrier at high operating temperatures, such as at a temperature of 85° C., as this could allow the stored data charges to leak from the floating gate over a long period of time.
  • the high barrier energy of a polysilicon floating gate material provides a longer than realistically needed data charge retention time that is estimated in millions of years.
  • the SiC composition x is selected to obtain a lower barrier energy, providing data retention times that are more suited to the particular application. In one embodiment of the present invention, the SiC composition x is selected to obtain typical data charge retention times between seconds and millions of years.
  • the invention includes operation of a SiC floating gate transistor memory device.
  • Floating gate 106 can be programmed, by way of example, but not by way of limitation, by providing about 12 volts to control gate 112 , and providing about 6 volts to drain 104 , and providing about 0 volts to source 102 . This creates an inversion layer in channel region 110 , in which electrons are accelerated from source 102 toward drain 104 , acquiring substantial kinetic energy. High energy “hot electrons’ are injected through thin oxide layer 118 onto the polycrystalline or microcrystalline SiC floating gate 106 . Floating gate 106 accumulates the hot electrons as stored data charges.
  • the change in the charge stored on floating gate 106 changes the threshold voltage of the n-channel floating gate FET of FIG. 4 .
  • control gate 112 is driven to a read voltage during a read operation, the change in charge stored on floating gate 106 results in a change in current between drain 104 and source 102 .
  • detection of the change in charge stored on floating gate 106 by sensing drain-source current conductance advantageously uses the appreciable transconductance gain of the floating gate FET of FIG. 4 .
  • Either analog or digital data can be stored as charge on floating gate 106 and read back as a conductance between drain region 104 and source region 102 .
  • the erase time for the memory cell is determined by the height of the barrier between floating gate 106 and thin oxide layer 118 .
  • a lower barrier energy results in a shorter tunneling distance, as described with respect to FIG. 2 . This, in turn, results in a faster erase operation, lower erasure voltages, or both faster erase operation and lower erasure voltages. Short erase times are normally particularly desirable in flash memories, in which many memory cells must be simultaneously erased.
  • a lower barrier energy also means a shorter data charge retention time due to thermal excitation of electrons over or tunneling of electrons through the barrier.
  • the barrier energy is varied by changing the SiC composition x.
  • the data charge retention time can be established at a value that is, for example, between seconds and millions of years.
  • a flash memory device that incorporates the SiC floating gate transistor provides a data charge retention time that is tailored to the particular application.
  • the flash memory device can be made to emulate a dynamic random access memory (DRAM), with data charge retention times on the order of seconds.
  • DRAM dynamic random access memory
  • the flash memory device can be made to emulate a hard disk drive, by providing a data charge retention time on the order of years.
  • one memory device provides different memory functions by selecting the SiC composition x.
  • floating gate transistors having different SiC compositions x are provided on the same integrated circuit, thereby providing differently functioning memory cells on the same integrated circuit.
  • FIG. 5 is a conceptual diagram, using rough order of magnitude estimates, that illustrates generally how erase and retention times vary with the barrier energy for a particular value of erasure voltage at a particular temperature of 85° C.
  • the probability of thermal excitation and emission over or tunneling through the barrier is an exponential function of the barrier energy.
  • a lower barrier provides exponentially shorter erase and retention times.
  • the particular memory application requirements determine the needed memory retention time, whether seconds or years. From this memory retention time, the barrier energy required and the erase time for a particular voltage can be determined using an engineering graph similar to that of FIG. 5 .
  • the SiC composition x is selected to provide a retention time on the order of seconds or years, depending upon the function required for the memory device.
  • the memory device can emulate or replace DRAMs or hard disk drives by selecting the SiC composition x to establish the appropriate data charge retention time.
  • FIG. 6 is a simplified block diagram illustrating generally one embodiment of a memory 600 system, according to one aspect of the present invention, in which SiC gate FETs are incorporated.
  • memory 600 is a flash EEPROM
  • the SiC gate FETs are floating gate transistors that are used for nonvolatile storage of data as charge on the SiC floating gates.
  • the SiC gate FETs can have electrically interconnected gates, and can be used in other types of memory systems, including SDRAM, SLDRAM and RDRAM devices, or in programmable logic arrays (PLAs), or in any other application in which transistors are used.
  • PDAs programmable logic arrays
  • FIG. 6 illustrates, by way of example, but not by way of limitation, a flash EEPROM memory 600 comprising a memory array 602 of multiple memory cells.
  • Row decoder 604 and column decoder 606 decode addresses provided on address lines 608 to access addressed SiC gate floating gate transistors in the memory cells in memory array 602 .
  • Command and control circuitry 610 controls the operation of memory 600 in response to control signals received on control lines 616 from a processor 601 or other memory controller during read, write, and erase operations.
  • Voltage control 614 is provided to apply appropriate voltages to the memory cells during programming and erasing operations. It will be appreciated by those skilled in the art that the memory of FIG. 6 has been simplified for the purpose of illustrating the present invention and is not intended to be a complete description of a flash EEPROM memory.
  • the SiC floating gate transistor of FIG. 4 is used in light detection applications, such as a photodetector or imaging device.
  • light is detected by the absorption of photons by the SiC floating gate 106 .
  • imaging devices such as sensors using a charge-coupled device (CCD) or a photodiode detector, in which light is absorbed in the semiconductor substrate, thereby producing charge carriers that are detected.
  • CCD charge-coupled device
  • photodiode detector in which light is absorbed in the semiconductor substrate, thereby producing charge carriers that are detected.
  • charge is stored on the SiC floating gate 106 , such as by known EEPROM charge storage techniques.
  • the imaging device is exposed to incident light. Incident photons having enough energy to eject an electron by photoelectric emission from floating gate 106 are detected by a resulting change in drain-source conductance of the imaging device.
  • the light detector of the present invention advantageously utilizes the transconductance gain of the floating gate transistor.
  • the wavelength to which the light detector is sensitive is established by selecting the SiC composition x of floating gate 106 .
  • FIG. 7 is a cross-sectional schematic diagram of the floating gate transistor that illustrates generally its application according to the present invention as a light detector or imaging device.
  • floating gate 106 is charged by the injection of hot electrons 700 through thin oxide layer 118 under the SiC floating gate 106 .
  • This change in charge on floating gate 106 changes the threshold voltage of the n-channel floating gate FET.
  • control gate 112 is driven to a read voltage during a read operation, a large change in drain-source current is obtained through the transconductance gain of the floating gate transistor.
  • FIG. 8 is a cross-sectional schematic diagram that illustrates generally how incident light 800 is detected by the absorption of photons by floating gate 106 .
  • the photons must have enough energy to cause electrons 700 stored on floating gate 106 to overcome the barrier at the interface between floating gate 106 and thin oxide layer 118 and be ejected from floating gate 106 back into the semiconductor or SOI substrate by the photoelectric effect.
  • a small electric field in thin oxide layer 118 such as results from the presence of electrons 700 stored on floating gate 106 , assists in ejecting the electrons 700 toward substrate 108 .
  • Detection or imaging of visible wavelengths of incident light 800 requires a low electron affinity floating gate 106 .
  • the present invention allows the electron affinity of floating gate 106 to be tailored by selecting the particular value of the SiC composition of floating gate 106 .
  • FIG. 9 is a graph that illustrates generally, by way of example, the SiC absorption coefficient as a function of wavelength and photon energy.
  • SiC composition x Several values of the SiC composition x are illustrated, where 0 ⁇ x ⁇ 1.0.
  • the SiC composition x 0.5 (i.e., approximately stoichiometric SiC)
  • the resulting light absorption is illustrated generally by line 910 .
  • the SiC composition x ⁇ 0 i.e., approximately pure polycrystalline or microcrystalline Si
  • the resulting light absorption is illustrated generally by line 912 .
  • the SiC composition described approximately by 0.5 ⁇ x ⁇ 1.0 the resulting light absorption is illustrated generally by line 914 .
  • FIG. 10 further illustrates the absorption of light energy by floating gate 106 .
  • the incident photons have sufficient energy to allow electrons 700 stored on floating gate 106 to overcome the “new” barrier 1000 such that they are emitted from floating gate 106 back toward the semiconductor or SOI substrate 108 , thereby discharging floating gate 106 .
  • “Old” barrier 1005 which represents a Si—SiO 2 interface, is higher than “new” barrier 1000 of the SiC—SiO 2 interface.
  • a light detector having an SiC floating gate 106 is sensitive to lower energy photons than a light detector having an Si floating gate.
  • SiC floating gate 106 is doped n-type to maximize the number of conduction band electrons 700 in floating gate 106 and the absorption of incident light. Visible light has a photon energy of about 2 eV. For detection of visible light, the barrier energy at the interface between floating gate 106 and thin oxide layer 118 should be less than or equal to about 2 eV. However, most common gate materials have larger barrier energies with an adjacent silicon dioxide insulator. For example, a conventional polysilicon floating gate 106 results in a barrier energy of about 3.3 eV.
  • polycrystalline or microcrystalline SiC is used as the material for floating gate 106 .
  • the SiC composition x is selected for sensitivity to particular wavelengths of light, and the barrier energy is established accordingly.
  • the SiC composition x is selected in the range 0.5 ⁇ x ⁇ 1.0 such that barrier energy is less than or equal to about 2 eV.
  • the floating gate transistor light detector is sensitive to visible light.
  • the floating gate transistor light detector is made sensitive to different portions of the light spectrum by adjusting the barrier energy through the selection of the SiC composition x.
  • the SiC composition x can also be different for different floating gate transistors on the same integrated circuit in order to yield different sensitivities to different wavelengths of light.
  • FIG. 11 illustrates generally how the above-described photoelectric absorption of incident light in the SiC floating gate 106 is distinguishable from, and independent of, valence-to-conduction band electron transitions, which is the common photon absorption mechanism of most diode or CCD photodetectors or imaging devices.
  • Conventional photon absorption is illustrated by the band-to-band electron energy transition 1100 .
  • Photon absorption according to the present invention is illustrated by the emission 1105 of a conduction band electron 700 from floating gate 106 over the barrier 1000 between the floating gate semiconductor conduction band 1110 and oxide conduction band 1115 .
  • the semiconductor bandgap is defined by the energy difference between semiconductor conduction band 1110 and semiconductor valence band 1120 . Exciting an electron from the valence band 1120 low energy state to a conduction band 1110 high energy state requires absorption of an incident photon of energy exceeding the bandgap of the semiconductor material. For diamond-like SiC compounds, these band-to-band transitions occur only at very high photon energies, such as for ultraviolet light. By contrast, photoelectric emission 1105 of electrons from floating gate 106 only requires that the incident photon energy exceed the barrier 1000 between floating gate 106 and thin oxide layer 118 . Since the present invention allows the barrier 1000 energy to be less than the 2 eV energy of a visible photon by an appropriate selection of the SiC composition x, and even allows a negative barrier 1000 energy, a wide spectrum of light detection is obtained.
  • the present invention In conventional photodetectors, only high energy photons are detected as the bandgap is increased (i.e., as the bandgap becomes larger, first red, then blue, and finally ultraviolet light is required for band-to-band photon absorption). According to the present invention, a larger bandgap typically results in a smaller barrier 1000 energy, thereby allowing detection of even lower energy photons as the bandgap is increased (i.e., as the bandgap becomes larger, the detector becomes sensitive not only to ultraviolet, but to blue, then red, and finally to infrared wavelengths). As a result, the present invention can be used for visible and infrared light detection and imaging, including camera-like operations, and can employ lenses, shutters, or other such known imaging techniques.
  • FIG. 11 illustrates generally, by way of example, but not by way of limitation, the absorption of red light with photon energies of around 2 eV in the SiC floating gate 106 .
  • the SiC composition x is selected such that the barrier 1000 energy between SiC floating gate 106 and thin oxide layer 118 is less than (or much less than) 2 eV, while the bandgap for the SiC floating gate 106 is much higher than 2 eV.
  • incident photons generate negligible electron-hole pairs or valence-to-conduction band transitions in floating gate 106 . Instead, absorption of photons is substantially entirely the result of photoelectric emission of electrons from floating gate 106 .
  • the floating gate transistor offers appreciable transconductance gain. Emitting a single electron from the floating gate changes the number of electrons flowing out of the drain 104 by thousands.
  • the floating gate detector device is adjusted for optimum response over almost the entire optical spectrum, from infrared through visible light to ultraviolet.
  • sensitivity is improved by doping the SiC floating gate 106 n-type, to increase the number of conduction band electrons stored on floating gate 106 .
  • FIGS. 12A-12G illustrate generally examples of CMOS-compatible process steps for fabricating n-channel and p-channel SiC gate FETs according to the present invention, including the fabrication of SiC floating gate transistors.
  • the transistors can be produced on a silicon or other semiconductor substrate, an SOI substrate, or any other suitable substrate 108 . Only the process steps that differ from conventional CMOS process technology are described in detail.
  • substrate 108 undergoes conventional CMOS processing up to the formation of the gate structure.
  • field oxide 1200 is formed for defining active regions 1202 .
  • well regions are formed, such as for carrying p-channel transistors.
  • an insulating layer such as thin oxide layer 118 or other suitable insulator, is formed on substrate 108 , such as by dry thermal oxidation, including over the portions of the active regions 1202 in which transistors will be fabricated.
  • thin oxide layer 118 is a gate oxide layer that can be approximately 100 angstroms ( ⁇ ) thick.
  • thin oxide layer 118 is a tunnel oxide material that can be approximately 50-100 ⁇ thick.
  • a thin film 1206 of conductively doped polycrystalline or microcrystalline SiC is then deposited, such as by chemical vapor deposition (CVD) over the entire wafer, including over thin oxide layer 118 .
  • the SiC composition x of film 1206 is differently selected according to the particular barrier energy desired at the interface between the gate 106 and adjacent thin oxide layer 118 , as described above.
  • Microcrystalline SiC compounds may be selected for their lower electron affinity than polycrystalline SiC compounds in order to obtain the desired barrier energy.
  • the SiC film 1206 can be in situ doped during deposition, or doped during a subsequent ion-implantation step.
  • the conductive doping can be n-type or p-type.
  • the SiC film 1206 is conductively doped n-type for enhanced photoelectric emission of electrons from floating gate 106 in response to incident light, as described above.
  • the SiC film 1206 is conductively doped p-type using a boron dopant, which advantageously diffuses from the SiC gate 106 less easily than from a polysilicon gate during subsequent thermal processing steps.
  • SiC film 1206 is deposited using low-pressure chemical vapor deposition (LPCVD), providing the structure illustrated in FIG. 12 C.
  • LPCVD low-pressure chemical vapor deposition
  • the LPCVD process uses either a hot-wall reactor or a cold-wall reactor with a reactive gas, such as a mixture of Si(CH 3 ) 4 and Ar.
  • SiC film 1206 can be deposited using other techniques such as, for example, enhanced CVD techniques known to those skilled in the art including low pressure rapid thermal chemical vapor deposition (LP-RTCVD), or by decomposition of hexamethyl disalene using ArF excimer laser irradiation, or by low temperature molecular beam epitaxy (MBE).
  • LP-RTCVD low pressure rapid thermal chemical vapor deposition
  • MBE low temperature molecular beam epitaxy
  • SiC film 1206 examples include reactive magnetron sputtering, DC plasma discharge, ion-beam assisted deposition, ion-beam synthesis of amorphous SiC films, laser crystallization of amorphous SiC, laser reactive ablation deposition, and epitaxial growth by vacuum anneal.
  • the conductivity of the SiC film 1206 can be changed by ion implantation during subsequent process steps, such as during the self-aligned formation of source/drain regions for the n-channel and p-channel FETs.
  • SiC film 1206 is patterned and etched, together with thin oxide layer 118 , to form SiC gate 106 .
  • SiC film 1206 is patterned using standard techniques and is etched using plasma etching, reactive ion etching (RIE) or a combination of these or other suitable methods.
  • RIE reactive ion etching
  • SiC film 1206 can be etched by RIE in a distributed cyclotron resonance reactor using a SF 6 /O 2 gas mixture using SiO 2 as a mask with a selectivity of 6.5.
  • SiC film 1206 can be etched by RE using the mixture SF 6 and O 2 and F 2 /Ar/O 2 .
  • the etch rate of SiC film 1206 can be significantly increased by using magnetron enhanced RIE.
  • FIG. 12E illustrates one embodiment in which SiC gate 106 is oxidized after formation, providing a thin layer 1210 represented by the dashed line in FIG. 12 E.
  • SiC gate 106 can be oxidized, for example, by plasma oxidation similar to reoxidation of polycrystalline silicon. During the oxidation process, the carbon is oxidized as carbon monoxide or carbon dioxide and vaporizes, leaving the thin layer 1210 of silicon oxide over SiC gate 106 .
  • thin layer 1210 is used as, or as a portion of, an intergate dielectric between floating and control gates in a floating gate transistor embodiment of the present invention.
  • FIG. 12F illustrates generally a self-aligned embodiment of the formation of n-channel FET n+ source region 102 and drain region 104 .
  • p+ source drain regions can be similarly formed.
  • the doping of SiC gate 106 can be changed by ion implantation, such as during the formation of n-channel FET or p-channel FET source/drain regions, or subsequently thereto.
  • a p-type SiC film 1206 can be deposited, and its doping then changed to n+ by leaving SiC gate 106 unmasked during the formation of the n+ source region 102 and drain region 104 for the n-channel FET.
  • FIG. 12G illustrates generally the formation of an insulating layer, such as oxide 114 or other suitable insulator, after formation of n-channel FET source region 102 and drain region 104 .
  • oxide 114 is deposited over the upper surface of the integrated circuit structure using a standard CVD process.
  • Oxide 114 isolates SiC gate 106 from other gates such as, for example, an overlying or adjacent control gate layer 112 where SiC gate 106 is a floating gate in a floating gate transistor.
  • Oxide 114 also isolates SiC gate 106 from any other conductive layer 112 , such as polysilicon layers, gates, metal lines, etc., that are fabricated above and over SiC gate 106 during subsequent process steps.
  • the invention includes a CMOS-compatible FET having a low electron affinity SiC gate that is either electrically isolated (floating) or interconnected.
  • the SiC composition x is selected to provide the desired barrier at the SiC—SiO 2 interface, such as 0.5 ⁇ x ⁇ 1.0.
  • the SiC composition x is selected to provide the desired programming and erase voltage and time or data charge retention time.
  • the SiC composition x is selected to provide sensitivity to the desired wavelength of light.
  • light is absorbed in the floating gate, thereby ejecting previously stored electrons therefrom.
  • the light detector according to the present invention is actually more sensitive to lower energy photons as the semiconductor bandgap is increased.

Abstract

A CMOS-compatible FET has a reduced electron affinity polycrystalline or microcrystalline SiC gate that is electrically isolated (floating) or interconnected. The SiC material composition is selected to establish the barrier energy between the SiC gate and a gate insulator. In a memory application, such as a flash EEPROM, the SiC composition is selected to establish a lower barrier energy to reduce write and erase voltages and times or accommodate the particular data charge retention time needed for the particular application. In a light detector or imaging application, the SiC composition is selected to provide sensitivity to the desired wavelength of light. Unlike conventional photodetectors, light is absorbed in the floating gate, thereby ejecting previously stored electrons therefrom. Also unlike conventional photodetectors, the light detector according to the present invention is actually more sensitive to lower energy photons as the semiconductor bandgap is increased.

Description

This application is a Divisional of U.S. application Ser. No. 08/903,452, filed on Jul. 29, 1997, now abandoned.
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit technology, and particularly to a silicon carbide gate transistor, such as a floating gate transistor, and complementary metal-oxide-semiconductor (CMOS) compatible methods of fabrication, and methods of use in memory and light detection devices.
BACKGROUND OF THE INVENTION
Field-effect transistors (FETs) are typically produced using a standard complementary metal-oxide-semiconductor (CMOS) integrated circuit fabrication process. Such a process allows a high degree of integration for obtaining high circuit density with relatively few processing steps. Resulting FETs typically have gate electrodes composed of n-type conductively doped polycrystalline silicon (polysilicon) material.
The intrinsic properties of the polysilicon gate material affects operating characteristics of the FET. Silicon (monocrystalline and polycrystalline) has intrinsic properties that include a relatively small energy bandgap (Eg), e.g. approximately 1.2 eV, and a corresponding electron affinity (χ) that is relatively large, e.g. χ=4.2 eV. For example, for p-channel FETs fabricated by a typical CMOS process, these and other material properties result in a large turn-on threshold voltage (VT) magnitude. As a result, the VT magnitude must be downwardly adjusted by doping the channel region that underlies the gate electrode of the FET.
Conventional polysilicon gate FETs also have drawbacks that arise during use as a nonvolatile storage devices, such as in electrically erasable and programmable read only memories (EEPROMs). EEPROM memory cells typically use FETs having an electrically isolated (floating) gate that affects conduction between source and drain regions of the FET. A gate dielectric is interposed between the floating gate and an underlying channel region between source and drain regions. A control gate is provided adjacent to the floating gate, separated therefrom by an intergate dielectric.
In such memory cells, data is represented by charge stored on the polysilicon floating gates. Fowler-Nordheim tunneling is one method that is used to store charge on the polysilicon floating gates during a write operation and to remove charge from the polysilicon floating gate during an erase operation. However, the relatively large electron affinity of the polysilicon floating gate presents a relatively large tunneling barrier energy at its interface with the underlying gate dielectric. The large tunneling barrier energy provides longer data retention times than realistically needed. For example, a data charge retention time at 85° C. is estimated to be in millions of years for some floating gate memory devices. The large tunneling barrier also increases the time needed to store charge on the polysilicon floating gates during the write operation and the time needed to remove charge from the polysilicon floating gate during the erase operation. This is particularly problematic for “flash” EEPROMs, which have an architecture that allows the simultaneous erasure of many floating gate transistor memory cells. Since more charge must be removed from the many floating gates in a flash EEPROM, even longer erasure times are needed to accomplish this simultaneous erasure. There is a need in the art to obtain floating gate transistors allowing faster storage and erasure, such as millisecond erasure periods in flash EEPROMs.
Other problems result from the large erasure voltages that are typically applied to a control gate of the floating gate transistor in order to remove charge from the floating gate. These large erasure voltages are a consequence of the large tunneling barrier energy between the polysilicon floating gate and the underlying gate dielectric. The large erasure voltages can result in hole injection into the gate dielectric. This can cause erratic overerasure, damage to the gate dielectric, and introduction of trapping states in the gate dielectric. The high electric fields that result from the large erasure voltages can also result in reliability problems, leading to device failure. There is a need in the art to obtain floating gate transistors that allow the use of lower erasure voltages. There is a need in the art for floating gate transistors capable of operating at lower programming and erasure voltages and having improved reliability.
Halvis et al. (U.S. Pat. No. 5,369,040) discloses a charge-coupled device (CCD) photodetector which has transparent gate MOS imaging transistors fabricated from polysilicon with the addition of up to 50% carbon, and preferably about 10% carbon, which makes the gate material more transparent to the visible portion of the energy spectrum. The Halvis et al. patent is one example of a class of conventional CCD photodetectors that are directed to improving gate transmissivity to allow a greater portion of incident light in the visible spectrum to penetrate through the gate for absorption in the semiconductor substrate. However, the absorption of photons in the semiconductor substrate is limited to high energy photons exceeding a bandgap energy of the semiconductor substrate. There is a need in the art to detect lower energy photons independently of the semiconductor bandgap energy limitation. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, the above described needs are unresolved in the art of fabrication of light detection devices, FETs, and EEPROMs using CMOS processes.
References
Y. Yamaguchi et al., “Properties of Heteropitaxial 3C-SiC Films Grown by LPCVD”, 8th International Conference on Solid-State Sensors and Actuators and Eurosensors IX, Digest of Technical Papers, p. 3, vol. (934+1030+85), pp. 190-3, vol. 2, 1995;
M. Andrieux, et al., “Interface and Adhesion of PECVD SiC Based Films on Metals“, Le Vide Science, Technique et applications (France), No. 279, pp. 212-214, 1996;
F. Lanois, “Angle Etch Control for Silicon Power Devices”, Applied Physics Letters, vol. 69, No. 2, pp. 236-238, July 1996;
N. J. Dartnell, et al., “Reactive Ion Etching of Silicon Carbide” Vacuum, vol. 46, No. 4, pp. 349-355, 1955.
SUMMARY OF THE INVENTION
The present invention includes a transistor having a gate formed of a silicon carbide compound Si1−xCx, wherein x is selected at a predetermined value approximately between 0 and 1.0 to establish a desired value of a barrier energy between the gate and an adjacent insulator. The SiC gate is either electrically isolated (floating) or interconnected. In one embodiment, the gate is an electrically isolated floating gate, and the transistor further includes a control gate, separated from the floating gate by an intergate dielectric.
Another aspect of the invention provides a method of producing a transistor on a semiconductor substrate. Source and drain regions are formed, thereby defining a channel region between the source and drain regions. An insulating layer is formed on the channel region. A gate is formed on the insulating layer. The gate comprises a silicon carbide compound Si1−xCx. The SiC composition x is selected at a predetermined value approximately between 0 and 1.0. In one embodiment, the value of the SiC composition x is selected to establish the value of a barrier energy between the gate and the insulator.
Another aspect of the invention provides light detection. Charge is stored on a floating gate of a transistor. Incident light is received at the floating gate, thereby removing at least a portion of the stored charge from the floating gate by the photoelectric effect. A change in conductance between the transistor source and drain is detected. In one embodiment, the method of detecting light includes selecting at least one wavelength of the incident light to which the floating gate transistor is most sensitive. In another light detecting embodiment, the invention provides a transistor that includes a floating gate separated from a channel region by an insulator. The, floating gate is formed of a silicon carbide compound Si1−xCx. The SiC composition variable x is selected at a predetermined value approximately between 0 and 1.0 to establish the wavelength of incident light absorption to which the floating gate is sensitive. Charge is stored on the floating gate. Incident light is received at the floating gate, thereby removing at least a portion of the stored charge from the floating gate by the photoelectric effect. A change in conductance between the transistor source and drain is detected. Unlike conventional photodetectors, light is absorbed in the floating gate, thereby ejecting previously stored electrons therefrom. Also unlike conventional photodetectors, the light detector according to the present invention is actually more sensitive to lower energy photons as the semiconductor bandgap is increased.
In another embodiment, the transistor is used in a memory device that includes a plurality of memory cells. Each memory cell includes a transistor having a floating gate separated from the channel region by an insulator. The floating gate is formed of a silicon carbide compound Si1−xCx, wherein x is selected at a predetermined value approximately between 0 and 1.0 to establish a desired value of a barrier energy between the gate and the insulator.
In a flash electrically erasable and programmable read only memory (EEPROM) application, the SiC composition x is selected to provide the desired programming and erase voltage and time or data charge retention time. The lower barrier energy and increased tunneling probability of the SiC gate advantageously provides faster programming and erasure times for floating SiC gate transistors in flash EEPROM memories. This is particularly advantageous for “flash” EEPROMs in which many floating gate transistor memory cells must be erased simultaneously. Writing and erasure voltages are also advantageously reduced, minimizing the need for complicated and noisy on-chip charge pump circuits to generate the large erasure voltage. Lower erasure voltages also reduce hole injection into the gate dielectric that can cause erratic overerasure, damage to the gate dielectric, and introduction of trapping states in the gate dielectric. Reducing the erasure voltage also lowers the electric fields, minimizing reliability problems that can lead to device failure, and better accommodating downward scaling of device dimensions. Data charge retention time is decreased. Since conventional data charge retention times are longer than what is realistically needed, a shorter data charge retention time can be accommodated in order to obtain the benefits of a smaller barrier energy. The data charge retention time can be selected between seconds and millions of years by selecting the value of the SiC composition x, such as to obtain different memory functionality.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings, like numerals describe substantially similar components throughout the several views.
FIG. 1 is a cross-sectional view illustrating generally one embodiment of a FET provided by the invention, which includes an electrically isolated (floating) or interconnected gate including a silicon carbide (SiC) compound.
FIG. 2 is a graph illustrating generally barrier energy versus tunneling distance for SiC and conventional polysilicon gates.
FIGS. 3A, 3B, and 3C illustrate generally electron affinities of various SiC compositions and of silicon dioxide, and the resulting interfacial barrier energy therebetween.
FIG. 4 is a cross-sectional view illustrating generally a variable electron affinity floating SiC gate field-effect transistor (FET) provided by the invention.
FIG. 5 is a graph that illustrates generally the relationship between retention time and barrier energy, and also the relationship between erase time and barrier energy.
FIG. 6 illustrates generally a flash EEPROM memory having memory cells that include an SiC gate transistor according to the present invention.
FIG. 7 is a cross-sectional schematic diagram of the floating gate transistor that illustrates generally its application according to the present invention as a light detector or imaging device.
FIG. 8 is a cross-sectional schematic diagram that illustrates generally how incident light is detected by the absorption of photons by the floating gate.
FIG. 9 is a graph that illustrates generally, by way of example, the SiC absorption coefficient as a function of wavelength and photon energy.
FIG. 10 is a graph illustrating generally barrier height versus tunneling distance, and further illustrating the absorption of light energy by the floating gate.
FIG. 11 is a graph illustrating generally barrier height versus tunneling distance, and distinguishing photoelectric absorption of incident light in the SiC floating gate from valence-to-conduction band electron transitions.
FIGS. 12A, 12B, 12C, 12D, 12E, 12F, and 12G illustrate generally examples of process steps for fabricating n-channel and p-channel SiC gate FETs according to the present invention, including the fabrication of SiC floating gate transistors.
DETAILED DESCRIPTION OF THE INVENTION
In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. The embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural and electrical changes may be made without departing from the scope of the present invention. The terms wafer and substrate used in the following description include any semiconductor-based structure having an exposed surface with which to form the integrated circuit structure of the invention. Wafer and substrate are used interchangeably to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.
The present invention includes a field-effect transistor (FET) having a gate that is formed of at least partially crystalline (e.g., monocrystalline, polycrystalline, microcrystalline, or nanocrystalline) diamond-like silicon carbide (SiC) material, which includes any material that incorporates both silicon and carbon into the gate region of a FET. The SiC gate FET includes characteristics such as, for example, a lower electron affinity than a conventional polycrystalline silicon (polysilicon) gate FET. Another aspect of the invention provides a tailored SiC material composition for use in conjunction with a particular gate dielectric, or for particular applications, such as data storage (memory) and imaging.
FIG. 1 is a cross-sectional view illustrating generally, by way of example, one embodiment of a n-channel FET provided by the invention. The invention is understood to also include a p-channel FET embodiment. The n-channel FET includes a source 102, a drain 104, and a gate 106. A gate dielectric, such as thin oxide layer 118 or other suitable insulator, is interposed between gate 106 and substrate 108. In one embodiment, source 102 and drain 104 are fabricated by forming highly doped (n+) regions in a lightly doped (p−) silicon semiconductor substrate 108. In another embodiment, substrate 108 includes a thin semiconductor surface layer formed on an underlying insulating portion, such as in a semiconductor-on-insulator (SOI) or other thin film transistor technology. Source 102 and drain 104 are separated by a predetermined length in which a channel region 110 is formed.
According to one aspect of the invention, gate 106 is formed of silicon carbide (SiC) material, which includes any material that incorporates both silicon and carbon into gate 106. The silicon carbide material forming gate 106 is described more generally as Si1−xCx, where x is a composition variable that defines the SiC material composition. According to another aspect of the invention, the SiC composition x is selected at a predetermined value that establishes the value of a barrier energy (also referred to as a barrier potential, potential barrier, tunneling barrier, interface barrier, or barrier) between gate 106 and thin oxide layer 118 (or other gate dielectric). For example, in one embodiment, the SiC composition is approximately stoichiometric, i.e., ≈0.5. However, other embodiments of the invention include less carbon (i.e., x<0.5) or more carbon (i.e., x>0.5). For example, but not by way of limitation, one embodiment of the SiC gate material is illustrated by 0.1<x<0.5. Another example embodiment is illustrated by way of example, but not by way of limitation, by 0.4<x<0.6. Still another embodiment is illustrated by way of example, but not by way of limitation, by 0.5<x<1.0. As described below, the SiC composition x is selected as a predetermined value in order to tailor the barrier for particular applications. In one embodiment, the SiC composition x is uniform over a particular integrated circuit die. In another embodiment, the SiC composition x is differently selected at different locations on the integrated circuit die, such as by additional masking or processing steps, to obtain different device characteristics on the same integrated circuit die.
In one embodiment, an insulating layer, such as silicon dioxide (oxide) 114 or other insulating layer, is formed by chemical vapor deposition (CVD). Oxide 114 isolates gate 106 from other layers, such as layer 112. In another embodiment, gate 106 is oxidized to form at least a portion of oxide 114 isolating gate 106 from other layers such as layer 112. In one embodiment, for example, layer 112 is a polysilicon or other control gate in a floating gate transistor. According to techniques of the present invention, the floating gate transistor is used in an electrically erasable and programmable read-only memory (EEPROM) memory cell, such as a flash EEPROM, or in a floating gate transistor photodetector or imaging device, as described below. In these embodiments, gate 106 is floating (electrically isolated) for charge storage thereupon. The present invention offers considerable advantages to the known EEPROM techniques used for charge storage on floating gate 106. In another embodiment, for example, layer 112 is a metal or other conductive interconnection line that is located above gate 106.
The upper layers, such as layer 112 are covered with a layer 116 of a suitable insulating material in the conventional manner, such as for isolating and protecting the physical integrity of the underlying features. Gate 106 is isolated from channel 110 by an insulating layer such as thin oxide layer 118, or any other suitable dielectric material. In one embodiment, thin oxide layer 118 is a gate oxide layer that can be approximately 100 angstroms (Å) thick, such as for conventional FET operation. In another embodiment, such as in a floating gate transistor, thin oxide layer 118 is a tunnel oxide material that can be approximately 50-100 Å thick.
The SiC gate 106 has particular advantages over polysilicon gates used in floating gate and conventional FETs fabricated using a conventional complementary metal-oxide-semiconductor (CMOS) process due to different characteristics of the SiC material. For example, stoichiometric SiC (x≈0.5) is a wide bandgap semiconductor material with a bandgap energy of about 2.1 eV, in contrast to silicon (monocrystalline or polycrystalline), which has a bandgap energy of about 1.2 eV. Stoichiometric SiC has an electron affinity of about 3.7 to 3.8 eV, while silicon has an electron affinity of about 4.2 eV.
The smaller electron affinity of the SiC gate 106 material reduces the barrier energy at the interface between gate 106 and thin oxide layer 118. In an embodiment in which thin oxide layer 118 is a tunnel oxide in a floating gate transistor EEPROM memory cell, the lower electron affinity of SiC reduces the tunneling distance and increases the tunneling probability. This speeds the write and erase operations of storing and removing charge to and from floating gate 106. This is particularly advantageous for “flash” EEPROMs in which many floating gate transistor memory cells must be erased simultaneously. The large charge that must be transported by Fowler-Nordheim tunneling during the erasure of a flash EEPROM typically results in relatively long erasure times. By reducing the tunneling distance and increasing the tunneling probability, the SiC gate 106 reduces erasure times in flash EEPROMs.
According to one aspect of the present invention, the exact value of the SiC composition x is selected to obtain the desired barrier potential for the particular application. The predetermined value the SiC composition x establishes the particular electron affinity, χ, such as between that of stoichiometric SiC (about 3.7 to 3.8 eV) and a value χ<0 eV. As a result, the barrier energy is further decreased from that of stoichiometric SiC by the exact amount desired. This speeds storage and removal of charge to and from the floating gate 106 during write and erase operations.
Lowering the barrier potential also decreases the data charge retention time of the charge stored on the floating gate 106. Conventional polysilicon floating gates have a data charge retention time estimated in the millions of years at a temperature of 85 degrees C. Since such long data charge retention times are longer than what is realistically needed, a shorter data charge retention time can be accommodated in order to obtain the benefits of a smaller barrier energy. According to one aspect of the present invention, the SiC composition x is selected to establish the particular data charge retention time. For example, the data charge retention time can be selected between seconds and millions of years.
FIG. 1 illustrates generally, by way of example, a complementary metal-oxide-semiconductor (CMOS) compatible n-channel FET that includes an SiC gate 106, which may be floating or electrically interconnected. In one embodiment, for example, the FET can be formed on substrate 108 using an n-well CMOS process for monolithic CMOS fabrication of n-channel and p-channel FETs on a common substrate. The invention includes both n-channel and p-channel FETs that have a polycrystalline or microcrystalline SiC gate 106. Thus, with appropriate doping, the FET of FIG. 1 can be a p-channel FET. The p-channel and n-channel SiC gate FETs are useful for any application in which conventionally formed polysilicon gate FETs are used, including both electrically driven and floating gate applications.
FIG. 2 illustrates generally how the smaller SiC electron affinity provides a smaller barrier energy than a conventional polysilicon gate. The smaller SiC barrier energy reduces the energy to which the electrons must be excited to be stored on the SiC gate 106 by thermionic emission. The smaller barrier energy also reduces the distance that electrons stored on the gate have to traverse, such as by Fowler-Nordheim tunneling, to be stored upon or removed from the SiC gate 106. The reduced tunneling distance allows easier charge transfer, such as during writing or erasing data in a floating gate transistor in a flash EEPROM memory cell. In FIG. 2, “do” represents the tunneling distance of a typical polysilicon floating gate transistor due to the barrier height represented by the dashed line “OLD”. The tunneling distance “dn” corresponds to a SiC gate and its smaller barrier height represented by the dashed line “NEW”. Even a small reduction in the tunneling distance results in a large increase in the tunneling probability, because the tunneling probability is an exponential function of the reciprocal of the tunneling distance. The increased tunneling probability of the SiC gate 106 advantageously provides faster programming and erasure times for floating SiC gate transistors in flash EEPROM memories. The smaller bandgap of floating SiC gate transistors have a smaller turn-on threshold voltage magnitude, thereby also allowing operation of such flash EEPROM memories at lower power supply voltages.
FIGS. 3A-3C illustrate generally by way of example, but not by way of limitation, different selections of the predetermined value of the SiC composition x. Differently selected values of the SiC composition x provide different resulting barrier energies at the interface between gate 106 and the adjacent thin oxide layer 118 (or other gate or tunneling dielectric). FIGS. 3A-3C illustrate, by way of example, but not by way of limitation, the use of a silicon dioxide gate insulator such as thin oxide layer 118. However, the invention includes the use of any other gate insulator materials in combination with the SiC gate 106.
In FIGS. 3A-3C, the electron affinities, χ, of each of the thin oxide layer 118 and SiC gate 106 are measured with respect to the vacuum level 300. In the thin oxide layer 118, the electron affinity, χ, is defined by the difference between the oxide conduction band 302 and the vacuum level 300. In the SiC gate 106, the electron affinity, χ, is defined by the difference between the semiconductor conduction band edge 305 and the vacuum level 300. The barrier energy at the interface between thin oxide layer 118 and SiC gate 106 is illustrated by the difference between their respective electron affinities, χ.
In FIG. 3A, the SiC composition is selected at x≈0, which is an extreme limit in which the SiC gate 106 material composition is approximately pure silicon (e.g., polycrystalline or microcrystalline). As seen in FIG. 3A, the resulting electron affinity in the gate 106 material is χ≈4.2 eV. The electron affinity in thin oxide layer 118 is χ≈0.9 eV. The resulting barrier energy is approximately 3.3 eV. In a memory application using a floating gate 106, the 3.3 eV barrier energy results in long data charge retention times (estimated in millions of years at a temperature of 85 degrees C.) together with large erasure voltages and long write and erase times. In an imaging application using a floating gate 106, the 3.3 eV barrier energy requires relatively high energy photons (i.e., high frequency and short wavelength) to eject stored electrons from the floating gate 106.
In FIG. 3B, the SiC composition is selected at x≈0.5, for which the SiC gate 106 material is approximately stoichiometric SiC. As seen in FIG. 3B, the resulting electron affinity in the gate 106 material is χ≈3.7 eV. The electron affinity in thin oxide layer 118 is χ≈0.9 eV. The resulting barrier energy is approximately 2.8 eV. In a memory application using a floating gate 106, the 2.8 eV barrier energy results in shorter charge retention times than are obtained than in the case described with respect to FIG. 3A, together with smaller erasure voltages and shorter write and erase times. In an imaging application using a floating gate 106, the 2.8 eV barrier energy needs less photon energy (i.e., lower frequency and longer wavelength) to eject electrons from the floating gate 106 than in the case described with respect to FIG. 3A.
In FIG. 3C, the SiC composition is selected at x≈1, which is an extreme limit in which the material is substantially pure carbon (i.e., diamond). As seen in FIG. 3C, the resulting electron affinity in the gate material is χ≈−0.4 eV. The electron affinity in the silicon dioxide insulator 118 is χ≈0.9 eV. The resulting barrier energy is approximately −1.3 eV. In this case, electrons will not stay in the conduction band of the diamond gate 106 material, but will instead move into the thin oxide layer 118.
Thus, the barrier energy at the interface between thin oxide layer 118 and SiC gate 106 is adjusted by tuning the SiC composition x. The SiC gate material compounds can be doped p-type or n-type, either during formation or by a subsequent doping step. However, the SiC films are quite conductive even when intrinsic. In floating gate applications, the SiC films need not be very conductive since they are not used for interconnection wiring. An SiC floating gate 106 need only allow for redistribution of carriers in the floating gate 106. Microcrystalline SiC compounds have a smaller electron affinity than polycrystalline SiC compounds. In one embodiment of the present invention, the barrier potential is adjusted by selecting between microcrystalline and polycrystalline SiC compounds for the gate 106 material.
Floating Gate Memory Device
FIG. 4 is a cross-sectional view of a transistor, similar to that of FIG. 1, illustrating generally a floating gate transistor embodiment of the invention, such as for use as a nonvolatile memory cell in a flash EEPROM. In one embodiment, floating gate 106 is a polycrystalline or microcrystalline SiC compound for which 0.5<x<1.0.
By using polycrystalline or microcrystalline SiC for floating gate 106, a lower barrier energy is obtained at the interface between gate 106 and thin oxide layer 118. The exact barrier energy is established by selecting the predetermined value of the SiC composition x. The lower barrier energy provides a larger tunneling probability during write and erase operations. Write and erasure voltages and times are reduced. Secondary problems that are normally associated with erasure of charge stored on polysilicon gates, such as electron trap creation and hole injection, are correspondingly reduced along with the erasure voltage.
In one embodiment, the exact value of the SiC composition x is selected to establish a barrier energy that is large enough to prevent electrons from being thermally excited over the barrier at high operating temperatures, such as at a temperature of 85° C., as this could allow the stored data charges to leak from the floating gate over a long period of time. The high barrier energy of a polysilicon floating gate material provides a longer than realistically needed data charge retention time that is estimated in millions of years. The SiC composition x is selected to obtain a lower barrier energy, providing data retention times that are more suited to the particular application. In one embodiment of the present invention, the SiC composition x is selected to obtain typical data charge retention times between seconds and millions of years.
In one embodiment, the invention includes operation of a SiC floating gate transistor memory device. Floating gate 106 can be programmed, by way of example, but not by way of limitation, by providing about 12 volts to control gate 112, and providing about 6 volts to drain 104, and providing about 0 volts to source 102. This creates an inversion layer in channel region 110, in which electrons are accelerated from source 102 toward drain 104, acquiring substantial kinetic energy. High energy “hot electrons’ are injected through thin oxide layer 118 onto the polycrystalline or microcrystalline SiC floating gate 106. Floating gate 106 accumulates the hot electrons as stored data charges.
The change in the charge stored on floating gate 106 changes the threshold voltage of the n-channel floating gate FET of FIG. 4. When control gate 112 is driven to a read voltage during a read operation, the change in charge stored on floating gate 106 results in a change in current between drain 104 and source 102. Thus, detection of the change in charge stored on floating gate 106 by sensing drain-source current conductance advantageously uses the appreciable transconductance gain of the floating gate FET of FIG. 4. Either analog or digital data can be stored as charge on floating gate 106 and read back as a conductance between drain region 104 and source region 102.
The erase time for the memory cell is determined by the height of the barrier between floating gate 106 and thin oxide layer 118. A lower barrier energy results in a shorter tunneling distance, as described with respect to FIG. 2. This, in turn, results in a faster erase operation, lower erasure voltages, or both faster erase operation and lower erasure voltages. Short erase times are normally particularly desirable in flash memories, in which many memory cells must be simultaneously erased. However, a lower barrier energy also means a shorter data charge retention time due to thermal excitation of electrons over or tunneling of electrons through the barrier.
According to the invention, the barrier energy is varied by changing the SiC composition x. By selecting the predetermined value of the SiC composition x, the data charge retention time can be established at a value that is, for example, between seconds and millions of years. By changing the SiC composition x, a flash memory device that incorporates the SiC floating gate transistor provides a data charge retention time that is tailored to the particular application.
For example, by setting the SiC composition at about 0.75<x<1.0, the flash memory device can be made to emulate a dynamic random access memory (DRAM), with data charge retention times on the order of seconds. On the other hand, for example, by setting the SiC composition at about 0.5<x<0.75, the flash memory device can be made to emulate a hard disk drive, by providing a data charge retention time on the order of years. According to one aspect of the present invention, one memory device provides different memory functions by selecting the SiC composition x. In one embodiment, floating gate transistors having different SiC compositions x are provided on the same integrated circuit, thereby providing differently functioning memory cells on the same integrated circuit.
FIG. 5 is a conceptual diagram, using rough order of magnitude estimates, that illustrates generally how erase and retention times vary with the barrier energy for a particular value of erasure voltage at a particular temperature of 85° C. The probability of thermal excitation and emission over or tunneling through the barrier is an exponential function of the barrier energy. A lower barrier provides exponentially shorter erase and retention times. The particular memory application requirements determine the needed memory retention time, whether seconds or years. From this memory retention time, the barrier energy required and the erase time for a particular voltage can be determined using an engineering graph similar to that of FIG. 5. Thus, the SiC composition x is selected to provide a retention time on the order of seconds or years, depending upon the function required for the memory device. According to one aspect of the present invention, for example, the memory device can emulate or replace DRAMs or hard disk drives by selecting the SiC composition x to establish the appropriate data charge retention time.
FIG. 6 is a simplified block diagram illustrating generally one embodiment of a memory 600 system, according to one aspect of the present invention, in which SiC gate FETs are incorporated. In one embodiment, memory 600 is a flash EEPROM, and the SiC gate FETs are floating gate transistors that are used for nonvolatile storage of data as charge on the SiC floating gates. However, the SiC gate FETs can have electrically interconnected gates, and can be used in other types of memory systems, including SDRAM, SLDRAM and RDRAM devices, or in programmable logic arrays (PLAs), or in any other application in which transistors are used.
FIG. 6 illustrates, by way of example, but not by way of limitation, a flash EEPROM memory 600 comprising a memory array 602 of multiple memory cells. Row decoder 604 and column decoder 606 decode addresses provided on address lines 608 to access addressed SiC gate floating gate transistors in the memory cells in memory array 602. Command and control circuitry 610 controls the operation of memory 600 in response to control signals received on control lines 616 from a processor 601 or other memory controller during read, write, and erase operations. Voltage control 614 is provided to apply appropriate voltages to the memory cells during programming and erasing operations. It will be appreciated by those skilled in the art that the memory of FIG. 6 has been simplified for the purpose of illustrating the present invention and is not intended to be a complete description of a flash EEPROM memory.
Floating Gate Imaging Device
According to another aspect of the present invention, the SiC floating gate transistor of FIG. 4 is used in light detection applications, such as a photodetector or imaging device. In this embodiment of the invention, light is detected by the absorption of photons by the SiC floating gate 106. This is distinguishable from other types of imaging devices, such as sensors using a charge-coupled device (CCD) or a photodiode detector, in which light is absorbed in the semiconductor substrate, thereby producing charge carriers that are detected.
According to one embodiment of the present invention, charge is stored on the SiC floating gate 106, such as by known EEPROM charge storage techniques. The imaging device is exposed to incident light. Incident photons having enough energy to eject an electron by photoelectric emission from floating gate 106 are detected by a resulting change in drain-source conductance of the imaging device. Thus, the light detector of the present invention advantageously utilizes the transconductance gain of the floating gate transistor. In one embodiment of the invention, the wavelength to which the light detector is sensitive is established by selecting the SiC composition x of floating gate 106.
FIG. 7 is a cross-sectional schematic diagram of the floating gate transistor that illustrates generally its application according to the present invention as a light detector or imaging device. In FIG. 7, floating gate 106 is charged by the injection of hot electrons 700 through thin oxide layer 118 under the SiC floating gate 106. This change in charge on floating gate 106 changes the threshold voltage of the n-channel floating gate FET. As a result, when control gate 112 is driven to a read voltage during a read operation, a large change in drain-source current is obtained through the transconductance gain of the floating gate transistor.
FIG. 8 is a cross-sectional schematic diagram that illustrates generally how incident light 800 is detected by the absorption of photons by floating gate 106. The photons must have enough energy to cause electrons 700 stored on floating gate 106 to overcome the barrier at the interface between floating gate 106 and thin oxide layer 118 and be ejected from floating gate 106 back into the semiconductor or SOI substrate by the photoelectric effect. A small electric field in thin oxide layer 118, such as results from the presence of electrons 700 stored on floating gate 106, assists in ejecting the electrons 700 toward substrate 108. Detection or imaging of visible wavelengths of incident light 800 requires a low electron affinity floating gate 106. The present invention allows the electron affinity of floating gate 106 to be tailored by selecting the particular value of the SiC composition of floating gate 106.
FIG. 9 is a graph that illustrates generally, by way of example, the SiC absorption coefficient as a function of wavelength and photon energy. Several values of the SiC composition x are illustrated, where 0<x<1.0. For example, by setting the SiC composition x≈0.5 (i.e., approximately stoichiometric SiC), the resulting light absorption is illustrated generally by line 910. In another example, by setting the SiC composition x≈0 (i.e., approximately pure polycrystalline or microcrystalline Si), the resulting light absorption is illustrated generally by line 912. In yet another example, by setting the SiC composition described approximately by 0.5<x<1.0, the resulting light absorption is illustrated generally by line 914.
FIG. 10 further illustrates the absorption of light energy by floating gate 106. In FIG. 10, the incident photons have sufficient energy to allow electrons 700 stored on floating gate 106 to overcome the “new” barrier 1000 such that they are emitted from floating gate 106 back toward the semiconductor or SOI substrate 108, thereby discharging floating gate 106. “Old” barrier 1005, which represents a Si—SiO2 interface, is higher than “new” barrier 1000 of the SiC—SiO2 interface. As a result, a light detector having an SiC floating gate 106 is sensitive to lower energy photons than a light detector having an Si floating gate.
In one embodiment, SiC floating gate 106 is doped n-type to maximize the number of conduction band electrons 700 in floating gate 106 and the absorption of incident light. Visible light has a photon energy of about 2 eV. For detection of visible light, the barrier energy at the interface between floating gate 106 and thin oxide layer 118 should be less than or equal to about 2 eV. However, most common gate materials have larger barrier energies with an adjacent silicon dioxide insulator. For example, a conventional polysilicon floating gate 106 results in a barrier energy of about 3.3 eV.
According to one aspect of the present invention, polycrystalline or microcrystalline SiC is used as the material for floating gate 106. The SiC composition x is selected for sensitivity to particular wavelengths of light, and the barrier energy is established accordingly. For example, in one embodiment, the SiC composition x is selected in the range 0.5<x<1.0 such that barrier energy is less than or equal to about 2 eV. As a result, the floating gate transistor light detector is sensitive to visible light. According to another aspect of the invention, the floating gate transistor light detector is made sensitive to different portions of the light spectrum by adjusting the barrier energy through the selection of the SiC composition x. The SiC composition x can also be different for different floating gate transistors on the same integrated circuit in order to yield different sensitivities to different wavelengths of light.
FIG. 11 illustrates generally how the above-described photoelectric absorption of incident light in the SiC floating gate 106 is distinguishable from, and independent of, valence-to-conduction band electron transitions, which is the common photon absorption mechanism of most diode or CCD photodetectors or imaging devices. Conventional photon absorption is illustrated by the band-to-band electron energy transition 1100. Photon absorption according to the present invention is illustrated by the emission 1105 of a conduction band electron 700 from floating gate 106 over the barrier 1000 between the floating gate semiconductor conduction band 1110 and oxide conduction band 1115.
The semiconductor bandgap is defined by the energy difference between semiconductor conduction band 1110 and semiconductor valence band 1120. Exciting an electron from the valence band 1120 low energy state to a conduction band 1110 high energy state requires absorption of an incident photon of energy exceeding the bandgap of the semiconductor material. For diamond-like SiC compounds, these band-to-band transitions occur only at very high photon energies, such as for ultraviolet light. By contrast, photoelectric emission 1105 of electrons from floating gate 106 only requires that the incident photon energy exceed the barrier 1000 between floating gate 106 and thin oxide layer 118. Since the present invention allows the barrier 1000 energy to be less than the 2 eV energy of a visible photon by an appropriate selection of the SiC composition x, and even allows a negative barrier 1000 energy, a wide spectrum of light detection is obtained.
In conventional photodetectors, only high energy photons are detected as the bandgap is increased (i.e., as the bandgap becomes larger, first red, then blue, and finally ultraviolet light is required for band-to-band photon absorption). According to the present invention, a larger bandgap typically results in a smaller barrier 1000 energy, thereby allowing detection of even lower energy photons as the bandgap is increased (i.e., as the bandgap becomes larger, the detector becomes sensitive not only to ultraviolet, but to blue, then red, and finally to infrared wavelengths). As a result, the present invention can be used for visible and infrared light detection and imaging, including camera-like operations, and can employ lenses, shutters, or other such known imaging techniques.
FIG. 11 illustrates generally, by way of example, but not by way of limitation, the absorption of red light with photon energies of around 2 eV in the SiC floating gate 106. In one embodiment, the SiC composition x is selected such that the barrier 1000 energy between SiC floating gate 106 and thin oxide layer 118 is less than (or much less than) 2 eV, while the bandgap for the SiC floating gate 106 is much higher than 2 eV. In this embodiment, incident photons generate negligible electron-hole pairs or valence-to-conduction band transitions in floating gate 106. Instead, absorption of photons is substantially entirely the result of photoelectric emission of electrons from floating gate 106. While the quantum efficiency associated with the photoelectric effect can be low (e.g., less than one electron emitted per one hundred photons) the floating gate transistor offers appreciable transconductance gain. Emitting a single electron from the floating gate changes the number of electrons flowing out of the drain 104 by thousands. By adjusting the SiC composition x of floating gate 106, the floating gate detector device is adjusted for optimum response over almost the entire optical spectrum, from infrared through visible light to ultraviolet. In a further embodiment of the invention, sensitivity is improved by doping the SiC floating gate 106 n-type, to increase the number of conduction band electrons stored on floating gate 106.
Process
FIGS. 12A-12G illustrate generally examples of CMOS-compatible process steps for fabricating n-channel and p-channel SiC gate FETs according to the present invention, including the fabrication of SiC floating gate transistors. The transistors can be produced on a silicon or other semiconductor substrate, an SOI substrate, or any other suitable substrate 108. Only the process steps that differ from conventional CMOS process technology are described in detail.
In FIG. 12A, substrate 108 undergoes conventional CMOS processing up to the formation of the gate structure. For example, field oxide 1200 is formed for defining active regions 1202. In a bulk semiconductor embodiment, well regions are formed, such as for carrying p-channel transistors.
In FIG. 12B, an insulating layer, such as thin oxide layer 118 or other suitable insulator, is formed on substrate 108, such as by dry thermal oxidation, including over the portions of the active regions 1202 in which transistors will be fabricated. In one embodiment, thin oxide layer 118 is a gate oxide layer that can be approximately 100 angstroms (Å) thick. In another embodiment, such as in a floating gate transistor, thin oxide layer 118 is a tunnel oxide material that can be approximately 50-100 Å thick.
In FIG. 12C, a thin film 1206 of conductively doped polycrystalline or microcrystalline SiC is then deposited, such as by chemical vapor deposition (CVD) over the entire wafer, including over thin oxide layer 118. The SiC composition x of film 1206 is differently selected according to the particular barrier energy desired at the interface between the gate 106 and adjacent thin oxide layer 118, as described above. Microcrystalline SiC compounds may be selected for their lower electron affinity than polycrystalline SiC compounds in order to obtain the desired barrier energy.
The SiC film 1206 can be in situ doped during deposition, or doped during a subsequent ion-implantation step. The conductive doping can be n-type or p-type. In one light detecting embodiment, the SiC film 1206 is conductively doped n-type for enhanced photoelectric emission of electrons from floating gate 106 in response to incident light, as described above. In another embodiment, the SiC film 1206 is conductively doped p-type using a boron dopant, which advantageously diffuses from the SiC gate 106 less easily than from a polysilicon gate during subsequent thermal processing steps.
In one embodiment, for example, SiC film 1206 is deposited using low-pressure chemical vapor deposition (LPCVD), providing the structure illustrated in FIG. 12C. The LPCVD process uses either a hot-wall reactor or a cold-wall reactor with a reactive gas, such as a mixture of Si(CH3)4 and Ar. However, SiC film 1206 can be deposited using other techniques such as, for example, enhanced CVD techniques known to those skilled in the art including low pressure rapid thermal chemical vapor deposition (LP-RTCVD), or by decomposition of hexamethyl disalene using ArF excimer laser irradiation, or by low temperature molecular beam epitaxy (MBE). Other examples of forming SiC film 1206 include reactive magnetron sputtering, DC plasma discharge, ion-beam assisted deposition, ion-beam synthesis of amorphous SiC films, laser crystallization of amorphous SiC, laser reactive ablation deposition, and epitaxial growth by vacuum anneal. The conductivity of the SiC film 1206 can be changed by ion implantation during subsequent process steps, such as during the self-aligned formation of source/drain regions for the n-channel and p-channel FETs.
In FIG. 12D, SiC film 1206 is patterned and etched, together with thin oxide layer 118, to form SiC gate 106. SiC film 1206 is patterned using standard techniques and is etched using plasma etching, reactive ion etching (RIE) or a combination of these or other suitable methods. For example, SiC film 1206 can be etched by RIE in a distributed cyclotron resonance reactor using a SF6/O2 gas mixture using SiO2 as a mask with a selectivity of 6.5. Alternatively, SiC film 1206 can be etched by RE using the mixture SF6 and O2 and F2/Ar/O2. The etch rate of SiC film 1206 can be significantly increased by using magnetron enhanced RIE.
FIG. 12E illustrates one embodiment in which SiC gate 106 is oxidized after formation, providing a thin layer 1210 represented by the dashed line in FIG. 12E. SiC gate 106 can be oxidized, for example, by plasma oxidation similar to reoxidation of polycrystalline silicon. During the oxidation process, the carbon is oxidized as carbon monoxide or carbon dioxide and vaporizes, leaving the thin layer 1210 of silicon oxide over SiC gate 106. In one embodiment, thin layer 1210 is used as, or as a portion of, an intergate dielectric between floating and control gates in a floating gate transistor embodiment of the present invention.
FIG. 12F illustrates generally a self-aligned embodiment of the formation of n-channel FET n+ source region 102 and drain region 104. For a p-channel FET, p+ source drain regions can be similarly formed. The doping of SiC gate 106 can be changed by ion implantation, such as during the formation of n-channel FET or p-channel FET source/drain regions, or subsequently thereto. For example, a p-type SiC film 1206 can be deposited, and its doping then changed to n+ by leaving SiC gate 106 unmasked during the formation of the n+ source region 102 and drain region 104 for the n-channel FET.
FIG. 12G illustrates generally the formation of an insulating layer, such as oxide 114 or other suitable insulator, after formation of n-channel FET source region 102 and drain region 104. In one embodiment, oxide 114 is deposited over the upper surface of the integrated circuit structure using a standard CVD process. Oxide 114 isolates SiC gate 106 from other gates such as, for example, an overlying or adjacent control gate layer 112 where SiC gate 106 is a floating gate in a floating gate transistor. Oxide 114 also isolates SiC gate 106 from any other conductive layer 112, such as polysilicon layers, gates, metal lines, etc., that are fabricated above and over SiC gate 106 during subsequent process steps.
Conclusion
Thus, the invention includes a CMOS-compatible FET having a low electron affinity SiC gate that is either electrically isolated (floating) or interconnected. The SiC composition x is selected to provide the desired barrier at the SiC—SiO2 interface, such as 0.5<x<1.0. In a flash EEPROM application, the SiC composition x is selected to provide the desired programming and erase voltage and time or data charge retention time. In an imaging application, the SiC composition x is selected to provide sensitivity to the desired wavelength of light. Unlike conventional photodetectors, light is absorbed in the floating gate, thereby ejecting previously stored electrons therefrom. Also unlike conventional photodetectors, the light detector according to the present invention is actually more sensitive to lower energy photons as the semiconductor bandgap is increased.
Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.

Claims (27)

What is claimed is:
1. A method of detecting light, the method comprising:
storing charge on a floating gate of a transistor, the floating gate comprising a silicon carbide compound Si1−xCx, wherein x is between 0.5 and 1.0, and the transistor further comprising a source and a drain in a substrate;
receiving incident light on the floating gate, thereby removing at least a portion of the stored charge from the floating gate by the photoelectric effect; and
detecting a change in conductance in the substrate between the source and the drain.
2. The method of claim 1, further comprising selecting at least one wavelength of the incident light for which the floating gate is sensitive.
3. The method of claim 1 wherein:
storing charge further comprises injecting hot electrons from a channel in a p-type silicon substrate between an n+-type source and an n+-type drain in the substrate through a layer of silicon dioxide into the floating gate;
receiving incident light on the floating gate further comprises receiving incident light on the floating gate to eject one or more electrons from the floating gate into the substrate by photoelectric emission, the floating gate comprising the silicon carbide compound Si1−xCx that is n-type doped and either polycrystalline or microcrystalline; and
detecting a change in conductance in the substrate further comprises driving a read voltage to a control gate separated from the floating gate by an intergate dielectric and sensing a current in the channel in the substrate.
4. A method of detecting light comprising:
adding charge to a gate comprising a silicon carbide compound Si1−xCx, wherein x is between 0.5 and 1.0;
exposing the gate to incident light; and
detecting a change in conductance in a substrate separated from the gate by an insulator.
5. The method of claim 4 wherein:
adding charge further comprises injecting hot electrons from a channel region between an n+-type source region and an n+-type drain region in a p-type silicon substrate through a layer of silicon dioxide into a floating gate, the floating gate comprising the silicon carbide compound Si1−xCx that is n-type doped and either polycrystalline or microcrystalline;
exposing the gate to incident light further comprises exposing the floating gate to the incident light to eject one or more electrons from the floating gate into the substrate by photoelectric emission;
detecting a change in conductance further comprises driving a read voltage to a control gate separated from the floating gate by an intergate dielectric and sensing a current in the channel region in the substrate.
6. A method of detecting light comprising:
adding charge to a gate comprising a silicon carbide compound Si1−xCx, wherein x is between 0.75 and 1.0;
exposing the gate to incident light; and
detecting a change in conductance in a substrate separated from the gate by an insulator.
7. The method of claim 6 wherein:
adding charge further comprises injecting hot electrons from a channel region between an n+-type source region and an n+-type drain region in a p-type silicon substrate through a layer of silicon dioxide into a floating gate, the floating gate comprising the silicon carbide compound Si1−xCx that is n-type doped and either polycrystalline or microcrystalline;
exposing the gate to incident light further comprises exposing the floating gate to the incident light to eject one or more electrons from the floating gate into the substrate by photoelectric emission;
detecting a change in conductance further comprises driving a read voltage to a control gate separated from the floating gate by an intergate dielectric and sensing a current in the channel region in the substrate.
8. A method of detecting light comprising:
adding charge to a gate comprising a silicon carbide compound Si1−xCx, wherein x is between 0.5 and 0.75;
exposing the gate to incident light; and
detecting a change in conductance in a substrate separated from the gate by an insulator.
9. The method of claim 8 wherein:
adding charge further comprises injecting hot electrons from a channel region between an n+-type source region and an n+-type drain region in a p-type silicon substrate through a layer of silicon dioxide into a floating gate, the floating gate comprising the silicon carbide compound Si1−xCx that is n-type doped and either polycrystalline or microcrystalline;
exposing the gate to incident light further comprises exposing the floating gate to the incident light to eject one or more electrons from the floating gate into the substrate by photoelectric emission;
detecting a change in conductance further comprises driving a read voltage to a control gate separated from the floating gate by an intergate dielectric and sensing a current in the channel region in the substrate.
10. A method of detecting light comprising:
adding charge to a floating gate comprising a silicon carbide compound Si1−xCx, wherein x is between 0.5 and 1.0;
exposing the floating gate to incident light;
driving a read voltage to a control gate separated from the floating gate by an intergate dielectric; and
sensing a current in a channel region between a source region and a drain region in a substrate separated from the floating gate by an insulator to detect a change in conductance in the channel region.
11. The method of claim 10 wherein:
adding charge further comprises injecting hot electrons from the channel region between an n+-type source region and an n+-type drain region in a p-type silicon substrate through a layer of silicon dioxide into the floating gate, the floating gate comprising the silicon carbide compound Si1−xCx that is n-type doped and either polycrystalline or microcrystalline;
exposing the floating gate to incident light further comprises exposing the floating gate to the incident light to eject one or more electrons from the floating gate into the substrate by photoelectric emission; and
driving a read voltage further comprises driving the read voltage to a polysilicon control gate separated from the floating gate by silicon dioxide.
12. A method of detecting light comprising:
adding charge to a floating gate comprising a silicon carbide compound Si1−xCx, wherein x is between 0.75 and 1.0;
exposing the floating gate to incident light;
driving a read voltage to a control gate separated from the floating gate by an intergate dielectric; and
sensing a current in a channel region between a source region and a drain region in a substrate separated from the floating gate by an insulator to detect a change in conductance in the channel region.
13. The method of claim 12 wherein:
adding charge further comprises injecting hot electrons from the channel region between an n+-type source region and an n+-type drain region in a p-type silicon substrate through a layer of silicon dioxide into the floating gate, the floating gate comprising the silicon carbide compound Si1−xCx that is n-type doped and either polycrystalline or microcrystalline;
exposing the floating gate to incident light further comprises exposing the floating gate to the incident light to eject one or more electrons from the floating gate into the substrate by photoelectric emission; and
driving a read voltage further comprises driving the read voltage to a polysilicon control gate separated from the floating gate by silicon dioxide.
14. A method of detecting light comprising:
adding charge to a floating gate comprising a silicon carbide compound Si1−xCx, wherein x is between 0.5 and 0.75;
exposing the floating gate to incident light;
driving a read voltage to a control gate separated from the floating gate by an intergate dielectric; and
sensing a current in a channel region between a source region and a drain region in a substrate separated from the floating gate by an insulator to detect a change in conductance in the channel region.
15. The method of claim 14 wherein:
adding charge further comprises injecting hot electrons from the channel region between an n+-type source region and an n+-type drain region in a p-type silicon substrate through a layer of silicon dioxide into the floating gate, the floating gate comprising the silicon carbide compound Si1−xCx that is n-type doped and either polycrystalline or microcrystalline;
exposing the floating gate to incident light further comprises exposing the floating gate to the incident light to eject one or more electrons from the floating gate into the substrate by photoelectric emission; and
driving a read voltage further comprises driving the read voltage to a polysilicon control gate separated from the floating gate by silicon dioxide.
16. A method of detecting light comprising:
adding charge to a floating gate comprising a silicon carbide compound Si1−xCx, wherein x is between 0.5 and 1.0;
exposing the floating gate to incident light;
driving a read voltage to a control gate separated from the floating gate by silicon dioxide; and
sensing a current in a channel region between an n+-type source region and an n+-type drain region in a p-type silicon substrate separated from the floating gate by a layer of silicon dioxide to detect a change in conductance in the channel region.
17. The method of claim 16 wherein:
adding charge further comprises injecting hot electrons from the channel region through the layer of silicon dioxide into the floating gate, the floating gate comprising the silicon carbide compound Si1−xCx that is n-type doped and either polycrystalline or microcrystalline;
exposing the floating gate to incident light further comprises exposing the floating gate to the incident light to eject one or more electrons from the floating gate into the substrate by photoelectric emission; and
driving a read voltage further comprises driving the read voltage to a polysilicon control gate separated from the floating gate by the silicon dioxide.
18. A method of detecting light comprising:
adding charge to a floating gate comprising a silicon carbide compound Si1−xCx, wherein x is between 0.75 and 1.0;
exposing the floating gate to incident light;
driving a read voltage to a control gate separated from the floating gate by silicon dioxide; and
sensing a current in a channel region between an n+-type source region and an n+-type drain region in a p-type silicon substrate separated from the floating gate by a layer of silicon dioxide to detect a change in conductance in the channel region.
19. The method of claim 18 wherein:
adding charge further comprises injecting hot electrons from the channel region through the layer of silicon dioxide into the floating gate, the floating gate comprising the silicon carbide compound Si1−xCx that is n-type doped and either polycrystalline or microcrystalline;
exposing the floating gate to incident light further comprises exposing the floating gate to the incident light to eject one or more electrons from the floating gate into the substrate by photoelectric emission; and
driving a read voltage further comprises driving the read voltage to a polysilicon control gate separated from the floating gate by the silicon dioxide.
20. A method of detecting light comprising:
adding charge to a floating gate comprising a silicon carbide compound Si1−xCx, wherein x is between 0.5 and 0.75;
exposing the floating gate to incident light;
driving a read voltage to a control gate separated from the floating gate by silicon dioxide; and
sensing a current in a channel region between an n+-type source region and an n+-type drain region in a p-type silicon substrate separated from the floating gate by a layer of silicon dioxide to detect a change in conductance in the channel region.
21. The method of claim 20 wherein:
adding charge further comprises injecting hot electrons from the channel region through the layer of silicon dioxide into the floating gate, the floating gate comprising the silicon carbide compound Si1−xCx that is n-type doped and either polycrystalline or microcrystalline;
exposing the floating gate to incident light further comprises exposing the floating gate to the incident light to eject one or more electrons from the floating gate into the substrate by photoelectric emission; and
driving a read voltage further comprises driving the read voltage to a polysilicon control gate separated from the floating gate by the silicon dioxide.
22. A method of detecting light comprising:
adding charge to a gate comprising a silicon carbide compound Si1−xCx, wherein x is between 0.5 and 1.0;
exposing the gate to incident light to eject one or more electrons from the gate into a substrate by photoelectric emission; and
detecting a change in conductance in the substrate that is separated from the gate by an insulator.
23. The method of claim 22 wherein:
adding charge further comprises injecting hot electrons from a channel region between an n+-type source region and an n+-type drain region in a p-type silicon substrate through a layer of silicon dioxide into a floating gate, the floating gate comprising the silicon carbide compound Si1−xCx that is n-type doped and either polycrystalline or microcrystalline;
exposing the gate to incident light further comprises exposing the floating gate to the incident light to eject one or more electrons from the floating gate into the substrate by photoelectric emission;
detecting a change in conductance further comprises driving a read voltage to a control gate separated from the floating gate by an intergate dielectric and sensing a current in the channel region in the substrate.
24. A method of detecting light comprising:
adding charge to a gate comprising a silicon carbide compound Si1−xCx, wherein x is between 0.75 and 1.0;
exposing the gate to incident light to eject one or more electrons from the gate into a substrate by photoelectric emission; and
detecting a change in conductance in the substrate that is separated from the gate by an insulator.
25. The method of claim 24 wherein:
adding charge further comprises injecting hot electrons from a channel region between an n+-type source region and an n+-type drain region in a p-type silicon substrate through a layer of silicon dioxide into a floating gate, the floating gate comprising the silicon carbide compound Si1−xCx that is n-type doped and either polycrystalline or microcrystalline;
exposing the gate to incident light further comprises exposing the floating gate to the incident light to eject one or more electrons from the floating gate into the substrate by photoelectric emission;
detecting a change in conductance further comprises driving a read voltage to a control gate separated from the floating gate by an intergate dielectric and sensing a current in the channel region in the substrate.
26. A method of detecting light comprising:
adding charge to a gate comprising a silicon carbide compound Si1−xCx, wherein x is between 0.5 and 0.75;
exposing the gate to incident light to eject one or more electrons from the gate into a substrate by photoelectric emission; and
detecting a change in conductance in the substrate that is separated from the gate by an insulator.
27. The method of claim 26 wherein:
adding charge further comprises injecting hot electrons from a channel region between an n+-type source region and an n+-type drain region in a p-type silicon substrate through a layer of silicon dioxide into a floating gate, the floating gate comprising the silicon carbide compound Si1−xCx that is n-type doped and either polycrystalline or microcrystalline;
exposing the gate to incident light further comprises exposing the floating gate to the incident light to eject one or more electrons from the floating gate into the substrate by photoelectric emission;
detecting a change in conductance further comprises driving a read voltage to a control gate separated from the floating gate by an intergate dielectric and sensing a current in the channel region in the substrate.
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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050130398A1 (en) * 2003-12-12 2005-06-16 Tuung Luoh Elimination of the fast-erase phenomena in flash memory
US20050146934A1 (en) * 1997-07-29 2005-07-07 Micron Technology, Inc. Transistor with variable electron affinity gate and methods of fabrication and use
US20050242387A1 (en) * 2004-04-29 2005-11-03 Micron Technology, Inc. Flash memory device having a graded composition, high dielectric constant gate insulator
US20060014345A1 (en) * 2004-07-14 2006-01-19 Te-Hsun Hsu Uniform channel programmable erasable flash EEPROM
US20060244062A1 (en) * 2005-04-28 2006-11-02 International Business Machines Corporation Silicon-on-insulator based radiation detection device and method
US20070045707A1 (en) * 2005-08-31 2007-03-01 Szu-Yu Wang Memory device and manufacturing method thereof
US20070051301A1 (en) * 2005-02-22 2007-03-08 Taisuke Hirooka Method of manufacturing sic single crystal wafer
US20090258464A1 (en) * 2008-04-09 2009-10-15 International Business Machines Corporation Methods for manufacturing a high voltage junction field effect transistor using a hybrid orientation technology wafer
US20090256174A1 (en) * 2008-04-09 2009-10-15 International Business Machines Corporation Device structures for a high voltage junction field effect transistor manufactured using a hybrid orientation technology wafer and design structures for a high voltage integrated circuit
US20110132448A1 (en) * 2010-02-08 2011-06-09 Suniva, Inc. Solar cells and methods of fabrication thereof
US20130056806A1 (en) * 2011-09-02 2013-03-07 Hoon Kim Unit pixel of color image sensor and photo detector thereof
CN103137775A (en) * 2011-12-03 2013-06-05 南京大学 Photosensitive controllable component based on flash memory structure
US20150035082A1 (en) * 2008-12-05 2015-02-05 Micron Technology, Inc. Semiconductor device structures including energy barriers, and related methods

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7160577B2 (en) 2002-05-02 2007-01-09 Micron Technology, Inc. Methods for atomic-layer deposition of aluminum oxides in integrated circuits
JP2004303766A (en) * 2003-03-28 2004-10-28 Seiko Epson Corp Process for fabricating semiconductor device
US7556982B2 (en) * 2003-08-07 2009-07-07 Uchicago Argonne, Llc Method to grow pure nanocrystalline diamond films at low temperatures and high deposition rates
US20050269621A1 (en) * 2004-06-03 2005-12-08 Micron Technology, Inc. Flash memory devices on silicon carbide
US7355238B2 (en) * 2004-12-06 2008-04-08 Asahi Glass Company, Limited Nonvolatile semiconductor memory device having nanoparticles for charge retention
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US7575978B2 (en) 2005-08-04 2009-08-18 Micron Technology, Inc. Method for making conductive nanoparticle charge storage element
US7989290B2 (en) 2005-08-04 2011-08-02 Micron Technology, Inc. Methods for forming rhodium-based charge traps and apparatus including rhodium-based charge traps
US8367506B2 (en) 2007-06-04 2013-02-05 Micron Technology, Inc. High-k dielectrics with gold nano-particles

Citations (101)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3792465A (en) 1971-12-30 1974-02-12 Texas Instruments Inc Charge transfer solid state display
US4113515A (en) 1975-06-04 1978-09-12 U.S. Philips Corporation Semiconductor manufacturing method using buried nitride formed by a nitridation treatment in the presence of active nitrogen
US4118795A (en) 1976-08-27 1978-10-03 Texas Instruments Incorporated Two-phase CCD regenerator - I/O circuits
US4384349A (en) 1979-10-01 1983-05-17 Texas Instruments Incorporated High density electrically erasable floating gate dual-injection programmable memory device
US4460670A (en) 1981-11-26 1984-07-17 Canon Kabushiki Kaisha Photoconductive member with α-Si and C, N or O and dopant
US4462150A (en) 1981-11-10 1984-07-31 Tokyo Shibaura Denki Kabushiki Kaisha Method of forming energy beam activated conductive regions between circuit elements
US4473836A (en) 1982-05-03 1984-09-25 Dalsa Inc. Integrable large dynamic range photodetector element for linear and area integrated circuit imaging arrays
US4507673A (en) * 1979-10-13 1985-03-26 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device
US4598305A (en) 1984-06-18 1986-07-01 Xerox Corporation Depletion mode thin film semiconductor photodetectors
US4657699A (en) 1984-12-17 1987-04-14 E. I. Du Pont De Nemours And Company Resistor compositions
US4736317A (en) 1985-07-17 1988-04-05 Syracuse University Microprogram-coupled multiple-microprocessor module with 32-bit byte width formed of 8-bit byte width microprocessors
US4738729A (en) 1984-10-19 1988-04-19 Toshihiko Yoshida Amorphous silicon semiconductor solar cell
US4768072A (en) 1984-01-20 1988-08-30 Fuji Electric Corporate Research And Development Co., Ltd. Multilayer semiconductor device having an amorphous carbon and silicon layer
US4769686A (en) 1983-04-01 1988-09-06 Hitachi, Ltd. Semiconductor device
JPS63291951A (en) * 1987-05-23 1988-11-29 Sumitomo Chem Co Ltd Polyetherpolyamide composition
US4816883A (en) 1986-07-10 1989-03-28 Sgs Microelettronica S.P.A. Nonvolatile, semiconductor memory device
US4841349A (en) 1984-11-16 1989-06-20 Fujitsu Limited Semiconductor photodetector device with light responsive PN junction gate
US4849797A (en) * 1987-01-23 1989-07-18 Hosiden Electronics Co., Ltd. Thin film transistor
US4893273A (en) 1985-03-28 1990-01-09 Kabushiki Kaisha Toshiba Semiconductor memory device for storing image data
US4897710A (en) 1986-08-18 1990-01-30 Sharp Kabushiki Kaisha Semiconductor device
US4980303A (en) 1987-08-19 1990-12-25 Fujitsu Limited Manufacturing method of a Bi-MIS semiconductor device
US4994401A (en) 1987-01-16 1991-02-19 Hosiden Electronics Co., Ltd. Method of making a thin film transistor
US5049950A (en) * 1987-07-14 1991-09-17 Sharp Kabushiki Kaisha MIS structure photosensor
US5111430A (en) 1989-06-22 1992-05-05 Nippon Telegraph And Telephone Corporation Non-volatile memory with hot carriers transmitted to floating gate through control gate
US5145741A (en) 1989-06-05 1992-09-08 Quick Nathaniel R Converting ceramic materials to electrical conductors and semiconductors
US5189504A (en) 1989-12-11 1993-02-23 Nippon Telegraph And Telephone Corporation Semiconductor device of MOS structure having p-type gate electrode
EP0291951B1 (en) 1987-05-22 1993-08-04 Fujitsu Limited A semiconductor field effect transistor using single crystalline silicon carbide as a gate insulating layer
US5235195A (en) 1990-08-08 1993-08-10 Minnesota Mining And Manufacturing Company Solid state electromagnetic radiation detector with planarization layer
US5260593A (en) 1991-12-10 1993-11-09 Micron Technology, Inc. Semiconductor floating gate device having improved channel-floating gate interaction
US5293560A (en) 1988-06-08 1994-03-08 Eliyahou Harari Multi-state flash EEPROM system using incremental programing and erasing methods
US5298796A (en) 1992-07-08 1994-03-29 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Nonvolatile programmable neural network synaptic array
US5317535A (en) 1992-06-19 1994-05-31 Intel Corporation Gate/source disturb protection for sixteen-bit flash EEPROM memory arrays
US5336361A (en) 1990-03-23 1994-08-09 Matsushita Electric Industrial Co., Ltd. Method of manufacturing an MIS-type semiconductor device
US5360491A (en) 1993-04-07 1994-11-01 The United States Of America As Represented By The United States Department Of Energy β-silicon carbide protective coating and method for fabricating same
US5366713A (en) 1992-06-03 1994-11-22 Showa Shell Sekiyu K.K. Method of forming p-type silicon carbide
US5367306A (en) 1993-06-04 1994-11-22 Hollon Blake D GPS integrated ELT system
US5369040A (en) 1992-05-18 1994-11-29 Westinghouse Electric Corporation Method of making transparent polysilicon gate for imaging arrays
US5371383A (en) 1993-05-14 1994-12-06 Kobe Steel Usa Inc. Highly oriented diamond film field-effect transistor
US5388069A (en) 1992-03-19 1995-02-07 Fujitsu Limited Nonvolatile semiconductor memory device for preventing erroneous operation caused by over-erase phenomenon
US5393999A (en) 1993-02-22 1995-02-28 Texas Instruments Incorporated SiC power MOSFET device structure
US5407845A (en) 1992-10-15 1995-04-18 Fujitsu Limited Method of manufacturing thin film transistors in a liquid crystal display apparatus
US5415126A (en) 1993-08-16 1995-05-16 Dow Corning Corporation Method of forming crystalline silicon carbide coatings at low temperatures
US5424993A (en) 1993-11-15 1995-06-13 Micron Technology, Inc. Programming method for the selective healing of over-erased cells on a flash erasable programmable read-only memory device
US5425860A (en) 1993-04-07 1995-06-20 The Regents Of The University Of California Pulsed energy synthesis and doping of silicon carbide
US5438544A (en) 1993-03-19 1995-08-01 Fujitsu Limited Non-volatile semiconductor memory device with function of bringing memory cell transistors to overerased state, and method of writing data in the device
US5441901A (en) 1993-10-05 1995-08-15 Motorola, Inc. Method for forming a carbon doped silicon semiconductor device having a narrowed bandgap characteristic
US5449941A (en) 1991-10-29 1995-09-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device
US5455432A (en) 1994-10-11 1995-10-03 Kobe Steel Usa Diamond semiconductor device with carbide interlayer
US5465249A (en) 1991-11-26 1995-11-07 Cree Research, Inc. Nonvolatile random access memory device having transistor and capacitor made in silicon carbide substrate
EP0681333A1 (en) 1994-04-29 1995-11-08 International Business Machines Corporation Low voltage memory
US5467306A (en) 1993-10-04 1995-11-14 Texas Instruments Incorporated Method of using source bias to increase threshold voltages and/or to correct for over-erasure of flash eproms
US5477485A (en) 1995-02-22 1995-12-19 National Semiconductor Corporation Method for programming a single EPROM or FLASH memory cell to store multiple levels of data that utilizes a floating substrate
US5493140A (en) 1993-07-05 1996-02-20 Sharp Kabushiki Kaisha Nonvolatile memory cell and method of producing the same
US5530581A (en) 1995-05-31 1996-06-25 Eic Laboratories, Inc. Protective overlayer material and electro-optical coating using same
US5557114A (en) 1995-01-12 1996-09-17 International Business Machines Corporation Optical fet
US5557122A (en) 1995-05-12 1996-09-17 Alliance Semiconductors Corporation Semiconductor electrode having improved grain structure and oxide growth properties
US5562769A (en) 1991-12-20 1996-10-08 Kobe Steel Usa, Inc. Methods of forming diamond semiconductor devices and layers on nondiamond substrates
US5604357A (en) 1994-07-12 1997-02-18 Matsushita Electric Industrial Co., Ltd. Semiconductor nonvolatile memory with resonance tunneling
US5623442A (en) 1993-07-13 1997-04-22 Nkk Corporation Memory cells and memory devices with a storage capacitor of parasitic capacitance and information storing method using the same
US5623160A (en) 1995-09-14 1997-04-22 Liberkowski; Janusz B. Signal-routing or interconnect substrate, structure and apparatus
US5654208A (en) 1995-04-10 1997-08-05 Abb Research Ltd. Method for producing a semiconductor device having a semiconductor layer of SiC comprising a masking step
US5661312A (en) 1995-03-30 1997-08-26 Motorola Silicon carbide MOSFET
US5670790A (en) 1995-09-21 1997-09-23 Kabushikik Kaisha Toshiba Electronic device
US5672889A (en) 1995-03-15 1997-09-30 General Electric Company Vertical channel silicon carbide metal-oxide-semiconductor field effect transistor with self-aligned gate for microwave and power applications, and method of making
US5698869A (en) 1994-09-13 1997-12-16 Kabushiki Kaisha Toshiba Insulated-gate transistor having narrow-bandgap-source
US5714766A (en) 1995-09-29 1998-02-03 International Business Machines Corporation Nano-structure memory device
US5719410A (en) 1993-12-28 1998-02-17 Kabushiki Kaisha Toshiba Semiconductor device wiring or electrode
US5734181A (en) 1995-09-14 1998-03-31 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method therefor
US5740104A (en) 1997-01-29 1998-04-14 Micron Technology, Inc. Multi-state flash memory cell and method for programming single electron differences
US5754477A (en) 1997-01-29 1998-05-19 Micron Technology, Inc. Differential flash memory cell and method for programming
US5786250A (en) 1997-03-14 1998-07-28 Micron Technology, Inc. Method of making a capacitor
US5798548A (en) 1995-05-18 1998-08-25 Sanyo Electric Co., Ltd. Semiconductor device having multiple control gates
US5801401A (en) 1997-01-29 1998-09-01 Micron Technology, Inc. Flash memory with microcrystalline silicon carbide film floating gate
US5808336A (en) 1994-05-13 1998-09-15 Canon Kabushiki Kaisha Storage device
US5828101A (en) 1995-03-30 1998-10-27 Kabushiki Kaisha Toshiba Three-terminal semiconductor device and related semiconductor devices
US5846859A (en) 1995-03-14 1998-12-08 Samsung Electronics Co., Ltd. Method for manufacturing a semiconductor memory device having capacitive storage
US5858811A (en) 1994-11-28 1999-01-12 Nec Corporation Method for fabricating charge coupled device (CCD) as semiconductor device of MOS structure
US5861346A (en) 1995-07-27 1999-01-19 Regents Of The University Of California Process for forming silicon carbide films and microcomponents
US5877041A (en) 1997-06-30 1999-03-02 Harris Corporation Self-aligned power field effect transistor in silicon carbide
US5886368A (en) 1997-07-29 1999-03-23 Micron Technology, Inc. Transistor with silicon oxycarbide gate and methods of fabrication and use
US5886379A (en) 1996-05-16 1999-03-23 Lg Semicon Co., Ltd. Semiconductor memory device with increased coupling ratio
US5886376A (en) 1996-07-01 1999-03-23 International Business Machines Corporation EEPROM having coplanar on-insulator FET and control gate
US5898197A (en) 1996-06-06 1999-04-27 Sanyo Electric Co., Ltd. Non-volatile semiconductor memory devices
US5907775A (en) 1997-04-11 1999-05-25 Vanguard International Semiconductor Corporation Non-volatile memory device with high gate coupling ratio and manufacturing process therefor
US5912837A (en) 1996-10-28 1999-06-15 Micron Technology, Inc. Bitline disturb reduction
US5926740A (en) 1997-10-27 1999-07-20 Micron Technology, Inc. Graded anti-reflective coating for IC lithography
US5976926A (en) 1996-11-12 1999-11-02 Micron Technology, Inc. Static memory cell and method of manufacturing a static memory cell
US5990531A (en) 1995-12-28 1999-11-23 Philips Electronics N.A. Corporation Methods of making high voltage GaN-AlN based semiconductor devices and semiconductor devices made
US6018166A (en) 1996-12-31 2000-01-25 Industrial Technology Research Institute Polysilicon carbon source/drain heterojunction thin-film transistor
US6031263A (en) 1997-07-29 2000-02-29 Micron Technology, Inc. DEAPROM and transistor with gallium nitride or gallium aluminum nitride gate
US6034001A (en) 1991-10-16 2000-03-07 Kulite Semiconductor Products, Inc. Method for etching of silicon carbide semiconductor using selective etching of different conductivity types
US6075259A (en) 1994-11-14 2000-06-13 North Carolina State University Power semiconductor devices that utilize buried insulating regions to achieve higher than parallel-plane breakdown voltages
US6084248A (en) 1996-06-28 2000-07-04 Seiko Epson Corporation Thin film transistor, manufacturing method thereof, and circuit and liquid crystal display device using the thin film transistor
US6093937A (en) 1996-02-23 2000-07-25 Semiconductor Energy Laboratory Co. Ltd. Semiconductor thin film, semiconductor device and manufacturing method thereof
US6099574A (en) 1996-12-19 2000-08-08 Kabushiki Kaisha Toshiba Method and apparatus for obtaining structure of semiconductor devices and memory for storing program for obtaining the same
US6130147A (en) 1994-04-07 2000-10-10 Sdl, Inc. Methods for forming group III-V arsenide-nitride semiconductor materials
US6144581A (en) 1996-07-24 2000-11-07 California Institute Of Technology pMOS EEPROM non-volatile data storage
US6163066A (en) 1997-02-07 2000-12-19 Micron Technology, Inc. Porous silicon dioxide insulator
US6166768A (en) 1994-01-28 2000-12-26 California Institute Of Technology Active pixel sensor array with simple floating gate pixels
US6271566B1 (en) 1997-03-25 2001-08-07 Toshiba Corporation Semiconductor device having a carbon containing insulation layer formed under the source/drain
US6365919B1 (en) 1998-09-02 2002-04-02 Infineon Technologies Ag Silicon carbide junction field effect transistor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4123357A1 (en) 1991-07-15 1993-01-21 Henkel Kgaa RENEWABLE ALUMINUM TRIFOROMATE FUELS IN HIGHLY CONCENTRATED WAESSRIG-GELOESTER AND STORAGE-STABLE FORM AND ITS USE
JP3222367B2 (en) 1995-10-11 2001-10-29 株式会社山武 Temperature measurement circuit

Patent Citations (111)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3792465A (en) 1971-12-30 1974-02-12 Texas Instruments Inc Charge transfer solid state display
US4113515A (en) 1975-06-04 1978-09-12 U.S. Philips Corporation Semiconductor manufacturing method using buried nitride formed by a nitridation treatment in the presence of active nitrogen
US4118795A (en) 1976-08-27 1978-10-03 Texas Instruments Incorporated Two-phase CCD regenerator - I/O circuits
US4384349A (en) 1979-10-01 1983-05-17 Texas Instruments Incorporated High density electrically erasable floating gate dual-injection programmable memory device
US4507673A (en) * 1979-10-13 1985-03-26 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device
US4462150A (en) 1981-11-10 1984-07-31 Tokyo Shibaura Denki Kabushiki Kaisha Method of forming energy beam activated conductive regions between circuit elements
US4460670A (en) 1981-11-26 1984-07-17 Canon Kabushiki Kaisha Photoconductive member with α-Si and C, N or O and dopant
US4473836A (en) 1982-05-03 1984-09-25 Dalsa Inc. Integrable large dynamic range photodetector element for linear and area integrated circuit imaging arrays
US4769686A (en) 1983-04-01 1988-09-06 Hitachi, Ltd. Semiconductor device
US4768072A (en) 1984-01-20 1988-08-30 Fuji Electric Corporate Research And Development Co., Ltd. Multilayer semiconductor device having an amorphous carbon and silicon layer
US4598305A (en) 1984-06-18 1986-07-01 Xerox Corporation Depletion mode thin film semiconductor photodetectors
US4738729A (en) 1984-10-19 1988-04-19 Toshihiko Yoshida Amorphous silicon semiconductor solar cell
US4841349A (en) 1984-11-16 1989-06-20 Fujitsu Limited Semiconductor photodetector device with light responsive PN junction gate
US4657699A (en) 1984-12-17 1987-04-14 E. I. Du Pont De Nemours And Company Resistor compositions
US4893273A (en) 1985-03-28 1990-01-09 Kabushiki Kaisha Toshiba Semiconductor memory device for storing image data
US4736317A (en) 1985-07-17 1988-04-05 Syracuse University Microprogram-coupled multiple-microprocessor module with 32-bit byte width formed of 8-bit byte width microprocessors
US4816883A (en) 1986-07-10 1989-03-28 Sgs Microelettronica S.P.A. Nonvolatile, semiconductor memory device
US4897710A (en) 1986-08-18 1990-01-30 Sharp Kabushiki Kaisha Semiconductor device
US4994401A (en) 1987-01-16 1991-02-19 Hosiden Electronics Co., Ltd. Method of making a thin film transistor
US4849797A (en) * 1987-01-23 1989-07-18 Hosiden Electronics Co., Ltd. Thin film transistor
EP0291951B1 (en) 1987-05-22 1993-08-04 Fujitsu Limited A semiconductor field effect transistor using single crystalline silicon carbide as a gate insulating layer
JPS63291951A (en) * 1987-05-23 1988-11-29 Sumitomo Chem Co Ltd Polyetherpolyamide composition
US5049950A (en) * 1987-07-14 1991-09-17 Sharp Kabushiki Kaisha MIS structure photosensor
US4980303A (en) 1987-08-19 1990-12-25 Fujitsu Limited Manufacturing method of a Bi-MIS semiconductor device
US5293560A (en) 1988-06-08 1994-03-08 Eliyahou Harari Multi-state flash EEPROM system using incremental programing and erasing methods
US5145741A (en) 1989-06-05 1992-09-08 Quick Nathaniel R Converting ceramic materials to electrical conductors and semiconductors
US5111430A (en) 1989-06-22 1992-05-05 Nippon Telegraph And Telephone Corporation Non-volatile memory with hot carriers transmitted to floating gate through control gate
US5189504A (en) 1989-12-11 1993-02-23 Nippon Telegraph And Telephone Corporation Semiconductor device of MOS structure having p-type gate electrode
US5336361A (en) 1990-03-23 1994-08-09 Matsushita Electric Industrial Co., Ltd. Method of manufacturing an MIS-type semiconductor device
US5235195A (en) 1990-08-08 1993-08-10 Minnesota Mining And Manufacturing Company Solid state electromagnetic radiation detector with planarization layer
US6034001A (en) 1991-10-16 2000-03-07 Kulite Semiconductor Products, Inc. Method for etching of silicon carbide semiconductor using selective etching of different conductivity types
US5449941A (en) 1991-10-29 1995-09-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device
US5629222A (en) 1991-10-29 1997-05-13 Semiconductor Energy Laboratory Co., Ltd. Method of forming semiconductor memory device by selectively forming an insulating film on the drain region
US5465249A (en) 1991-11-26 1995-11-07 Cree Research, Inc. Nonvolatile random access memory device having transistor and capacitor made in silicon carbide substrate
US5260593A (en) 1991-12-10 1993-11-09 Micron Technology, Inc. Semiconductor floating gate device having improved channel-floating gate interaction
US5562769A (en) 1991-12-20 1996-10-08 Kobe Steel Usa, Inc. Methods of forming diamond semiconductor devices and layers on nondiamond substrates
US5580380A (en) 1991-12-20 1996-12-03 North Carolina State University Method for forming a diamond coated field emitter and device produced thereby
US5388069A (en) 1992-03-19 1995-02-07 Fujitsu Limited Nonvolatile semiconductor memory device for preventing erroneous operation caused by over-erase phenomenon
US5369040A (en) 1992-05-18 1994-11-29 Westinghouse Electric Corporation Method of making transparent polysilicon gate for imaging arrays
US5366713A (en) 1992-06-03 1994-11-22 Showa Shell Sekiyu K.K. Method of forming p-type silicon carbide
US5317535A (en) 1992-06-19 1994-05-31 Intel Corporation Gate/source disturb protection for sixteen-bit flash EEPROM memory arrays
US5298796A (en) 1992-07-08 1994-03-29 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Nonvolatile programmable neural network synaptic array
US5407845A (en) 1992-10-15 1995-04-18 Fujitsu Limited Method of manufacturing thin film transistors in a liquid crystal display apparatus
US5393999A (en) 1993-02-22 1995-02-28 Texas Instruments Incorporated SiC power MOSFET device structure
US5438544A (en) 1993-03-19 1995-08-01 Fujitsu Limited Non-volatile semiconductor memory device with function of bringing memory cell transistors to overerased state, and method of writing data in the device
US5360491A (en) 1993-04-07 1994-11-01 The United States Of America As Represented By The United States Department Of Energy β-silicon carbide protective coating and method for fabricating same
US5425860A (en) 1993-04-07 1995-06-20 The Regents Of The University Of California Pulsed energy synthesis and doping of silicon carbide
US5371383A (en) 1993-05-14 1994-12-06 Kobe Steel Usa Inc. Highly oriented diamond film field-effect transistor
US5367306A (en) 1993-06-04 1994-11-22 Hollon Blake D GPS integrated ELT system
US5493140A (en) 1993-07-05 1996-02-20 Sharp Kabushiki Kaisha Nonvolatile memory cell and method of producing the same
US5623442A (en) 1993-07-13 1997-04-22 Nkk Corporation Memory cells and memory devices with a storage capacitor of parasitic capacitance and information storing method using the same
US5415126A (en) 1993-08-16 1995-05-16 Dow Corning Corporation Method of forming crystalline silicon carbide coatings at low temperatures
US5467306A (en) 1993-10-04 1995-11-14 Texas Instruments Incorporated Method of using source bias to increase threshold voltages and/or to correct for over-erasure of flash eproms
US5441901A (en) 1993-10-05 1995-08-15 Motorola, Inc. Method for forming a carbon doped silicon semiconductor device having a narrowed bandgap characteristic
US5424993A (en) 1993-11-15 1995-06-13 Micron Technology, Inc. Programming method for the selective healing of over-erased cells on a flash erasable programmable read-only memory device
US6100193A (en) 1993-12-28 2000-08-08 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
US5719410A (en) 1993-12-28 1998-02-17 Kabushiki Kaisha Toshiba Semiconductor device wiring or electrode
US6166768A (en) 1994-01-28 2000-12-26 California Institute Of Technology Active pixel sensor array with simple floating gate pixels
US6130147A (en) 1994-04-07 2000-10-10 Sdl, Inc. Methods for forming group III-V arsenide-nitride semiconductor materials
US5508543A (en) 1994-04-29 1996-04-16 International Business Machines Corporation Low voltage memory
EP0681333A1 (en) 1994-04-29 1995-11-08 International Business Machines Corporation Low voltage memory
US5808336A (en) 1994-05-13 1998-09-15 Canon Kabushiki Kaisha Storage device
US5604357A (en) 1994-07-12 1997-02-18 Matsushita Electric Industrial Co., Ltd. Semiconductor nonvolatile memory with resonance tunneling
US5698869A (en) 1994-09-13 1997-12-16 Kabushiki Kaisha Toshiba Insulated-gate transistor having narrow-bandgap-source
US5455432A (en) 1994-10-11 1995-10-03 Kobe Steel Usa Diamond semiconductor device with carbide interlayer
US6075259A (en) 1994-11-14 2000-06-13 North Carolina State University Power semiconductor devices that utilize buried insulating regions to achieve higher than parallel-plane breakdown voltages
US5858811A (en) 1994-11-28 1999-01-12 Nec Corporation Method for fabricating charge coupled device (CCD) as semiconductor device of MOS structure
US5557114A (en) 1995-01-12 1996-09-17 International Business Machines Corporation Optical fet
US5789276A (en) 1995-01-12 1998-08-04 International Business Machines Corporation Optical FET
US5477485A (en) 1995-02-22 1995-12-19 National Semiconductor Corporation Method for programming a single EPROM or FLASH memory cell to store multiple levels of data that utilizes a floating substrate
US5846859A (en) 1995-03-14 1998-12-08 Samsung Electronics Co., Ltd. Method for manufacturing a semiconductor memory device having capacitive storage
US5672889A (en) 1995-03-15 1997-09-30 General Electric Company Vertical channel silicon carbide metal-oxide-semiconductor field effect transistor with self-aligned gate for microwave and power applications, and method of making
US5828101A (en) 1995-03-30 1998-10-27 Kabushiki Kaisha Toshiba Three-terminal semiconductor device and related semiconductor devices
US5661312A (en) 1995-03-30 1997-08-26 Motorola Silicon carbide MOSFET
US5654208A (en) 1995-04-10 1997-08-05 Abb Research Ltd. Method for producing a semiconductor device having a semiconductor layer of SiC comprising a masking step
US5557122A (en) 1995-05-12 1996-09-17 Alliance Semiconductors Corporation Semiconductor electrode having improved grain structure and oxide growth properties
US5798548A (en) 1995-05-18 1998-08-25 Sanyo Electric Co., Ltd. Semiconductor device having multiple control gates
US5530581A (en) 1995-05-31 1996-06-25 Eic Laboratories, Inc. Protective overlayer material and electro-optical coating using same
US5861346A (en) 1995-07-27 1999-01-19 Regents Of The University Of California Process for forming silicon carbide films and microcomponents
US5623160A (en) 1995-09-14 1997-04-22 Liberkowski; Janusz B. Signal-routing or interconnect substrate, structure and apparatus
US5734181A (en) 1995-09-14 1998-03-31 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method therefor
US5670790A (en) 1995-09-21 1997-09-23 Kabushikik Kaisha Toshiba Electronic device
US5714766A (en) 1995-09-29 1998-02-03 International Business Machines Corporation Nano-structure memory device
US5990531A (en) 1995-12-28 1999-11-23 Philips Electronics N.A. Corporation Methods of making high voltage GaN-AlN based semiconductor devices and semiconductor devices made
US6093937A (en) 1996-02-23 2000-07-25 Semiconductor Energy Laboratory Co. Ltd. Semiconductor thin film, semiconductor device and manufacturing method thereof
US5886379A (en) 1996-05-16 1999-03-23 Lg Semicon Co., Ltd. Semiconductor memory device with increased coupling ratio
US5898197A (en) 1996-06-06 1999-04-27 Sanyo Electric Co., Ltd. Non-volatile semiconductor memory devices
US6084248A (en) 1996-06-28 2000-07-04 Seiko Epson Corporation Thin film transistor, manufacturing method thereof, and circuit and liquid crystal display device using the thin film transistor
US5886376A (en) 1996-07-01 1999-03-23 International Business Machines Corporation EEPROM having coplanar on-insulator FET and control gate
US6144581A (en) 1996-07-24 2000-11-07 California Institute Of Technology pMOS EEPROM non-volatile data storage
US5912837A (en) 1996-10-28 1999-06-15 Micron Technology, Inc. Bitline disturb reduction
US5976926A (en) 1996-11-12 1999-11-02 Micron Technology, Inc. Static memory cell and method of manufacturing a static memory cell
US6099574A (en) 1996-12-19 2000-08-08 Kabushiki Kaisha Toshiba Method and apparatus for obtaining structure of semiconductor devices and memory for storing program for obtaining the same
US6018166A (en) 1996-12-31 2000-01-25 Industrial Technology Research Institute Polysilicon carbon source/drain heterojunction thin-film transistor
US5989958A (en) 1997-01-29 1999-11-23 Micron Technology, Inc. Flash memory with microcrystalline silicon carbide film floating gate
US5754477A (en) 1997-01-29 1998-05-19 Micron Technology, Inc. Differential flash memory cell and method for programming
US6166401A (en) 1997-01-29 2000-12-26 Micron Technology, Inc. Flash memory with microcrystalline silicon carbide film floating gate
US5740104A (en) 1997-01-29 1998-04-14 Micron Technology, Inc. Multi-state flash memory cell and method for programming single electron differences
US5801401A (en) 1997-01-29 1998-09-01 Micron Technology, Inc. Flash memory with microcrystalline silicon carbide film floating gate
US6163066A (en) 1997-02-07 2000-12-19 Micron Technology, Inc. Porous silicon dioxide insulator
US5786250A (en) 1997-03-14 1998-07-28 Micron Technology, Inc. Method of making a capacitor
US6271566B1 (en) 1997-03-25 2001-08-07 Toshiba Corporation Semiconductor device having a carbon containing insulation layer formed under the source/drain
US5907775A (en) 1997-04-11 1999-05-25 Vanguard International Semiconductor Corporation Non-volatile memory device with high gate coupling ratio and manufacturing process therefor
US5877041A (en) 1997-06-30 1999-03-02 Harris Corporation Self-aligned power field effect transistor in silicon carbide
US5886368A (en) 1997-07-29 1999-03-23 Micron Technology, Inc. Transistor with silicon oxycarbide gate and methods of fabrication and use
US6031263A (en) 1997-07-29 2000-02-29 Micron Technology, Inc. DEAPROM and transistor with gallium nitride or gallium aluminum nitride gate
US6297521B1 (en) 1997-07-29 2001-10-02 Micron Technology, Inc. Graded anti-reflective coating for IC lithography
US6307775B1 (en) 1997-07-29 2001-10-23 Micron Technology, Inc. Deaprom and transistor with gallium nitride or gallium aluminum nitride gate
US6309907B1 (en) 1997-07-29 2001-10-30 Micron Technology, Inc. Method of fabricating transistor with silicon oxycarbide gate
US5926740A (en) 1997-10-27 1999-07-20 Micron Technology, Inc. Graded anti-reflective coating for IC lithography
US6365919B1 (en) 1998-09-02 2002-04-02 Infineon Technologies Ag Silicon carbide junction field effect transistor

Non-Patent Citations (114)

* Cited by examiner, † Cited by third party
Title
Akasaki, I., et al., "Effects of AIN Buffer Layer on Crystallographic Structure and on Electrical and Optical Properties of GaN and Ga(1-x)Al(x)N [0<x (<or =)0.4] Films on Grown on Sapphire Substrate by MOVPE", J, Crystal Growth, 98, (1989),209-219.
Alok, D., et al., "Electrical Properties of Thermal Oxide Grown on N-type 6H-Silicon Carbide", Applied Physcis Letters, 64, (May 23, 1994),2845-2846.
Andrieux, M., et al., "Interface and Adhesion of PACVD SiC Based Films on Metals", Supp. Le Vide: science, technique et applications, 279, (1996),212-214.
Bachmann, P., et al., "Influence on Surface Modifications on the Electronic Properties of CVD Diamond Films", Diamond and Related Materials, 5, (1996), 1378-1383.
Baglee, D., "Characteristics & Reliability of 100 Angstrom Oxides", IEEE 22nd Annual Proc.: Reliability Physics, Las Vegas,(Apr. 3-5, 1984),152-155.
Beheim, G., et al., "Magnetron Plasma Etching of SiC for Microstructures", Proc: SPIE -Integrated Optics and Microstructures III, San Jose, CA,(Jan. 29, 1996),82-86.
Beltram, F., et al., "GaAlAs/GaAs Floating-Gate Memory Devices with Graded-Gap Injector Grown by Molecular-Beam Epitaxy", IEEE Transactions on Electron Devices, 35, Abstract No. VA-7,(Dec. 1988),2451.
Beltram, F., et al., "Memory phenomena in heterojunction structures: Evidence for suppressed thermionic emission", Appl. Phys. Lett., 53(5), (1988), pp. 376-378.
Bengtsson, S., et al., "Applications of Aluminum Nitride Films Deposited by Reactive Sputtering to Silicon-On-Insulator Materials", Japanese J. Applied Physics, 35, (1996), 4175-4181.
Benjamin, M., et al., "UV Photoemission Study of Heteroepitaxial AlGaN Films Grown on 6H-SiC", Applied Surface Science, 104/105, (1996), 455-460.
Bermudez, V., et al., "The Growth and Properties of Al and AIN Films on GaN(0001)-(1 x 1)", J. Applied Physics, 79, (Jan. 1996), 110-119.
Boeringer, Daniel W., et al., "Avalanche amplification of multiple resonant tunneling through parallel silicon microcrystallites", Physical Rev. B,51, (1995), pp. 13337-13343.
Burns, S. G., et al., In: Principles of Electronic Circuits, West Publishing Company, St. Paul, MN,(1987), pp. 382-383
Burns, S., et al., In: Principles of Electronic Circuits, West Publishing Company, (1987), p. 380.
Burns, S.G., et al., In: Principles of Electronic Circuits, West Publishing Co., St. Paul, MN, (1987), 382-383.
Capasso, F., et al., "New Floating-Gate AlGaAs/GaAs Memory Devices with Graded-Gap Electron Injector and Long Retention Times", IEEE Electron Device Letters, (1988), pp. 377-379.
Casey, H., et al., "Low Interface Trap Density for Remote Plasma Deposited SiO2 on n-type GaN", Applied Phys. Lett., 68, (Mar. 1996), 1850-1852.
Chang, C., et al., "Novel Passivation Dielectrics-The Boron-or Phosphorus-Doped Hydrogenated Amorphous Silicon Carbide Films", Journal of the Electrochemical Society, 132, (Feb. 1985), 418-422.
Choi, J., et al., "Effect of Deposition Conditions and Pretreatments on the Microstructure of MPECVD Diamond Thin Films", Materials Chemistry and Physics, (1996), 176-179.
Clarke, G., et al., "The Infrared Properties of Magnetron-Sputtered Diamond-Like Thin Films", Thin Solid Films, 280, (1996), 130-135.
Compagnini, G., et al., "Spectroscopic Characterization of Annealed Si(1-x)C(x) Films", J. Materials Res., 11, (Sep. 1996), 2269-2273.
Dartnell, N., et al., "Reactive Ion Etching of Silicon Carbide (Si(x)C(1-x))", Vacuum, 46, (1995), 349-355.
DeMichelis, F., et al., "Influence of Doping on the Structural and Optoelectronic Properties of Amorphous and Microcrystalline Silicon Carbide", Journal of Applied Physics, 72, (Aug. 15, 1992), 1327-1333.
DeMichelis, F., et al., "Physical Properties of Undoped and Doped Microcrystalline SiC:H Deposited by PECVD", Materials Research Society Symposium Proceedings, 219, Anaheim, CA, (Apr. 30 -May 3, 1991), 413-418.
Dipert, B., et al., "Flash Memory Goes Mainstream", IEEE Spectrum, 30, (Oct. 1993), pp. 48-52.
Edelberg, E., et al., "Visible Luminescence from Nanocrystalline silicon films produced by plasma enhanced chemical vapor deposition", Appl. Phys. Lett., 68, (1996), pp. 1415-1417.
Fissel, A., et al. , "Epitaxial Growth of SiC Thin Films on Si-stabilized alpha-SiC (0001) at Low Temperatures by Solid-source Molecular Beam Epitaxy", Journal of Crystal Growth, 154, (1995), 72-80.
Friedrichs, P., et al., "Interface Properties of Metal-Oxide-Semiconductor Structures on N-Type 6H and 4H-SiC", J. Applied Physics, 79, (May 15, 1996), 7814-7819.
Fujii, T., et al., "Bonding Structures in Highly Photoconductive a-SiC:H Films Deposited by Hybrid-Plasma Chemical Vapor Deposition", Journal of Non-Crystalline Solids, 198-200, (1996), 577-581.
Goetzberger, A., et al., Applied Solid State Science: Advances in Materials and Device Research, R. Wolfe, ed., Academic Press, New York, (1969),Including p. 233.
Graul, J., et al., "Growth Mechanism of Polycrystalline beta-SiC Layers on Silicon Substrate", Applied Phys. Lett., 21, (Jul. 1972), 67-69.
He, Z., et al., "Ion-beam-assisted Deposition of Si-carbide Films", Thin Solid Films, 260, (1995), 32-37.
Hu, G., et al., "Will Flash Memory Replace Hard Disk Drive?", 1994 IEEE International Electron Device Meeting, Panel Discussion, Session 24, Outline, (Dec. 1994), 2 pages.
Hwang, J., et al., "High Mobility beta-SiC Epilayer Prepared by Low-pressure Rapid Thermal Chemical Vapor Deposition on a (100) Silicon Substrate", Thin Solid Films, 272, (1996), 4-6.
Hybertsen, Mark S., "Absorption and Emission of Light in Nanoscale Silicon Structures", Phys. Rev. Lett., 72, (1994), pp. 1514-1517.
Jou, S., et al., "Electron Emission Characterization of Diamond Thin Films Grown from a Solid Carbon Source", Thin Solid Films, 280, (1996), 256-261.
Kato, Masataka, et al., "Read-Disturb Degradation Mechanism due to Electron Trappping in the Tunnel Oxide for Low-voltage Flash Memories", IEEE Electron Device Meeting, (1994), pp. 45-48.
Kothandaraman, M., et al., "Reactive Ion Etching of Trenches in 6H-SiC", J. Electronic Materials, 25, (1996), 875-878.
Kumbhar, A., et al., "Growth of Clean Amorphous Silicon-Carbon Alloy Films by Hot-Filament Assisted Chemical Vapor Deposition Technique", Applied Phys. Lett, 66, (Apr. 1995), 1741-1743.
Lakshmi, E., et al., "Interface-State Characteristics of GaN/GaAs MIS Capacitors", Solid-State Electronics, 25, (1982), 811-815.
Lanois, F., et al., "Angle Etch Control for Silicon Carbide Power Devices", Applied Phys. Lett., 69, (Jul. 1996), 236-238.
Leggieri, G., et al., "Laser Ablation Deposition of Silicon Carbide Films", Applied Surface Sceince, 96-98, (1996), 866-869.
Lei, T., et al., "Epitaxial Growth and Characterization of Zinc-Blende Gallium Nitride on (001) Silicon", J. Appl. Phys., 71, (May 1992), 4933-4943.
Lin, B., et al., "Dramatic Reduction of Sidegating in MODFET's ", IEEE Transactions on Electron Devices, 35, Abstract No. VA-6, (1988), p. 2451.
Liu, J., et al., "Formation of SiC Films on Silicon Field Emitters", Materials Res. Soc. Symp. Proc., 311, San Francisco, CA, (Apr. 13-15, 1993).
Liu, J., et al., "Modification of Si Field Emitter Surfaces by Chemical Conversion to SiC", J. Vac. Sci. Technology, B12, (1994), 717-721.
Lott, J., et al., "Anisotropic thermionic emission of electrons contained in GaAs/AlAs floating gate device structures", Appl. Phys. Lett., 55(12), (1989), pp. 1226-1228.
Lott, J.A., et al., "Charge Storage in In AlAs/InGaAs/InP Floating Gate Heterostructures", Electronics Letters, 26, (Jul. 5, 1990), 972-973.
Luo, J., et al., "Localized Epitaxial Growth of Hexagonal and Cubic SiC Films on Si by Vacuum Annealing", Applied Phys. Lett., 69, (Aug. 1996), 916-918.
Martins, R., et al., "Transport Properties of Doped Silicon Oxycarbide Microcrystalline Films Produced by Spatial Separation Techniques", Solar Energy Materials and Solar Cells, 41-42, (1996), 493-517.
Martins, R., et al., "Wide Band Gap Microcrystalline Silicon Thin Films", Diffusion and Defect Data : Solid State Phenomena, 44-46, Part 1, Scitec Publications, (1995), 299-346.
Maury, F., et al., "Chemical Vapor Co-Deposition of C and SiC at Moderate Temperature for the Synthesis of Compositionally Modulated Si(x)C(1-x) Ceramic Layers", Surface and Coatings Technology, 76-77, (1995), 119-125.
McLane, G., et al., "High Etch Rates of SiC in Magnetron Enhanced SF (6) Plasmas", Applied Phys Lett., 68, (Jun. 1996), 3755-3757.
McLane, G., et al., "High Etch Rates of SiC in Magnetron Enhanced SF(6) Plasmas", Applied Phys. Lett., 68, (Jun. 1996), 3755-3757.
Mogab, C., et al., "Conversion of Si to Epitaxial SiC by Reaction with C(2)H(2)", J. Applied Physics, 45, (Mar. 1974), 1075-1084.
Mohammad, S.N., et al., "Emerging Gallium Nitride Based Devices", Proceedings of the IEEE, 83, (Oct. 1995), 1306-1355.
Molnar, R, et al., "Growth of Gallium Nitride by Electron-Cyclotron Resonance Plasma-Assisted Molecular-Beam Epitaxy: The Role of Charged Species", J. Appl. Phys., 76, (1994), 4587-4595.
Muller, K., et al., "Trench Storage Node Technology for Gigabit DRAM Generations", Digest IEEE International Electron Devices Meeting, San Francisco, CA, (Dec. 1996), 507-510.
Nakamura, J., et al., "CMOS Active Pixel Image Sensor with Simple Floating Gate Pixels", IEEE Transactions on Electron Devices, 42, (1995), 1693-1694.
Nemanich, P., et al., "Diamond Negative Electron Affinity Surfaces, Structures and Devices", Proc.: Third International Conference on Applications of Diamond Films and Related Materials, 1, Gaithersburg, MD, (1995), 17-24.
Nemanich, R., et al., "Negative Electron Affinity Surfaces of Aluminum Nitride and Diamond", Diamond and Related Materials, 5, (1996), 790-796.
Neudeck, P., et al., "Electrical Characterization of a JFET-Accessed GaAs Dynamic RAM Cell", IEEE Electron Device Letters, 10 11), (1989), pp. 477-480.
Ng, K., In: Completer Guide to Semiconductor Devices, McGraw-Hill, Inc. New York, (1995), pp.322-328, 605-608.
Ouyang, M., et al., "Deposition of Diamond-Like Carbon Films via Excimer Laser Ablation of Polybutadiene", Materials Science and Engineering, B39, (1996), 228-231.
Pankove, J., "Photoelectric Emission", In: Optical Processes in Semiconductors, Dover Publications Inc., New York, (1971), 287-301.
Pankove, J., et al., "Photoemission from GaN", Applied Phys. Lett., 25, (1974), 53-55.
Papadas, C., et al., "Modeling of the Intrinsic Retention Characteristics of FLOTOX EEPROM Cells Under Elevated Temperature Conditions", IEEE Transaction on Electron Devices, 42, (Apr. 1995), 678-682.
Patuwathavithane, C., et al., "Oxidation Studies for 6H-SiC", Proc: 4th Int. Conf. on Amorphous and Crystalline Silicon Carbide IV, Santa Clara, CA, (Oct. 9-11, 1991), 163-169.
Pereyra, I., et al., "Wide Gap a-Si(1-x)C(x): H Thin Films Obtained Under Starving Plasma Deposition Conditions", J. Non-Crystalline Solids, 201, (1996), 110-118.
Pollack, S., "Electron Transport Through Insulating Thin Films", Appl. Solid-State Scienc, 1, (1969), 345-355.
Prendergast, Jim., "Flash or DRAM: Memory Choice for the Future", IEEE Electron Device Meeting, Session25, Phoenix, AZ, (1995).
Qian, Q., et al., "Multi-Day Dynamic Storage of Holes at the AlAs/GaAs Interface", IEEE Electron Device Letters, EDL-7(11), (1986), pp. 607-609.
Rahman, M., et al., "Preparation and Electrical Properties of An Amorphous SiC/Crystalline Si p(+)n Heterostructure", Japanese J. Applied Physics, 23, (May 1984), 515-524.
Renlund, G., et al., "Silicon Oxycarbide Glasses: Part I. Preparation and Chemistry", Journal of Materials Research, 6, (Dec. 1991), 2716-2722.
Renlund, G., et al., "Silicon Oxycarbide Glasses: Part II. Structure and Properties", Journal of Materials Research, 6, (Dec. 1991), 2723-2734.
Ruska, W. S., "Microelectronic Processing", McGraw-Hill Book Co., (1987), 281.
S. P. Lau et al., Optoelectronic properties of highly conductive microcrystalline SiC produced by laser crystallisation of amorphous SiC., Journal Of Non-Crystalline Solids 198-200 (1966), pp 907-910.* *
Sakata, I., et al., "Amorphorous Silicon/Amorphous Silicon Carbide Heterojunctions Applied to Memory Device Structures", Electronics Letters, 30(9), (1994), 688-689.
Schmidt, I., et al., "Low Temperature Diamond Growth Using Fluorinated Hydrocarbons", Diamond and Related Materials, 5, (1996), 1318-1322.
Schoenfeld, O., et al., "Formation of Si Quantum dots in Nanocrystalline silicon", Proc.7th Int. Conf. on Modulated Semiconductor Structures, Madrid, (1995), pp. 605-608.
Serre, C., et al., "Ion-Beam Synthesis of Amorphous SiC Films: Structural Analysis and Recrystallization", J. Appl. Phys., 79, (May 1996), 6907-6913.
Sharma, B., et al., "Heterojunction Devices", In: Semiconductor Heterojunctions, Pergamon Press, New York, (1974), pp. 133-137.
Sim, S., et al., "A New Planar Stacked Technology (PST) for Scaled and Embedded DRAMs", Digest IEEE Int. Electron Devices Meeting, San Francisco, CA, (Dec. 1996), 504-507.
Streetman, B., In: Solid State Electronic Devices, 4th Edition, Prentice Hall, New Jersey, (1995), pp. 217-219, 392-394.
Suzaki, Y., et al., "Quantum Size Effects of a-Si(:H)/a-SiC(:H) Multilayer Films Prepared by rf Sputtering", Abstracts of Papers Published in the Int. J. Japenese Soc. for Precision Engineering, 28 , Abstract of Paper in vol. 60, (Jun. 1994), 182.
Svirkova, N., et al., "Deposition Conditions and Density-of-States Spectrum of a-Si(1-x)C(x) :H Films Obtained by Sputtering", Semiconductors, 28, (Dec. 1994), 1164-1169.
Sze, S., Physics of Semiconductors, 2nd Edition, John Wiley & Sons, Pub., New York, ISBN 0471056618, (1981).
Sze, S.M., In: Physics of Semiconductor Devices, Wiley-Interscience, New York, (1969), pp. 496-497.
Sze, S.M., In: Physics of Semiconductor Devices. 2nd Edition, John Wiley & Sons, New York, (1981), pp. 122-129, 700-703, 708-710, 763-765.
Tenhover, M., et al., "DC-Magnetron Sputtered Silicon Carbide", Materials Res. Soc. Symp. Proc., 356, Boston, MA, (Nov. 28 -Dec. 02, 1994), 227-232.
Thomas, J., et al., "Plasma Etching and Surface Analysis of a-SiC :H Films Deposited by Low Temperature Plasma Enhanced Chemical Vapor Deposition", Materials Res. Soc. Symp. Proc., 334, Boston, MA, (Nov. 29-Dec. 02, 1993), 445-450.
Tiwari, S., et al., "A silicon nanocrystal based memory", Appl. Physics Lett., 68, (1996), 1377-1379.
Tiwari, S., et al., "Volatile and Non-Volatile Memories in Silicon with Nano-Crystal Storage", Int'l Electron Devices Meeting: Technical Digest, Washington, DC, (Dec. 1995), 521-524.
Tsu, R., et al., "Tunneling in Nanoscale Silicon Particles Embedded in an a-SiO2 Matrix", Abstract, IEEE Devices Research Conference, (1996), pp. 178-179.
Tsu, R., et al., k"Tunneling in Nanoscale Silicon Particles Embedded in an a-SiO2 Matrix", Abstract, IEEE Devices Research Conference, (1996), pp. 178-179.
Tsu, Raphael, et al., "Slow Conductance oscillations in nanoscale silicon clusters of quantum dots", Appl. Phys. Lett., 65, (1994), pp. 842-844.
Tucker, C., et al., "Ion-beam-assisted Deposition of Nonhydrogenated a-Si:C Films", Can. J. Physics, 74, (1996), 97-101.
Van Der Weide, J., et al., "Negative-electron-affinity Effects on the Diamond (100) Surface", Physical Review B [Condensed Matter], 50, (Aug. 15, 1994), 5803-5806.
Vodakov, Y., et al., "Diffusion and Solubility of impurities in Silicon Carbide", In: Silicon Carbide, R.C. Marshall, et al., eds., Univ. of South Carolina Press, (1973), 508-519.
Wahab, Q., et al., "3C-SiC / Si / 3C-SiC Epitaxial Trilayer Films Deposited on Si (111) Substrates by Reactive Magnetron Sputtering", J. Materials Res., 10, Press, (1973), 508-519.
Wolf, "Semiconductor Memory Process Integration", Silicon Processing for the VLSI Era vol.2: Process Integration, Lattice Press, California, (1990), 623-626.
Wolf, S., "Semiconductor Memory Process Integration", Silicon Processsing for the VLSI Era, vol. 2: Process Integration, (1990), pp. 623-628.
Wolf, S., Silicon Processing for the VLSI Era, vol.3, Lattice Press, Sunset Beach, CA,(1995),311-312.
Wolter, S., et al., "Textured Growth of Diamond on Silicon via in situ Carburization and Bias-Enhanced Nucleation", Appl. Phys. Lett., 62, (Mar. 1993), 1215-1217.
Wu, K., et al., "The Growth and Characterization of Silicon/Silicon Carbide Heteroepitaxial Films on Silicon Substrates by Rapid Thermal Chemical Vapor Deposition", Japanese J. Appl. Phys., 35, (1996), 3836-3840.
Y, Hamakawa et al., Optoelectronics and photovoltaic Applications Of Microcrystalline SiC., Mat. Res Soc. Symp. Proc. vol. 164, 1960.* *
Y. Tauri, Flash Memory Features Simple Structure, Superior Integration, JEE Sep. 1993, pp 84-87.* *
Yamaguchi, Y., et al., "Properties of Heteroepitaxial 3C-SiC Films Grown by LPCVD", Digest of Tech. Papers: 8th Int. Conf. on Solid-State Sensors and Actuators and Eurosensors IX, vol.2, Stockholm, Sweden, (Jun. 1995), 190-193.
Yamanashi, H., et al., "Deposition of Silicon Compound Thin Films in DC Discharge Plasma Using Hydrogen-Hexamethyldisilane Gas Mixture", Proc.: Int. Symp. Surfaces and Thin Films of Electronic Materials Bull. of the Res. Institute of Electronics, Shizuoka University, 30, (1995), 95-98.
Ye, Qiu-Yi, et al., "Resonant Tunneling via Microcrystalline-silicon quantum confinement", Physical Rev. B, 44, (1991), pp. 1806-1811.
Yee, A., et al., "The Effect of Nitrogen on Pulsed Laser Deposition of Amorphous Silicon Carbide Films: Properties and Structure", J. Materials Research, 11, (1996), 1979-1986.
Yoder, M., "Wide Bandgap Semiconductor Materials and Devices", IEEE Transactions on Electron Devices, 43, (Oct. 1996), 1633-1636.
Zhao, X., et al., "Nanocrystalline Si: a material constructed by Si quantum dots", 1st Int. Conf. on Low Dimensional Structures and Devices, Singapore, (1995), pp. 467-471.
Zirinsky, S., et al., "Electrical Resistivity of Amorphous Silicon Resistor Films", Extended Abstracts of the Spring Meeting of the Electrochemical Society, Washington, DC, (1971), pp. 147-149.

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