US6649511B1 - Method of manufacturing a seed layer with annealed region for integrated circuit interconnects - Google Patents
Method of manufacturing a seed layer with annealed region for integrated circuit interconnects Download PDFInfo
- Publication number
- US6649511B1 US6649511B1 US10/272,760 US27276002A US6649511B1 US 6649511 B1 US6649511 B1 US 6649511B1 US 27276002 A US27276002 A US 27276002A US 6649511 B1 US6649511 B1 US 6649511B1
- Authority
- US
- United States
- Prior art keywords
- layer
- seed
- manufacturing
- integrated circuit
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
- H01L23/53252—Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/927—Electromigration resistant metallization
Definitions
- the present invention relates generally to semiconductor technology and more specifically to seed materials in semiconductor processing.
- dual damascene In one interconnection process, which is called a “dual damascene” technique, two channels of conductor materials are separated by interlayer dielectric layers in vertically separated planes perpendicular to each other and interconnected by a vertical connection, or “via”, at their closest point.
- the dual damascene technique is performed over the individual devices which are in a device dielectric layer with the gate and source/drain contacts, extending up through the device dielectric layer to contact one or more channels in a first channel dielectric layer.
- the first channel formation of the dual damascene process starts with the deposition of a thin first channel stop layer.
- the first channel stop layer is an etch stop layer which is subject to a photolithographic processing step which involves deposition, patterning, exposure, and development of a photoresist, and an anisotropic etching step through the patterned photoresist to provide openings to the device contacts.
- the photoresist is then stripped.
- a first channel dielectric layer is formed on the first channel stop layer.
- the first channel dielectric layer is of an oxide material, such as silicon oxide (SiO 2 )
- the first channel stop layer is a nitride, such as silicon nitride (SiN), so the two layers can be selectively etched.
- the first channel dielectric layer is then subject to further photolithographic process and etching steps to form first channel openings in the pattern of the first channels.
- the photoresist is then stripped.
- Adhesion layers for copper (Cu) conductor materials are composed of compounds such as tantalum nitride (TaN), titanium nitride (TiN), or tungsten nitride (WN).
- nitride compounds have good adhesion to the dielectric materials and provide good barrier resistance to the diffusion of copper from the copper conductor materials to the dielectric material. High barrier resistance is necessary with conductor materials such as copper to prevent diffusion of subsequently deposited copper into the dielectric layer, which can cause short circuits in the integrated circuit.
- pure refractory metals such as tantalum (Ta), titanium (Ti), or tungsten (W) are deposited on the adhesion layer to line the adhesion layer in the first channel openings.
- the refractory metals are good barrier materials, have lower electrical resistance than their nitrides, and have good adhesion to copper.
- the barrier material has sufficient adhesion to the dielectric material that the adhesion layer is not required, and in other cases, the adhesion and barrier material become integral.
- the adhesion and barrier layers are often collectively referred to as a “barrier” layer herein.
- a seed layer is deposited on the barrier layer and lines the barrier layer in the first channel openings.
- the seed layer generally of copper, is deposited to act as an electrode for the electroplating process.
- a first conductor material is deposited on the seed layer and fills the first channel opening.
- the first conductor material and the seed layer generally become integral, and are often collectively referred to as the conductor core when discussing the main current-carrying portion of the channels.
- a chemical-mechanical polishing (CMP) process is then used to remove the first conductor material, the seed layer, and the barrier layer above the first channel dielectric layer to form the first channels.
- CMP chemical-mechanical polishing
- the via formation step of the dual damascene process begins with the deposition of a thin via stop layer over the first channels and the first channel dielectric layer.
- the via stop layer is an etch stop layer which is subject to photolithographic processing and anisotropic etching steps to provide openings to the first channels.
- the photoresist is then stripped.
- a via dielectric layer is formed on the via stop layer.
- the via dielectric layer is of an oxide material, such as silicon oxide
- the via stop layer is a nitride, such as silicon nitride, so the two layers can be selectively etched.
- the via dielectric layer is then subject to further photolithographic process and etching steps to form the pattern of the vias.
- the photoresist is then stripped.
- a second channel dielectric layer is formed on the via dielectric layer.
- the via stop layer is a nitride, such as silicon nitride, so the two layers can be selectively etched.
- the second channel dielectric layer is then subject to further photolithographic process and etching steps to simultaneously form second channel and via openings in the pattern of the second channels and the vias.
- the photoresist is then stripped.
- An optional thin adhesion layer is deposited on the second channel dielectric layer and lines the second channel and the via openings.
- a barrier layer is then deposited on the adhesion layer and lines the adhesion layer in the second channel openings and the vias.
- a seed layer is deposited by electroless deposition on the barrier layer and lines the barrier layer in the second channel openings and the vias.
- a second conductor material is deposited on the seed layer and fills the second channel openings and the vias.
- a CMP process is then used to remove the second conductor material, the seed layer, and the barrier layer above the second channel dielectric layer to form the first channels.
- a layer is placed over the second channels as a final layer, it is called a “cap” layer and the “dual” damascene process is completed.
- the layer may be processed further for placement of additional levels of channels and vias over it.
- the use of the single and dual damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metallization process.
- the elimination of metal etch steps is important as the semiconductor industry moves from aluminum (Al) to other metallization materials, such as copper, which are very difficult to etch.
- EM electromigration
- This surface EM is particularly problematic with copper conductors and causes these voids to occur in different locations, but most often in the vias, and leads to open circuits.
- the present invention provides a method for manufacturing an integrated circuit having a semiconductor substrate with a semiconductor device.
- a dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer.
- a barrier layer is deposited to line the opening and is amorphized.
- a seed layer is deposited on the barrier layer and securely bonds to the barrier layer.
- a conductor layer is deposited to fill the channel opening over the barrier layer.
- a planarization technique is used to planarize the barrier, seed layer, and conductor layers to be coplanar with the dielectric layer to form a conductor channel.
- the seed layer is securely bonded to the barrier layer in an annealing process, which prevents electromigration along the surface between the seed and barrier layers.
- FIG. 1 is a plan view of aligned channels with a connecting via
- FIG. 2 (PRIOR ART) is a cross-section of FIG. 1 along line 2 — 2 ;
- FIG. 3 is a cross-section showing the barrier layer of the present invention.
- FIG. 4 is close-up of FIG. 3 of the barrier layer after deposition in accordance with the present invention.
- FIG. 5 is FIG. 4 after deposition and anneal of the seed layer in accordance with the present invention.
- FIG. 1 PRIOR ART
- the first and second channels 102 and 104 are respectively disposed in first and second dielectric layers 108 and 110 .
- the via 106 is an integral part of the second channel 104 and is disposed in a via dielectric layer 112 .
- horizontal as used in herein is defined as a plane parallel to the conventional plane or surface of a wafer, such as the semiconductor wafer 100 , regardless of the orientation of the wafer.
- vertical refers to a direction perpendicular to the horizontal as just defined. Terms, such as “on”, “above”, “below”, “side” (as in “sidewall”), “higher”, “lower”, “over”, and “under”, are defined with respect to the horizontal plane.
- FIG. 2 PRIOR ART
- a cross-section of FIG. 1 along line 2 — 2 .
- a portion of the first channel 102 is disposed in a first channel stop layer 114 and is on a device dielectric layer 116 .
- metal contacts are formed in the device dielectric layer 116 to connect to an operative semiconductor device (not shown). This is represented by the contact of the first channel 102 with a semiconductor contact 118 embedded in the device dielectric layer 116 .
- the various layers above the device dielectric layer 116 are sequentially: the first channel stop layer 114 , the first channel dielectric layer 108 , a via stop layer 120 , the via dielectric layer 112 , a second channel stop layer 122 , the second channel dielectric layer 110 , and a next channel stop layer 124 (not shown in FIG. 1 ).
- the first channel 102 includes a barrier layer 126 , which could optionally be a combined adhesion and barrier layer, and a seed layer 128 around a conductor core 130 .
- the second channel 104 and the via 106 include a barrier layer 132 , which could also optionally be a combined adhesion and barrier layer, and a seed layer 134 around a conductor core 136 .
- the barrier layers 126 and 132 are used to prevent diffusion of the conductor materials into the adjacent areas of the semiconductor device.
- the seed layers 128 and 134 form electrodes on which the conductor material of the conductor cores 130 and 136 is deposited.
- the seed layers 128 and 134 are of substantially the same conductor material of the conductor cores 130 and 136 and become part of the respective conductor cores 130 and 136 after the deposition.
- the deposition of the barrier layer 132 is such that it fills the bottom of the via 106 at barrier layer portion 138 so as to effectively separate the conductor cores 130 and 136 .
- barrier materials such as tantalum nitride (TaN), titanium nitride (TiN), or tungsten nitride (WN) were used as barrier materials to prevent diffusion.
- TaN tantalum nitride
- TiN titanium nitride
- WN tungsten nitride
- FIG. 3 therein is shown a cross-section similar to that shown in FIG. 2 (PRIOR ART) of a semiconductor wafer 200 of the present invention.
- the semiconductor wafer 200 has first and second channels 202 and 204 connected by a via 206 .
- the first and second channels 202 and 204 are respectively disposed in first and second dielectric layers 208 and 210 .
- the via 206 is a part of the second channel 204 and is disposed in a via dielectric layer 212 .
- a portion of the first channel 202 is disposed in a first channel stop layer 214 and is on a device dielectric layer 216 .
- metal contacts (not shown) are formed in the device dielectric layer 216 to connect to an operative semiconductor device (not shown). This is represented by the contact of the first channel 202 with a semiconductor device gate 218 embedded in the device dielectric layer 216 .
- the various layers above the device dielectric layer 216 are sequentially: the first channel stop layer 214 , the first channel dielectric layer 208 , a via stop layer 220 , the via dielectric layer 212 , a second channel stop layer 222 , the second channel dielectric layer 210 , and a next channel stop layer 224 .
- the first channel 202 includes a barrier layer 226 and a seed layer 228 around a conductor core 230 .
- the second channel 204 and the via 206 include a barrier layer 232 and a seed layer 234 around a conductor core 236 .
- the barrier layers 226 and 232 are used to prevent diffusion of the conductor materials into the adjacent areas of the semiconductor device.
- the seed layers 228 and 234 form electrodes on which the conductor material of the conductor cores 230 and 236 is deposited.
- the seed layers 228 and 234 are of substantially the same conductor material of the conductor cores 230 and 236 and become part of the respective conductor cores 230 and 236 after the deposition.
- the seed layers 228 and 234 are deposited and annealed so as to interlock with the barrier layers 226 and 232 , respectively, in annealed seed regions 240 and 242 , respectively, so as to prevent surface electro-migration.
- the barrier layer 226 is deposited by a process such as chemical vapor deposition or sputtering over silicon substrate of the wafer 200 on the device dielectric layer 216 .
- the barrier layer 226 is deposited with substantially planar upper and side surfaces, as exemplified by the smooth surface 244 .
- the seed layer 228 is deposited on the barrier layer 226 by a process such as physical vapor deposition or ionized metal plasma deposition, which leaves a smooth surface therebetween.
- FIG. 4 therein is shown FIG. 4 after deposition and anneal of the seed layer 228 in accordance with the present invention.
- the seed layer 228 is subjected to an anneal up to 400° C. for up to one hour followed by rapid cooling at a rate of more than 1° C. per second. Due to the mobility of the atoms of the conductor of the seed layer 228 during anneal, the smooth surface between the seed layer 228 and the barrier layer 226 will be roughened to interlock and form the annealed seed region 240 which is under 25% of the thickness of the seed layer 228 .
- the step at which the anneal is performed is not critical.
- the anneal may be performed after the deposition of each seed layer, after the deposition of the conductor cores, after one or more levels of interconnects, etc.
- the barrier layers are of materials such as tantalum (Ta), titanium (Ti), tungsten (W), compounds thereof, and combinations thereof.
- the seed layers (where used) are of materials such as copper (Cu), gold (Au), silver (Ag); compounds thereof and combinations thereof with one or more of the above elements.
- the conductor cores with or without seed layers are of materials such as copper, aluminum (Al), gold, silver, compounds thereof, and combinations thereof.
- the dielectric layers are of dielectric materials such as silicon oxide (SiO x ), tetraethoxysilane (TEOS), borophosphosilicate (BPSG) glass, etc.
- the stop layers and capping layers are of materials such as silicon nitride (Si x N x ) or silicon oxynitride (SiON).
Abstract
Description
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/272,760 US6649511B1 (en) | 2000-11-06 | 2002-10-16 | Method of manufacturing a seed layer with annealed region for integrated circuit interconnects |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US24630000P | 2000-11-06 | 2000-11-06 | |
US09/848,979 US6498397B1 (en) | 2000-11-06 | 2001-05-04 | Seed layer with annealed region for integrated circuit interconnects |
US10/272,760 US6649511B1 (en) | 2000-11-06 | 2002-10-16 | Method of manufacturing a seed layer with annealed region for integrated circuit interconnects |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/848,979 Division US6498397B1 (en) | 2000-11-06 | 2001-05-04 | Seed layer with annealed region for integrated circuit interconnects |
Publications (1)
Publication Number | Publication Date |
---|---|
US6649511B1 true US6649511B1 (en) | 2003-11-18 |
Family
ID=26937860
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/848,979 Expired - Lifetime US6498397B1 (en) | 2000-11-06 | 2001-05-04 | Seed layer with annealed region for integrated circuit interconnects |
US10/272,760 Expired - Lifetime US6649511B1 (en) | 2000-11-06 | 2002-10-16 | Method of manufacturing a seed layer with annealed region for integrated circuit interconnects |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/848,979 Expired - Lifetime US6498397B1 (en) | 2000-11-06 | 2001-05-04 | Seed layer with annealed region for integrated circuit interconnects |
Country Status (1)
Country | Link |
---|---|
US (2) | US6498397B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005106946A1 (en) * | 2004-04-30 | 2005-11-10 | Infineon Technologies Ag | Long-term annealed integrated circuit arrangements and method for producing the same |
US8304863B2 (en) | 2010-02-09 | 2012-11-06 | International Business Machines Corporation | Electromigration immune through-substrate vias |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7070687B2 (en) * | 2001-08-14 | 2006-07-04 | Intel Corporation | Apparatus and method of surface treatment for electrolytic and electroless plating of metals in integrated circuit manufacturing |
US7061095B2 (en) * | 2001-09-26 | 2006-06-13 | Intel Corporation | Printed circuit board conductor channeling |
US7622382B2 (en) * | 2006-03-29 | 2009-11-24 | Intel Corporation | Filling narrow and high aspect ratio openings with electroless deposition |
US9721889B1 (en) * | 2016-07-26 | 2017-08-01 | Globalfoundries Inc. | Middle of the line (MOL) metal contacts |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5391517A (en) * | 1993-09-13 | 1995-02-21 | Motorola Inc. | Process for forming copper interconnect structure |
US5674787A (en) * | 1996-01-16 | 1997-10-07 | Sematech, Inc. | Selective electroless copper deposited interconnect plugs for ULSI applications |
US5677244A (en) * | 1996-05-20 | 1997-10-14 | Motorola, Inc. | Method of alloying an interconnect structure with copper |
US5747360A (en) * | 1993-09-17 | 1998-05-05 | Applied Materials, Inc. | Method of metalizing a semiconductor wafer |
US5939788A (en) * | 1998-03-11 | 1999-08-17 | Micron Technology, Inc. | Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with cooper |
US6096648A (en) * | 1999-01-26 | 2000-08-01 | Amd | Copper/low dielectric interconnect formation with reduced electromigration |
US6159853A (en) * | 1999-08-04 | 2000-12-12 | Industrial Technology Research Institute | Method for using ultrasound for assisting forming conductive layers on semiconductor devices |
US6181012B1 (en) * | 1998-04-27 | 2001-01-30 | International Business Machines Corporation | Copper interconnection structure incorporating a metal seed layer |
US6218302B1 (en) * | 1998-07-21 | 2001-04-17 | Motorola Inc. | Method for forming a semiconductor device |
US6268291B1 (en) * | 1995-12-29 | 2001-07-31 | International Business Machines Corporation | Method for forming electromigration-resistant structures by doping |
US6297158B1 (en) * | 2000-05-31 | 2001-10-02 | Taiwan Semiconductor Manufacturing Company | Stress management of barrier metal for resolving CU line corrosion |
US6440849B1 (en) * | 1999-10-18 | 2002-08-27 | Agere Systems Guardian Corp. | Microstructure control of copper interconnects |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0199078B1 (en) * | 1985-04-11 | 1989-06-07 | Siemens Aktiengesellschaft | Integrated semiconductor circuit having an aluminium or aluminium alloy contact conductor path and an intermediate tantalum silicide layer as a diffusion barrier |
JPS6373660A (en) * | 1986-09-17 | 1988-04-04 | Fujitsu Ltd | Semiconductor device |
US4990997A (en) * | 1988-04-20 | 1991-02-05 | Fujitsu Limited | Crystal grain diffusion barrier structure for a semiconductor device |
JP3119957B2 (en) * | 1992-11-30 | 2000-12-25 | 株式会社東芝 | Method for manufacturing semiconductor device |
US6136682A (en) * | 1997-10-20 | 2000-10-24 | Motorola Inc. | Method for forming a conductive structure having a composite or amorphous barrier layer |
US6140234A (en) * | 1998-01-20 | 2000-10-31 | International Business Machines Corporation | Method to selectively fill recesses with conductive metal |
US6281121B1 (en) * | 1998-03-06 | 2001-08-28 | Advanced Micro Devices, Inc. | Damascene metal interconnects using highly directional deposition of barrier and/or seed layers including (III) filling metal |
US6093966A (en) * | 1998-03-20 | 2000-07-25 | Motorola, Inc. | Semiconductor device with a copper barrier layer and formation thereof |
US6130156A (en) * | 1998-04-01 | 2000-10-10 | Texas Instruments Incorporated | Variable doping of metal plugs for enhanced reliability |
US6331484B1 (en) * | 1999-03-29 | 2001-12-18 | Lucent Technologies, Inc. | Titanium-tantalum barrier layer film and method for forming the same |
-
2001
- 2001-05-04 US US09/848,979 patent/US6498397B1/en not_active Expired - Lifetime
-
2002
- 2002-10-16 US US10/272,760 patent/US6649511B1/en not_active Expired - Lifetime
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5391517A (en) * | 1993-09-13 | 1995-02-21 | Motorola Inc. | Process for forming copper interconnect structure |
US5747360A (en) * | 1993-09-17 | 1998-05-05 | Applied Materials, Inc. | Method of metalizing a semiconductor wafer |
US6268291B1 (en) * | 1995-12-29 | 2001-07-31 | International Business Machines Corporation | Method for forming electromigration-resistant structures by doping |
US5674787A (en) * | 1996-01-16 | 1997-10-07 | Sematech, Inc. | Selective electroless copper deposited interconnect plugs for ULSI applications |
US5677244A (en) * | 1996-05-20 | 1997-10-14 | Motorola, Inc. | Method of alloying an interconnect structure with copper |
US5939788A (en) * | 1998-03-11 | 1999-08-17 | Micron Technology, Inc. | Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with cooper |
US6181012B1 (en) * | 1998-04-27 | 2001-01-30 | International Business Machines Corporation | Copper interconnection structure incorporating a metal seed layer |
US6218302B1 (en) * | 1998-07-21 | 2001-04-17 | Motorola Inc. | Method for forming a semiconductor device |
US6096648A (en) * | 1999-01-26 | 2000-08-01 | Amd | Copper/low dielectric interconnect formation with reduced electromigration |
US6159853A (en) * | 1999-08-04 | 2000-12-12 | Industrial Technology Research Institute | Method for using ultrasound for assisting forming conductive layers on semiconductor devices |
US6440849B1 (en) * | 1999-10-18 | 2002-08-27 | Agere Systems Guardian Corp. | Microstructure control of copper interconnects |
US6297158B1 (en) * | 2000-05-31 | 2001-10-02 | Taiwan Semiconductor Manufacturing Company | Stress management of barrier metal for resolving CU line corrosion |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005106946A1 (en) * | 2004-04-30 | 2005-11-10 | Infineon Technologies Ag | Long-term annealed integrated circuit arrangements and method for producing the same |
US20070105366A1 (en) * | 2004-04-30 | 2007-05-10 | Oliver Aubel | Long-term heat-treated integrated circuit arrangements and methods for producing the same |
CN101626012B (en) * | 2004-04-30 | 2012-09-05 | 英飞凌科技股份公司 | Long-term annealed integrated circuit arrangements and method for producing the same |
US8643183B2 (en) | 2004-04-30 | 2014-02-04 | Infineon Technologies Ag | Long-term heat-treated integrated circuit arrangements and methods for producing the same |
DE102004021239B4 (en) * | 2004-04-30 | 2017-04-06 | Infineon Technologies Ag | Long annealed integrated circuit arrangements and their manufacturing processes |
US8304863B2 (en) | 2010-02-09 | 2012-11-06 | International Business Machines Corporation | Electromigration immune through-substrate vias |
US9153558B2 (en) | 2010-02-09 | 2015-10-06 | International Business Machines Corporation | Electromigration immune through-substrate vias |
Also Published As
Publication number | Publication date |
---|---|
US6498397B1 (en) | 2002-12-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6972254B1 (en) | Manufacturing a conformal atomic liner layer in an integrated circuit interconnect | |
US6989604B1 (en) | Conformal barrier liner in an integrated circuit interconnect | |
US7253097B2 (en) | Integrated circuit system using dual damascene process | |
US6555909B1 (en) | Seedless barrier layers in integrated circuits and a method of manufacture therefor | |
US6406996B1 (en) | Sub-cap and method of manufacture therefor in integrated circuit capping layers | |
US6465867B1 (en) | Amorphous and gradated barrier layer for integrated circuit interconnects | |
US6348410B1 (en) | Low temperature hillock suppression method in integrated circuit interconnects | |
US6642145B1 (en) | Method of manufacturing an integrated circuit with a dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers | |
US6500754B1 (en) | Anneal hillock suppression method in integrated circuit interconnects | |
US6674170B1 (en) | Barrier metal oxide interconnect cap in integrated circuits | |
US6403466B1 (en) | Post-CMP-Cu deposition and CMP to eliminate surface voids | |
US6531780B1 (en) | Via formation in integrated circuit interconnects | |
US6482755B1 (en) | HDP deposition hillock suppression method in integrated circuits | |
US6583051B2 (en) | Method of manufacturing an amorphized barrier layer for integrated circuit interconnects | |
WO2002056364A2 (en) | Conductor reservoir volume for integrated circuit interconnects | |
US6649511B1 (en) | Method of manufacturing a seed layer with annealed region for integrated circuit interconnects | |
US6417566B1 (en) | Void eliminating seed layer and conductor core integrated circuit interconnects | |
US6541286B1 (en) | Imaging of integrated circuit interconnects | |
US6518648B1 (en) | Superconductor barrier layer for integrated circuit interconnects | |
US6841473B1 (en) | Manufacturing an integrated circuit with low solubility metal-conductor interconnect cap | |
US6590288B1 (en) | Selective deposition in integrated circuit interconnects | |
US6479898B1 (en) | Dielectric treatment in integrated circuit interconnects | |
US6501177B1 (en) | Atomic layer barrier layer for integrated circuit interconnects | |
US20020127849A1 (en) | Method of manufacturing dual damascene structure | |
US6455938B1 (en) | Integrated circuit interconnect shunt layer |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
CC | Certificate of correction | ||
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: AFFIRMATION OF PATENT ASSIGNMENT;ASSIGNOR:ADVANCED MICRO DEVICES, INC.;REEL/FRAME:023119/0083 Effective date: 20090630 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, DELAWARE Free format text: SECURITY AGREEMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049490/0001 Effective date: 20181127 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:054633/0001 Effective date: 20201022 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001 Effective date: 20201117 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001 Effective date: 20201117 |