US6319775B1 - Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device - Google Patents

Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device Download PDF

Info

Publication number
US6319775B1
US6319775B1 US09/433,037 US43303799A US6319775B1 US 6319775 B1 US6319775 B1 US 6319775B1 US 43303799 A US43303799 A US 43303799A US 6319775 B1 US6319775 B1 US 6319775B1
Authority
US
United States
Prior art keywords
oxide layer
silicon oxide
gate electrode
nitrogen
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US09/433,037
Inventor
Arvind Halliyal
Robert B. Ogle
Susan G. Kim
Kenneth Au
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Morgan Stanley Senior Funding Inc
Monterey Research LLC
Spansion Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US09/433,037 priority Critical patent/US6319775B1/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Assigned to ADVANCED MICRO DEVICES, INC. reassignment ADVANCED MICRO DEVICES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OGLE, ROBERT B., KIM, SUSAN G., AU, KENNETH, HALLIYAL, ARVIND
Application granted granted Critical
Publication of US6319775B1 publication Critical patent/US6319775B1/en
Assigned to SPANSION INC. reassignment SPANSION INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ADVANCED MICRO DEVICES, INC.
Assigned to SPANSION LLC reassignment SPANSION LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SPANSION INC.
Assigned to BARCLAYS BANK PLC reassignment BARCLAYS BANK PLC SECURITY AGREEMENT Assignors: SPANSION INC., SPANSION LLC, SPANSION TECHNOLOGY INC., SPANSION TECHNOLOGY LLC
Assigned to SPANSION LLC, SPANSION TECHNOLOGY LLC, SPANSION INC. reassignment SPANSION LLC RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: BARCLAYS BANK PLC
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. reassignment MORGAN STANLEY SENIOR FUNDING, INC. SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CYPRESS SEMICONDUCTOR CORPORATION, SPANSION LLC
Assigned to CYPRESS SEMICONDUCTOR CORPORATION reassignment CYPRESS SEMICONDUCTOR CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SPANSION, LLC
Assigned to SPANSION LLC, CYPRESS SEMICONDUCTOR CORPORATION reassignment SPANSION LLC PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Assignors: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Assigned to MONTEREY RESEARCH, LLC reassignment MONTEREY RESEARCH, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CYPRESS SEMICONDUCTOR CORPORATION
Anticipated expiration legal-status Critical
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. reassignment MORGAN STANLEY SENIOR FUNDING, INC. CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Assignors: CYPRESS SEMICONDUCTOR CORPORATION, SPANSION LLC
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides

Definitions

  • the present invention relates generally to non-volatile memory devices and to methods for their fabrication and, more particularly, to the fabrication of ONO layers in non-volatile memory devices.
  • Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated.
  • Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices.
  • EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased.
  • Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
  • an EEPROM device typically includes a floating-gate electrode upon which electrical charge is stored.
  • the floating-gate electrode overlies a channel region residing between source and drain regions in a semiconductor substrate.
  • the floating-gate electrode together with the source and drain regions forms an enhancement transistor.
  • the threshold voltage of the enhancement transistor is brought to a relatively high value.
  • the threshold voltage of the enhancement transistor is brought to a relatively low value.
  • the threshold level of the enhancement transistor determines the current flow through the transistor when the transistor is turned on by the application of appropriate voltages to the gate and drain. When the threshold voltage is high, no current will flow through the transistor, which is defined as a logic 0 state. Correspondingly, when the threshold voltage is low, current will flow through the transistor, which is defined as a logic 1 state.
  • a flash EEPROM device electrons are transferred to a floating-gate electrode through a dielectric layer overlying the channel region of the enhancement transistor.
  • the electron transfer is initiated by either hot electron injection, or by Fowler-Nordheim tunneling.
  • a voltage potential is applied to the floating-gate by an overlying control-gate electrode.
  • the control-gate electrode is capacitively coupled to the floating-gate electrode, such that a voltage applied on the control-gate electrode is coupled to the floating-gate electrode.
  • the flash EEPROM device is programmed by applying a high positive voltage to the control-gate electrode, and a lower positive voltage to the drain region, which transfers electrons from the channel region to the floating-gate electrode.
  • the flash EEPROM device is erased by grounding the control-gate electrode and applying a high positive voltage through either the source or drain region of the enhancement transistor. Under erase voltage conditions, electrons are removed from the floating-gate electrode and transferred into either the source or drain regions in the semiconductor substrate.
  • oxide-nitride-oxide One important dielectric material for the fabrication of the floating-gate electrode is an oxide-nitride-oxide (ONO) structure.
  • ONO oxide-nitride-oxide
  • During programming electrical charge is transferred from the substrate to the silicon nitride layer in the ONO structure. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom silicon dioxide layer and become trapped in the silicon nitride layer. Electrons are trapped near the drain region because the electric fields are the strongest near the drain. Reversing the potentials applied to the source and drain will cause electrons to travel along the channel in the opposite direction and be injected into the silicon nitride layer near the source region.
  • ONO oxide-nitride-oxide
  • silicon nitride is not electrically conductive, the charge introduced into the silicon nitride layer tends to remain localized. Accordingly, depending upon the application of voltage potentials, electrical charge can be stored in discrete regions within a single continuous silicon nitride layer.
  • Non-volatile memory designers have taken advantage of the localized nature of electron storage within a silicon nitride layer and have designed memory circuits that utilize two regions of stored charge within an ONO layer.
  • This type of non-volatile memory device is known as a two-bit EEPROM.
  • the two-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size.
  • a left and right bit is stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell. Programming methods are then used that enable two-bits to be programmed and read simultaneously.
  • the two-bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions.
  • the present invention is for a process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device.
  • Fabrication of a two-bit EEPROM device using an ONO floating-gate electrode requires the formation of a high quality ONO structure. This is because proper functionality of the two-bit EEPROM device requires localized charge storage within the ONO structure.
  • the top oxide layer must have a density sufficient to minimize the formation of charge traps. The formation of charge traps in the top oxide layer can lead to undesirable charge leakage within the top oxide layer and at the interface between the top oxide layer and the underlying silicon nitride layer. In a properly formed ONO structure, all electrical charge is stored in the silicon nitride layer. By fabricating a high quality top oxide layer, stored charge in the ONO structure remains localized within predetermined regions in the silicon nitride layer.
  • a process for fabricating an ONO floating-gate electrode includes providing a semiconductor substrate, and thermally growing a first silicon oxide layer on the semiconductor substrate. Then, a silicon nitride layer is formed to overlie the first silicon oxide layer. A second layer of silicon oxide is then formed to overlie the silicon nitride layer using an oxidation process. After forming the second silicon oxide layer, a nitridation process is carried out to transform second silicon oxide layer into a nitrogenated silicon oxide layer. The nitridation process is preferably carried out by annealing semiconductor substrate 16 in a nitrogen-containing gas atmosphere.
  • FIG. 1 illustrates, in cross-section, a portion of a semiconductor substrate containing a floating-gate transistor that incorporates an ONO structure fabricated in accordance with the invention
  • FIGS. 2-4 illustrate, in cross-section, process steps for the fabrication of an ONO structure in accordance with the invention.
  • FIG. 1 Shown in FIG. 1, in cross-section, is a floating-gate transistor 10 suitable for use in a two-bit EEPROM device.
  • Floating-gate transistor 10 includes source/drain regions 12 and 14 located in a semiconductor substrate 16 and separated by a channel region 18 .
  • First and second bit line oxide regions 20 and 22 overlie source/drain regions 12 and 14 , respectively.
  • a control gate electrode 24 overlies channel region 18 and is separated therefrom by an ONO structure 26 .
  • Control gate electrode 24 and ONO structure 26 form a stacked-gate structure.
  • ONO structure 26 includes a first silicon oxide layer 28 overlying channel region 18 .
  • a silicon nitride layer 30 overlies first silicon oxide layer 28 .
  • a second silicon oxide layer (or top oxide layer) 32 overlies silicon nitride layer 30 .
  • floating-gate transistor 10 In the operation of floating-gate transistor 10 , voltages are applied to control-gate electrode 24 and to source/drain regions 12 and 14 that cause electrical charge from source/drain regions 12 and 14 to propagate across channel region 18 . Once the charge encounters a sufficiently strong vertical field, the charge is either injected or tunnels from channel region 18 into silicon nitride layer 30 . For example, depending upon the particular voltage levels applied to control-gate electrode 24 and to source/drain regions 12 and 14 , electrical charge 34 is transferred into silicon nitride layer 30 and is localized to regions in proximity to either source/drain region 12 , or source/drain region 14 .
  • a two-bit EEPROM device necessarily requires that electrical charge 34 remain isolated in the regions of silicon nitride layer 30 to which it is initially introduced.
  • the proper maintenance of electrical charge 34 in localized regions of silicon nitride layer 30 is critical to the proper performance of a two-bit EEPROM device.
  • the quality of ONO structure 26 must be such that charge leakage paths are minimized at the interface between the first and second silicon oxide layers 28 and 32 , and silicon nitride layer.
  • second silicon oxide layer 32 must be of sufficient density, such that charge trapping sites are minimized within the silicon oxide material.
  • charge leakage within ONO structure 26 is minimized by forming a high-quality nitrogenated top oxide layer.
  • the reduced charge leakage and improved floating-gate transistor performance obtained by the present invention can be better understood following a description of an ONO fabrication process carried out in accordance with the invention.
  • first silicon dioxide layer 28 is formed to overlie the surface of semiconductor substrate 16 .
  • semiconductor substrate 16 is a single crystal silicon substrate.
  • Semiconductor substrate 16 has an upper surface 36 previously processed to remove debris and native oxides.
  • first silicon oxide layer 28 is formed by thermally oxidizing surface 36 at an elevated temperature in the presence of dry molecular oxygen.
  • the oxidation process is carried out at a temperature of about 900 to about 1100° C.
  • the oxidation process forms a silicon oxide layer preferably having a thickness of about 50 to about 150 angstroms, and more preferably a thickness of about 100 angstroms.
  • the oxidation process can be carried out in either a batch-type thermal oxidation furnace, or alternatively, in a single-wafer oxidation apparatus.
  • silicon nitride layer 30 is formed to overlie first silicon oxide layer 28 , as illustrated in FIG. 3 .
  • silicon nitride layer 30 is formed by means of a rapid-thermal-chemical-vapor-deposition (RTCVD) process.
  • the RTCVD process is carried out at a temperature of about 700 to about 800° C.
  • the silicon nitride material is formed by reacting ammonia (NH 3 ) with either dichlorosilane (SiCl 2 H 2 ) or silane (SiH 4 ).
  • NH 3 ammonia
  • SiCl 2 H 2 dichlorosilane
  • SiH 4 silane
  • the processes is carried out for a period of time and at gas flow rates sufficient to form a silicon nitride layer preferably having a thickness of about 50 to about 150 angstroms, and more preferably about 100 angstroms.
  • ammonia is introduced in the RTCVD apparatus at a flow rate of about 1 standard liter per minute (slpm) and either dichlorosilane or silane is introduced at a flow rate of about 30 to about 50 standard-cubic-centimeters-per-minute (sccm).
  • the RTCVD process is carried out in three steps including an initial temperature ramp, a deposition step, and cool-down step.
  • the total residence time of substrate 16 in the RTCVD apparatus is about 3 minutes.
  • the silicon nitride deposition step is completed in about 2 minutes.
  • silicon nitride layer 30 can be formed by means of a low-pressure-chemical-vapor-deposition (LPCVD) process.
  • LPCVD low-pressure-chemical-vapor-deposition
  • the silicon nitride can be formed in a batch deposition apparatus.
  • the LPCVD process is preferably carried out at a pressure of about 200 to about 500 millitor (mtorr), at temperatures 700-800° C. using ammonia and either dichlorosilane or silane gas.
  • second silicon oxide layer 32 is formed to overlie silicon nitride layer 30 , as illustrated in FIG. 4 .
  • second silicon oxide layer 32 is formed by either an RTCVD or an LPCVD process.
  • the second silicon oxide layer 32 is formed in an RTCVD apparatus using nitrous oxide (N 2 O) and dichlorosilane.
  • the RTCVD processes preferably carried out at a temperature of about 700 to about 800° C. and for a total processing time of about 3 minutes.
  • a three-step deposition sequence is used including a ramp up step, a deposition step, and a cool down step.
  • the total processing time in the RTCVD apparatus is about 3 minutes.
  • about 1 to about 3 slpm, and more preferably, about 2 slpm of nitrous oxide is used.
  • about 25 to about 75 sccm, and more preferably, about 50 sccm of dichlorosilane is used.
  • the RTCVD process forms a silicon oxide layer having a preferred thickness of about 50 to about 150 angstroms, and more preferably about 100 angstroms.
  • the second oxide is deposited on nitride in a batch type of furnace at temperatures of 700-800° C.
  • the foregoing RTCVD process for the formation of both the silicon nitride layer and the top oxide layer advantageously provides an in-situ process for the sequential formation of individual layers within the ONO structure.
  • the formation of silicon nitride layer 30 and second silicon oxide layer 32 in a sequential, in-situ deposition sequence minimizes contamination at the silicon nitride/silicon oxide interface.
  • uncontrolled native oxidation can be reduced to insure that a single, high-density silicon oxide layer is deposited over silicon nitride layer 30 .
  • An important aspect of the invention includes the sequential formation of silicon nitride layer 30 and second silicon oxide layer 32 in the absence of exposure of silicon nitride layer 30 to ambient atmosphere.
  • substrate 16 is transferred to an oxide deposition chamber under vacuum conditions without exposing the substrate to ambient atmosphere.
  • a positive-pressure inert gas atmosphere can be introduced during wafer transfer.
  • the in-situ nitride and oxide deposition response can be carried out in a batch-type LPCVD system.
  • nitride layer 30 is not exposed to ambient atmosphere prior to the deposition of second silicon oxide layer 32 .
  • a cluster/tool apparatus can be used in which semiconductor substrate 16 is transferred from a nitride deposition chamber to an oxide deposition chamber in a continuous vacuum environment, or in a positive pressure inert gas atmosphere.
  • the nitride deposition and oxide deposition processes can be sequentially carried out in a single deposition chamber that is configured to receive various processing gases. Accordingly, all such variations and modifications are contemplated in the present invention.
  • a nitridation process is carried out to transform second silicon oxide layer into a nitrogenated silicon oxide layer.
  • the nitridation process is preferably carried out by annealing semiconductor substrate 16 in a nitrogen-containing gas atmosphere.
  • gases such as ammonia, nitrogen oxide (NO), and nitrous oxide can be introduced into a batch-type thermal annealing furnace.
  • An annealing process is then carried out at a temperature of preferably about 800° C. to about 1100° C.
  • the annealing process transforms second silicon oxide layer 32 into a nitrogenated silicon oxide layer having a nitrogen concentration of about 0 wt. % to about 10 wt. %.
  • the nitrogenation process is carried out in an RTCVD apparatus.
  • the same nitrogen-containing gases can be used in both the RTCVD process and the batch type furnace annealing process.
  • control-gate electrode 24 can be formed with polycrystalline silicon, amphorous silicon, a refractory metal silicide, and the like.

Abstract

A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a nitrogenated top oxide layer. The process includes the sequential formation of a silicon nitride layer and a top oxide layer using an in-situ LPCVD or RTCVD deposition process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. After forming the top oxide layer, an annealing process is carried out to diffuse nitrogen into the top oxide layer. The formation of a nitrogenated top oxide layer provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
Related subject matter is disclosed in the following co-pending and commonly assigned U.S. patent applications filed on an even date herewith, and are all herein incorporated by reference.
U.S. patent application Ser. No. 09/426,239, filed Oct. 25, 1999, now U.S. Pat. No. 6,218,227. “A METHOD TO GENERATE A MONOS TYPE FLASH CELL USING POLYCRYSTALLINE SILICON AS AN ONO TOP LAYER”.
U.S. patent application Ser. No. 09/426,255, filed Oct. 25, 1999, now U.S. Pat. No. 6,207,502. “METHOD OF USING SOURCE/DRAIN NITRIDE FOR PERIPHERY FIELD OXIDE AND BIT-LINE OXIDE”.
U.S. patent application Ser. No. 09/426,672, filed Oct. 25, 1999, now U.S. Pat. No. 6,265,268. “HIGH TEMPERATURE OXIDE DEPOSITION PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO-BIT EEPROM DEVICE”.
U.S. patent application Ser. No. 09/426,240, filed Oct. 25, 1999, now U.S. Pat. No. 6,180,538. “PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO-BIT EEPROM DEVICE USING RAPID-THERMAL-CHEMICAL-VAPOR-DEPOSITION”.
U.S. patent application Ser. No. 09/426,430, filed Oct. 25, 1999, now U.S. Pat. No. 6,248,628 “METHOD OF FABRICATING AN ONO DIELECTRIC BY NITRIDATION FOR MNOS MEMORY CELLS”.
U.S. patent application Ser. No. 09/433,041, filed Oct. 25, 1999. “PROCESS FOR FABRICATING AN ONO STRUCTURE HAVING A SILICON-RICH SILICON NITRIDE LAYER,”.
U.S. patent application Ser. No. 09/433,186, filed Oct. 25, 1999. “PROCESS FOR FABRICATING AN ONO STRUCTURE”.
FIELD OF THE INVENTION
The present invention relates generally to non-volatile memory devices and to methods for their fabrication and, more particularly, to the fabrication of ONO layers in non-volatile memory devices.
BACKGROUND OF THE INVENTION
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Typically, an EEPROM device includes a floating-gate electrode upon which electrical charge is stored. The floating-gate electrode overlies a channel region residing between source and drain regions in a semiconductor substrate. The floating-gate electrode together with the source and drain regions forms an enhancement transistor. By storing electrical charge on the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively high value. Correspondingly, when charge is removed from the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively low value. The threshold level of the enhancement transistor determines the current flow through the transistor when the transistor is turned on by the application of appropriate voltages to the gate and drain. When the threshold voltage is high, no current will flow through the transistor, which is defined as a logic 0 state. Correspondingly, when the threshold voltage is low, current will flow through the transistor, which is defined as a logic 1 state.
In a flash EEPROM device, electrons are transferred to a floating-gate electrode through a dielectric layer overlying the channel region of the enhancement transistor. The electron transfer is initiated by either hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage potential is applied to the floating-gate by an overlying control-gate electrode. The control-gate electrode is capacitively coupled to the floating-gate electrode, such that a voltage applied on the control-gate electrode is coupled to the floating-gate electrode. The flash EEPROM device is programmed by applying a high positive voltage to the control-gate electrode, and a lower positive voltage to the drain region, which transfers electrons from the channel region to the floating-gate electrode. The flash EEPROM device is erased by grounding the control-gate electrode and applying a high positive voltage through either the source or drain region of the enhancement transistor. Under erase voltage conditions, electrons are removed from the floating-gate electrode and transferred into either the source or drain regions in the semiconductor substrate.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. Many of the foregoing research goals can be addressed through development of materials and processes for the fabrication of the floating-gate electrode. Recently, development efforts have focused on dielectric materials for fabrication of the floating-gate electrode. Silicon nitride in combination with silicon dioxide is known to provide satisfactory dielectric separation between the control-gate electrode and the channel region of the enhancement transistor, while possessing electrical characteristics sufficient to store electrical charge.
One important dielectric material for the fabrication of the floating-gate electrode is an oxide-nitride-oxide (ONO) structure. During programming, electrical charge is transferred from the substrate to the silicon nitride layer in the ONO structure. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom silicon dioxide layer and become trapped in the silicon nitride layer. Electrons are trapped near the drain region because the electric fields are the strongest near the drain. Reversing the potentials applied to the source and drain will cause electrons to travel along the channel in the opposite direction and be injected into the silicon nitride layer near the source region. Because silicon nitride is not electrically conductive, the charge introduced into the silicon nitride layer tends to remain localized. Accordingly, depending upon the application of voltage potentials, electrical charge can be stored in discrete regions within a single continuous silicon nitride layer.
Non-volatile memory designers have taken advantage of the localized nature of electron storage within a silicon nitride layer and have designed memory circuits that utilize two regions of stored charge within an ONO layer. This type of non-volatile memory device is known as a two-bit EEPROM. The two-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size. A left and right bit is stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell. Programming methods are then used that enable two-bits to be programmed and read simultaneously. The two-bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions.
While the recent advances in EEPROM technology have enabled memory designers to double the memory capacity of EEPROM arrays using two-bit data storage, numerous challenges exist in the fabrication of material layers within these devices. In particular, the ONO layer must be carefully fabricated to avoid the creation of interface states that could provide charge leakage paths within the ONO layer. Accordingly, advances in ONO fabrication technology are necessary to insure proper charge isolation in ONO structures used in two-bit EEPROM devices.
SUMMARY OF THE INVENTION
The present invention is for a process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device. Fabrication of a two-bit EEPROM device using an ONO floating-gate electrode requires the formation of a high quality ONO structure. This is because proper functionality of the two-bit EEPROM device requires localized charge storage within the ONO structure. In particular, the top oxide layer must have a density sufficient to minimize the formation of charge traps. The formation of charge traps in the top oxide layer can lead to undesirable charge leakage within the top oxide layer and at the interface between the top oxide layer and the underlying silicon nitride layer. In a properly formed ONO structure, all electrical charge is stored in the silicon nitride layer. By fabricating a high quality top oxide layer, stored charge in the ONO structure remains localized within predetermined regions in the silicon nitride layer.
In one form, a process for fabricating an ONO floating-gate electrode includes providing a semiconductor substrate, and thermally growing a first silicon oxide layer on the semiconductor substrate. Then, a silicon nitride layer is formed to overlie the first silicon oxide layer. A second layer of silicon oxide is then formed to overlie the silicon nitride layer using an oxidation process. After forming the second silicon oxide layer, a nitridation process is carried out to transform second silicon oxide layer into a nitrogenated silicon oxide layer. The nitridation process is preferably carried out by annealing semiconductor substrate 16 in a nitrogen-containing gas atmosphere.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates, in cross-section, a portion of a semiconductor substrate containing a floating-gate transistor that incorporates an ONO structure fabricated in accordance with the invention; and
FIGS. 2-4 illustrate, in cross-section, process steps for the fabrication of an ONO structure in accordance with the invention.
It should be appreciated that for simplicity and clarity of illustration, elements shown in the Figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to each other for clarity. Further, where considered appropriate, reference numerals have been repeated among the Figures to indicate corresponding elements.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Shown in FIG. 1, in cross-section, is a floating-gate transistor 10 suitable for use in a two-bit EEPROM device. Floating-gate transistor 10 includes source/ drain regions 12 and 14 located in a semiconductor substrate 16 and separated by a channel region 18. First and second bit line oxide regions 20 and 22 overlie source/ drain regions 12 and 14, respectively. A control gate electrode 24 overlies channel region 18 and is separated therefrom by an ONO structure 26. Control gate electrode 24 and ONO structure 26 form a stacked-gate structure.
ONO structure 26 includes a first silicon oxide layer 28 overlying channel region 18. A silicon nitride layer 30 overlies first silicon oxide layer 28. A second silicon oxide layer (or top oxide layer) 32 overlies silicon nitride layer 30.
In the operation of floating-gate transistor 10, voltages are applied to control-gate electrode 24 and to source/ drain regions 12 and 14 that cause electrical charge from source/ drain regions 12 and 14 to propagate across channel region 18. Once the charge encounters a sufficiently strong vertical field, the charge is either injected or tunnels from channel region 18 into silicon nitride layer 30. For example, depending upon the particular voltage levels applied to control-gate electrode 24 and to source/ drain regions 12 and 14, electrical charge 34 is transferred into silicon nitride layer 30 and is localized to regions in proximity to either source/drain region 12, or source/drain region 14.
Those skilled in the art will recognize that the proper functioning of a two-bit EEPROM device necessarily requires that electrical charge 34 remain isolated in the regions of silicon nitride layer 30 to which it is initially introduced. The proper maintenance of electrical charge 34 in localized regions of silicon nitride layer 30 is critical to the proper performance of a two-bit EEPROM device. In particular, the quality of ONO structure 26 must be such that charge leakage paths are minimized at the interface between the first and second silicon oxide layers 28 and 32, and silicon nitride layer. Additionally, second silicon oxide layer 32 must be of sufficient density, such that charge trapping sites are minimized within the silicon oxide material.
In accordance with the invention, charge leakage within ONO structure 26 is minimized by forming a high-quality nitrogenated top oxide layer. The reduced charge leakage and improved floating-gate transistor performance obtained by the present invention can be better understood following a description of an ONO fabrication process carried out in accordance with the invention.
Referring to FIG. 2, first silicon dioxide layer 28 is formed to overlie the surface of semiconductor substrate 16. Preferably, semiconductor substrate 16 is a single crystal silicon substrate. Semiconductor substrate 16 has an upper surface 36 previously processed to remove debris and native oxides. Preferably, first silicon oxide layer 28 is formed by thermally oxidizing surface 36 at an elevated temperature in the presence of dry molecular oxygen. Preferably, the oxidation process is carried out at a temperature of about 900 to about 1100° C. The oxidation process forms a silicon oxide layer preferably having a thickness of about 50 to about 150 angstroms, and more preferably a thickness of about 100 angstroms. The oxidation process can be carried out in either a batch-type thermal oxidation furnace, or alternatively, in a single-wafer oxidation apparatus.
After forming first silicon oxide layer 28, silicon nitride layer 30 is formed to overlie first silicon oxide layer 28, as illustrated in FIG. 3.
Preferably, silicon nitride layer 30 is formed by means of a rapid-thermal-chemical-vapor-deposition (RTCVD) process. The RTCVD process is carried out at a temperature of about 700 to about 800° C. The silicon nitride material is formed by reacting ammonia (NH3) with either dichlorosilane (SiCl2H2) or silane (SiH4). The processes is carried out for a period of time and at gas flow rates sufficient to form a silicon nitride layer preferably having a thickness of about 50 to about 150 angstroms, and more preferably about 100 angstroms. In one embodiment of the invention, ammonia is introduced in the RTCVD apparatus at a flow rate of about 1 standard liter per minute (slpm) and either dichlorosilane or silane is introduced at a flow rate of about 30 to about 50 standard-cubic-centimeters-per-minute (sccm). The RTCVD process is carried out in three steps including an initial temperature ramp, a deposition step, and cool-down step. Preferably, the total residence time of substrate 16 in the RTCVD apparatus is about 3 minutes. Preferably, the silicon nitride deposition step is completed in about 2 minutes.
Alternatively, silicon nitride layer 30 can be formed by means of a low-pressure-chemical-vapor-deposition (LPCVD) process. In the alternative method, the silicon nitride can be formed in a batch deposition apparatus. The LPCVD process is preferably carried out at a pressure of about 200 to about 500 millitor (mtorr), at temperatures 700-800° C. using ammonia and either dichlorosilane or silane gas.
After forming silicon nitride layer 30, second silicon oxide layer 32 is formed to overlie silicon nitride layer 30, as illustrated in FIG. 4. In accordance with the invention, second silicon oxide layer 32 is formed by either an RTCVD or an LPCVD process. The second silicon oxide layer 32 is formed in an RTCVD apparatus using nitrous oxide (N2O) and dichlorosilane. The RTCVD processes preferably carried out at a temperature of about 700 to about 800° C. and for a total processing time of about 3 minutes. In similarity with the RTCVD process used to deposit silicon nitride layer 30, a three-step deposition sequence is used including a ramp up step, a deposition step, and a cool down step. The total processing time in the RTCVD apparatus is about 3 minutes. Preferably, during the deposition step about 1 to about 3 slpm, and more preferably, about 2 slpm of nitrous oxide is used. Additionally, about 25 to about 75 sccm, and more preferably, about 50 sccm of dichlorosilane is used. The RTCVD process forms a silicon oxide layer having a preferred thickness of about 50 to about 150 angstroms, and more preferably about 100 angstroms. In the LPCVD process, the second oxide is deposited on nitride in a batch type of furnace at temperatures of 700-800° C.
The foregoing RTCVD process for the formation of both the silicon nitride layer and the top oxide layer advantageously provides an in-situ process for the sequential formation of individual layers within the ONO structure. In particular, the formation of silicon nitride layer 30 and second silicon oxide layer 32 in a sequential, in-situ deposition sequence, minimizes contamination at the silicon nitride/silicon oxide interface. Additionally, uncontrolled native oxidation can be reduced to insure that a single, high-density silicon oxide layer is deposited over silicon nitride layer 30.
An important aspect of the invention includes the sequential formation of silicon nitride layer 30 and second silicon oxide layer 32 in the absence of exposure of silicon nitride layer 30 to ambient atmosphere. Following the deposition of silicon nitride layer 30 onto first silicon oxide layer 28, substrate 16 is transferred to an oxide deposition chamber under vacuum conditions without exposing the substrate to ambient atmosphere. Alternatively, a positive-pressure inert gas atmosphere can be introduced during wafer transfer. The in-situ nitride and oxide deposition response can be carried out in a batch-type LPCVD system.
Those skilled in the art will appreciate that various means exist for insuring that silicon nitride layer 30 is not exposed to ambient atmosphere prior to the deposition of second silicon oxide layer 32. For example, a cluster/tool apparatus can be used in which semiconductor substrate 16 is transferred from a nitride deposition chamber to an oxide deposition chamber in a continuous vacuum environment, or in a positive pressure inert gas atmosphere. Alternatively, the nitride deposition and oxide deposition processes can be sequentially carried out in a single deposition chamber that is configured to receive various processing gases. Accordingly, all such variations and modifications are contemplated in the present invention.
After forming the second silicon oxide layer, a nitridation process is carried out to transform second silicon oxide layer into a nitrogenated silicon oxide layer. The nitridation process is preferably carried out by annealing semiconductor substrate 16 in a nitrogen-containing gas atmosphere. In one embodiment, gases such as ammonia, nitrogen oxide (NO), and nitrous oxide can be introduced into a batch-type thermal annealing furnace. An annealing process is then carried out at a temperature of preferably about 800° C. to about 1100° C. The annealing process transforms second silicon oxide layer 32 into a nitrogenated silicon oxide layer having a nitrogen concentration of about 0 wt. % to about 10 wt. %.
In an alternative embodiment, the nitrogenation process is carried out in an RTCVD apparatus. The same nitrogen-containing gases can be used in both the RTCVD process and the batch type furnace annealing process.
Following the formation of ONO structure 26, the stacked-gate structure shown in FIG. 1 is completed by depositing a layer of gate forming material overlying second silicon oxide layer 32. A lithographic patterning and etching process is then carried out to define control-gate electrode 34 and an ONO floating-gate electrode. Those skilled in the art will recognize that various gate-forming materials can be used to fabricate control-gate electrode 24. For example, control-gate electrode 24 can be formed with polycrystalline silicon, amphorous silicon, a refractory metal silicide, and the like.
Thus, there has been disclosed in accordance with the invention a nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device that fully provides the advantages set forth above. Although the invention has been described and illustrated with reference to specific illustrative embodiments thereof, it is not intended that the invention be limited to those illustrative embodiments. Those skilled in the art will recognize that variations and modifications can be made without departing from the spirit of the invention. For example, the thicknesses of the individual layers making up the ONO structure can be varied from that described herein. It is therefore intended to include within the invention all such variations and modifications that fall within the scope of the appended claims and equivalents thereof.

Claims (14)

What is claimed is:
1. A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device comprising the steps of:
providing a semiconductor substrate;
forming a first silicon oxide layer overlying the semiconductor substrate;
forming a silicon nitride layer overlying the first silicon oxide layer;
forming a second silicon oxide layer overlying the silicon nitride layer by a first rapid thermal chemical vapor deposition process at a temperature from about 700° C. to about 800° C. using nitrous oxide and dichlorosilane; and
subjecting the second silicon oxide layer to a second rapid thermal chemical vapor deposition process with exposure to a nitrogen-containing gas to form a nitridated silicon oxide layer, and to form said ONO floating-gate electrode.
2. The process of claim 1, wherein subjecting the second silicon oxide layer to a second rapid thermal chemical vapor deposition process in a nitrogen-containing gas is carried out at a temperature from about 800° C. to about 1100° C.
3. The process of claim 1, wherein the nitrogen-containing gas is selected from the group consisting of ammonia, nitrogen oxide, and nitrous oxide.
4. The process of claim 1, further comprising:
prior to forming the second silicon oxide layer, transferring the semiconductor structure to an oxide deposition chamber under vacuum conditions to mitigate exposing the silicon nitride layer to ambient air.
5. The process of claim 1, wherein nitridating the second silicon oxide layer comprises flowing the nitrogen-containing gas into a rapid thermal chemical vapor deposition process apparatus.
6. The process of claim 1, wherein the step of forming a nitrogenated silicon oxide layer comprises forming a nitrogenated silicon oxide layer having a nitrogen concentration of about 0 wt. % to about 10 wt. %.
7. A process for fabricating a stacked-gate structure including an ONO floating-gate electrode in a two-bit EEPROM device comprising:
providing a semiconductor substrate having a first bit-line oxide layer and a second bit-line oxide layer therein separated by a substrate surface region;
forming the ONO floating-gate electrode on the substrate surface region comprising:
sequentially forming a first silicon oxide layer on the substrate surface region, a silicon nitride layer overlying the first silicon oxide layer, and a second silicon oxide layer overlying the silicon nitride layer; and
subjecting the second silicon oxide layer to a rapid thermal chemical vapor deposition process in a nitrogen-containing gas to form a nitridated silicon oxide layer, and to form said ONO floating-gate electrodes; and
depositing a control gate electrode layer overlying the ONO floating gate electrode to form a stacked-gate structure on the substrate surface region.
8. The process of claim 7, wherein subjecting the second silicon oxide layer to a rapid thermal chemical vapor deposition process in a nitrogen-containing gas is carried out at a temperature of about 700° C. to about 1000° C.
9. The process of claim 7, wherein the nitrogen-containing gas is selected from the group consisting of ammonia, nitrogen oxide, and nitrous oxide.
10. The process of claim 7, further comprising:
prior to forming the second silicon oxide layer, transferring the semiconductor structure to an oxide deposition chamber under vacuum conditions to mitigate exposing the silicon nitride layer to ambient air.
11. The process of claim 7, wherein nitridating the second silicon oxide layer comprises flowing the nitrogen-containing gas into a rapid thermal chemical vapor deposition process apparatus.
12. The process of claim 2, wherein the step of forming a nitrogenated silicon oxide layer comprises forming a nitrogenated silicon oxide layer having a nitrogen concentration of about 0 wt. % to about 10 wt. %.
13. A process for fabricating an ONO floating-gate electrode in a two-bit device comprising the steps of:
providing a semiconductor substrate having a silicon surface region;
depositing a bottom silicon oxide layer overlying the surface region;
depositing a silicon nitride layer overlying the bottom silicon oxide layer;
depositing a top silicon oxide layer overlying the silicon nitride layer by a first rapid thermal chemical vapor deposition process at a temperature from about 700° C. to about 800° C. using nitrous oxide and dichlorosilane; and
subjecting the top silicon layer to a second rapid thermal chemical vapor deposition process in a nitrogen-containing gas ambient selected from the group consisting of ammonia, nitrogen oxide, and nitrous oxide to form a nitridated silicon oxide layer having a nitrogen concentration from about 0 wt. % to about 10 wt. % to form said ONO floating-gate electrode,
wherein the second rapid thermal chemical vapor deposition process is carried out at a temperature from about 700° C. to about 1000° C.
14. The process of claim 13, further comprising:
prior to depositing the top silicon oxide layer, transferring the semiconductor structure to an oxide deposition chamber under vacuum conditions to mitigate exposing the silicon nitride layer to ambient air.
US09/433,037 1999-10-25 1999-10-25 Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device Expired - Lifetime US6319775B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/433,037 US6319775B1 (en) 1999-10-25 1999-10-25 Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/433,037 US6319775B1 (en) 1999-10-25 1999-10-25 Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device

Publications (1)

Publication Number Publication Date
US6319775B1 true US6319775B1 (en) 2001-11-20

Family

ID=23718607

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/433,037 Expired - Lifetime US6319775B1 (en) 1999-10-25 1999-10-25 Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device

Country Status (1)

Country Link
US (1) US6319775B1 (en)

Cited By (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6440797B1 (en) * 2001-09-28 2002-08-27 Advanced Micro Devices, Inc. Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SONOS flash memory
US6509231B1 (en) * 2002-01-04 2003-01-21 Macronix International Co., Ltd. Nitride ready only memory cell with two top oxide layers and the method for manufacturing the same
US6514831B1 (en) * 2001-11-14 2003-02-04 Macronix International Co., Ltd. Nitride read only memory cell
US20030054664A1 (en) * 2001-09-20 2003-03-20 Yoshirou Tsurugida Method for selectively oxidizing a silicon wafer
US6559014B1 (en) 2001-10-15 2003-05-06 Advanced Micro Devices, Inc. Preparation of composite high-K / standard-K dielectrics for semiconductor devices
US6562491B1 (en) 2001-10-15 2003-05-13 Advanced Micro Devices, Inc. Preparation of composite high-K dielectrics
US20030155582A1 (en) * 2002-02-19 2003-08-21 Maitreyee Mahajani Gate dielectric structures for integrated circuits and methods for making and using such gate dielectric structures
US6635584B2 (en) * 2001-12-28 2003-10-21 Texas Instruments Incorporated Versatile system for forming uniform wafer surfaces
US20030232507A1 (en) * 2002-06-12 2003-12-18 Macronix International Co., Ltd. Method for fabricating a semiconductor device having an ONO film
US6674138B1 (en) 2001-12-31 2004-01-06 Advanced Micro Devices, Inc. Use of high-k dielectric materials in modified ONO structure for semiconductor devices
US20040051134A1 (en) * 2002-09-12 2004-03-18 Chuch Jang Atomic layer deposition of interpoly oxides in a non-volatile memory device
US20040053468A1 (en) * 2002-09-12 2004-03-18 Zhong Dong Method for forming a protective buffer layer for high temperature oxide processing
US6709927B1 (en) * 2000-08-11 2004-03-23 Advanced Micro Devices, Inc. Process for treating ONO dielectric film of a floating gate memory cell
US20040069990A1 (en) * 2002-10-15 2004-04-15 Matrix Semiconductor, Inc. Thin film transistor with metal oxide layer and method of making same
US6740605B1 (en) * 2003-05-05 2004-05-25 Advanced Micro Devices, Inc. Process for reducing hydrogen contamination in dielectric materials in memory devices
US20040169218A1 (en) * 2002-11-27 2004-09-02 Randolph Mark W. Method and system for erasing a nitride memory device
US6790755B2 (en) 2001-12-27 2004-09-14 Advanced Micro Devices, Inc. Preparation of stack high-K gate dielectrics with nitrided layer
US20040185647A1 (en) * 2002-02-08 2004-09-23 Zhong Dong Floating gate nitridation
US20050064667A1 (en) * 2003-09-19 2005-03-24 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method
US20050067634A1 (en) * 2003-09-30 2005-03-31 Cay-Uwe Pinnow Nonvolatile integrated semiconductor memory
EP1552554A2 (en) * 2002-10-18 2005-07-13 Advanced Micro Devices, Inc. Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer
US20050156228A1 (en) * 2004-01-16 2005-07-21 Jeng Erik S. Manufacture method and structure of a nonvolatile memory
US20050179095A1 (en) * 2003-11-06 2005-08-18 Ching-Hsiang Hsu Non-volatile memory cell
US6949433B1 (en) 2003-02-07 2005-09-27 Fasl Llc Method of formation of semiconductor resistant to hot carrier injection stress
US6949481B1 (en) 2003-12-09 2005-09-27 Fasl, Llc Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device
US6955965B1 (en) 2003-12-09 2005-10-18 Fasl, Llc Process for fabrication of nitride layer with reduced hydrogen content in ONO structure in semiconductor device
US20060180916A1 (en) * 2003-07-30 2006-08-17 Koninklijke Philips Electronics N.V. Ground arch for wirebond ball grid arrays
US20060214256A1 (en) * 2003-04-28 2006-09-28 Masaaki Shinohara Semiconductor device and a method of manufacturing the same
US7115469B1 (en) 2001-12-17 2006-10-03 Spansion, Llc Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process
US20070093012A1 (en) * 2005-10-20 2007-04-26 Applied Materials, Inc. Method for fabricating a gate dielectric of a field effect transistor
US20070093013A1 (en) * 2005-10-20 2007-04-26 Chua Thai C Method for fabricating a gate dielectric of a field effect transistor
US7214593B2 (en) * 2001-02-01 2007-05-08 International Business Machines Corporation Passivation for improved bipolar yield
CN100353527C (en) * 2004-06-10 2007-12-05 旺宏电子股份有限公司 Method for producing elements with memory cells and memory cell array
US7365403B1 (en) * 2002-02-13 2008-04-29 Cypress Semiconductor Corp. Semiconductor topography including a thin oxide-nitride stack and method for making the same
US20080150003A1 (en) * 2006-12-20 2008-06-26 Jian Chen Electron blocking layers for electronic devices
US20080150009A1 (en) * 2006-12-20 2008-06-26 Nanosys, Inc. Electron Blocking Layers for Electronic Devices
US20090101965A1 (en) * 2006-12-20 2009-04-23 Nanosys, Inc. Electron blocking layers for electronic devices
WO2010042323A1 (en) * 2008-10-08 2010-04-15 Nanosys, Inc. Electron blocking layers for electronic devices
US20110241128A1 (en) * 2010-03-31 2011-10-06 Tokyo Electron Limited Multilayer sidewall spacer for seam protection of a patterned structure
US8664102B2 (en) 2010-03-31 2014-03-04 Tokyo Electron Limited Dual sidewall spacer for seam protection of a patterned structure
US8691647B1 (en) 2002-10-07 2014-04-08 Spansion Llc Memory devices containing a high-K dielectric layer

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5304829A (en) * 1989-01-17 1994-04-19 Kabushiki Kaisha Toshiba Nonvolatile semiconductor device
US5371028A (en) * 1993-08-02 1994-12-06 Chartered Semiconductor Manufacturing Pte Ltd. Method for making single transistor non-volatile electrically alterable semiconductor memory device
US5496753A (en) * 1992-05-29 1996-03-05 Citizen Watch, Co., Ltd. Method of fabricating a semiconductor nonvolatile storage device
US5851881A (en) * 1997-10-06 1998-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making monos flash memory for multi-level logic
US5888870A (en) * 1997-10-22 1999-03-30 Advanced Micro Devices, Inc. Memory cell fabrication employing an interpoly gate dielectric arranged upon a polished floating gate
US5966603A (en) * 1997-06-11 1999-10-12 Saifun Semiconductors Ltd. NROM fabrication method with a periphery portion
US6063666A (en) * 1998-06-16 2000-05-16 Advanced Micro Devices, Inc. RTCVD oxide and N2 O anneal for top oxide of ONO film
US6069041A (en) * 1996-11-27 2000-05-30 Sharp Kabushiki Kaisha Process for manufacturing non-volatile semiconductor memory device by introducing nitrogen atoms
US6074917A (en) * 1998-06-16 2000-06-13 Advanced Micro Devices, Inc. LPCVD oxide and RTA for top oxide of ONO film to improve reliability for flash memory devices

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5304829A (en) * 1989-01-17 1994-04-19 Kabushiki Kaisha Toshiba Nonvolatile semiconductor device
US5496753A (en) * 1992-05-29 1996-03-05 Citizen Watch, Co., Ltd. Method of fabricating a semiconductor nonvolatile storage device
US5371028A (en) * 1993-08-02 1994-12-06 Chartered Semiconductor Manufacturing Pte Ltd. Method for making single transistor non-volatile electrically alterable semiconductor memory device
US6069041A (en) * 1996-11-27 2000-05-30 Sharp Kabushiki Kaisha Process for manufacturing non-volatile semiconductor memory device by introducing nitrogen atoms
US5966603A (en) * 1997-06-11 1999-10-12 Saifun Semiconductors Ltd. NROM fabrication method with a periphery portion
US5851881A (en) * 1997-10-06 1998-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making monos flash memory for multi-level logic
US5888870A (en) * 1997-10-22 1999-03-30 Advanced Micro Devices, Inc. Memory cell fabrication employing an interpoly gate dielectric arranged upon a polished floating gate
US6063666A (en) * 1998-06-16 2000-05-16 Advanced Micro Devices, Inc. RTCVD oxide and N2 O anneal for top oxide of ONO film
US6074917A (en) * 1998-06-16 2000-06-13 Advanced Micro Devices, Inc. LPCVD oxide and RTA for top oxide of ONO film to improve reliability for flash memory devices

Cited By (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6709927B1 (en) * 2000-08-11 2004-03-23 Advanced Micro Devices, Inc. Process for treating ONO dielectric film of a floating gate memory cell
US7214593B2 (en) * 2001-02-01 2007-05-08 International Business Machines Corporation Passivation for improved bipolar yield
US6818567B2 (en) * 2001-09-20 2004-11-16 Oki Electric Industry Co., Ltd. Method for selectively oxidizing a silicon wafer
US20030054664A1 (en) * 2001-09-20 2003-03-20 Yoshirou Tsurugida Method for selectively oxidizing a silicon wafer
US6680509B1 (en) 2001-09-28 2004-01-20 Advanced Micro Devices, Inc. Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory
US6440797B1 (en) * 2001-09-28 2002-08-27 Advanced Micro Devices, Inc. Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SONOS flash memory
US6562491B1 (en) 2001-10-15 2003-05-13 Advanced Micro Devices, Inc. Preparation of composite high-K dielectrics
US6559014B1 (en) 2001-10-15 2003-05-06 Advanced Micro Devices, Inc. Preparation of composite high-K / standard-K dielectrics for semiconductor devices
US6514831B1 (en) * 2001-11-14 2003-02-04 Macronix International Co., Ltd. Nitride read only memory cell
US7115469B1 (en) 2001-12-17 2006-10-03 Spansion, Llc Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process
US6790755B2 (en) 2001-12-27 2004-09-14 Advanced Micro Devices, Inc. Preparation of stack high-K gate dielectrics with nitrided layer
US6635584B2 (en) * 2001-12-28 2003-10-21 Texas Instruments Incorporated Versatile system for forming uniform wafer surfaces
US6674138B1 (en) 2001-12-31 2004-01-06 Advanced Micro Devices, Inc. Use of high-k dielectric materials in modified ONO structure for semiconductor devices
US6803272B1 (en) 2001-12-31 2004-10-12 Advanced Micro Devices, Inc. Use of high-K dielectric material in modified ONO structure for semiconductor devices
US6509231B1 (en) * 2002-01-04 2003-01-21 Macronix International Co., Ltd. Nitride ready only memory cell with two top oxide layers and the method for manufacturing the same
US20040185647A1 (en) * 2002-02-08 2004-09-23 Zhong Dong Floating gate nitridation
US7001810B2 (en) 2002-02-08 2006-02-21 Promos Technologies Inc. Floating gate nitridation
US7867918B1 (en) 2002-02-13 2011-01-11 Cypress Semiconductor Corporation Semiconductor topography including a thin oxide-nitride stack and method for making the same
US7365403B1 (en) * 2002-02-13 2008-04-29 Cypress Semiconductor Corp. Semiconductor topography including a thin oxide-nitride stack and method for making the same
US20030155582A1 (en) * 2002-02-19 2003-08-21 Maitreyee Mahajani Gate dielectric structures for integrated circuits and methods for making and using such gate dielectric structures
US20030232507A1 (en) * 2002-06-12 2003-12-18 Macronix International Co., Ltd. Method for fabricating a semiconductor device having an ONO film
US20040051134A1 (en) * 2002-09-12 2004-03-18 Chuch Jang Atomic layer deposition of interpoly oxides in a non-volatile memory device
US7122415B2 (en) * 2002-09-12 2006-10-17 Promos Technologies, Inc. Atomic layer deposition of interpoly oxides in a non-volatile memory device
US20040053468A1 (en) * 2002-09-12 2004-03-18 Zhong Dong Method for forming a protective buffer layer for high temperature oxide processing
US20060008997A1 (en) * 2002-09-12 2006-01-12 Chuck Jang Atomic layer deposition of interpoly oxides in a non-volatile memory device
US6893920B2 (en) 2002-09-12 2005-05-17 Promos Technologies, Inc. Method for forming a protective buffer layer for high temperature oxide processing
US8691647B1 (en) 2002-10-07 2014-04-08 Spansion Llc Memory devices containing a high-K dielectric layer
US6858899B2 (en) 2002-10-15 2005-02-22 Matrix Semiconductor, Inc. Thin film transistor with metal oxide layer and method of making same
US20040069990A1 (en) * 2002-10-15 2004-04-15 Matrix Semiconductor, Inc. Thin film transistor with metal oxide layer and method of making same
EP1552554A2 (en) * 2002-10-18 2005-07-13 Advanced Micro Devices, Inc. Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer
US6906959B2 (en) * 2002-11-27 2005-06-14 Advanced Micro Devices, Inc. Method and system for erasing a nitride memory device
EP1568085A1 (en) * 2002-11-27 2005-08-31 Advanced Micro Devices, Inc. Silicon nitrade charge trapping memory device
US20040169218A1 (en) * 2002-11-27 2004-09-02 Randolph Mark W. Method and system for erasing a nitride memory device
US6949433B1 (en) 2003-02-07 2005-09-27 Fasl Llc Method of formation of semiconductor resistant to hot carrier injection stress
US20060214256A1 (en) * 2003-04-28 2006-09-28 Masaaki Shinohara Semiconductor device and a method of manufacturing the same
US7663179B2 (en) * 2003-04-28 2010-02-16 Renesas Technology Corp. Semiconductor device with rewritable nonvolatile memory cell
US6740605B1 (en) * 2003-05-05 2004-05-25 Advanced Micro Devices, Inc. Process for reducing hydrogen contamination in dielectric materials in memory devices
US20060180916A1 (en) * 2003-07-30 2006-08-17 Koninklijke Philips Electronics N.V. Ground arch for wirebond ball grid arrays
US7217997B2 (en) 2003-07-30 2007-05-15 Nxp Bv. Ground arch for wirebond ball grid arrays
US7816215B2 (en) * 2003-09-19 2010-10-19 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method
US20050064667A1 (en) * 2003-09-19 2005-03-24 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method
US7084454B2 (en) 2003-09-30 2006-08-01 Infineon Technologies Ag Nonvolatile integrated semiconductor memory
DE10345475A1 (en) * 2003-09-30 2005-05-04 Infineon Technologies Ag Non-volatile integrated semiconductor memory
US20050067634A1 (en) * 2003-09-30 2005-03-31 Cay-Uwe Pinnow Nonvolatile integrated semiconductor memory
DE10345475B4 (en) * 2003-09-30 2008-04-17 Infineon Technologies Ag Non-volatile integrated semiconductor memory
US20050179095A1 (en) * 2003-11-06 2005-08-18 Ching-Hsiang Hsu Non-volatile memory cell
US6949481B1 (en) 2003-12-09 2005-09-27 Fasl, Llc Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device
US6955965B1 (en) 2003-12-09 2005-10-18 Fasl, Llc Process for fabrication of nitride layer with reduced hydrogen content in ONO structure in semiconductor device
US20050156228A1 (en) * 2004-01-16 2005-07-21 Jeng Erik S. Manufacture method and structure of a nonvolatile memory
CN100353527C (en) * 2004-06-10 2007-12-05 旺宏电子股份有限公司 Method for producing elements with memory cells and memory cell array
US20070093012A1 (en) * 2005-10-20 2007-04-26 Applied Materials, Inc. Method for fabricating a gate dielectric of a field effect transistor
US7888217B2 (en) 2005-10-20 2011-02-15 Applied Materials, Inc. Method for fabricating a gate dielectric of a field effect transistor
US20070093013A1 (en) * 2005-10-20 2007-04-26 Chua Thai C Method for fabricating a gate dielectric of a field effect transistor
US7727828B2 (en) * 2005-10-20 2010-06-01 Applied Materials, Inc. Method for fabricating a gate dielectric of a field effect transistor
US7847341B2 (en) 2006-12-20 2010-12-07 Nanosys, Inc. Electron blocking layers for electronic devices
US20090101965A1 (en) * 2006-12-20 2009-04-23 Nanosys, Inc. Electron blocking layers for electronic devices
US20080150009A1 (en) * 2006-12-20 2008-06-26 Nanosys, Inc. Electron Blocking Layers for Electronic Devices
US8686490B2 (en) 2006-12-20 2014-04-01 Sandisk Corporation Electron blocking layers for electronic devices
US20080150003A1 (en) * 2006-12-20 2008-06-26 Jian Chen Electron blocking layers for electronic devices
US9214525B2 (en) 2006-12-20 2015-12-15 Sandisk Corporation Gate stack having electron blocking layers on charge storage layers for electronic devices
WO2010042323A1 (en) * 2008-10-08 2010-04-15 Nanosys, Inc. Electron blocking layers for electronic devices
CN102171835A (en) * 2008-10-08 2011-08-31 纳诺西斯有限公司 Electron blocking layers for electronic devices
US20110241128A1 (en) * 2010-03-31 2011-10-06 Tokyo Electron Limited Multilayer sidewall spacer for seam protection of a patterned structure
US8664102B2 (en) 2010-03-31 2014-03-04 Tokyo Electron Limited Dual sidewall spacer for seam protection of a patterned structure
US8673725B2 (en) * 2010-03-31 2014-03-18 Tokyo Electron Limited Multilayer sidewall spacer for seam protection of a patterned structure

Similar Documents

Publication Publication Date Title
US6319775B1 (en) Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device
US6265268B1 (en) High temperature oxide deposition process for fabricating an ONO floating-gate electrode in a two bit EEPROM device
US6248628B1 (en) Method of fabricating an ONO dielectric by nitridation for MNOS memory cells
US6406960B1 (en) Process for fabricating an ONO structure having a silicon-rich silicon nitride layer
US7115469B1 (en) Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process
US6458677B1 (en) Process for fabricating an ONO structure
US6180538B1 (en) Process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device using rapid-thermal-chemical-vapor-deposition
US5585293A (en) Fabrication process for a 1-transistor EEPROM memory device capable of low-voltage operation
JP5132024B2 (en) Method for forming non-volatile semiconductor memory device
US6445030B1 (en) Flash memory erase speed by fluorine implant or fluorination
US6309928B1 (en) Split-gate flash cell
US6252276B1 (en) Non-volatile semiconductor memory device including assymetrically nitrogen doped gate oxide
WO2004079824A2 (en) Charge-trapping memory arrays
US7442989B2 (en) Nonvolatile semiconductor memory device and method of manufacturing thereof
US6458656B1 (en) Process for creating a flash memory cell using a photoresist flow operation
US5972753A (en) Method of self-align cell edge implant to reduce leakage current and improve program speed in split-gate flash
JP4792620B2 (en) Nonvolatile semiconductor memory device and manufacturing method thereof
JPH06506798A (en) Electrically variable non-volatile single transistor semiconductor memory device and method
US6218227B1 (en) Method to generate a MONOS type flash cell using polycrystalline silicon as an ONO top layer
US6849897B2 (en) Transistor including SiON buffer layer
JP4696383B2 (en) Method for manufacturing nonvolatile semiconductor memory device
JP2002261175A (en) Nonvolatile semiconductor memory and its manufacturing method
US20080116460A1 (en) Non-volatile memory device and fabrication method of non-volatile memory device and memory apparatus including non-volatile memory device
JP4969748B2 (en) Nonvolatile semiconductor memory device and method of manufacturing nonvolatile memory cell
US7190024B2 (en) Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method

Legal Events

Date Code Title Description
AS Assignment

Owner name: ADVANCED MICRO DEVICES, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HALLIYAL, ARVIND;OGLE, ROBERT B.;KIM, SUSAN G.;AND OTHERS;REEL/FRAME:010507/0365;SIGNING DATES FROM 19991210 TO 20000114

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: SPANSION INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ADVANCED MICRO DEVICES, INC.;REEL/FRAME:019047/0526

Effective date: 20070131

AS Assignment

Owner name: SPANSION LLC, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SPANSION INC.;REEL/FRAME:019069/0187

Effective date: 20070131

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: BARCLAYS BANK PLC,NEW YORK

Free format text: SECURITY AGREEMENT;ASSIGNORS:SPANSION LLC;SPANSION INC.;SPANSION TECHNOLOGY INC.;AND OTHERS;REEL/FRAME:024522/0338

Effective date: 20100510

Owner name: BARCLAYS BANK PLC, NEW YORK

Free format text: SECURITY AGREEMENT;ASSIGNORS:SPANSION LLC;SPANSION INC.;SPANSION TECHNOLOGY INC.;AND OTHERS;REEL/FRAME:024522/0338

Effective date: 20100510

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: SPANSION INC., CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BARCLAYS BANK PLC;REEL/FRAME:035201/0159

Effective date: 20150312

Owner name: SPANSION TECHNOLOGY LLC, CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BARCLAYS BANK PLC;REEL/FRAME:035201/0159

Effective date: 20150312

Owner name: SPANSION LLC, CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BARCLAYS BANK PLC;REEL/FRAME:035201/0159

Effective date: 20150312

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., NEW YORK

Free format text: SECURITY INTEREST;ASSIGNORS:CYPRESS SEMICONDUCTOR CORPORATION;SPANSION LLC;REEL/FRAME:035240/0429

Effective date: 20150312

AS Assignment

Owner name: CYPRESS SEMICONDUCTOR CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SPANSION, LLC;REEL/FRAME:036032/0154

Effective date: 20150601

AS Assignment

Owner name: SPANSION LLC, CALIFORNIA

Free format text: PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT;REEL/FRAME:039708/0001

Effective date: 20160811

Owner name: CYPRESS SEMICONDUCTOR CORPORATION, CALIFORNIA

Free format text: PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT;REEL/FRAME:039708/0001

Effective date: 20160811

AS Assignment

Owner name: MONTEREY RESEARCH, LLC, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CYPRESS SEMICONDUCTOR CORPORATION;REEL/FRAME:040911/0238

Effective date: 20160811

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., NEW YORK

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST;ASSIGNORS:CYPRESS SEMICONDUCTOR CORPORATION;SPANSION LLC;REEL/FRAME:058002/0470

Effective date: 20150312