US5523623A - Ohmic electrode for a p-type compound semiconductor and a bipolar transistor incorporating the ohmic electrode - Google Patents

Ohmic electrode for a p-type compound semiconductor and a bipolar transistor incorporating the ohmic electrode Download PDF

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US5523623A
US5523623A US08/399,180 US39918095A US5523623A US 5523623 A US5523623 A US 5523623A US 39918095 A US39918095 A US 39918095A US 5523623 A US5523623 A US 5523623A
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layer
ohmic electrode
compound semiconductor
electrode
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Manabu Yanagihara
Akiyoshi Tamura
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors

Definitions

  • the present invention relates to a low resistance ohmic electrode for semiconductors composed of III--V group compounds having a p-type conductivity (hereinafter, such a semiconductor will be referred to as a "p-type III-V compound semiconductor"), and a bipolar transistor incorporating the ohmic electrode.
  • the present invention relates to a method for producing the ohmic electrode end a method for producing the bipolar transistor.
  • a Pt/Ti/Pt/Au electrode As a low resistance ohmic electrode for p-type GaAs layers, a Pt/Ti/Pt/Au electrode is drawing much attention (H. Okada, et al., Japanese Journal of Applied Physics Vol. 30, 1991, pp. L558-L560).
  • This ohmic electrode includes a Pt film, a Ti film, a Pt film, and an Au film layered on a p-type GaAs substrate in this order. Since the Schottky junction of Pt is low relative to that of p-type GaAs, the lowermost Pt layer acts to reduce the contact resistance of the electrode.
  • the Ti layer and the middle Pt layer function to prevent mutual diffusion between the Ga and As and the uppermost Au layer.
  • an electrode of this structure as a base electrode for a bipolar transistor, and subjecting it to a heat treatment at 350° C., an extremely low base resistance can be obtained, thereby making the high frequency characteristics of the bipolar transistor excellent. This is reported in Extended Abstracts of the 1993 International Conference on Solid State Devices and Materials, pp. 1062-1064.
  • an electrode of an Ni/Ti/Ag structure is known as a low-contact resistance electrode for n-type Si layers, as is disclosed in Japanese Laid-Open Patent Publication No. 65-234322.
  • the above-mentioned ohmic electrode has a problem in that, since the low resistance ohmic contact is achieved by conducting an alloying process at a relatively low temperature, the resistance of the ohmic contact increases when the electrode is kept at a temperature exceeding about 350° C.
  • the contact resistance of the Pt/Ti/Pt/Au electrode becomes minimum when the heat treatment is conducted at about 350° C., and increases at any temperature above 350° C. This is considered to be because compounds, such as PtAs 2 , that increases the contact resistance is generated at about 400° C. during the heat treatment.
  • a p-type semiconductor layer included in the ohmic electrode is as thin as a base layer of a hetero-junction bipolar transistor (HBT), PtAs 2 and the like may be formed deep from the surface of the p-type semiconductor. As a result, the thickness of the p-type semiconductor layer remaining under the PtAs 2 is inevitably reduced, thereby further increasing the contact resistance.
  • HBT hetero-junction bipolar transistor
  • n-type AuGe/Ni type ohmic electrodes that are commonly used as collector electrodes of bipolar transistors have such characteristics that the contact resistance thereof becomes minimum at about 400° C. Accordingly, in the fabrication process of a bipolar transistor, it is required to first form a collector electrode, subject the collector electrode to a heat treatment at 400° C., and then form a base electrode and subject the base electrode to a heat treatment at 350° C. so that the contact resistance of a Pt/Ti/Pt/Au base electrode and the contact resistance of an AuGe/Ni type collector electrode are minimized. In other words, it is impossible to form the collector electrode after the formation of the base electrode, creating problems so that the fabrication process of HBTs allows less freedom and that separate heat treatments must be conducted for the base electrode and the collector electrode, respectively.
  • the ohmic electrode for a p-type III-V compound semiconductor of the invention formed on a p-type III-V compound semiconductor layer, includes nickel (Ni), titanium (Ti), and platinum (Pt) as main components in an interface between the ohmic electrode and the p-type III-V compound semiconductor layer.
  • the ohmic electrode includes palladium (Pd) instead of (Pt).
  • a method for producing an ohmic electrode for a p-type III-V compound semiconductor includes the steps of: forming a metal layer including Ni, Pt, and Ti as main components on a p-type III-V compound semiconductor layer directly or via a thin layer; and alloying the metal layer with a portion of the p-type III-V compound semiconductor layer by a heat treatment.
  • the metal layer includes a multilayer film comprising a Ni layer, a Ti layer, and a Pt layer, the Pt layer being an upper-most layer, and the Ti layer having a thickness of 10 nm or less.
  • Pd is used instead of Pt.
  • the heat treatment is conducted at a temperature in the range of 360° C. to 460° C. during the alloying step.
  • a bipolar transistor includes: a semiconductor multilayer structure including at least on a p-type III-V compound semiconductor layer; and a p-type ohmic electrode formed on the p-type III-V compound semiconductor layer and including Ni, Ti, and Pt as main components.
  • the semiconductor multilayer structure further includes at least on an n-type III-V compound semiconductor layer and the bipolar transistor further comprises an n-type ohmic electrode formed on the n-type III-V compound semiconductor layer and including gold (Au), germanium (Ge), and Ni as main components.
  • the ohmic electrode includes Pd instead of Pt.
  • a method for producing a bipolar transistor includes the steps of: forming a first metal layer including Ni, Pt, and Ti as main components on a p-type III-V compound semiconductor layer directly or via a thin layer; and alloying the first metal layer with a portion of the p-type III-V compound semiconductor layer by a heat treatment.
  • the first metal layer comprises a multilayer film including a Ni layer, a Pt layer, and a Ti layer, the Pt layer being an uppermost layer, wherein the Ti layer and the Ni layer each have a thickness of 10 nm or less.
  • the method further includes a step of forming a second metal layer including Au, Ge, and Ni as main components on an n-type III-V compound semiconductor layer directly or via another thin layer, the step being conducted between the step of forming the first metal layer and the alloying step.
  • the second metal layer is simultaneously alloyed with the n-type III-V compound semiconductor layer at the alloying step.
  • a method for producing a bipolar transistor includes the steps of: etching a part of a semiconductor multilayer structure from the upper face thereof, wherein the semiconductor multilayer structure includes a first n-type III-V compound semiconductor layer, a p-type III-V compound semiconductor layer stacked above the first n-type III-V compound semiconductor layer, and a second n-type III-V compound semiconductor layer stacked above the p-type III-V compound semiconductor layer, and etching is performed until the p-type III-V compound semiconductor layer is exposed or until a thin layer remains on the p-type III-V compound semiconductor layer; forming a first metal film on the exposed p-type semiconductor layer or the exposed thin layer, the first metal film including Ni, Ti, and Pt or Pd; simultaneously etching the first metal film and the p-type III-V compound semiconductor layer until the first n-type III-V compound semiconductor layer is exposed or until another thin layer remains on the first n-type III-V compound semiconductor layer;
  • the method further includes The steps of: forming a side wall on a side face of the semiconductor multilayer structure exposed by the first etching step, after forming the first metal film; and forming a low resistance metal layer on the first metal film.
  • the low resistance metal layer is formed by plating.
  • Ni and Ti prevents the generation of high resistance compounds such as PtAs 2 or acts to prevent the Pt from becoming diffused deeply into the p-type III-V compound semiconductor layer, thereby providing a low contact resistance between the ohmic electrode and the p-type semiconductor layer.
  • an alloy composed of Ni, Ti, and Pt has a lower Schottky junction with respect to p-type semiconductors than that obtained in the case of Pt alone.
  • the heat treatment for the formation of an ohmic contact having a low contact resistivity is performed at a temperature substantially equal to the temperature of the heat treatment conducted for the formation of n-type ohmic electrodes composed of Au, Ge, and Ni, it is possible to simultaneously perform the heat treatment for the p-type ohmic electrode and the heat treatment for the n-type ohmic electrode at the same time.
  • ohmic electrode of the present invention By applying the ohmic electrode of the present invention to a bipolar transistor, it becomes possible to form n-type ohmic electrodes and p-type ohmic electrodes in any desired order, thereby increasing the freedom in designing the production method and structure of the device.
  • the base resistance of the device is further reduced, thereby improving the high-frequency characteristics of the device operating at a high speed.
  • the invention described herein makes possible the advantages of (1) providing a ohmic electrode having a low contact resistance which becomes minimum in the vicinity of an optimum temperature for the heat treatment for n-type AuGe/Ni type ohmic electrodes, and a bipolar transistor incorporating the ohmic electrode; and (2) providing a method for producing the ohmic electrode and a method for producing the bipolar transistor.
  • FIG. 1 is a schematic cross-sectional view showing the construction of an electrode incorporating an ohmic electrode according to the present invention.
  • FIGS. 2A to 2E are cross-sectional views for describing a method for producing a p-type ohmic electrode according to the present invention.
  • FIG. 3 is a graph showing the relationships between the duration of a heat treatment at 350° C. and the contact resistivity of the p-type ohmic electrode of the present invention and a conventional p-type ohmic electrode.
  • FIG. 4 is a graph showing the relationships between the duration of a heat treatment at 400° C. and the contact resistivity of the p-type ohmic electrode of the present invention and a conventional p-type ohmic electrode.
  • FIG. 5 is a graph showing the relationship between the storage temperature and the MTTF of the p-type ohmic electrode of the present invention and a conventional p-type ohmic electrode.
  • FIGS. 6A and 6B at a cross-sectional views for describing another method for producing a p-type ohmic electrode according to the present invention.
  • FIG. 7 is a cross-sectional view showing the construction of a bipolar transistor according to the present invention.
  • FIGS. 8A to 8F are cross-sectional views for describing a method for producing the bipolar transistor shown in FIG. 7.
  • FIGS. 9A to 9D are cross-sectional views for describing a method for producing an Au layer on a p-type ohmic electrode of the bipolar transistor shown in FIG. 7.
  • FIG. 10 is a graph showing the relationship between the temperature of a heat treatment and the contact resistivity of a conventional p-type ohmic electrode as obtained by the, inventors of the present invention through experiments.
  • FIG. 11 is a graph showing the relationship between the temperature of a heat treatment and the contact resistivity of a conventional n-type ohmic electrode as obtained by the inventors of the present invention through experiments.
  • FIG. 1 schematically shows a cross section of an electrode 7 in which an ohmic electrode 4 of the present invention is used.
  • a p-type GaAs layer 2 is formed on a semi-insulating GaAs substrate 1.
  • the p-type ohmic electrode 4 and the GaAs layer 2 are alloyed to each other in the diffusion layer 3.
  • a titanium layer 5 is formed on the p-type ohmic electrode 4.
  • a platinum layer 6 Is formed on the titanium layer 5.
  • the electrode 7 is formed by the following method, for example.
  • the p-type GaAs layer 2 is epitaxially grown on the semi-insulating GaAs substrate 1.
  • the p-type GaAs layer 2, on which the ohmic electrode 4 is to be formed may be any GaAs semiconductor layer having a p-type conductivity; the impurity concentration and thickness thereof may be adjusted to a specific purpose.
  • the p-type GaAs layer 2 has a thickness of 150 nm and a carrier density of 2 ⁇ 10 19 cm -3 .
  • a resist pattern 13 with an opening having a desired shape is formed on the p-type GaAs layer 2.
  • the Ni film 14, Ti film 15, and the Pt film 16 constitute a metal multilayer film 21 to become the p-type ohmic electrode 4.
  • the Ni film 14 and the Ti film 15 may be reversed.
  • the Ti film 15 may be formed on the p-type GaAs layer 2 in this order.
  • the titanium film 17 and the Pt film 18 merely function as a pad, and therefore are dispensable as an ohmic electrode for p-type compound semiconductors. Accordingly, an ohmic electrode for p-type compound semiconductors should only include the Ni film 14, Ti film 15, and the Pt film 16, with the Pt film 16 being the uppermost layer of the metal multilayer film 21.
  • the thicknesses of the Ni film 14 and the Ti film 15 are preferably in the range of 1 nm to 50 nm, and more preferably 2 nm to 10 nm.
  • the Ni film 14, Ti film 15, and Pt film 16 are alloyed with one another by conducting a heat treatment at 400° C. for 10 minutes so as to form the p-type ohmic electrode 4. Moreover, a portion of Ni, Ti, and Pt constituting the Ni film 14, Ti film 15, and Pt film 16 is diffused into the p-type GaAs layer 2, whereby the diffusion layer 3 is obtained.
  • the temperature and duration of the heat treatment can be selected, in order to attain a desired contact resistivity, in accordance with the specific characteristics required for an element to which the p-type ohmic electrode 4 is applied. However, the heat treatment is preferably conducted at a temperature in the range of 360° C.
  • a metal layer composed of Au or the like may be formed on the uppermost Pt layer 18 in order to reduce the resistance of the electrode itself.
  • FIGS. 3 and 4 show the measurement results of the contact resistivity of the electrode 7 including the p-type ohmic electrode 4 produced in the above-mentioned manner.
  • FIG. 3 shows the relationship between the duration of a heat treatment conducted at 350° C. for the formation of the electrode and the contact resistivity.
  • FIG. 4 shows the relationship between the duration of a heat treatment conducted at 400° C. for the formation of the electrode and the contact resistivity. Measurement results of a conventional Pt/Ti/Pt ohmic electrode are also indicated in FIGS. 3 and 4 for comparison.
  • the electrode 7 provides a contact resistivity of about: 3.8 ⁇ 10 -7 ⁇ cm 2 by conducting a heat treatment at 350° C. for 10 minutes.
  • the contact resistivity thereof hardly increases even if the electrode 7 is subjected to a heat treatment for a long time.
  • the contact resistivity is about 4.2 ⁇ 10 -7 ⁇ cm 2 after 80 minutes of heat treatment.
  • the conventional Pt/Ti/Pt ohmic electrode provides a contact resistivity of about 3.6 -10 -7 ⁇ cm 2 by conducting a heat treatment at 350° C. for 10 minutes.
  • the contact resistivity increases as the duration of the heat treatment increases.
  • the contact resistivity is about 7.0 ⁇ 10 -7 ⁇ cm 2 after 80 minutes of heat treatment.
  • the ohmic: electrode of the present invention has a high heat resistance.
  • the electrode 7 of the present example provides a contact resistivity of about 2.1 ⁇ 10.sup. ⁇ 7 ⁇ cm 2 by conducting a heat treatment at 400° C. for 10 minutes.
  • the contact resistivity increases as the duration of the heat treatment increases, the contact resistivity remains at about 5.6 ⁇ 10 -7 ⁇ cm 2 even after 80 minutes of heat treatment.
  • the conventional Pt/Ti/Pt ohmic electrode provides a contact resistivity of about 7.0 ⁇ 10 -7 ⁇ cm 2 by conducting a heat treatment at 400° C. for 10 minutes.
  • the contact resistivity increases to about 8.4 ⁇ 10 -7 ⁇ cm 2 after 80 minutes of heat treatment.
  • the electrode 7 of the present example has a minimum contact resistivity when the heat treatment is conducted at 400° C., and achieves a lower contact resistivity than that of a conventional p-type Pt/Ti/Pt/Au ohmic electrode.
  • FIG. 5 shows the results of a high temperature storage test in which the electrode 7 of the present example, obtained by a heat treatment at 400° C. for 10 minutes and a conventional Pt/Ti/Pt ohmic electrode obtained by a heat treatment at 350° C. for 10 minutes are left at temperatures ranging from 300° C. to 400° C.
  • the MTTF Mel Time To Failure
  • the gradient of the line representing the electrode 7 is substantially equal to the gradient of the line representing the conventional ohmic electrode. Based on these gradients, the activation energy of the deterioration reaction for the ohmic electrodes is deduced to be about 1.6 eV.
  • the electrode 7 of the present example and the conventional ohmic electrode may deteriorate by the same deterioration mechanism.
  • electrode 7 of the present example takes a longer deterioration time than the conventional ohmic electrode when left at the same temperature. For example, while the MTTF at 150° C. is 6.5 ⁇ 10 6 hours for the electrode 7, it is 1.3 ⁇ 10 6 hours for the conventional ohmic electrode, indicating the comparative excellence of the electrode 7 is five times. It will be appreciated that the electrode 7 of the present example is also excellent in terms of reliability.
  • the Ni and Ti prevent the generation of high resistance compounds such as PtAs 2 at temperatures in the vicinity of 400° C., or prevent the Pt from becoming diffused deeply into the p-type semiconductor layer, thereby leading to the low contact resistance between the ohmic electrode of the present invention and any p-type semiconductor. It is further presumed that an alloy composed of Ni, Tt, and Pt has a lower Schottky Junction with respect to p-type semiconductors than that obtained in the case of Pt alone.
  • the metal multilayer film 21 is formed directly on the p-type GaAs layer 2, a thin semiconductor layer may be interposed between the metal multilayer film 21 and the p-type GaAs layer 2 if a portion of Ni, Ti, and Pt of the metal multilayer film 21 is diffused into the p-type GaAs layer 2, whereby the diffusion layer 3 is obtained by heat treatment, as shown in FIG. 2C.
  • a thin semiconductor layer 19 is formed on the p-type GaAs layer 2 and the metal multilayer film 21 is formed on the p-type GaAs layer 2 via the thin semiconductor layer 19. Then, as shown in FIG.
  • a portion of Ni, Ti, and Pt of the metal multilayer film 21 is diffused into the p-type GaAs layer 2 through the thin semiconductor layer 19 or is diffused into the p-type GaAs layer 2 accompanying the thin semiconductor layer 19.
  • the p-type ohmic electrode 4 is formed on the p-type GaAs layer 2 by alloying the metal multilayer film 21.
  • the metal multilayer film may contain films of Ni, Ti and Pt wherein Pt is the top layer
  • the metal multilayer film may also contain films of Ni, Ti and Pd (which is the same group as Pt) in which the Pt film is replaced by a film of Pd.
  • the metal multilayer film may also contain films of Ni, Ti and Pd (which is the same group as Pt) in which the Pt film is replaced by a film of Pd.
  • an alloy film 22 of Ni, Ti, and Pt may be formed on a p-type GaAs layer 2 directly or via a thin semiconductor layer (not shown.), and after conducting a lift-off method, a p-type ohmic electrode 4 may be formed by a heat treatment, resulting in a configuration shown in FIG. 6B.
  • the alloy film 22 may be deposited by simultaneously evaporating the respective metals.
  • the alloy film 22 may be obtained by depositing a pre-fabricated alloy containing Ni, Ti, and Pt at the above-mentioned range of ratios.
  • the p-type ohmic electrode of the present invention is applicable to any other p-type III-V group semiconductor layer, as well as p-type GaAs layer.
  • III-V group semiconductors include AlGaAs, GaInAsP, AlGaInAs, AlGaAsSb, InAsSbP, AlGaInP, and GaAlN.
  • a bipolar transistor 41 includes a semiconductor multilayer structure 42 formed on a semi-insulating GaAs substrate 31.
  • the semiconductor multilayer structure 42 includes a collect or contact layer 32 of n + -GaAs, a collector layer 33 of n 31 -GaAs, a base layer 34 of p + -GaAs, an emitter layer 35 of n-AlGaAs, and an emitter contact layer 36 of n + -InGaAs.
  • An AlGaAs semiconductor constituting the emitter layer 35 has a larger band gap than of GaAs semiconductor constituting the base layer 34, the bipolar transistor 41 has therefore, a hetero-3unction structure.
  • a collector electrode 37 composed of an alloy of Au, Ge, and Ni is formed, as an n-type ohmic electrode, on a portion of the collector contact layer 32.
  • a base electrode 38 is formed, as a p-type ohmic electrode, on a portion of the base layer 34.
  • the base electrode 38 is composed of an alloy of Ni, Ti, and Pt, as described in the above-mentioned example.
  • a diffusion layer 39 is formed in the base layer 34 in a portion below the base electrode 38.
  • an emitter electrode 40 is formed on the emitter contact layer 36.
  • FIG. 8A the collector contact layer 32 of n - -GaAs, the collector layer 33 of n - -GaAs, the base layer 34 of p-GaAs, the emitter layer 35 of n-AlGaAs, and the emitter contact layer 36 of n + -InGaAs are epitaxially grown on the semi-insulating GaAs substrate 31 in this order.
  • a tungsten silicide (WSi) film 57 is formed on the emitter contact layer 36 by sputtering.
  • a resist pattern 58 is formed on the tungsten silicide film 57 by photolithography.
  • the tungsten silicide film 57 is etched by RIE (Reactive Ion Etching) while using the resist pattern 58 as a mask so as to form an electrode 59 as shown in FIG. 8C. Since the Schottky barrier height created by the contact between n + -InGaAs and tungsten silicide is small, the electrode 59 is in contact with the emitter contact layer 36 with a low contact resistance without conducting a heat treatment.
  • RIE Reactive Ion Etching
  • the emitter contact layer 36 and the emitter layer 35 are etched by wet etching while using the electrode 59 as a mask, so as to expose the surface of the base layer 34.
  • a thin semiconductor layer of a portion of the emitter layer 35 may remain on the base layer 34. Since the emitter contact layer 36 and the emitter layer 35 are etched in an isotropical manner, the width W 2 of the emitter contact layer 36 and the emitter layer 35 becomes smaller than the width W 1 of the electrode 59.
  • a metal multilayer film 60 is vapor deposited by an electron beam method so as to cover the entire semi-insulating GaAs substrate 31.
  • the metal multilayer film 60 includes a Ni layer (thickness: 5 nm), a Ti layer (thickness: 5 nm), a Pt layer (thickness: 5 nm), a Ti layer (thickness: 30 nm), and a Pt layer (thickness: 100 nm).
  • a resist pattern 61 is formed so as to cover the emitter contact layer 36.
  • the metal multilayer film 60 and the base layer 34 are simultaneously etched by an ion milling method, while using the resist pattern 61 as a mask, until the collector layer 33 is exposed. Furthermore, a portion of the collector layer 33 is etched.
  • the collector contact layer 32 is exposed by photolithography and wet etching, and a metal multilayer film 64 composed of an Au-Ge layer (thickness: 100 nm), a Ni layer (thickness: 20 nm), and an Au layer (thickness: 200 nm) is formed by a lift-off method.
  • the metal multilayer film 64 and the collector layer 33 are alloyed with each other, whereby the base electrode 38 composed of an alloy of Ni, Ti, and Pt is obtained. Since the collector electrode 37 and the base electrode 38 are formed into alloys under optimum conditions, i.e., at 400° C., the former as an n-type ohmic electrode and the latter as a p-type ohmic electrode, they achieve extremely low contact resistances.
  • the metal multilayer film 60 and the electrode 59 constitute the emitter electrode 40.
  • the emitter contact layer 36 and the electrode 59 are heated during the above-mentioned heat treatment, the heat treatment is not particularly necessary for the emitter contact layer 36 and the electrode 59, a sufficient ohmic contact is achieved between the emitter contact layer 36 and the electrode 59 in a non-alloy ohmic contact manner.
  • the metal multilayer film 60 and the base layer 34 are simultaneously etched by using the resist pattern 61 as a mask after the metal multilayer film 60, which becomes the base electrode 38, is formed on the base layer 34.
  • the base electrode 38 is formed in a self-alignment with the base layer 34. This maximizes the contact area between the base electrode 38 and the base layer 34, and yet reduces the base-collector capacitance.
  • a bipolar transistor having excellent high-frequency characteristics can be produced.
  • either the collector electrode 37 or the base electrode 38 can be formed first, so that increased freedom is provided in the designing of the element structure.
  • a metal layer 71 having a low resistance on the base electrode 38 of the bipolar transistor 41 in order to reduce the resistance of the base electrode 38.
  • the insulating film 73 composed of silicon oxide or the like, is deposited so as to cover the entire semi-insulating GaAs substrate 31, as shown in FIG. 9A.
  • the insulating film 73 is etched by an anisotropy etching method until the surface of the metal multilayer film 60 is exposed, so as to be left as a side wall 74 covering the sides of the emitter layer 35 and the emitter contact layer 36.
  • the metal layer 71 composed of Au, is formed on the metal multilayer film 60 by a plating method using the metal multilayer film 60 as an electrode.
  • the resist pattern 61 is formed, and the Au layer 71, the metal multilayer film 60, and the base layer 34 are etched by an ion milling method. Moreover, a portion of the collector layer 33 is etched. Thereafter, the process described with reference to FIG. 8F is continued.
  • the Au layer 71 can be formed with a large thickness on the base electrode 38, without being electrically short-circuited with the emitter layer 35, the emitter contact layer 36, or the emitter electrode 40.
  • the metallic resistance of the base electrode 38 can also be reduced. This structure is particularly advantageous if the base electrode is to be formed in a minute shape. Moreover, the high frequency characteristics of a high frequency device can be improved.
  • the present invention is applicable to a collector-up structure, in which a collector is disposed in an upper portion of the bipolar transistor.
  • an npn-type bipolar transistor was described in the above example, the electrode of the present invention can be used as a collector electrode or as an emitter electrode of a pnp-type bipolar transistor.
  • a p-type ohmic electrode of the invention and an n-type ohmic electrode may be formed directly on the base, emitter, and collector layers having an appropriate conductivity type, or on contact layers formed in contact with these layers.
  • a p-type ohmic electrode of the invention has a low Schottky barrier height against a p-type semiconductor, therefore, a p-type ohmic electrode has a high Schottky barrier height against an n-type semiconductor and as good a characteristic as a Schottky electrode.
  • metal layers including Ni, Ti, and Pt or Pd may be applied to a gate electrode for n-channel MESFET. In this case, heat treatment is required for diffusing Pt into a n-type semiconductor layer.
  • a highly reliable p-type ohmic electrode having a low contact resistivity can be provided.

Abstract

An ohmic electrode for a p-type III-V compound semiconductor is disclosed. The ohmic electrode formed on a p-type III-V compound semiconductor layer includes nickel (Ni), titanium (Ti), and platinum (Pt) as main components in an interface between the ohmic electrode and the p-type III-V compound semiconductor layer.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a low resistance ohmic electrode for semiconductors composed of III--V group compounds having a p-type conductivity (hereinafter, such a semiconductor will be referred to as a "p-type III-V compound semiconductor"), and a bipolar transistor incorporating the ohmic electrode. The present invention relates to a method for producing the ohmic electrode end a method for producing the bipolar transistor.
2. Description of the Related Art
As a low resistance ohmic electrode for p-type GaAs layers, a Pt/Ti/Pt/Au electrode is drawing much attention (H. Okada, et al., Japanese Journal of Applied Physics Vol. 30, 1991, pp. L558-L560). This ohmic electrode includes a Pt film, a Ti film, a Pt film, and an Au film layered on a p-type GaAs substrate in this order. Since the Schottky junction of Pt is low relative to that of p-type GaAs, the lowermost Pt layer acts to reduce the contact resistance of the electrode. The Ti layer and the middle Pt layer function to prevent mutual diffusion between the Ga and As and the uppermost Au layer.
By using an electrode of this structure as a base electrode for a bipolar transistor, and subjecting it to a heat treatment at 350° C., an extremely low base resistance can be obtained, thereby making the high frequency characteristics of the bipolar transistor excellent. This is reported in Extended Abstracts of the 1993 International Conference on Solid State Devices and Materials, pp. 1062-1064.
On the other hand, an electrode of an Ni/Ti/Ag structure is known as a low-contact resistance electrode for n-type Si layers, as is disclosed in Japanese Laid-Open Patent Publication No. 65-234322.
However, the above-mentioned ohmic electrode has a problem in that, since the low resistance ohmic contact is achieved by conducting an alloying process at a relatively low temperature, the resistance of the ohmic contact increases when the electrode is kept at a temperature exceeding about 350° C. According to an experiment by the inventors of the present invention, as shown in FIG. 10, the contact resistance of the Pt/Ti/Pt/Au electrode becomes minimum when the heat treatment is conducted at about 350° C., and increases at any temperature above 350° C. This is considered to be because compounds, such as PtAs2, that increases the contact resistance is generated at about 400° C. during the heat treatment. When a p-type semiconductor layer included in the ohmic electrode is as thin as a base layer of a hetero-junction bipolar transistor (HBT), PtAs2 and the like may be formed deep from the surface of the p-type semiconductor. As a result, the thickness of the p-type semiconductor layer remaining under the PtAs2 is inevitably reduced, thereby further increasing the contact resistance.
Moreover, the following problem arises during the fabrication of bipolar transistors.
According to an experiment by the inventors, as shown in FIG. 11, n-type AuGe/Ni type ohmic electrodes that are commonly used as collector electrodes of bipolar transistors have such characteristics that the contact resistance thereof becomes minimum at about 400° C. Accordingly, in the fabrication process of a bipolar transistor, it is required to first form a collector electrode, subject the collector electrode to a heat treatment at 400° C., and then form a base electrode and subject the base electrode to a heat treatment at 350° C. so that the contact resistance of a Pt/Ti/Pt/Au base electrode and the contact resistance of an AuGe/Ni type collector electrode are minimized. In other words, it is impossible to form the collector electrode after the formation of the base electrode, creating problems so that the fabrication process of HBTs allows less freedom and that separate heat treatments must be conducted for the base electrode and the collector electrode, respectively.
SUMMARY OF THE INVENTION
The ohmic electrode for a p-type III-V compound semiconductor of the invention, formed on a p-type III-V compound semiconductor layer, includes nickel (Ni), titanium (Ti), and platinum (Pt) as main components in an interface between the ohmic electrode and the p-type III-V compound semiconductor layer.
In one embodiment of the invention, the ohmic electrode includes palladium (Pd) instead of (Pt).
According to another aspect of the invention, a method for producing an ohmic electrode for a p-type III-V compound semiconductor, includes the steps of: forming a metal layer including Ni, Pt, and Ti as main components on a p-type III-V compound semiconductor layer directly or via a thin layer; and alloying the metal layer with a portion of the p-type III-V compound semiconductor layer by a heat treatment.
In one embodiment of the invention, the metal layer includes a multilayer film comprising a Ni layer, a Ti layer, and a Pt layer, the Pt layer being an upper-most layer, and the Ti layer having a thickness of 10 nm or less.
In another embodiment of the invention, Pd is used instead of Pt.
In still another aspect of the invention, the heat treatment is conducted at a temperature in the range of 360° C. to 460° C. during the alloying step.
According to still another aspect of the invention, a bipolar transistor includes: a semiconductor multilayer structure including at least on a p-type III-V compound semiconductor layer; and a p-type ohmic electrode formed on the p-type III-V compound semiconductor layer and including Ni, Ti, and Pt as main components.
In one embodiment of the invention, the semiconductor multilayer structure further includes at least on an n-type III-V compound semiconductor layer and the bipolar transistor further comprises an n-type ohmic electrode formed on the n-type III-V compound semiconductor layer and including gold (Au), germanium (Ge), and Ni as main components.
In one embodiment of the invention, the ohmic electrode includes Pd instead of Pt.
According to still another aspect of the invention, a method for producing a bipolar transistor includes the steps of: forming a first metal layer including Ni, Pt, and Ti as main components on a p-type III-V compound semiconductor layer directly or via a thin layer; and alloying the first metal layer with a portion of the p-type III-V compound semiconductor layer by a heat treatment.
In one embodiment of the invention, the first metal layer comprises a multilayer film including a Ni layer, a Pt layer, and a Ti layer, the Pt layer being an uppermost layer, wherein the Ti layer and the Ni layer each have a thickness of 10 nm or less.
In another embodiment of the invention, the method further includes a step of forming a second metal layer including Au, Ge, and Ni as main components on an n-type III-V compound semiconductor layer directly or via another thin layer, the step being conducted between the step of forming the first metal layer and the alloying step.
In still another aspect of the invention, the second metal layer is simultaneously alloyed with the n-type III-V compound semiconductor layer at the alloying step.
According to still another aspect of the invention, a method for producing a bipolar transistor includes the steps of: etching a part of a semiconductor multilayer structure from the upper face thereof, wherein the semiconductor multilayer structure includes a first n-type III-V compound semiconductor layer, a p-type III-V compound semiconductor layer stacked above the first n-type III-V compound semiconductor layer, and a second n-type III-V compound semiconductor layer stacked above the p-type III-V compound semiconductor layer, and etching is performed until the p-type III-V compound semiconductor layer is exposed or until a thin layer remains on the p-type III-V compound semiconductor layer; forming a first metal film on the exposed p-type semiconductor layer or the exposed thin layer, the first metal film including Ni, Ti, and Pt or Pd; simultaneously etching the first metal film and the p-type III-V compound semiconductor layer until the first n-type III-V compound semiconductor layer is exposed or until another thin layer remains on the first n-type III-V compound semiconductor layer; forming a second metal film on the exposed first n-type III-V compound semiconductor layer or the exposed another thin layer, the second metal film including Au, Ge, and Ni; and alloying the first metal film with the p-type III-V compound semiconductor layer and alloying the second metal film with the first n-type III-V compound semiconductor layer by a heat treatment such that a p-type ohmic electrode and an n-type ohmic electrode are simultaneously formed on the p-type III-V compound semiconductor layer n-type III-V compound semiconductor layer, respectively.
In one embodiment of the invention, the method further includes The steps of: forming a side wall on a side face of the semiconductor multilayer structure exposed by the first etching step, after forming the first metal film; and forming a low resistance metal layer on the first metal film.
In another embodiment of the invention, the low resistance metal layer is formed by plating.
By forming a metal layer including Ni, Ti, and Pt on a p-type III-V compound semiconductor layer directly or via a thin layer, and subjecting the metal layer to a heat treatment, the Ni and Ti prevents the generation of high resistance compounds such as PtAs2 or acts to prevent the Pt from becoming diffused deeply into the p-type III-V compound semiconductor layer, thereby providing a low contact resistance between the ohmic electrode and the p-type semiconductor layer. Furthermore, an alloy composed of Ni, Ti, and Pt has a lower Schottky junction with respect to p-type semiconductors than that obtained in the case of Pt alone.
Since the heat treatment for the formation of an ohmic contact having a low contact resistivity is performed at a temperature substantially equal to the temperature of the heat treatment conducted for the formation of n-type ohmic electrodes composed of Au, Ge, and Ni, it is possible to simultaneously perform the heat treatment for the p-type ohmic electrode and the heat treatment for the n-type ohmic electrode at the same time.
By applying the ohmic electrode of the present invention to a bipolar transistor, it becomes possible to form n-type ohmic electrodes and p-type ohmic electrodes in any desired order, thereby increasing the freedom in designing the production method and structure of the device.
Furthermore, by providing a low resistance layer on a p-type ohmic electrode so as to become a base electrode, the base resistance of the device is further reduced, thereby improving the high-frequency characteristics of the device operating at a high speed.
Thus, the invention described herein makes possible the advantages of (1) providing a ohmic electrode having a low contact resistance which becomes minimum in the vicinity of an optimum temperature for the heat treatment for n-type AuGe/Ni type ohmic electrodes, and a bipolar transistor incorporating the ohmic electrode; and (2) providing a method for producing the ohmic electrode and a method for producing the bipolar transistor.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic cross-sectional view showing the construction of an electrode incorporating an ohmic electrode according to the present invention.
FIGS. 2A to 2E are cross-sectional views for describing a method for producing a p-type ohmic electrode according to the present invention.
FIG. 3 is a graph showing the relationships between the duration of a heat treatment at 350° C. and the contact resistivity of the p-type ohmic electrode of the present invention and a conventional p-type ohmic electrode.
FIG. 4 is a graph showing the relationships between the duration of a heat treatment at 400° C. and the contact resistivity of the p-type ohmic electrode of the present invention and a conventional p-type ohmic electrode.
FIG. 5 is a graph showing the relationship between the storage temperature and the MTTF of the p-type ohmic electrode of the present invention and a conventional p-type ohmic electrode.
FIGS. 6A and 6B at a cross-sectional views for describing another method for producing a p-type ohmic electrode according to the present invention.
FIG. 7 is a cross-sectional view showing the construction of a bipolar transistor according to the present invention.
FIGS. 8A to 8F are cross-sectional views for describing a method for producing the bipolar transistor shown in FIG. 7.
FIGS. 9A to 9D are cross-sectional views for describing a method for producing an Au layer on a p-type ohmic electrode of the bipolar transistor shown in FIG. 7.
FIG. 10 is a graph showing the relationship between the temperature of a heat treatment and the contact resistivity of a conventional p-type ohmic electrode as obtained by the, inventors of the present invention through experiments.
FIG. 11 is a graph showing the relationship between the temperature of a heat treatment and the contact resistivity of a conventional n-type ohmic electrode as obtained by the inventors of the present invention through experiments.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Hereinafter, the present invention will be described by way of examples with reference to the accompanying figures.
First, the ohmic electrode according to the present invention and the method for producing the same will be described.
FIG. 1 schematically shows a cross section of an electrode 7 in which an ohmic electrode 4 of the present invention is used. As shown in FIG. 1, a p-type GaAs layer 2 is formed on a semi-insulating GaAs substrate 1. The p-type ohmic electrode 4, which is composed of an alloy layer of nickel, titanium, and platinum, is formed on the p-type GaAs layer 2. A diffusion layer 3, in which nickel, titanium, and platinum (which constitute the p-type ohmic electrode 4) are diffused, is formed in the p-type GaAs layer 2 in the portion below the p-type ohmic electrode 4. In other words, the p-type ohmic electrode 4 and the GaAs layer 2 are alloyed to each other in the diffusion layer 3. A titanium layer 5 is formed on the p-type ohmic electrode 4. A platinum layer 6 Is formed on the titanium layer 5.
The electrode 7 is formed by the following method, for example.
As shown in FIG. 2A, the p-type GaAs layer 2 is epitaxially grown on the semi-insulating GaAs substrate 1. The p-type GaAs layer 2, on which the ohmic electrode 4 is to be formed,.may be any GaAs semiconductor layer having a p-type conductivity; the impurity concentration and thickness thereof may be adjusted to a specific purpose. In the present example,the p-type GaAs layer 2 has a thickness of 150 nm and a carrier density of 2×1019 cm-3. Furthermore, a resist pattern 13 with an opening having a desired shape is formed on the p-type GaAs layer 2.
Next, as shown in FIG. 2B, a Ni film 14 (thickness: 5 mm), a titanium film 15 (thickness: 5 nm), a Pt film 16 (thickness: 5 nm), a titanium film 17 (thickness: 30 nm), and a P=film 18 (thickness: 100 nm) are successively deposited by an electron beam vapor deposition method in this order. The Ni film 14, Ti film 15, and the Pt film 16 constitute a metal multilayer film 21 to become the p-type ohmic electrode 4. Alternatively, the Ni film 14 and the Ti film 15 may be reversed. That is, the Ti film 15 (thickness: 5 nm), the Ni film 14 (thickness: 5 nm), the Pt film 16 (thickness: 5 nm), the titanium film 17 (thickness: 30 nm), and the Pt film 18 (thickness: 100 nm) may be formed on the p-type GaAs layer 2 in this order. Moreover, the titanium film 17 and the Pt film 18 merely function as a pad, and therefore are dispensable as an ohmic electrode for p-type compound semiconductors. Accordingly, an ohmic electrode for p-type compound semiconductors should only include the Ni film 14, Ti film 15, and the Pt film 16, with the Pt film 16 being the uppermost layer of the metal multilayer film 21.
If the thicknesses of the Ni film 14 and the Ti film 15 are too large, it becomes difficult for Pt atoms in the Pt film 16 to enter the p-type GaAs layer 2 during a subsequent heat treatment, so that the diffusion layer 3 shown in FIG. 2C may not be formed. Therefore, the thicknesses of the Ni film 14 and the Ti film 15 are preferably in the range of 1 nm to 50 nm, and more preferably 2 nm to 10 nm.
Thereafter, a lift-off method is conducted where the resist pattern 13 is dissolved with acetone, and the respective metal films are patterned into desired shapes.
Next, as shown in FIG. 2C, the Ni film 14, Ti film 15, and Pt film 16 are alloyed with one another by conducting a heat treatment at 400° C. for 10 minutes so as to form the p-type ohmic electrode 4. Moreover, a portion of Ni, Ti, and Pt constituting the Ni film 14, Ti film 15, and Pt film 16 is diffused into the p-type GaAs layer 2, whereby the diffusion layer 3 is obtained. The temperature and duration of the heat treatment can be selected, in order to attain a desired contact resistivity, in accordance with the specific characteristics required for an element to which the p-type ohmic electrode 4 is applied. However, the heat treatment is preferably conducted at a temperature in the range of 360° C. to 460° C., more preferably in the range of 370° C. to 420° C. in order to form a p-type ohmic electrode having a low contact resistivity. Since this range of temperatures substantially coincides with the temperature of the heat treatment conducted for the formation of n-type ohmic electrodes composed of Au, Ge, and Ni, it is possible to simultaneously perform a heat treatment for the formation of n-type ohmic electrodes and a heat treatment for the formation of p-type ohmic electrodes at the same temperature.
A metal layer composed of Au or the like may be formed on the uppermost Pt layer 18 in order to reduce the resistance of the electrode itself.
FIGS. 3 and 4 show the measurement results of the contact resistivity of the electrode 7 including the p-type ohmic electrode 4 produced in the above-mentioned manner. FIG. 3 shows the relationship between the duration of a heat treatment conducted at 350° C. for the formation of the electrode and the contact resistivity. FIG. 4 shows the relationship between the duration of a heat treatment conducted at 400° C. for the formation of the electrode and the contact resistivity. Measurement results of a conventional Pt/Ti/Pt ohmic electrode are also indicated in FIGS. 3 and 4 for comparison.
As seen from FIG. 3, the electrode 7 provides a contact resistivity of about: 3.8×10-7 Ω·cm2 by conducting a heat treatment at 350° C. for 10 minutes. The contact resistivity thereof hardly increases even if the electrode 7 is subjected to a heat treatment for a long time. For example, the contact resistivity is about 4.2×10-7 Ω·cm2 after 80 minutes of heat treatment.
On the other hand, the conventional Pt/Ti/Pt ohmic electrode provides a contact resistivity of about 3.6 -10-7 ωcm2 by conducting a heat treatment at 350° C. for 10 minutes. However, the contact resistivity increases as the duration of the heat treatment increases. For example, the contact resistivity is about 7.0×10-7 Ω·cm2 after 80 minutes of heat treatment. As will be appreciated, the ohmic: electrode of the present invention has a high heat resistance.
The advantage of the present invention becomes clearer in the case of a heat treatment at 400° C. As shown in FIG. 4, the electrode 7 of the present example provides a contact resistivity of about 2.1×10.sup.×7 Ω·cm2 by conducting a heat treatment at 400° C. for 10 minutes. Although the contact resistivity increases as the duration of the heat treatment increases, the contact resistivity remains at about 5.6×10-7 Ω·cm2 even after 80 minutes of heat treatment.
On the other hand, the conventional Pt/Ti/Pt ohmic electrode provides a contact resistivity of about 7.0 ×10-7 ω·cm2 by conducting a heat treatment at 400° C. for 10 minutes. The contact resistivity increases to about 8.4×10-7 Ω·cm2 after 80 minutes of heat treatment.
Accordingly, the electrode 7 of the present example has a minimum contact resistivity when the heat treatment is conducted at 400° C., and achieves a lower contact resistivity than that of a conventional p-type Pt/Ti/Pt/Au ohmic electrode.
FIG. 5 shows the results of a high temperature storage test in which the electrode 7 of the present example, obtained by a heat treatment at 400° C. for 10 minutes and a conventional Pt/Ti/Pt ohmic electrode obtained by a heat treatment at 350° C. for 10 minutes are left at temperatures ranging from 300° C. to 400° C. In FIG. 5, the MTTF (Mean Time To Failure) is defined as the mean time required for the contact resistivity to increase by 50%.
As shown in FIG. 5, the gradient of the line representing the electrode 7 is substantially equal to the gradient of the line representing the conventional ohmic electrode. Based on these gradients, the activation energy of the deterioration reaction for the ohmic electrodes is deduced to be about 1.6 eV. This indicates that the electrode 7 of the present example and the conventional ohmic electrode may deteriorate by the same deterioration mechanism. However, electrode 7 of the present example takes a longer deterioration time than the conventional ohmic electrode when left at the same temperature. For example, while the MTTF at 150° C. is 6.5×106 hours for the electrode 7, it is 1.3×106 hours for the conventional ohmic electrode, indicating the comparative excellence of the electrode 7 is five times. It will be appreciated that the electrode 7 of the present example is also excellent in terms of reliability.
Considering the above test results and the like, it is presumed that according to the present invention, the Ni and Ti prevent the generation of high resistance compounds such as PtAs2 at temperatures in the vicinity of 400° C., or prevent the Pt from becoming diffused deeply into the p-type semiconductor layer, thereby leading to the low contact resistance between the ohmic electrode of the present invention and any p-type semiconductor. It is further presumed that an alloy composed of Ni, Tt, and Pt has a lower Schottky Junction with respect to p-type semiconductors than that obtained in the case of Pt alone.
In the above example, as shown in FIG. 2B, the metal multilayer film 21 is formed directly on the p-type GaAs layer 2, a thin semiconductor layer may be interposed between the metal multilayer film 21 and the p-type GaAs layer 2 if a portion of Ni, Ti, and Pt of the metal multilayer film 21 is diffused into the p-type GaAs layer 2, whereby the diffusion layer 3 is obtained by heat treatment, as shown in FIG. 2C. For example, as shown in FIG. 2D, a thin semiconductor layer 19 is formed on the p-type GaAs layer 2 and the metal multilayer film 21 is formed on the p-type GaAs layer 2 via the thin semiconductor layer 19. Then, as shown in FIG. 2E, a portion of Ni, Ti, and Pt of the metal multilayer film 21 is diffused into the p-type GaAs layer 2 through the thin semiconductor layer 19 or is diffused into the p-type GaAs layer 2 accompanying the thin semiconductor layer 19. Simultaneously, the p-type ohmic electrode 4 is formed on the p-type GaAs layer 2 by alloying the metal multilayer film 21.
Although the metal multilayer film may contain films of Ni, Ti and Pt wherein Pt is the top layer, the metal multilayer film may also contain films of Ni, Ti and Pd (which is the same group as Pt) in which the Pt film is replaced by a film of Pd. Moreover, instead of separately forming a Ni film, a Ti film, and a Pt film, it is applicable to form an alloy film composed of Ni, Ti, and Pt. For example, as shown in FIG. 6A, an alloy film 22 of Ni, Ti, and Pt may be formed on a p-type GaAs layer 2 directly or via a thin semiconductor layer (not shown.), and after conducting a lift-off method, a p-type ohmic electrode 4 may be formed by a heat treatment, resulting in a configuration shown in FIG. 6B. The alloy film 22 may be deposited by simultaneously evaporating the respective metals. Alternatively, the alloy film 22 may be obtained by depositing a pre-fabricated alloy containing Ni, Ti, and Pt at the above-mentioned range of ratios.
The p-type ohmic electrode of the present invention is applicable to any other p-type III-V group semiconductor layer, as well as p-type GaAs layer. Preferable examples of III-V group semiconductors include AlGaAs, GaInAsP, AlGaInAs, AlGaAsSb, InAsSbP, AlGaInP, and GaAlN.
Hereinafter, an example will be described where the p-type ohmic electrode of the present invention is used as a base electrode of a bipolar transistor. As shown in FIG. 7, a bipolar transistor 41 according to the present invention includes a semiconductor multilayer structure 42 formed on a semi-insulating GaAs substrate 31. The semiconductor multilayer structure 42 includes a collect or contact layer 32 of n+ -GaAs, a collector layer 33 of n31 -GaAs, a base layer 34 of p+ -GaAs, an emitter layer 35 of n-AlGaAs, and an emitter contact layer 36 of n+ -InGaAs. An AlGaAs semiconductor constituting the emitter layer 35 has a larger band gap than of GaAs semiconductor constituting the base layer 34, the bipolar transistor 41 has therefore, a hetero-3unction structure.
A collector electrode 37 composed of an alloy of Au, Ge, and Ni is formed, as an n-type ohmic electrode, on a portion of the collector contact layer 32. A base electrode 38 is formed, as a p-type ohmic electrode, on a portion of the base layer 34. The base electrode 38 is composed of an alloy of Ni, Ti, and Pt, as described in the above-mentioned example. A diffusion layer 39 is formed in the base layer 34 in a portion below the base electrode 38. Moreover, an emitter electrode 40 is formed on the emitter contact layer 36.
A method for producing the bipolar transistor 41 will be described with reference to FIGS. 8A to 8F. As shown in FIG. 8A, the collector contact layer 32 of n- -GaAs, the collector layer 33 of n- -GaAs, the base layer 34 of p-GaAs, the emitter layer 35 of n-AlGaAs, and the emitter contact layer 36 of n+ -InGaAs are epitaxially grown on the semi-insulating GaAs substrate 31 in this order. Next, as shown in FIG. 8B, a tungsten silicide (WSi) film 57 is formed on the emitter contact layer 36 by sputtering. Then, a resist pattern 58 is formed on the tungsten silicide film 57 by photolithography.
The tungsten silicide film 57 is etched by RIE (Reactive Ion Etching) while using the resist pattern 58 as a mask so as to form an electrode 59 as shown in FIG. 8C. Since the Schottky barrier height created by the contact between n+ -InGaAs and tungsten silicide is small, the electrode 59 is in contact with the emitter contact layer 36 with a low contact resistance without conducting a heat treatment.
Next, the emitter contact layer 36 and the emitter layer 35 are etched by wet etching while using the electrode 59 as a mask, so as to expose the surface of the base layer 34. A thin semiconductor layer of a portion of the emitter layer 35 may remain on the base layer 34. Since the emitter contact layer 36 and the emitter layer 35 are etched in an isotropical manner, the width W2 of the emitter contact layer 36 and the emitter layer 35 becomes smaller than the width W1 of the electrode 59.
Thereafter, as shown in FIG. 8D, a metal multilayer film 60 is vapor deposited by an electron beam method so as to cover the entire semi-insulating GaAs substrate 31. The metal multilayer film 60 includes a Ni layer (thickness: 5 nm), a Ti layer (thickness: 5 nm), a Pt layer (thickness: 5 nm), a Ti layer (thickness: 30 nm), and a Pt layer (thickness: 100 nm).
As shown in FIG. 8E, a resist pattern 61 is formed so as to cover the emitter contact layer 36. The emitter layer 35, and a portion of the metal multilayer film 60 that will become the base electrode 38. The metal multilayer film 60 and the base layer 34 are simultaneously etched by an ion milling method, while using the resist pattern 61 as a mask, until the collector layer 33 is exposed. Furthermore, a portion of the collector layer 33 is etched.
As shown in FIG. 8F, after removing the resist pattern 61, the collector contact layer 32 is exposed by photolithography and wet etching, and a metal multilayer film 64 composed of an Au-Ge layer (thickness: 100 nm), a Ni layer (thickness: 20 nm), and an Au layer (thickness: 200 nm) is formed by a lift-off method.
Finally, a heat treatment is conducted at 400° C. for 10 minutes, so as to alloy the metal multilayer film 64 and the collector layer 33 with each other, whereby the collector electrode 37 composed of an alloy of Au, Ge, and Ni is obtained. At the same time, the metal multilayer film 60 and the base layer 34 are alloyed with each other, whereby the base electrode 38 composed of an alloy of Ni, Ti, and Pt is obtained. Since the collector electrode 37 and the base electrode 38 are formed into alloys under optimum conditions, i.e., at 400° C., the former as an n-type ohmic electrode and the latter as a p-type ohmic electrode, they achieve extremely low contact resistances. The metal multilayer film 60 and the electrode 59 constitute the emitter electrode 40. Although the emitter contact layer 36 and the electrode 59 are heated during the above-mentioned heat treatment, the heat treatment is not particularly necessary for the emitter contact layer 36 and the electrode 59, a sufficient ohmic contact is achieved between the emitter contact layer 36 and the electrode 59 in a non-alloy ohmic contact manner.
In the above-described method for producing a bipolar transistor, the metal multilayer film 60 and the base layer 34 are simultaneously etched by using the resist pattern 61 as a mask after the metal multilayer film 60, which becomes the base electrode 38, is formed on the base layer 34. As a result, the base electrode 38 is formed in a self-alignment with the base layer 34. This maximizes the contact area between the base electrode 38 and the base layer 34, and yet reduces the base-collector capacitance. As a result, a bipolar transistor having excellent high-frequency characteristics can be produced. Moreover, either the collector electrode 37 or the base electrode 38 can be formed first, so that increased freedom is provided in the designing of the element structure.
On the other hand, in the case of the production of a bipolar transistor incorporating a conventional Pt/Ti/Pt/Au base electrode, those processes which require heat treatments at higher temperatures must be conducted first. Therefore, the base electrode must be formed after establishing a base layer and forming a collector electrode on a collector layer thereby making it very difficult to form the base electrode in a self-matching manner with respect to the base layer. As a result, a very complicated production process is required.
As shown in FIG. 7, it is applicable to provide a metal layer 71 having a low resistance on the base electrode 38 of the bipolar transistor 41 in order to reduce the resistance of the base electrode 38. In this case, it is preferable to cover side faces of the emitter layer 35 and the emitter contact layer 36 with an insulating film 73. A method for obtaining such an metal layer 71 and an insulating film 72 will be described below.
After vapor depositing the metal multilayer film 60 so as to cover the entire semi-insulating GaAs substrate 31 as described with reference to FIG. 8D, the insulating film 73, composed of silicon oxide or the like, is deposited so as to cover the entire semi-insulating GaAs substrate 31, as shown in FIG. 9A. Next, as shown in FIG. 9B, the insulating film 73 is etched by an anisotropy etching method until the surface of the metal multilayer film 60 is exposed, so as to be left as a side wall 74 covering the sides of the emitter layer 35 and the emitter contact layer 36.
Subsequently, as shown in FIG. 9C, the metal layer 71, composed of Au, is formed on the metal multilayer film 60 by a plating method using the metal multilayer film 60 as an electrode. Then, as shown in FIG. 9D, the resist pattern 61 is formed, and the Au layer 71, the metal multilayer film 60, and the base layer 34 are etched by an ion milling method. Moreover, a portion of the collector layer 33 is etched. Thereafter, the process described with reference to FIG. 8F is continued.
In accordance with the above-mentioned structure, the Au layer 71 can be formed with a large thickness on the base electrode 38, without being electrically short-circuited with the emitter layer 35, the emitter contact layer 36, or the emitter electrode 40. The metallic resistance of the base electrode 38 can also be reduced. This structure is particularly advantageous if the base electrode is to be formed in a minute shape. Moreover, the high frequency characteristics of a high frequency device can be improved.
Although an emitter-up type structure, in which an emitter is disposed in an upper portion of the bipolar transistor was described in the above example, the present invention is applicable to a collector-up structure, in which a collector is disposed in an upper portion of the bipolar transistor. Although an npn-type bipolar transistor was described in the above example, the electrode of the present invention can be used as a collector electrode or as an emitter electrode of a pnp-type bipolar transistor.
As is appreciated form the aforementioned example, in a bipolar transistor of the invention, a p-type ohmic electrode of the invention and an n-type ohmic electrode may be formed directly on the base, emitter, and collector layers having an appropriate conductivity type, or on contact layers formed in contact with these layers.
Although a vertical-type transistor was described in the above example, it will be appreciated that the present invention is applicable to other compound semiconductor elements incorporating p-type ohmic electrodes as well.
In addition, a p-type ohmic electrode of the invention has a low Schottky barrier height against a p-type semiconductor, therefore, a p-type ohmic electrode has a high Schottky barrier height against an n-type semiconductor and as good a characteristic as a Schottky electrode. Accordingly, metal layers including Ni, Ti, and Pt or Pd may be applied to a gate electrode for n-channel MESFET. In this case, heat treatment is required for diffusing Pt into a n-type semiconductor layer.
According to the present invention, a highly reliable p-type ohmic electrode having a low contact resistivity can be provided.
Moreover, it is possible to simultaneously perform a heat treatment for the formation of a p-type ohmic electrode and an n-type ohmic electrode at the same temperature in the production of a bipolar transistor, thereby simplifying the production process. Since either of the p-type ohmic electrode or the n-type ohmic electrode can be formed first, it becomes possible to freely design a transistor without being limited by the production process thereof. Furthermore, by providing a low resistance layer on a p-type ohmic electrode so as to become a base electrode, the base resistance of the device is further reduced, thereby improving the high-frequency characteristics of the device operating at a high speed.
Various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be broadly construed.

Claims (15)

What is claimed is:
1. An ohmic electrode for a p-type III-V compound semiconductor, the ohmic electrode being formed on a p-type III-V compound semiconductor layer, wherein the ohmic electrode includes nickel (Ni), titanium (Ti), and one of platinum (Pt) or palladium (Pal) as main components in an interface between the ohmic electrode and the p-type III-V compound semiconductor layer.
2. The ohmic electrode for a p-type III-V compound semiconductor according to claim 1, wherein the ohmic electrode includes Pd.
3. The ohmic electrode for a p-type III-V compound semiconductor according to claim 1, wherein the ohmic electrode includes Pt.
4. The ohmic electrode for a p-type III-V compound semiconductor according to claim 1, wherein the ohmic electrode is prepared by forming a metal layer made of Ni, Ti, and one of Pt or Pd on the p-type III-V compound semiconductor and alloying the metal layer with a portion of the p-type III-V compound semiconductor through a heat treatment at a temperature in a range of 360° C. to 460° C.
5. The ohmic electrode for a p-type III-V compound semiconductor according to claim 4, wherein the heat treatment is conducted at a temperature in a range of 370° C. to 420° C.
6. The ohmic electrode for a p-type III-V compound semiconductor according to claim 4, wherein the metal layer comprises a multilayer film comprising a Ni layer, a Ti layer, and a Pt layer, the Pt layer being an uppermost layer.
7. The ohmic electrode for a p-type III-V compound semiconductor according to claim 6, wherein the Ti layer has a thickness of 10 nm or less.
8. A bipolar transistor comprising: a p-type III-V compound semiconductor layer; and an ohmic electrode formed on the p-type III-V compound semiconductor layer wherein the ohmic electrode comprises Ni, Ti, and one of Pt or Pd as main components.
9. The bipolar transistor according to claim 8 further comprising an n-type III-V compound semiconductor layer and a second ohmic electrode formed on the n-type 1II-V compound semiconductor layer wherein the second ohmic electrode comprises gold (Au), germanium (Ge), and nickel (Ni) as main components.
10. The bipolar transistor according to claim 9, wherein the ohmic electrode includes Pd.
11. The bipolar transistor according to claim 8, wherein the ohmic electrode includes pt.
12. The bipolar transistor according to claim 8, wherein the ohmic electrode is prepared by forming a metal layer made of Ni, Ti, and one of Pt or Pd on the p-type III-V compound semicoductor and alloying the metal layer with a portion of the p-type III-V compound semiconductor through a heat treatment at a temperature of 370° C. to 420° C.
13. The bipolar transistor according to claim 12, wherein the heat treatment is conducted at a temperature in a range of 370° C. to 420° C.
14. The bipolar transistor according to claim 12, wherein the metal layer comprises a multiplayer film comprising a Ni layer, a Ti layer, and a Pt layer, the Pt layer being an uppermost layer.
15. the bipolar transistor according to claim 14, wherein, the Ti layer has a thickness of 10 nm or less.
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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6222863B1 (en) * 1998-01-31 2001-04-24 Lucent Technologies, Inc. Article comprising a stable, low-resistance ohmic contact
US6392262B1 (en) * 1999-01-28 2002-05-21 Nec Corporation Compound semiconductor device having low-resistive ohmic contact electrode and process for producing ohmic electrode
US6469319B1 (en) * 1999-12-04 2002-10-22 National Science Council Ohmic contact to a II-VI compound semiconductor device and a method of manufacturing the same
US6614115B2 (en) * 2000-11-22 2003-09-02 Agere Systems Inc. Enhancement of carrier concentration in As-containing layers
US20040222434A1 (en) * 1998-05-13 2004-11-11 Toyoda Gosei Co., Ltd. Light-emitting semiconductor device using group III nitride compound
US20050029525A1 (en) * 2003-08-06 2005-02-10 Atomic Energy Council - Institute Of Nuclear Energy Research Semiconductor device and method for fabricating the same
US6858522B1 (en) * 2000-09-28 2005-02-22 Skyworks Solutions, Inc. Electrical contact for compound semiconductor device and method for forming same
US20090065811A1 (en) * 2007-09-07 2009-03-12 Ping-Chih Chang Semiconductor Device with OHMIC Contact and Method of Making the Same
US20100219394A1 (en) * 2007-08-31 2010-09-02 Lattice Power (Jiangxi) Corporation Method for fabricating a low-resistivity ohmic contact to a p-type iii-v nitride semiconductor material at low temperature
US20140097540A1 (en) * 2012-10-05 2014-04-10 Chipbond Technology Corporation Semiconductor structure
CN103730437A (en) * 2012-10-15 2014-04-16 颀邦科技股份有限公司 Semiconductor structure
FR3084774A1 (en) * 2018-08-01 2020-02-07 Commissariat A L'energie Atomique Et Aux Energies Alternatives PROCESS FOR PRODUCING THERMALLY STABLE OHMIC CONTACT ON INP OR INGAAS SEMICONDUCTOR
CN112447859A (en) * 2019-08-29 2021-03-05 阿聚尔斯佩西太阳能有限责任公司 Multi-junction solar cell in the form of a stack with metallization layers comprising a multilayer system
US11195721B2 (en) * 2018-01-16 2021-12-07 Princeton Optronics, Inc. Ohmic contacts and methods for manufacturing the same

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61102071A (en) * 1984-10-25 1986-05-20 Nec Corp Semiconductor device
EP0222395A1 (en) * 1985-11-13 1987-05-20 Kabushiki Kaisha Toshiba Improvement in electrode structure of photosemiconductor device
US4673593A (en) * 1984-03-07 1987-06-16 Sumitomo Electric Industries Ltd. Process for forming an ohmic electrode on a p-type III-V compound semiconductor
JPS62219518A (en) * 1986-03-19 1987-09-26 Nec Corp Formation of electrode of compound semiconductor element
JPS62234322A (en) * 1986-04-04 1987-10-14 Nec Corp Manufacture of semiconductor device
US4853346A (en) * 1987-12-31 1989-08-01 International Business Machines Corporation Ohmic contacts for semiconductor devices and method for forming ohmic contacts
JPH0246773A (en) * 1988-08-09 1990-02-16 Toshiba Corp Compound semiconductor device and formation of its electrode
JPH0264474A (en) * 1988-08-31 1990-03-05 Fujitsu Ltd Earth detection circuit
JPH0297067A (en) * 1988-10-03 1990-04-09 Mitsubishi Electric Corp Electrode structure of semiconductor device
JPH03184377A (en) * 1989-12-13 1991-08-12 Hitachi Ltd Electrode for compound semiconductor
JPH03286526A (en) * 1990-04-02 1991-12-17 Sumitomo Electric Ind Ltd Formation of electrode
US5077599A (en) * 1989-06-16 1991-12-31 Sumitomo Electric Industries, Ltd. Electrode structure for iii-v compound semiconductor element and method of manufacturing the same
JPH0492471A (en) * 1990-08-08 1992-03-25 Fujitsu Ltd Semiconductor device
US5179041A (en) * 1989-06-16 1993-01-12 Sumitomo Electric Industries, Ltd. Method for manufacturing an electrode structure for III-V compound semiconductor element
US5284798A (en) * 1989-08-30 1994-02-08 Mitsubishi Kasei Polytec Co. Method for forming an electrode for a compound semiconductor

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4673593A (en) * 1984-03-07 1987-06-16 Sumitomo Electric Industries Ltd. Process for forming an ohmic electrode on a p-type III-V compound semiconductor
JPS61102071A (en) * 1984-10-25 1986-05-20 Nec Corp Semiconductor device
EP0222395A1 (en) * 1985-11-13 1987-05-20 Kabushiki Kaisha Toshiba Improvement in electrode structure of photosemiconductor device
JPS62219518A (en) * 1986-03-19 1987-09-26 Nec Corp Formation of electrode of compound semiconductor element
JPS62234322A (en) * 1986-04-04 1987-10-14 Nec Corp Manufacture of semiconductor device
US4853346A (en) * 1987-12-31 1989-08-01 International Business Machines Corporation Ohmic contacts for semiconductor devices and method for forming ohmic contacts
JPH0246773A (en) * 1988-08-09 1990-02-16 Toshiba Corp Compound semiconductor device and formation of its electrode
JPH0264474A (en) * 1988-08-31 1990-03-05 Fujitsu Ltd Earth detection circuit
JPH0297067A (en) * 1988-10-03 1990-04-09 Mitsubishi Electric Corp Electrode structure of semiconductor device
US5077599A (en) * 1989-06-16 1991-12-31 Sumitomo Electric Industries, Ltd. Electrode structure for iii-v compound semiconductor element and method of manufacturing the same
US5179041A (en) * 1989-06-16 1993-01-12 Sumitomo Electric Industries, Ltd. Method for manufacturing an electrode structure for III-V compound semiconductor element
US5284798A (en) * 1989-08-30 1994-02-08 Mitsubishi Kasei Polytec Co. Method for forming an electrode for a compound semiconductor
JPH03184377A (en) * 1989-12-13 1991-08-12 Hitachi Ltd Electrode for compound semiconductor
JPH03286526A (en) * 1990-04-02 1991-12-17 Sumitomo Electric Ind Ltd Formation of electrode
JPH0492471A (en) * 1990-08-08 1992-03-25 Fujitsu Ltd Semiconductor device

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
Mochizuki et al., Au/Pt/Ti/Ni Ohmic Contacts to p ZnSe, Electronics Letters, Nov. 10, 1994, vol. 30, No. 23, pp. 1984 1985. *
Mochizuki et al., Au/Pt/Ti/Ni Ohmic Contacts to p-ZnSe, Electronics Letters, Nov. 10, 1994, vol. 30, No. 23, pp. 1984-1985.
Okada et al, Japanese Journal of Appl. Physics, vol. 30, No. 4A, pp. L558 L 560, 1991, Electrical Characteristics & Reliability of Pt/Ti/Pt/Au . . . . *
Okada et al, Japanese Journal of Appl. Physics, vol. 30, No. 4A, pp. L558-L-560, 1991, "Electrical Characteristics & Reliability of Pt/Ti/Pt/Au . . . ".
Sugiyama et al, Extended Abs. of 1993 Intl. Conf. on Solid State Devices & Materials, Makuhari, pp. 1062 1064, 1993. *
Sugiyama et al, Extended Abs. of 1993 Intl. Conf. on Solid State Devices & Materials, Makuhari, pp. 1062-1064, 1993.

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6222863B1 (en) * 1998-01-31 2001-04-24 Lucent Technologies, Inc. Article comprising a stable, low-resistance ohmic contact
US20040222434A1 (en) * 1998-05-13 2004-11-11 Toyoda Gosei Co., Ltd. Light-emitting semiconductor device using group III nitride compound
US7109529B2 (en) 1998-05-13 2006-09-19 Toyoda Gosei Co., Ltd. Light-emitting semiconductor device using group III nitride compound
US6936859B1 (en) * 1998-05-13 2005-08-30 Toyoda Gosei Co., Ltd. Light-emitting semiconductor device using group III nitride compound
US6392262B1 (en) * 1999-01-28 2002-05-21 Nec Corporation Compound semiconductor device having low-resistive ohmic contact electrode and process for producing ohmic electrode
US6469319B1 (en) * 1999-12-04 2002-10-22 National Science Council Ohmic contact to a II-VI compound semiconductor device and a method of manufacturing the same
US6858522B1 (en) * 2000-09-28 2005-02-22 Skyworks Solutions, Inc. Electrical contact for compound semiconductor device and method for forming same
US6614115B2 (en) * 2000-11-22 2003-09-02 Agere Systems Inc. Enhancement of carrier concentration in As-containing layers
US7075113B2 (en) * 2003-08-06 2006-07-11 Atomic Energy Council Institute Of Nuclear Energy Research Semiconductor device and method for fabricating the same
US20050029525A1 (en) * 2003-08-06 2005-02-10 Atomic Energy Council - Institute Of Nuclear Energy Research Semiconductor device and method for fabricating the same
US20100219394A1 (en) * 2007-08-31 2010-09-02 Lattice Power (Jiangxi) Corporation Method for fabricating a low-resistivity ohmic contact to a p-type iii-v nitride semiconductor material at low temperature
US8431475B2 (en) * 2007-08-31 2013-04-30 Lattice Power (Jiangxi) Corporation Method for fabricating a low-resistivity ohmic contact to a p-type III-V nitride semiconductor material at low temperature
US20090065811A1 (en) * 2007-09-07 2009-03-12 Ping-Chih Chang Semiconductor Device with OHMIC Contact and Method of Making the Same
US20140097540A1 (en) * 2012-10-05 2014-04-10 Chipbond Technology Corporation Semiconductor structure
TWI555148B (en) * 2012-10-05 2016-10-21 頎邦科技股份有限公司 Semiconductor structure
CN103730437A (en) * 2012-10-15 2014-04-16 颀邦科技股份有限公司 Semiconductor structure
US11195721B2 (en) * 2018-01-16 2021-12-07 Princeton Optronics, Inc. Ohmic contacts and methods for manufacturing the same
FR3084774A1 (en) * 2018-08-01 2020-02-07 Commissariat A L'energie Atomique Et Aux Energies Alternatives PROCESS FOR PRODUCING THERMALLY STABLE OHMIC CONTACT ON INP OR INGAAS SEMICONDUCTOR
CN112447859A (en) * 2019-08-29 2021-03-05 阿聚尔斯佩西太阳能有限责任公司 Multi-junction solar cell in the form of a stack with metallization layers comprising a multilayer system

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