US20160308014A1 - Fabrication of channel wraparound gate structure for field-effect transistor - Google Patents

Fabrication of channel wraparound gate structure for field-effect transistor Download PDF

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US20160308014A1
US20160308014A1 US15/197,563 US201615197563A US2016308014A1 US 20160308014 A1 US20160308014 A1 US 20160308014A1 US 201615197563 A US201615197563 A US 201615197563A US 2016308014 A1 US2016308014 A1 US 2016308014A1
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gate electrode
semiconductor body
gate
semiconductor
channel
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US15/197,563
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Marko Radosavljevic
Amlan Majumdar
Suman Datta
Jack T. Kavalieros
Brian S. Doyle
Justin K. Brask
Robert S. Chau
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Tahoe Research Ltd
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Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHAU, ROBERT S., DOYLE, BRIAN S., DATTA, SUMAN, RADOSAVLJEVIC, MARKO, KAVALIEROS, JACK T., MAJUMDAR, AMLAN, BRASK, JUSTIN K.
Assigned to TAHOE RESEARCH, LTD. reassignment TAHOE RESEARCH, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTEL CORPORATION
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Definitions

  • the invention is in the field of Field-Effect Transistors.
  • CMOS complementary metal-oxide-semiconductor
  • Examples of transistors having reduced bodies along with tri-gate structures are shown in US 2004/0036127.
  • Other small transistors are delta-doped transistors fanned in lightly doped or undoped epitaxial layers grown on a heavily doped substrate. See, for instance, “Metal Gate Transistor with Epitaxial Source and Drain Regions,” application Ser. No. 10/955,669, filed Sep. 29, 2004, assigned to the assignee of the present application.
  • Off-state current reduces the switching efficiency and robs system power. This is particularly significant in planar CMOS transistors, where substrate leakage paths account for most of the current flow in the off state. While three-dimensional structures such as tri-gates and fin-FETs are more scalable, since they have more effective electrostatic control, there still remains a leakage path in the channel.
  • FIG. 1 is a cross-sectional, elevation view of a silicon-on-insulator (SOI) substrate.
  • SOI silicon-on-insulator
  • FIG. 2 is a perspective view of the structure of FIG. 1 , after the formation of a silicon body, sometimes referred to as a fin.
  • FIG. 3 illustrates the structure of FIG. 2 , after a dummy gate is fabricated and during a first ion implantation step.
  • FIG. 4 illustrates the structure of FIG. 3 , after spacers are fabricated and during a second ion implantation step.
  • FIG. 5 illustrates the structure of FIG. 4 , after forming a dielectric layer and after the removal of the dummy gate.
  • FIG. 6 is a cross-sectional, elevation view of the structure of FIG. 5 through section line 6 - 6 of FIG. 5 .
  • FIG. 7 illustrates the structure of FIG. 6 during an ion implantation step.
  • FIG. 8 illustrates the structure of FIG. 7 after an etching step which removes the BOX under the channel region. This view is generally through section line 8 - 8 of FIG. 5 .
  • FIG. 9 is an enlarged view of the region beneath the gate after the formation of a gate dielectric layer and a gate metal.
  • FIG. 10 is a cross-sectional, elevation view taken through the same plane as FIG. 6 , this view illustrates the formation of the gate encircling the entire channel region of a semiconductor body.
  • CMOS field-effect transistors A process for fabricating CMOS field-effect transistors and the resultant transistors are described.
  • numerous specific details are set forth, such as specific dimensions and chemical regimes, in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known processing steps, such as cleaning steps, are not described in detail, in order to not unnecessarily obscure the present invention, Also in the description below, the fabrication of a single transistor is described. As will be appreciated in the typical integrated circuit, both n and p channel transistors are fabricated.
  • transistors are fabricated on a buried oxide layer (BOX) 20 which is disposed on a silicon substrate 21 shown in FIG. 1 .
  • Transistor bodies are fabricated from a monocrystalline, silicon layer 24 disposed on BOX 20 .
  • This silicon-on-insulation (SOI) substrate is well-known in the semiconductor industry.
  • the SOI substrate is fabricated by bonding the oxide layer 20 and silicon layer 24 onto the substrate 21 , and then planarizing the layer 24 until it is relatively thin.
  • Other techniques are known for forming an SOI substrate eluding, for instance, the implantation of oxygen into a silicon substrate to form a buried oxide layer.
  • Other semiconductor materials, other than silicon, may also be used such as gallium arsenide.
  • the BOX is seeded through ion implantation beneath the channel region of a transistor to make the oxide more readily etchable than the overlying, silicon body.
  • An electrically inactive species is implemented so as to not alter the electrical characteristics of the semiconductor body. Then, after removal of the BOX beneath the channel, a gate insulator and gate are formed entirely around the channel.
  • the layer 24 may be selectively ion implanted with a p type dopant in regions where n channel transistors are to be fabricated, and with an type dopant in those regions where p channel devices are to be fabricated. This is used to provide the relatively light doping typically found in the channel regions of MOS devices fabricated in a CMOS integrated circuit.
  • a protective oxide is disposed on the silicon layer 24 followed by the deposition of a silicon nitride layer (both not shown).
  • the nitride layer acts as a hard mask to define silicon bodies such as the silicon body 25 of FIG. 2 .
  • the body 25 may have a height and width of 20-30 nm.
  • An oxide (not shown) which subsequently acts as an etchant stop is formed over body 25 .
  • a polysilicon layer is formed over the structure of FIG. 2 and etched to define a dummy gate 30 which extends over the body 25 as seen in FIG. 3 .
  • the region of the body 25 below the dummy gate 30 is the channel region in this replacement gate process.
  • phosphorous or arsenic may be implanted into the body 25 for an n channel transistor, or boron for a p channel transistor in alignment with the dummy gate, as illustrated by the ion implantation 26 . This ion implantation defines the tip or extension source and drain regions frequently used in CMOS transistors.
  • a layer of silicon nitride is conformally deposited over the structure of FIG. 3 to fabricate the spacers 38 shown in FIG. 4 .
  • Ordinary, well-known, anisotropic etching is used to fabricate the spacers.
  • a carbon-doped nitride, doped with 5-13% carbon concentration is used for the spacers.
  • the main part of the source and drain regions are formed through ion implantation 35 shown in FIG. 4 .
  • arsenic or phosphorous is used with an implant dose of up to 1 ⁇ 10 19 -1 ⁇ 10 20 atoms/cm 3 .
  • a similar dose range of boron may be used for a p channel transistor.
  • the silicon body 25 Following the implantation of the main source and drain region, the silicon body 25 , to the extent that it extends beyond the spacers 38 , receives a suicide or salicide layer 39 as is often done on exposed silicon in field-effect transistors.
  • An annealing step to activate the source and drain dopant is used, also commonly used cleaning steps common in the fabrication of a field-effect transistor are not shown.
  • a dielectric layer 40 is now conformally deposited over the structure of FIG. 4 , as shown in FIG. 5 .
  • This may comprise a silicon dioxide layer which will become an interlayer dielectric (ILD) in an integrated circuit or a low-k ILD may be used. Alternatively, a sacrificial dielectric layer may be used.
  • the layer 40 typically has the mechanical strength to withstand a planarization process such as chemical mechanical polishing (CMP) so that it may be polished level with the top of the spacers 38 .
  • CMP chemical mechanical polishing
  • FIG. 6 After the deposition and planarization of the dielectric layer 40 , a wet etch is used to remove the dummy polysilicon gate 30 , leaving the opening 45 , as shown in FIG. 5 . (A dummy gate oxide (not shown) may also be removed.)
  • the cross-sectional view of FIG. 6 taken through section line 6 - 6 of FIG. 5 , also shows the body 25 . This view is a better reference for the ion implantation of FIG. 7 .
  • the wafer having the structure of FIG. 6 is now ion implanted at an angle of ⁇ ° relative to the normal of the wafer with the wafer at two different angles of rotation. These angles of rotation are in the plane of the wafer and are referred to below as the wafer rotation angle.
  • the angle between the normal to the wafer and the ion beam is referred to below as the ion implantation angle ⁇ .
  • the wafer is ion implanted at the angle ⁇ with the wafer rotated to an angle of 90°.
  • implantation occurs again at the angle ⁇ with the wafer rotated to an angle of 270°.
  • the wafer rotation angles of 90° and 270°, shown in FIG. 2 are perpendicular to the body 25 . Since 90° and 270° are 180° apart, the net effect is the same as implanting at ⁇ , as shown in FIG. 7 .
  • the implanted ions are implanted into the dielectric 40 , in the exposed portions of the BOX 20 , as well as under the channel region of the body 25 and in the channel region of body 25 .
  • ⁇ may be in the range of 30°-60°, the angle is selected so as to insure that the ions are implanted into all the BOX 20 under the body 25 .
  • Ions seeded into the upper portion of BOX 20 shown as region 20 a, cause BOX 20 to be more readily etched and to provide better selectivity between the region 20 a versus the body 25 and the non-implanted regions of BOX. 20 .
  • the ions alter the crystalline nature of BOX 20 , in effect, amorphizing or modifying the structure making it less resistant to selected chemistry without making body 25 or non-implanted regions of the BOX 20 more readily etched.
  • the implanted region 20 a is etched more readily in the presence of the wet etchant compared to the body 25 or unexposed portions of the BOX 20 , allowing the implanted portion of the BOX 20 (region 20 a ), including beneath the body 25 to be removed without substantially affecting the dimensions of the body 25 .
  • pre-etch implantation may be found in US2004/0118805. Wet etchant discrimination ratio of 6-1 between implanted silicon dioxide and non-implanted silicon dioxide are achievable.
  • Ions selected for the implantation shown in FIG. 7 are electrically inactive in the BOX 20 and the semiconductor body 25 .
  • silicon can be implanted where the body 25 is a silicon body, to disrupt the structure of the silicon dioxide without altering the electrical properties of the body 25 .
  • the additional silicon ions implanted in body 25 are re-crystallized and have substantially no impact on the transistor characteristics.
  • electrically inactive species such as nitrogen or halogens (fluorine, chlorine, etc.) may be implanted to create structural alteration with the resultant modification of the wet etch rate without adversely effecting the electrical behavior of the transistor. These species remain in the silicon without altering the electrical characteristics of the transistor which is subsequently formed.
  • Relatively low implantation energies and dose levels are adequate to sufficiently seed the BOX 20 beneath the body 25 to allow removal of the oxide below the body.
  • energy levels for implanting silicon in the range of 0.5-2.0 KeV, to a dose of 1 ⁇ 10 18 atoms/cm 2 are sufficient for a silicon body having dimensions of approximately 20 ⁇ 20 nm.
  • a wet etch is used to remove the region 20 a including the region 20 a under the body 25 .
  • Many wet chemical etchants are known to be effective and controllable on such thin film materials. As would be apparent to one skilled in the art, they may be appropriately matched with substrate and thin film materials, such as those above, to provide desirable selective etching.
  • Suitable etchants include but are not limited to phosphoric acid (H 3 PO 4 ), hydrofluoric acid (HF), buffered HF, hydrochloric acid (HCl), nitric acid (HNO 3 ), acetic acid (CH 3 COOH), ammonium hydroxide (NH 4 OH, alcohols, potassium permanganate (KMnO 4 ), ammonium fluoride (NH 4 F), and others, as would be listed in known Wet chemical etching references such as Thin Film Processes, Academic Press 1978), edited by John L. Vossen and Werner Kern, Mixtures of these and other etchant chemicals are also conventionally used.
  • the wet etchant of the region 20 a of layer 20 defines a trench aligned with the opening 45 which extends beneath the body 25 .
  • This trench is best seen in FIG. 8 as trench 50 . Note, this view is taken through the section lines 8 - 8 of FIG. 5 . In this view the source and drain regions 55 are visible.
  • the trench 50 is encircled with the circle 60 , and enlarged in FIG. 9 , as will be subsequently discussed.
  • a gate dielectric 62 may now be formed on exposed surfaces which includes the sides, top and bottom of the body 25 ,
  • the gate dielectric has a high dielectric constant (k), such as a metal oxide dielectric, for instance, HfO 2 or ZrO 2 or other high k dielectrics, such as PZT or BST.
  • the gate dielectric may be formed by any well-known technique such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). Alternately, the gate dielectric may be a grown dielectric.
  • the gate dielectric 62 may be a silicon dioxide film grown with a wet or dry oxidation process to a thickness between 5-50 ⁇ .
  • a gate electrode (metal) layer 63 is formed over the gate dielectric layer 62 .
  • the gate electrode layer 62 may be formed by blanket deposition of a suitable gate electrode material.
  • a gate electrode material comprises a metal film such as tungsten, tantalum, titanium and/or nitrides and alloys thereof.
  • n channel transistors a work function in the range of 3.9 to 4.6 eV may be used.
  • p channel transistors a work function of 4.6 to 5.2 eV may be used. Accordingly, for substrates with both n channel and p channel transistors, two separate metal deposition processes may need to be used. Only approximately 100 ⁇ of the metal needs to be formed through ALD to set the work function. The remainder of the gate may be formed of polysilicon.
  • the formation of the gate beneath the body 25 may not be as well defined as the gate on the sides and top of the body 25 .
  • a void 64 may occur.
  • Such a void will not affect the performance of the transistor.
  • some of the BOX 20 (not shown) may remain directly under the body 25 in the trench 50 . This oxide, which is subsequently covered with both the high-k dielectric 62 and the metal 63 , will not meaningfully impact transistor performance.
  • the above described method may also be used cm other three dimensional (3D)) semiconductor bodies such as semiconducting carbon nanotubes, Group 3-5 nanowires and silicon nanowires.
  • the surface upon which the 3D semiconductor nanostructure rests is ion implanted to alter its etching rate to make it more etchable than the nanostructure.
  • ALD is then used to form a dielectric and gate entirely around the semiconductor body for one embodiment.

Abstract

A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of U.S. patent application Ser. No. 13/042,973, flied Mar. 8, 2011, which is a continuation of U.S. patent application Ser. No. 11/240,440, filed Sep. 29, 2005, now U.S. Pat. No. 7,915,167, issued Mar. 29, 2011, the entire contents of which are hereby incorporated by reference herein.
    • FIELD OF THE INVENTION
  • The invention is in the field of Field-Effect Transistors.
    • PRIOR ART AND RELATED ART
  • The continuing trend in the fabrication of complementary metal-oxide-semiconductor (CMOS) transistors is to scale the transistors. Examples of transistors having reduced bodies along with tri-gate structures are shown in US 2004/0036127. Other small transistors are delta-doped transistors fanned in lightly doped or undoped epitaxial layers grown on a heavily doped substrate. See, for instance, “Metal Gate Transistor with Epitaxial Source and Drain Regions,” application Ser. No. 10/955,669, filed Sep. 29, 2004, assigned to the assignee of the present application.
  • The ability to continue scaling CMOS transistors to even smaller geometries is hindered by the off-state leakage current. Off-state current reduces the switching efficiency and robs system power. This is particularly significant in planar CMOS transistors, where substrate leakage paths account for most of the current flow in the off state. While three-dimensional structures such as tri-gates and fin-FETs are more scalable, since they have more effective electrostatic control, there still remains a leakage path in the channel.
  • One structure for providing a more completely wrapped around gate is described in “Nonplanar Semiconductor Device with Partially or Fully Wrapped Around Gate Electrode and Methods of Fabrication,” U.S. patent application Ser. No. 10/607,769, filed Jun. 27, 2003.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional, elevation view of a silicon-on-insulator (SOI) substrate.
  • FIG. 2 is a perspective view of the structure of FIG. 1, after the formation of a silicon body, sometimes referred to as a fin.
  • FIG. 3 illustrates the structure of FIG. 2, after a dummy gate is fabricated and during a first ion implantation step.
  • FIG. 4 illustrates the structure of FIG. 3, after spacers are fabricated and during a second ion implantation step.
  • FIG. 5 illustrates the structure of FIG. 4, after forming a dielectric layer and after the removal of the dummy gate.
  • FIG. 6 is a cross-sectional, elevation view of the structure of FIG. 5 through section line 6-6 of FIG. 5.
  • FIG. 7 illustrates the structure of FIG. 6 during an ion implantation step.
  • FIG. 8 illustrates the structure of FIG. 7 after an etching step which removes the BOX under the channel region. This view is generally through section line 8-8 of FIG. 5.
  • FIG. 9 is an enlarged view of the region beneath the gate after the formation of a gate dielectric layer and a gate metal.
  • FIG. 10 is a cross-sectional, elevation view taken through the same plane as FIG. 6, this view illustrates the formation of the gate encircling the entire channel region of a semiconductor body.
    •  DETAILED DESCRIPTION
  • A process for fabricating CMOS field-effect transistors and the resultant transistors are described. In the following description, numerous specific details are set forth, such as specific dimensions and chemical regimes, in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known processing steps, such as cleaning steps, are not described in detail, in order to not unnecessarily obscure the present invention, Also in the description below, the fabrication of a single transistor is described. As will be appreciated in the typical integrated circuit, both n and p channel transistors are fabricated.
  • In one embodiment, transistors are fabricated on a buried oxide layer (BOX) 20 which is disposed on a silicon substrate 21 shown in FIG. 1. Transistor bodies are fabricated from a monocrystalline, silicon layer 24 disposed on BOX 20. This silicon-on-insulation (SOI) substrate is well-known in the semiconductor industry. By way of example, the SOI substrate is fabricated by bonding the oxide layer 20 and silicon layer 24 onto the substrate 21, and then planarizing the layer 24 until it is relatively thin. Other techniques are known for forming an SOI substrate eluding, for instance, the implantation of oxygen into a silicon substrate to form a buried oxide layer. Other semiconductor materials, other than silicon, may also be used such as gallium arsenide.
  • As will be seen, the BOX is seeded through ion implantation beneath the channel region of a transistor to make the oxide more readily etchable than the overlying, silicon body. An electrically inactive species is implemented so as to not alter the electrical characteristics of the semiconductor body. Then, after removal of the BOX beneath the channel, a gate insulator and gate are formed entirely around the channel.
  • Referring to FIG. 1, the layer 24 may be selectively ion implanted with a p type dopant in regions where n channel transistors are to be fabricated, and with an type dopant in those regions where p channel devices are to be fabricated. This is used to provide the relatively light doping typically found in the channel regions of MOS devices fabricated in a CMOS integrated circuit.
  • A protective oxide is disposed on the silicon layer 24 followed by the deposition of a silicon nitride layer (both not shown). The nitride layer acts as a hard mask to define silicon bodies such as the silicon body 25 of FIG. 2. By way of example, the body 25 may have a height and width of 20-30 nm.
  • An oxide (not shown) which subsequently acts as an etchant stop is formed over body 25. A polysilicon layer is formed over the structure of FIG. 2 and etched to define a dummy gate 30 which extends over the body 25 as seen in FIG. 3. The region of the body 25 below the dummy gate 30, as will be seen, is the channel region in this replacement gate process. Once the. dummy gate 30 has been defined, phosphorous or arsenic may be implanted into the body 25 for an n channel transistor, or boron for a p channel transistor in alignment with the dummy gate, as illustrated by the ion implantation 26. This ion implantation defines the tip or extension source and drain regions frequently used in CMOS transistors.
  • Now, a layer of silicon nitride is conformally deposited over the structure of FIG. 3 to fabricate the spacers 38 shown in FIG. 4. Ordinary, well-known, anisotropic etching is used to fabricate the spacers. In one embodiment, a carbon-doped nitride, doped with 5-13% carbon concentration is used for the spacers. After the spacer formation, the main part of the source and drain regions are formed through ion implantation 35 shown in FIG. 4. For the n channel transistor, arsenic or phosphorous is used with an implant dose of up to 1×1019-1×1020 atoms/cm3. A similar dose range of boron may be used for a p channel transistor.
  • Following the implantation of the main source and drain region, the silicon body 25, to the extent that it extends beyond the spacers 38, receives a suicide or salicide layer 39 as is often done on exposed silicon in field-effect transistors.
  • An annealing step to activate the source and drain dopant is used, also commonly used cleaning steps common in the fabrication of a field-effect transistor are not shown.
  • A dielectric layer 40 is now conformally deposited over the structure of FIG. 4, as shown in FIG. 5. This may comprise a silicon dioxide layer which will become an interlayer dielectric (ILD) in an integrated circuit or a low-k ILD may be used. Alternatively, a sacrificial dielectric layer may be used. In any event, the layer 40 typically has the mechanical strength to withstand a planarization process such as chemical mechanical polishing (CMP) so that it may be polished level with the top of the spacers 38.
  • After the deposition and planarization of the dielectric layer 40, a wet etch is used to remove the dummy polysilicon gate 30, leaving the opening 45, as shown in FIG. 5. (A dummy gate oxide (not shown) may also be removed.) The cross-sectional view of FIG. 6, taken through section line 6-6 of FIG. 5, also shows the body 25. This view is a better reference for the ion implantation of FIG. 7.
  • Referring to FIG. 7, the wafer having the structure of FIG. 6 is now ion implanted at an angle of θ° relative to the normal of the wafer with the wafer at two different angles of rotation. These angles of rotation are in the plane of the wafer and are referred to below as the wafer rotation angle. The angle between the normal to the wafer and the ion beam is referred to below as the ion implantation angle θ.
  • First, for instance, the wafer is ion implanted at the angle θ with the wafer rotated to an angle of 90°. Then, implantation occurs again at the angle θ with the wafer rotated to an angle of 270°. The wafer rotation angles of 90° and 270°, shown in FIG. 2 are perpendicular to the body 25. Since 90° and 270° are 180° apart, the net effect is the same as implanting at ±θ, as shown in FIG. 7. The implanted ions are implanted into the dielectric 40, in the exposed portions of the BOX 20, as well as under the channel region of the body 25 and in the channel region of body 25. θ may be in the range of 30°-60°, the angle is selected so as to insure that the ions are implanted into all the BOX 20 under the body 25.
  • Ions seeded into the upper portion of BOX 20, shown as region 20 a, cause BOX 20 to be more readily etched and to provide better selectivity between the region 20 a versus the body 25 and the non-implanted regions of BOX. 20. The ions alter the crystalline nature of BOX 20, in effect, amorphizing or modifying the structure making it less resistant to selected chemistry without making body 25 or non-implanted regions of the BOX 20 more readily etched. More specifically, by selecting, suitable ions and a suitable wet etchant, the implanted region 20 a is etched more readily in the presence of the wet etchant compared to the body 25 or unexposed portions of the BOX 20, allowing the implanted portion of the BOX 20 (region 20 a), including beneath the body 25 to be removed without substantially affecting the dimensions of the body 25. A discussion of pre-etch implantation may be found in US2004/0118805. Wet etchant discrimination ratio of 6-1 between implanted silicon dioxide and non-implanted silicon dioxide are achievable.
  • Ions selected for the implantation shown in FIG. 7 are electrically inactive in the BOX 20 and the semiconductor body 25. For example, silicon can be implanted where the body 25 is a silicon body, to disrupt the structure of the silicon dioxide without altering the electrical properties of the body 25. In subsequent annealing, the additional silicon ions implanted in body 25 are re-crystallized and have substantially no impact on the transistor characteristics. Further, electrically inactive species such as nitrogen or halogens (fluorine, chlorine, etc.) may be implanted to create structural alteration with the resultant modification of the wet etch rate without adversely effecting the electrical behavior of the transistor. These species remain in the silicon without altering the electrical characteristics of the transistor which is subsequently formed.
  • Relatively low implantation energies and dose levels are adequate to sufficiently seed the BOX 20 beneath the body 25 to allow removal of the oxide below the body. For example, energy levels for implanting silicon in the range of 0.5-2.0 KeV, to a dose of 1×1018 atoms/cm2 are sufficient for a silicon body having dimensions of approximately 20×20 nm.
  • Following the implantation, a wet etch is used to remove the region 20 a including the region 20 a under the body 25. Many wet chemical etchants are known to be effective and controllable on such thin film materials. As would be apparent to one skilled in the art, they may be appropriately matched with substrate and thin film materials, such as those above, to provide desirable selective etching. Suitable etchants include but are not limited to phosphoric acid (H3PO4), hydrofluoric acid (HF), buffered HF, hydrochloric acid (HCl), nitric acid (HNO3), acetic acid (CH3COOH), ammonium hydroxide (NH4OH, alcohols, potassium permanganate (KMnO4), ammonium fluoride (NH4F), and others, as would be listed in known Wet chemical etching references such as Thin Film Processes, Academic Press 1978), edited by John L. Vossen and Werner Kern, Mixtures of these and other etchant chemicals are also conventionally used.
  • The wet etchant of the region 20 a of layer 20 defines a trench aligned with the opening 45 which extends beneath the body 25. This trench is best seen in FIG. 8 as trench 50. Note, this view is taken through the section lines 8-8 of FIG. 5. In this view the source and drain regions 55 are visible. The trench 50 is encircled with the circle 60, and enlarged in FIG. 9, as will be subsequently discussed.
  • A gate dielectric 62 may now be formed on exposed surfaces which includes the sides, top and bottom of the body 25, The gate dielectric has a high dielectric constant (k), such as a metal oxide dielectric, for instance, HfO2 or ZrO2 or other high k dielectrics, such as PZT or BST. The gate dielectric may be formed by any well-known technique such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). Alternately, the gate dielectric may be a grown dielectric. For instance, the gate dielectric 62, may be a silicon dioxide film grown with a wet or dry oxidation process to a thickness between 5-50 Å.
  • Following this a gate electrode (metal) layer 63 is formed over the gate dielectric layer 62. The gate electrode layer 62 may be formed by blanket deposition of a suitable gate electrode material. In one embodiment a gate electrode material comprises a metal film such as tungsten, tantalum, titanium and/or nitrides and alloys thereof. For the n channel transistors, a work function in the range of 3.9 to 4.6 eV may be used. For the p channel transistors, a work function of 4.6 to 5.2 eV may be used. Accordingly, for substrates with both n channel and p channel transistors, two separate metal deposition processes may need to be used. Only approximately 100 Å of the metal needs to be formed through ALD to set the work function. The remainder of the gate may be formed of polysilicon.
  • Standard processing is now used to complete the transistor of FIG. 10.
  • The formation of the gate beneath the body 25 may not be as well defined as the gate on the sides and top of the body 25. For instance, as shown in FIG. 9, a void 64 may occur. Such a void, however, will not affect the performance of the transistor. Moreover, some of the BOX 20 (not shown) may remain directly under the body 25 in the trench 50. This oxide, which is subsequently covered with both the high-k dielectric 62 and the metal 63, will not meaningfully impact transistor performance.
  • The above described method may also be used cm other three dimensional (3D)) semiconductor bodies such as semiconducting carbon nanotubes, Group 3-5 nanowires and silicon nanowires. The surface upon which the 3D semiconductor nanostructure rests is ion implanted to alter its etching rate to make it more etchable than the nanostructure.
  • Thus, a method has been described for forming a gate entirely around a silicon body in a replacement gate process. Ion implantation damages the insulation beneath the semiconductor body in the channel region allowing it to be more readily etched. ALD is then used to form a dielectric and gate entirely around the semiconductor body for one embodiment.

Claims (14)

What is claimed is:
1. A semiconductor structure, comprising:
a semiconductor body above a substrate, the semiconductor body having a top surface, a pair of sidewalls, and a bottom;
a gate electrode haying a first portion over a portion of the top surface of the semiconductor body, a second portion adjacent a portion of the sidewalls of the semiconductor body, and a third portion below the bottom surface of the semiconductor body, wherein the first portion of the gate electrode is continuous with the second portion of the gate electrode, and wherein the third portion of the gate electrode is continuous with the second portion of the gate electrode;
a gate dielectric layer between the first portion of the gate electrode and the portion of the top surface of the semiconductor body, between the second portion of the gate electrode and the portion of the sidewalls of the semiconductor body, and between the third portion of the gate electrode and the bottom surface of the semiconductor body, Wherein is continuous around a top surface, sidewall surfaces and a bottom surface of the third portion of the gate electrode;
an insulating layer above the substrate and laterally adjacent to the third portion of the gate electrode;
a source region at a first side of the gate electrode; and
a drain region at a second side of the gate electrode opposite the first side of the gate electrode.
2. The semiconductor structure of claim 1, wherein the insulating layer is laterally adjacent to a portion of the gate dielectric layer between the third portion of the gate electrode and the bottom surface of the semiconductor body.
3. The semiconductor structure of claim 1, wherein the third portion of the gate electrode comprises a void surrounded by a top portion, sidewall portions and a bottom portion of the third portion of the gate electrode.
4. The semiconductor structure of claim 1, wherein the third portion of the gate electrode is void-free.
5. The semiconductor structure of claim 1, wherein the gate dielectric layer comprises a high-k dielectric material.
6. The semiconductor structure of claim 5, wherein the gate electrode comprises a metal and has a work function between 3.9 to 5.2 eV.
7. The semiconductor structure of claim 1, wherein the gate electrode comprises a metal and has a work function between 3.9 to 5.2 eV.
8. A method of fabricating a semiconductor structure, the method comprising:
forming a semiconductor body above a substrate, the semiconductor body having a top surface, a pair of sidewalls, and a bottom;
forming a gate electrode having a first portion over a portion of the top surface of the semiconductor body, a second portion adjacent a portion of the sidewalls of the semiconductor body, and a third portion below the bottom surface of the semiconductor body, wherein the first portion of the gate electrode is continuous with the second portion of the gate electrode, and wherein the third portion of the gate electrode is continuous with the second portion of the gate electrode;
forming a gate dielectric layer between the first portion of the gate electrode and the portion of the top surface of the semiconductor body, between the second portion of the gate electrode and the portion of the sidewalls of the semiconductor body, and between the third portion of the gate electrode and the bottom surface of the semiconductor body, wherein is continuous around a top surface, sidewall surfaces and a bottom surface of the third portion of the gate electrode;
forming an insulating layer above the substrate and laterally adjacent to the third portion of the gate electrode forming a source region at a first side of the gate electrode; and
forming a drain region at a second side of the gate electrode opposite the first side of the gate electrode.
9. The method of claim 8, wherein the insulating layer is laterally adjacent to a portion of the gate dielectric layer between the third portion of the gate electrode and the bottom surface of the semiconductor body.
10. The method of claim 8, wherein the third portion of the gate electrode comprises a void surrounded by a top portion, sidewall portions and a bottom portion of the third portion of the gate electrode.
11. The method of claim 8, wherein the third portion of the gate electrode is void-free.
12. The method of claim 8, wherein the gate dielectric layer comprises a high-k dielectric material.
13. The method of claim 12, wherein the gate electrode comprises a metal and has a work function between 3.9 to 5.2 eV.
14. The method of claim 8, wherein the gate electrode comprises a metal and has a work function between 3.9 to 5.2 eV.
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US13/042,973 US20110156145A1 (en) 2004-09-29 2011-03-08 Fabrication of channel wraparound gate structure for field-effect transistor
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