US20150333062A1 - Finfet fabrication method - Google Patents

Finfet fabrication method Download PDF

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US20150333062A1
US20150333062A1 US14/809,216 US201514809216A US2015333062A1 US 20150333062 A1 US20150333062 A1 US 20150333062A1 US 201514809216 A US201514809216 A US 201514809216A US 2015333062 A1 US2015333062 A1 US 2015333062A1
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Prior art keywords
spacers
semiconductor device
nanometers
fins
regions
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US14/809,216
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Xusheng Wu
Wanxun He
Hongliang Shen
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Alsephina Innovations Inc
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GlobalFoundries Inc
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Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. CORRECTIVE ASSIGNMENT TO CORRECT THE SERIAL NUMBER 14/809,213 PREVIOUSLY RECORDED AT REEL: 036179 FRAME: 0198. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Assignors: HE, WANXUN, SHEN, HONGLIANG, WU, XUSHENG
Publication of US20150333062A1 publication Critical patent/US20150333062A1/en
Assigned to ALSEPHINA INNOVATIONS INC. reassignment ALSEPHINA INNOVATIONS INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES INC.
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the present invention relates generally to semiconductor fabrication, and more particularly to improved methods for finFET fabrication.
  • the finFET fin field effect transistor
  • the channel is formed by a semiconductor fin and a gate electrode is located on at least two sides of the fin.
  • a finFET device generally has faster switching times, equivalent or higher current density, and much improved short channel control than planar CMOS technology utilizing similar critical dimensions. FinFETs have applications in a variety of integrated circuits. In some cases, multiple fins may be merged together as part of a single transistor. In other cases, such as with static random access memory (SRAM), a transistor may comprise a single fin.
  • SRAM static random access memory
  • embodiments of the present invention provide a method of forming a semiconductor structure, comprising: forming a nitride liner on a semiconductor substrate; forming a plurality of sacrificial material regions on the nitride liner; forming a first set of spacers on a first side of each of the sacrificial material regions and a second set of spacers on a second side of each of the sacrificial material regions; removing the plurality of sacrificial material regions; removing the second set of spacers while preserving the first set of spacers; and forming fins on the semiconductor substrate.
  • embodiments of the present invention provide a method of forming a circuit comprising a plurality of finFET devices, wherein each finFET device comprises a single fin, and wherein each fin of the plurality of finFET devices is formed by: forming a nitride liner on a semiconductor substrate; forming a plurality of sacrificial material regions on the nitride liner; forming a first set of spacers on a first side of each of the sacrificial material regions and a second set of spacers on a second side of each of the sacrificial material regions; removing the plurality of sacrificial material regions; removing the second set of spacers while preserving the first set of spacers; and forming fins on the semiconductor substrate.
  • embodiments of the present invention provide a method of forming a semiconductor structure, comprising: forming a nitride liner on a semiconductor substrate; forming a plurality of sacrificial material regions on the nitride liner, wherein a pitch between adjacent sacrificial material regions ranges from about 50 nanometers to about 90 nanometers; forming a first set of spacers on a first side of each of the sacrificial material regions and a second set of spacers on a second side of each of the sacrificial material regions; removing the plurality of sacrificial material regions; removing the second set of spacers while preserving the first set of spacers; and forming fins on the semiconductor substrate.
  • FIG. 1 is a semiconductor structure at a starting point for illustrative embodiments
  • FIG. 2 is a semiconductor structure after a subsequent process step of forming sacrificial material regions, in accordance with illustrative embodiments
  • FIG. 3 is a semiconductor structure after subsequent process steps of forming left and right spacers and removing the sacrificial material, in accordance with illustrative embodiments;
  • FIG. 4 is a semiconductor structure after a subsequent process step of removing the underlying nitride liner, in accordance with illustrative embodiments
  • FIG. 5 is a semiconductor structure after a subsequent process step of dummy spacer removal
  • FIG. 6 is a semiconductor structure after a subsequent process step of fin formation
  • FIG. 7 is a semiconductor structure after subsequent process steps of shallow trench isolation refilling and recessing
  • FIG. 8 is a semiconductor structure at a starting point for alternative illustrative embodiments utilizing shallow trench isolation
  • FIG. 9 is a semiconductor structure after subsequent process steps of forming left and right spacers and removing the sacrificial material, in accordance with alternative illustrative embodiments.
  • FIG. 10 is a semiconductor structure after a subsequent process step of removing the underlying nitride liner, in accordance with alternative illustrative embodiments
  • FIG. 11 is a semiconductor structure after a subsequent process step of forming fins, in accordance with alternative illustrative embodiments.
  • FIG. 12 is a semiconductor structure after subsequent process steps of removing intermediate layers and refilling the shallow trench isolation, in accordance with alternative illustrative embodiments.
  • FIG. 13 is a flowchart indicating process steps for embodiments of the present invention.
  • Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finFETs).
  • Sacrificial regions are formed on a semiconductor substrate.
  • Spacers are formed adjacent to two sides of the sacrificial regions.
  • Fins are formed based on the spacers.
  • One set of spacers is treated as dummy spacers, and is removed prior to fin formation, leaving the other set of spacers to be used for forming fins on the final semiconductor structure. All the fins on the final semiconductor structure are formed from spacers on one side of the sacrificial material. This reduces variation in width of the fins, and improves product reliability and yield for devices that employ single-fin finFETs, such as SRAM integrated circuits (ICs), latches, and ring oscillators.
  • ICs integrated circuits
  • latches latches
  • ring oscillators ring oscillators
  • first element such as a first structure (e.g., a first layer)
  • second element such as a second structure (e.g. a second layer)
  • intervening elements such as an interface structure (e.g. interface layer)
  • FIG. 1 is a semiconductor structure 100 at a starting point for illustrative embodiments.
  • Semiconductor structure 100 includes a semiconductor substrate 102 , which may be a silicon substrate.
  • Substrate 102 may be a bulk substrate, such as in the form of a wafer. However, embodiments of the present invention may also be used with silicon-on-insulator (SOI) technology.
  • SOI silicon-on-insulator
  • Disposed on substrate 102 is a pad nitride liner 104 .
  • pad nitride liner 104 may be comprised of silicon nitride.
  • liner 104 may have a thickness X ranging from about 10 nanometers to about 100 nanometers.
  • liner 104 may be deposited via a chemical vapor deposition (CVD) process.
  • CVD chemical vapor deposition
  • FIG. 2 is a semiconductor structure 200 after a subsequent process step of forming sacrificial material regions 206 , in accordance with illustrative embodiments.
  • sacrificial material regions 206 may be comprised of amorphous silicon and may be deposited via industry-standard patterning and deposition techniques.
  • sacrificial material regions 206 may comprise an oxide, such as silicon oxide.
  • similar elements may be referred to by similar numbers in various figures (FIGs) of the drawing, in which case typically the last two significant digits may be the same.
  • substrate 202 of FIG. 2 is similar to substrate 102 of FIG. 1 .
  • the pitch P between adjacent sacrificial material regions 206 and 208 ranges from about 50 nanometers to about 90 nanometers. In some embodiments, the width W of a sacrificial material region ( 206 , 208 ) may range from about 15 nanometers to about 30 nanometers.
  • FIG. 3 is a semiconductor structure 300 after a subsequent process step of forming left and right spacers, in accordance with illustrative embodiments.
  • the spacers 310 L, 310 R, 312 L, and 312 R are formed in a single deposition process.
  • the sacrificial material regions ( 206 of FIG. 2 ) are then removed with an etch process. In some embodiments, a reactive ion etch (RIE) process may be used for removal of the sacrificial material regions.
  • RIE reactive ion etch
  • the sacrificial material region 206 should preferably have high selectivity to the material used for spacers 310 L, 310 R, 312 L, and 312 R.
  • the spacers 310 L, 310 R, 312 L, and 312 R may be comprised of a nitride, such as silicon nitride. In some embodiments, the spacers 310 L, 310 R, 312 L, and 312 R may be comprised of an oxide, such as a silicon oxide.
  • the material used for the spacers 310 L, 310 R, 312 L, and 312 R is preferably highly selectable to the sacrificial material regions ( 206 of FIG. 2 ).
  • the width of spacer 310 L would be the same as the width of spacer 310 R. However, in practice, this is rarely the case. In practice, there is variation in thickness between the left and right side spacers due to variations in deposition and etch processes used in forming the spacers.
  • the left spacers 310 L and 312 L have a thickness T 1
  • the right spacers 310 R and 312 R have a thickness T 2 , where T 1 is not equal to T 2 .
  • Spacers formed on the same side are normally substantially equal to each other.
  • right spacers are normally substantially equal to other right spacers
  • left spacers are normally substantially equal to other left spacers, due to the nature of etching and deposition processes.
  • the difference between thickness T 1 and thickness T 2 could cause variation in fin width.
  • the variation in fin width could have adverse effects on yield and device performance.
  • Embodiments of the present invention mitigate this problem by utilizing fins from only one side in the final semiconductor integrated circuit. Fins from the other side are removed prior to completion of the integrated circuit. In this way, the mismatch between thickness T 1 and thickness T 2 does not affect the fin width in the final semiconductor integrated circuit.
  • embodiments of the present invention can significantly improve product yield and device performance.
  • FIG. 4 is a semiconductor structure 400 after a subsequent process step of removing most of the underlying nitride liner. A portion of the nitride liner remains under the spacers.
  • the nitride liner portions 414 L, 414 R, 416 L, and 416 R are also subject to the variations in thickness between T 1 and T 2 .
  • FIG. 5 is a semiconductor structure 500 after a subsequent process step of dummy spacer removal.
  • the right spacers ( 410 R and 412 R of FIG. 4 ) have been removed.
  • the removal of the dummy spacers may be accomplished via industry standard lithographic and etching techniques.
  • the spacers 510 L and 512 L are from the left set of spacers, and will be used to form the fins.
  • one of the sets of spacers is treated as a set of dummy spacers that will not be used to form fins.
  • the other set of spacers is treated as a set of functional spacers that will be used to form fins on the completed integrated circuit.
  • FIG. 6 is a semiconductor structure 600 after a subsequent process step of fin formation.
  • An anisotropic etch is performed, resulting in the formation of fins 618 L and 620 L underneath the functional spacers 610 L and 612 L.
  • the left fins 618 L and 620 L are formed based on spacers 610 L and 612 L respectively.
  • other embodiments may utilize the right side spacers as functional spacers, and utilize the left side spacers as dummy spacers.
  • FIG. 7 is a semiconductor structure 700 after subsequent process steps forming shallow trench isolation (STI) regions 715 .
  • the STI regions 715 may be comprised of an oxide, such as silicon oxide.
  • the STI regions 715 may be formed by depositing oxide via a chemical vapor deposition (CVD) process, followed by a recess process to place the top of the STI regions at a desired level.
  • CVD chemical vapor deposition
  • FIG. 8 is a semiconductor structure 800 at a starting point for alternative illustrative embodiments utilizing shallow trench isolation (STI).
  • the sacrificial material regions 806 and 808 are formed in an off-center alignment with corresponding shallow trench isolation regions 815 , such that, for example, left edge 813 A of the sacrificial material region 808 is located to the left of the left edge 817 A of shallow trench isolation region 815 , and right edge 813 B of sacrificial material region 808 is located to the right of left edge 817 A of shallow trench isolation region 815 , and is also located to the left of right edge 817 B of shallow trench isolation region 815 .
  • Shallow trench isolation regions 815 may be comprised of silicon oxide or other suitable insulating material.
  • FIG. 9 is a semiconductor structure 900 after subsequent process steps of forming left and right spacers and removing the sacrificial material, in accordance with alternative illustrative embodiments.
  • Left spacers 910 L and 912 L are formed above the semiconductor substrate 902 , and are used as functional spacers in this example.
  • Right spacers 910 R and 912 R are formed above the shallow trench isolation regions 915 .
  • the right spacers represent “dummy spacers” that are not used to form active fins, while the left spacers are functional spacers, and thus are used to form active fins.
  • FIG. 10 is a semiconductor structure 1000 after a subsequent process step of removing the underlying nitride liner, in accordance with alternative illustrative embodiments.
  • Left nitride portions 1014 L and 1016 L are formed over the semiconductor substrate 1002
  • right nitride portions 1014 R and 1016 R are formed over shallow trench isolation regions 1015 .
  • FIG. 11 is a semiconductor structure 1100 after a subsequent process step of forming fins, in accordance with alternative illustrative embodiments.
  • Fins 1118 L and 1120 L are formed from semiconductor substrate 1002 , and are part of the final integrated circuit.
  • No fins are formed under dummy spacers 1110 R and 1112 R, as those spacers are formed above STI regions 1115 .
  • FIG. 12 is a semiconductor structure after subsequent process steps of removing intermediate layers and refilling the shallow trench isolation.
  • Functional and dummy spacers e.g., 1110 R, 1110 L, 1112 R, and 1112 L from FIG. 11
  • the material underneath the dummy spacers is comprised of shallow trench isolation material, such as silicon oxide, and may therefore be removed by a selective etch process.
  • FIG. 13 is a flowchart 1300 indicating process steps for embodiments of the present invention.
  • a nitride liner is deposited on a semiconductor substrate.
  • sacrificial material regions are formed.
  • functional and dummy spacers are formed adjacent to the sacrificial material regions, and the sacrificial material regions are then removed.
  • the dummy spacers (from either the left or right side) are removed.
  • the fins are formed, based on the functional spacers. All the fins in the remaining set are from one side.
  • all the fins are formed either from all left-side spacers or all right-side spacers.

Abstract

Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finFETs). Sacrificial regions are formed on a semiconductor substrate. Spacers are formed adjacent to two sides of the sacrificial regions. Fins are formed based on the spacers. One set of spacers is treated as dummy spacers, and is removed prior to fin formation, leaving the other set of spacers to be used for forming fins on the final semiconductor structure. All the fins on the final semiconductor structure are formed from spacers on one side of the sacrificial material. This reduces variation in width of the fins.

Description

    BACKGROUND OF THE INVENTION
  • This application is a continuation of co-pending U.S. application Ser. No. 14/044,533 filed Oct. 2, 2013.
    • FIELD OF THE INVENTION
  • The present invention relates generally to semiconductor fabrication, and more particularly to improved methods for finFET fabrication.
    • BACKGROUND
  • As integrated circuits continue to scale downward in size, the finFET (fin field effect transistor) is becoming an attractive device for use with smaller nodes (e.g., the 22 nm node and beyond). In a finFET, the channel is formed by a semiconductor fin and a gate electrode is located on at least two sides of the fin. A finFET device generally has faster switching times, equivalent or higher current density, and much improved short channel control than planar CMOS technology utilizing similar critical dimensions. FinFETs have applications in a variety of integrated circuits. In some cases, multiple fins may be merged together as part of a single transistor. In other cases, such as with static random access memory (SRAM), a transistor may comprise a single fin.
    • SUMMARY
  • In a first aspect, embodiments of the present invention provide a method of forming a semiconductor structure, comprising: forming a nitride liner on a semiconductor substrate; forming a plurality of sacrificial material regions on the nitride liner; forming a first set of spacers on a first side of each of the sacrificial material regions and a second set of spacers on a second side of each of the sacrificial material regions; removing the plurality of sacrificial material regions; removing the second set of spacers while preserving the first set of spacers; and forming fins on the semiconductor substrate.
  • In a second aspect, embodiments of the present invention provide a method of forming a circuit comprising a plurality of finFET devices, wherein each finFET device comprises a single fin, and wherein each fin of the plurality of finFET devices is formed by: forming a nitride liner on a semiconductor substrate; forming a plurality of sacrificial material regions on the nitride liner; forming a first set of spacers on a first side of each of the sacrificial material regions and a second set of spacers on a second side of each of the sacrificial material regions; removing the plurality of sacrificial material regions; removing the second set of spacers while preserving the first set of spacers; and forming fins on the semiconductor substrate.
  • In a third aspect, embodiments of the present invention provide a method of forming a semiconductor structure, comprising: forming a nitride liner on a semiconductor substrate; forming a plurality of sacrificial material regions on the nitride liner, wherein a pitch between adjacent sacrificial material regions ranges from about 50 nanometers to about 90 nanometers; forming a first set of spacers on a first side of each of the sacrificial material regions and a second set of spacers on a second side of each of the sacrificial material regions; removing the plurality of sacrificial material regions; removing the second set of spacers while preserving the first set of spacers; and forming fins on the semiconductor substrate.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Certain elements in some of the figures may be omitted, or illustrated not-to-scale, for illustrative clarity. The cross-sectional views may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines which would otherwise be visible in a “true” cross-sectional view, for illustrative clarity. Furthermore, for clarity, some reference numbers may be omitted in certain drawings.
  • Often, similar elements may be referred to by similar numbers in various figures (FIGs) of the drawing, in which case typically the last two significant digits may be the same, the most significant digit being the number of the drawing figure (FIG.).
  • Features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings in which:
  • FIG. 1 is a semiconductor structure at a starting point for illustrative embodiments;
  • FIG. 2 is a semiconductor structure after a subsequent process step of forming sacrificial material regions, in accordance with illustrative embodiments;
  • FIG. 3 is a semiconductor structure after subsequent process steps of forming left and right spacers and removing the sacrificial material, in accordance with illustrative embodiments;
  • FIG. 4 is a semiconductor structure after a subsequent process step of removing the underlying nitride liner, in accordance with illustrative embodiments;
  • FIG. 5 is a semiconductor structure after a subsequent process step of dummy spacer removal;
  • FIG. 6 is a semiconductor structure after a subsequent process step of fin formation;
  • FIG. 7 is a semiconductor structure after subsequent process steps of shallow trench isolation refilling and recessing;
  • FIG. 8 is a semiconductor structure at a starting point for alternative illustrative embodiments utilizing shallow trench isolation;
  • FIG. 9 is a semiconductor structure after subsequent process steps of forming left and right spacers and removing the sacrificial material, in accordance with alternative illustrative embodiments;
  • FIG. 10 is a semiconductor structure after a subsequent process step of removing the underlying nitride liner, in accordance with alternative illustrative embodiments;
  • FIG. 11 is a semiconductor structure after a subsequent process step of forming fins, in accordance with alternative illustrative embodiments;
  • FIG. 12 is a semiconductor structure after subsequent process steps of removing intermediate layers and refilling the shallow trench isolation, in accordance with alternative illustrative embodiments; and
  • FIG. 13 is a flowchart indicating process steps for embodiments of the present invention.
    •  DETAILED DESCRIPTION
  • Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finFETs). Sacrificial regions are formed on a semiconductor substrate. Spacers are formed adjacent to two sides of the sacrificial regions. Fins are formed based on the spacers. One set of spacers is treated as dummy spacers, and is removed prior to fin formation, leaving the other set of spacers to be used for forming fins on the final semiconductor structure. All the fins on the final semiconductor structure are formed from spacers on one side of the sacrificial material. This reduces variation in width of the fins, and improves product reliability and yield for devices that employ single-fin finFETs, such as SRAM integrated circuits (ICs), latches, and ring oscillators.
  • It will be appreciated that this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. For example, as used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms “a”, “an”, etc., do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. It will be further understood that the terms “comprises” and/or “comprising”, or “includes” and/or “including”, when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
  • Reference throughout this specification to “one embodiment,” “an embodiment,” “embodiments,” “exemplary embodiments,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” “in embodiments” and similar language throughout this specification may, but do not necessarily all refer to the same embodiment.
  • The terms “overlying” or “atop”, “positioned on” or “positioned atop”, “underlying”, “beneath” or “below” mean that a first element, such as a first structure (e.g., a first layer), is present on a second element, such as a second structure (e.g. a second layer), wherein intervening elements, such as an interface structure (e.g. interface layer), may be present between the first element and the second element.
  • FIG. 1 is a semiconductor structure 100 at a starting point for illustrative embodiments. Semiconductor structure 100 includes a semiconductor substrate 102, which may be a silicon substrate. Substrate 102 may be a bulk substrate, such as in the form of a wafer. However, embodiments of the present invention may also be used with silicon-on-insulator (SOI) technology. Disposed on substrate 102 is a pad nitride liner 104. In embodiments, pad nitride liner 104 may be comprised of silicon nitride. In some embodiments, liner 104 may have a thickness X ranging from about 10 nanometers to about 100 nanometers. In embodiments, liner 104 may be deposited via a chemical vapor deposition (CVD) process.
  • FIG. 2 is a semiconductor structure 200 after a subsequent process step of forming sacrificial material regions 206, in accordance with illustrative embodiments. In embodiments, sacrificial material regions 206 may be comprised of amorphous silicon and may be deposited via industry-standard patterning and deposition techniques. In other embodiments, sacrificial material regions 206 may comprise an oxide, such as silicon oxide. As stated previously, similar elements may be referred to by similar numbers in various figures (FIGs) of the drawing, in which case typically the last two significant digits may be the same. For example, substrate 202 of FIG. 2 is similar to substrate 102 of FIG. 1. In some embodiments, the pitch P between adjacent sacrificial material regions 206 and 208 ranges from about 50 nanometers to about 90 nanometers. In some embodiments, the width W of a sacrificial material region (206, 208) may range from about 15 nanometers to about 30 nanometers.
  • FIG. 3 is a semiconductor structure 300 after a subsequent process step of forming left and right spacers, in accordance with illustrative embodiments. The spacers 310L, 310R, 312L, and 312R are formed in a single deposition process. The sacrificial material regions (206 of FIG. 2) are then removed with an etch process. In some embodiments, a reactive ion etch (RIE) process may be used for removal of the sacrificial material regions. The sacrificial material region 206 should preferably have high selectivity to the material used for spacers 310L, 310R, 312L, and 312R. In some embodiments, the spacers 310L, 310R, 312L, and 312R may be comprised of a nitride, such as silicon nitride. In some embodiments, the spacers 310L, 310R, 312L, and 312R may be comprised of an oxide, such as a silicon oxide. The material used for the spacers 310L, 310R, 312L, and 312R is preferably highly selectable to the sacrificial material regions (206 of FIG. 2).
  • In an ideal case, the width of spacer 310L would be the same as the width of spacer 310R. However, in practice, this is rarely the case. In practice, there is variation in thickness between the left and right side spacers due to variations in deposition and etch processes used in forming the spacers. For example, the left spacers 310L and 312L have a thickness T1, and the right spacers 310R and 312R have a thickness T2, where T1 is not equal to T2. Spacers formed on the same side are normally substantially equal to each other. For example, right spacers are normally substantially equal to other right spacers, and left spacers are normally substantially equal to other left spacers, due to the nature of etching and deposition processes. When fins are formed based on both sets of spacers, the difference between thickness T1 and thickness T2 could cause variation in fin width. For single-fin finFET applications, such as SRAM, the variation in fin width could have adverse effects on yield and device performance. Embodiments of the present invention mitigate this problem by utilizing fins from only one side in the final semiconductor integrated circuit. Fins from the other side are removed prior to completion of the integrated circuit. In this way, the mismatch between thickness T1 and thickness T2 does not affect the fin width in the final semiconductor integrated circuit. For SRAMs and other applications utilizing single-fin finFETs, including, but not limited to, latches, ring oscillators, and logic gates, embodiments of the present invention can significantly improve product yield and device performance.
  • FIG. 4 is a semiconductor structure 400 after a subsequent process step of removing most of the underlying nitride liner. A portion of the nitride liner remains under the spacers. The nitride liner portions 414L, 414R, 416L, and 416R are also subject to the variations in thickness between T1 and T2.
  • FIG. 5 is a semiconductor structure 500 after a subsequent process step of dummy spacer removal. In this example, the right spacers (410R and 412R of FIG. 4) have been removed. The removal of the dummy spacers may be accomplished via industry standard lithographic and etching techniques. The spacers 510L and 512L are from the left set of spacers, and will be used to form the fins. In embodiments of the present invention, one of the sets of spacers is treated as a set of dummy spacers that will not be used to form fins. The other set of spacers is treated as a set of functional spacers that will be used to form fins on the completed integrated circuit.
  • FIG. 6 is a semiconductor structure 600 after a subsequent process step of fin formation. An anisotropic etch is performed, resulting in the formation of fins 618L and 620L underneath the functional spacers 610L and 612L. In this example, the left fins 618L and 620L are formed based on spacers 610L and 612L respectively. However, other embodiments may utilize the right side spacers as functional spacers, and utilize the left side spacers as dummy spacers.
  • FIG. 7 is a semiconductor structure 700 after subsequent process steps forming shallow trench isolation (STI) regions 715. In embodiments, the STI regions 715 may be comprised of an oxide, such as silicon oxide. The STI regions 715 may be formed by depositing oxide via a chemical vapor deposition (CVD) process, followed by a recess process to place the top of the STI regions at a desired level.
  • FIG. 8 is a semiconductor structure 800 at a starting point for alternative illustrative embodiments utilizing shallow trench isolation (STI). In this embodiment, the sacrificial material regions 806 and 808 are formed in an off-center alignment with corresponding shallow trench isolation regions 815, such that, for example, left edge 813A of the sacrificial material region 808 is located to the left of the left edge 817A of shallow trench isolation region 815, and right edge 813B of sacrificial material region 808 is located to the right of left edge 817A of shallow trench isolation region 815, and is also located to the left of right edge 817B of shallow trench isolation region 815. Shallow trench isolation regions 815 may be comprised of silicon oxide or other suitable insulating material.
  • FIG. 9 is a semiconductor structure 900 after subsequent process steps of forming left and right spacers and removing the sacrificial material, in accordance with alternative illustrative embodiments. Left spacers 910L and 912L are formed above the semiconductor substrate 902, and are used as functional spacers in this example. Right spacers 910R and 912R are formed above the shallow trench isolation regions 915. The right spacers represent “dummy spacers” that are not used to form active fins, while the left spacers are functional spacers, and thus are used to form active fins.
  • FIG. 10 is a semiconductor structure 1000 after a subsequent process step of removing the underlying nitride liner, in accordance with alternative illustrative embodiments. Left nitride portions 1014L and 1016L are formed over the semiconductor substrate 1002, while right nitride portions 1014R and 1016R are formed over shallow trench isolation regions 1015.
  • FIG. 11 is a semiconductor structure 1100 after a subsequent process step of forming fins, in accordance with alternative illustrative embodiments. Fins 1118L and 1120L are formed from semiconductor substrate 1002, and are part of the final integrated circuit. No fins are formed under dummy spacers 1110R and 1112R, as those spacers are formed above STI regions 1115.
  • FIG. 12 is a semiconductor structure after subsequent process steps of removing intermediate layers and refilling the shallow trench isolation. Functional and dummy spacers (e.g., 1110R, 1110L, 1112R, and 1112L from FIG. 11) are removed. In this embodiment, the material underneath the dummy spacers is comprised of shallow trench isolation material, such as silicon oxide, and may therefore be removed by a selective etch process.
  • FIG. 13 is a flowchart 1300 indicating process steps for embodiments of the present invention. In process step 1350, a nitride liner is deposited on a semiconductor substrate. In process step 1352, sacrificial material regions are formed. In process step 1354, functional and dummy spacers are formed adjacent to the sacrificial material regions, and the sacrificial material regions are then removed. In process step 1356, the dummy spacers (from either the left or right side) are removed. In process step 1358, the fins are formed, based on the functional spacers. All the fins in the remaining set are from one side. That is, all the fins are formed either from all left-side spacers or all right-side spacers. By having all the fins formed from the spacers of one side, thickness mismatch between the two sides is eliminated in the fins, improving product yield and device performance.
  • While the invention has been particularly shown and described in conjunction with exemplary embodiments, it will be appreciated that variations and modifications will occur to those skilled in the art. For example, although the illustrative embodiments are described herein as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events unless specifically stated. Some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the formation and/or processing of structures illustrated and described herein as well as in association with other structures not illustrated. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and changes that fall within the true spirit of the invention.

Claims (18)

What is claimed is:
1. A semiconductor device, comprising:
a semiconductor substrate comprising a substrate material; and
a plurality of fins, wherein each fin comprises a lower region comprising the substrate material, a middle region comprising a nitride material, and an upper region comprising a spacer material, and the fins have substantially equal widths.
2. The semiconductor device of claim 1, wherein the spacer material comprises silicon nitride.
3. The semiconductor device of claim 1, further comprising:
a plurality of shallow trench isolation (STI) regions in the semiconductor substrate, wherein each STI region is disposed between adjacent fins.
4. The semiconductor device of claim 3, wherein the plurality of STI regions comprise silicon oxide.
5. The semiconductor device of claim 3, wherein the distance between each STI region and a first adjacent fin ranges from about 15 nanometers to about 30 nanometers.
6. The semiconductor device of claim 1, wherein the middle region has a height ranging from about 10 nanometers to about 100 nanometers.
7. A semiconductor device, comprising:
a semiconductor substrate comprising a substrate material; and
a plurality of finFET devices, wherein each finFET device comprises a single fin, wherein the fin of each of the plurality of FinFET devices comprises a lower region comprising the substrate material, a middle region comprising a nitride material, and an upper region comprising a spacer material, and wherein the fins of the plurality of FinFET devices are formed by a process comprising:
forming a nitride liner on the semiconductor substrate;
forming a plurality of sacrificial material regions on the nitride liner;
forming a first set of spacers on a first side of each of the sacrificial material regions and a second set of spacers on a second side of each of the sacrificial material regions;
removing the plurality of sacrificial material regions;
removing each of the second set of spacers while preserving the first set of spacers.
8. The semiconductor device of claim 7, wherein the spacer material comprises silicon nitride.
9. The semiconductor device of claim 7, further comprising:
a plurality of shallow trench isolation (STI) regions in the semiconductor substrate, wherein each STI region is disposed between adjacent fins.
10. The semiconductor device of claim 9, wherein the plurality of STI regions comprise silicon oxide.
11. The semiconductor device of claim 9, wherein the distance between each STI region and a first adjacent fin ranges from about 15 nanometers to about 30 nanometers.
12. The semiconductor device of claim 7, wherein the middle region has a height ranging from about 10 nanometers to about 100 nanometers.
13. A semiconductor device, comprising:
a semiconductor substrate comprising a substrate material; and
a plurality of fins, wherein each fin comprises a lower region comprising the substrate material, a middle region comprising a nitride material, an upper region comprising a spacer material, and a first side, wherein a pitch between the first sides of adjacent fins ranges from about 50 nanometers to about 90 nanometers.
14. The semiconductor device of claim 13, wherein the spacer material comprises silicon nitride.
15. The semiconductor device of claim 13, further comprising:
a plurality of shallow trench isolation (STI) regions in the semiconductor substrate, wherein each STI region is disposed between adjacent fins.
16. The semiconductor device of claim 15, wherein the plurality of STI regions comprise silicon oxide.
17. The semiconductor device of claim 15, wherein the distance between each STI region and a first adjacent fin ranges from about 15 nanometers to about 30 nanometers.
18. The semiconductor device of claim 13, wherein the middle region has a height ranging from about 10 nanometers to about 100 nanometers.
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