US20140312428A1 - Epitaxial replacement of a raised source/drain - Google Patents

Epitaxial replacement of a raised source/drain Download PDF

Info

Publication number
US20140312428A1
US20140312428A1 US14/318,936 US201414318936A US2014312428A1 US 20140312428 A1 US20140312428 A1 US 20140312428A1 US 201414318936 A US201414318936 A US 201414318936A US 2014312428 A1 US2014312428 A1 US 2014312428A1
Authority
US
United States
Prior art keywords
rsd
faceted
spacer
gate
gate structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/318,936
Inventor
Thomas N. Adam
Kangguo Cheng
Ali Khakifirooz
Alexander Reznicek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US14/318,936 priority Critical patent/US20140312428A1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ADAM, THOMAS N., CHENG, KANGGUO, REZNICEK, ALEXANDER, KHAKIFIROOZ, ALI
Publication of US20140312428A1 publication Critical patent/US20140312428A1/en
Assigned to GLOBALFOUNDRIES U.S. 2 LLC reassignment GLOBALFOUNDRIES U.S. 2 LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES U.S. 2 LLC, GLOBALFOUNDRIES U.S. INC.
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to semiconductor integrated circuits and, more particularly, relates to enhancing the performance of raised source/drains in MOSFET semiconductor devices.
  • RSD In-situ doped raised source/drain
  • MOSFET metal oxide semiconductor field effect transistors
  • a side effect of RSD is the parasitic capacitance between the gate and the RSD. Faceted RSD has been demonstrated as an effective means to reduce the gate-to-source/drain parasitic capacitance.
  • a semiconductor article including: a semiconductor substrate; a plurality of gate structures, each gate structure having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer at a juncture of the gate structure and the semiconductor substrate is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and a raised source/drain (RSD) for each of the plurality of gate structures such that each RSD is adjacent to one of the gate structure wherein the RSD is an RSD that is formed above a channel of the gate structure, the RSD filling the faceted space and also having a surface parallel to the semiconductor substrate.
  • At least one gate structure of the plurality of gate structures is for an nFET and at least one gate structure of the plurality of gate structures is for a pFET.
  • a semiconductor article including: a semiconductor substrate; a gate structure having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer at a juncture of the gate structure and the semiconductor substrate is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and a raised source/drain (RSD) adjacent to the gate structure wherein the RSD is an RSD that is formed above a channel of the gate structure, the RSD filling the faceted space and having a faceted surface wherein the RSD comprises two contiguous portions, the first portion having the faceted surface in the faceted space and a first height with respect to the substrate, the second portion outside the faceted space having a second height with respect to the substrate wherein the first height is less than the second height
  • RSD raised source/drain
  • a semiconductor article including a semiconductor substrate; a plurality of gate structures, each gate structure having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer at a juncture of the gate structure and the semiconductor substrate is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and a raised source/drain (RSD) for each of the plurality of gate structures such that each RSD is adjacent to one of the gate structures wherein the RSD is an RSD that is formed above a channel of the gate structure, the RSD filling the faceted space and having a faceted surface wherein the RSD comprises two contiguous portions, the first portion having the faceted surface in the faceted space and a first height with respect to the substrate, the second portion outside the faceted space having a second height with respect to the substrate wherein the first height is less than the second height.
  • At least one gate structure of the plurality of gate structures is for an nFET and at
  • FIGS. 1 to 10 are cross-sectional views illustrating the manufacturing of a semiconductor structure with epitaxial replacement of a raised source/drain according to the exemplary embodiments wherein:
  • FIG. 1 illustrates the forming of gate structures on a semiconductor substrate having nFET and pFET regions
  • FIG. 2 illustrates the forming of dummy RSDs adjacent to the gate structures
  • FIG. 3 illustrates the deposition of a dielectric layer over the gate structures and dummy RSDs
  • FIG. 4 illustrates the masking of the nFET region while removing the dielectric layer in the pFET region
  • FIG. 5 illustrates the removal of the dummy RSD in the pFET region
  • FIG. 6 illustrates the forming of the real RSD in the pFET region
  • FIG. 7 illustrates the masking of the pFET region and removing of the dielectric layer in the nFET region
  • FIG. 8 illustrates the removal of the dummy RSD in the nFET region
  • FIG. 9 illustrates the forming of the real RSD in the nFET region.
  • FIG. 10 illustrates the annealing of the semiconductor structure to form extensions in the semiconductor substrate.
  • a faceted epitaxy process is preferably employed.
  • manufacturing MOSFETs with RSD by epitaxy with a faceted profile and high dopant concentration, particularly for the highly scaled devices with tight pitches, has been found extremely difficult to achieve. Therefore, there is a need for improving the manufacturing of MOSFETs with in-situ doped RSD.
  • a replacement RSD scheme which decouples the faceted RSD profile requirement and the in-situ doping.
  • a dummy RSD with a faceted profile is first formed after gate patterning and a spacer is then formed. The dummy RSD then may be removed and an in-situ doped epitaxy is performed to form the real RSD.
  • the semiconductor substrate may be any semiconductor substrate including bulk semiconductor substrates and semiconductor on insulator (SOI) substrates such as ETSOI (extra thin semiconductor on insulator) and PDSOI (partially-depleted semiconductor on insulator).
  • SOI semiconductor on insulator
  • ETSOI extra thin semiconductor on insulator
  • PDSOI partially-depleted semiconductor on insulator
  • the semiconductor material making up the bulk semiconductor substrate may be any semiconductor material, including but not limited to, silicon, silicon germanium, germanium, carbon doped silicon (carbon 0.2 atomic percent (a/o) to 6 a/o, with 0.5 a/o to 2.5 a/o typical), a III-V compound semiconductor, or a II-VI compound semiconductor.
  • the semiconductor material making up the semiconductor on insulator (SOI) layer of an SOI substrate may be any semiconductor material, including but not limited to, silicon, silicon germanium, germanium, a III-V compound semiconductor, or a II-VI compound semiconductor.
  • the semiconductor substrate 12 may also comprise a layered semiconductor such as, for example, silicon/silicon germanium, a silicon-on-insulator or a silicon germanium-on-insulator. A portion of the semiconductor substrate 12 or the entire semiconductor substrate 12 may be amorphous, polycrystalline, or monocrystalline.
  • the semiconductor substrate 12 shown in FIG. 1 may be an SOI substrate and may be an ETSOI substrate or a PDSOI substrate.
  • the semiconductor substrate 12 includes a semiconductor base 18 , a buried insulating layer 20 and a top semiconductor layer 22 .
  • the buried insulating layer 20 may be an oxide layer and, further, may be referred to as a BOX (buried oxide) layer.
  • the semiconductor substrate 12 may be formed by conventional means.
  • the semiconductor substrate 12 may further include a first device region 24 and a second device region 26 separated by an isolation region 28 .
  • a first gate structure 14 may be positioned in the first device region 24 of the substrate 12 and a second gate structure 16 may be positioned in the second device region 26 of the substrate 12 .
  • First device region 24 may also be referred to as an N-type device region (where an nFET device may be formed) or a P-type device region (where a pFET device may be formed), while second region 26 may also be referred to as a P-type device region or an N-type device region, in which the first device region 24 has a different conductivity than the second device region 26 .
  • FIG. 1 illustrates a first device region 24 where an nFET device may be formed and second device region 26 where a pFET device may be formed.
  • the isolation region 28 separates the device regions 24 , 26 of the SOI layer 22 and may be in direct physical contact with an upper surface of the BOX layer 20 or may extend into BOX layer 20 .
  • Isolation region 28 , as well as isolation regions 30 , 32 may be formed by conventional means.
  • the first and second gate structures 14 , 16 may be formed by conventional means.
  • the first and second gate structures 14 , 16 may each include a gate conductor 34 atop a gate dielectric 36 .
  • Gate conductor 34 material may be polysilicon, but may also include elemental metals, metal alloys, metal silicides, and/or other conductive materials.
  • Gate dielectric 36 may be a dielectric material, such as silicon oxide (SiO2), silicon nitride, oxynitride, or alternatively high-k dielectrics, such as oxides of Ta, Zr, Al, Hf or combinations thereof.
  • the first and second gate structures 14 , 16 may also include a gate cap 38 such as silicon nitride.
  • a set of first spacers 40 may be conventionally formed in direct contact with the sidewalls of the first gate structure 14 and second gate structure 16 .
  • the first spacers 40 may be composed of a dielectric, such as nitride, oxide, oxynitride, or a combination thereof.
  • the thickness of the first spacers 40 determines the proximity of the subsequently formed raised source/drain (RSD) regions to the channel of the device.
  • RSD raised source/drain
  • the first and second gate structures 14 , 16 may be the real gate structures in the case of a gate-first process or may be dummy gate structures in the case of a gate-last process.
  • dummy RSD structures 42 may be formed.
  • the dummy RSD structures 42 may comprise silicon germanium (SiGe).
  • the dummy RSD structures 42 are faceted and may be grown from the SOI layer 22 in a selective epitaxial deposition process. Faceting may be tailored during the selective epitaxial deposition process by adjusting the alloy and dopant concentration, and reactor temperature, pressure, and etchant and precursor flows.
  • high-germanium percentage silicon germanium >20%) favors the evolution of ⁇ 111> facets at low temperatures ( ⁇ 6500), low pressures ( ⁇ 50 T, preferably UHV), and high partial pressures of HCl.
  • Silicon germanium is preferably used since it may be removed selectively to silicon later, when the dummy epitaxy is removed. Any other epitaxial material that forms facets and may be removed selectively to the silicon underneath it may be used. Silicon germanium is preferred because of its selectivity to silicon and can be easily selectively removed. Phosphorous doped silicon (Si:P) can work too, since it may be removed selectively to silicon, but not as easily as silicon germanium.
  • the dummy RSD structures 42 will be selectively removed in a later process step but are important now for forming a facet with respect to the first and second gate structures 14 , 16 .
  • a dielectric layer 44 is blanket deposited so as to cover the semiconductor structure 10 including the first and second gate structures 14 , 16 and dummy RSD structures 42 .
  • the dielectric layer 44 may comprise, for example, silicon nitride, silicon oxide, silicon oxynitride, boron nitride, high-k dielectric or any combination of these materials.
  • high-k materials include but are not limited to metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc ni
  • the first device region 24 is masked off with a photoresist 46 while the second device region 26 is not masked off.
  • the photoresist mask 46 may be conventionally formed by blanket deposition of a photoresist, exposing the photoresist to a suitable source of radiation and then developing to remove the unwanted photoresist.
  • the semiconductor structure 10 then may undergo a reactive ion etching (RIE) process, indicated by arrows 48 , to remove the dielectric layer 44 from the dummy RSD structures 42 in the second device region 26 and form second spacer 50 adjacent to second gate structure 16 .
  • RIE reactive ion etching
  • the photoresist mask 46 shown in FIG. 4 may be conventionally stripped such as by an oxygen plasma to result in the structure illustrated in FIG. 5 .
  • the dummy RSD structures 42 in the second device region 26 are also removed such as by a gas-based HCl etch (or any other halide-based etch, i.e. chlorine, fluorine, etc.).
  • the gas-based etch may be performed in the epitaxial reactor,
  • the RSD structures 42 may also be removed by a wet etch such as TMAH (Tetramethylammonium hydroxide).
  • TMAH Tetramethylammonium hydroxide
  • the dummy RSD structures 42 being made from SiGe, may be easily and selectively removed by the HCl etch in the second device region 26 without adversely affecting the underlying SOI layer 22 . It is noted that with the removal of the dummy RSD structures 42 from the second device region 26 , facets 52 remain in the second spacer 50 .
  • an in-situ doped RSD 54 is epitaxially grown on SOI layer 22 in the second device region 26 .
  • in-situ doped it is meant that the RSD 54 is doped while the RSD 54 is epitaxially grown, with the dopant gas flowing at the same time as the deposition gases. It should be understood that in-situ doping is optional and the RSD 54 may be doped by other means.
  • the RSD 54 is grown by a non-faceted epitaxial growth process so that a planar surface 56 approximately parallel with SOI layer 22 is obtained.
  • the non-faceted epitaxially grown RSD 54 may be formed by adjusting the epitaxial deposition parameters as described previously.
  • the in-situ doped RSD 54 may be in-situ boron-doped silicon germanium (ISBD SiGe).
  • the boron doping may be approximately 1 ⁇ 10 18 to 1 ⁇ 10 22 atoms/cm 3 with 1 ⁇ 10 20 to 4 ⁇ 10 20 atoms/cm 3 being more common.
  • a thin hardmask 58 such as 3 nanometers of silicon oxide, is selectively deposited in the second device region 26 so as to cover the second gate structure 16 , second spacer 50 and RSD 54 .
  • the hardmask 58 may be removed from the first device region 24 by any etch selective to the dielectric layer 44 .
  • oxide may be etched by an aqueous etchant containing hydrofluoric acid selective to nitride.
  • the hardmask 58 may be removed from the dielectric layer 44 in the first device region 24 as just described.
  • the photoresist mask 60 may be conventionally formed by blanket deposition of a photoresist, exposing the photoresist to a suitable source of radiation and then developing to remove the unwanted photoresist.
  • the semiconductor structure 10 then may undergo a reactive ion etching (RIE) process, indicated by arrows 62 , to remove the dielectric layer 44 from the dummy RSD structures 42 in the first device region 24 and form second spacer 64 adjacent to first gate structure 14 .
  • RIE reactive ion etching
  • the process step of removing the hardmask 58 from the dielectric layer 44 in the first device region 24 may be skipped and then after the RIE process described above, the hardmask 58 would become part of the spacer 64 in the first device region 24 .
  • the photoresist 60 shown in FIG. 7 may be conventionally stripped such as by an oxygen plasma to result in the structure illustrated in FIG. 8 .
  • the dummy RSD structures 42 in the first device region 24 are also removed such as by an HCl etch.
  • the dummy RSD structures 42 being made from SiGe, may be easily and selectively removed by the HCl etch without affecting the underlying SOI layer 22 . It is noted that with the removal of the dummy RSD structures 42 from the first device region 24 , facets 66 remain in the second spacer 64 .
  • the second gate structure 16 and RSD 54 in the second device region 26 are protected by hardmask 58 and so are not affected by the etching of the dummy RSD structures 42 in the first device region 24 .
  • an in-situ doped RSD 68 is epitaxially grown in the first device region 24 . It should be understood that in-situ doping is optional and the RSD 68 may be doped by other means.
  • the RSD 68 is grown by a non-faceted epitaxial growth process similar to that for RSD 54 so that a planar surface 70 approximately parallel with SOI layer 22 is obtained. While the RSD 68 is grown by a non-faceted epitaxial growth process, the RSD 68 fills the facet 66 in second spacer 64 so that the RSD 68 forms a faceted interface with first gate structure 14 at the corner of the first gate structure 14 and SOI layer 22 .
  • the in-situ doped RSD 68 may be in-situ phosphorus-doped silicon (ISPD Si), in-situ phosphorus-doped and carbon-doped silicon (ISPD Si:C), in-situ arsenic-doped silicon (ISAD Si) or in-situ phosphorus-doped silicon germanium (ISPD SiGe).
  • the approximate doping of the silicon or silicon germanium may be 1 ⁇ 10 18 to 1 ⁇ 10 22 atoms/cm 3 with 1 ⁇ 10 20 to 7 ⁇ 10 20 atoms/cm 3 being more common.
  • the semiconductor structure 10 then may undergo a fast anneal to drive the dopants from the RSD 68 into the SOI layer 22 to form extensions 72 and the dopants from the RSD 54 into the SOI layer 22 to form extensions 74 .
  • the resulting structure is illustrated in FIG. 10 .
  • the fast anneal may be a spike anneal in which the semiconductor structure is rapidly heated to a peak temperature of approximately 1000-1100° C. and then immediately cooled after reaching the peak temperature.
  • the fast anneal may also include rapid thermal anneal (RTA), laser anneal, flash anneal, furnace anneal, or any suitable combination of these techniques.
  • the anneal temperature depending on the anneal technique, may range from 600 C to 1300 C.
  • the fast anneal may be optional in those cases where it is not necessary to drive in the dopants.
  • a light anneal may just be necessary to link up the RSD with the extension.
  • first and second gate structures 14 , 16 cannot tolerate the high temperatures of the fast anneal, then a gate-last process may be needed to replace the first and second gate structures 14 , 16 (which would be dummy gate structures) after the fast anneal with the real first and second gate structures 14 , 16 .
  • the hardmask 58 shown in FIG. 9 may be conventionally removed either before or after the fast anneal. Conventional removal of the hardmask 58 may be by any suitable etch. For example, in the case that the hardmask 58 is silicon oxide, it may be removed by an aqueous solution containing hydrofluoric acid. However, the hardmask 58 should be in place during the formation of the in-situ doped RSD 68 .
  • the first and second gate structures 14 , 16 may be the real gate structures which would remain in place during further processing. These first and second gate structures 14 , 16 may be formed by a gate first process. Alternatively, the first and second gate structures 14 , 16 shown, for example, in FIG. 1 may be dummy structures and it may be desirable to replace the dummy first and second gate structures 14 , 16 with real first and second gate structures 14 , 16 after formation of the epitaxially formed RSDs 54 , 68 shown, for example, in FIG. 10 in a gate last process.
  • a first significant advantage is that the RSD that replaces the dummy RSD is grown by a non-faceted epitaxial process and yet a faceted epitaxial RSD is obtained at the corner where the RSD meets the gate structure.
  • Another significant advantage is the first spacer is the same for both the nFET and pFET gate structures so that the replacement RSD is spaced from the channel the same amount for both the nFET and pFET gate structures.

Abstract

Disclosed is a semiconductor article which includes a semiconductor substrate; a plurality of gate structures having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and a raised source/drain adjacent to each of the gate structures, the raised source/drain filling the faceted space and having a surface parallel to the semiconductor substrate. At least one gate structure of the plurality of gate structures is for an nFET and at least one gate structure of the plurality of gate structures is for a pFET.

Description

    RELATED APPLICATION
  • The present application is a divisional of U.S. patent application Ser. 13/355,691, filed Jan. 23, 2012, entitled “EPITAXIAL REPLACEMENT OF A RAISED SOURCE/DRAIN”, now U.S. Pat. No. ______.
    • BACKGROUND
  • The present invention relates to semiconductor integrated circuits and, more particularly, relates to enhancing the performance of raised source/drains in MOSFET semiconductor devices.
  • In-situ doped raised source/drain (RSD) has become a viable approach to enhance the performance of advanced MOSFETs (metal oxide semiconductor field effect transistors) by lowering the raised source/drain and simultaneously achieving ultra shallow junction. A side effect of RSD is the parasitic capacitance between the gate and the RSD. Faceted RSD has been demonstrated as an effective means to reduce the gate-to-source/drain parasitic capacitance.
    • BRIEF SUMMARY
  • The various advantages and purposes of the exemplary embodiments as described above and hereafter are achieved by providing, according to a first aspect of the exemplary embodiments, a semiconductor article including: a semiconductor substrate; a plurality of gate structures, each gate structure having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer at a juncture of the gate structure and the semiconductor substrate is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and a raised source/drain (RSD) for each of the plurality of gate structures such that each RSD is adjacent to one of the gate structure wherein the RSD is an RSD that is formed above a channel of the gate structure, the RSD filling the faceted space and also having a surface parallel to the semiconductor substrate. At least one gate structure of the plurality of gate structures is for an nFET and at least one gate structure of the plurality of gate structures is for a pFET.
  • According to a second aspect of the exemplary embodiments, there is provided a semiconductor article including: a semiconductor substrate; a gate structure having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer at a juncture of the gate structure and the semiconductor substrate is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and a raised source/drain (RSD) adjacent to the gate structure wherein the RSD is an RSD that is formed above a channel of the gate structure, the RSD filling the faceted space and having a faceted surface wherein the RSD comprises two contiguous portions, the first portion having the faceted surface in the faceted space and a first height with respect to the substrate, the second portion outside the faceted space having a second height with respect to the substrate wherein the first height is less than the second height
  • According to a third aspect of the exemplary embodiments, there is provided a semiconductor article including a semiconductor substrate; a plurality of gate structures, each gate structure having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer at a juncture of the gate structure and the semiconductor substrate is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and a raised source/drain (RSD) for each of the plurality of gate structures such that each RSD is adjacent to one of the gate structures wherein the RSD is an RSD that is formed above a channel of the gate structure, the RSD filling the faceted space and having a faceted surface wherein the RSD comprises two contiguous portions, the first portion having the faceted surface in the faceted space and a first height with respect to the substrate, the second portion outside the faceted space having a second height with respect to the substrate wherein the first height is less than the second height. At least one gate structure of the plurality of gate structures is for an nFET and at least one gate structure of the plurality of gate structures is for a pFET.
    • BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS
  • The features of the exemplary embodiments believed to be novel and the elements characteristic of the exemplary embodiments are set forth with particularity in the appended claims. The Figures are for illustration purposes only and are not drawn to scale. The exemplary embodiments, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which:
  • FIGS. 1 to 10 are cross-sectional views illustrating the manufacturing of a semiconductor structure with epitaxial replacement of a raised source/drain according to the exemplary embodiments wherein:
  • FIG. 1 illustrates the forming of gate structures on a semiconductor substrate having nFET and pFET regions;
  • FIG. 2 illustrates the forming of dummy RSDs adjacent to the gate structures;
  • FIG. 3 illustrates the deposition of a dielectric layer over the gate structures and dummy RSDs;
  • FIG. 4 illustrates the masking of the nFET region while removing the dielectric layer in the pFET region;
  • FIG. 5 illustrates the removal of the dummy RSD in the pFET region;
  • FIG. 6 illustrates the forming of the real RSD in the pFET region;
  • FIG. 7 illustrates the masking of the pFET region and removing of the dielectric layer in the nFET region;
  • FIG. 8 illustrates the removal of the dummy RSD in the nFET region;
  • FIG. 9 illustrates the forming of the real RSD in the nFET region; and
  • FIG. 10 illustrates the annealing of the semiconductor structure to form extensions in the semiconductor substrate.
    •  DETAILED DESCRIPTION
  • To reduce any possible penalties in parasitic capacitance due to the RSD structure, a faceted epitaxy process is preferably employed. However, manufacturing MOSFETs with RSD by epitaxy with a faceted profile and high dopant concentration, particularly for the highly scaled devices with tight pitches, has been found extremely difficult to achieve. Therefore, there is a need for improving the manufacturing of MOSFETs with in-situ doped RSD.
  • There is proposed in the exemplary embodiments a replacement RSD scheme which decouples the faceted RSD profile requirement and the in-situ doping. According to the exemplary embodiments, a dummy RSD with a faceted profile is first formed after gate patterning and a spacer is then formed. The dummy RSD then may be removed and an in-situ doped epitaxy is performed to form the real RSD.
  • Referring to the Figures in more detail, and particularly referring to FIG. 1, there is illustrated the results of initial processing steps that produce a semiconductor structure 10 that includes semiconductor substrate 12 having semiconductor gate structures 14, 16. The semiconductor substrate may be any semiconductor substrate including bulk semiconductor substrates and semiconductor on insulator (SOI) substrates such as ETSOI (extra thin semiconductor on insulator) and PDSOI (partially-depleted semiconductor on insulator). The particular semiconductor substrate is unimportant to the present invention.
  • The semiconductor material making up the bulk semiconductor substrate may be any semiconductor material, including but not limited to, silicon, silicon germanium, germanium, carbon doped silicon (carbon 0.2 atomic percent (a/o) to 6 a/o, with 0.5 a/o to 2.5 a/o typical), a III-V compound semiconductor, or a II-VI compound semiconductor. Similarly, the semiconductor material making up the semiconductor on insulator (SOI) layer of an SOI substrate may be any semiconductor material, including but not limited to, silicon, silicon germanium, germanium, a III-V compound semiconductor, or a II-VI compound semiconductor.
  • The semiconductor substrate 12 may also comprise a layered semiconductor such as, for example, silicon/silicon germanium, a silicon-on-insulator or a silicon germanium-on-insulator. A portion of the semiconductor substrate 12 or the entire semiconductor substrate 12 may be amorphous, polycrystalline, or monocrystalline.
  • For purposes of illustration and not limitation, the semiconductor substrate 12 shown in FIG. 1 may be an SOI substrate and may be an ETSOI substrate or a PDSOI substrate. The semiconductor substrate 12 includes a semiconductor base 18, a buried insulating layer 20 and a top semiconductor layer 22. The buried insulating layer 20 may be an oxide layer and, further, may be referred to as a BOX (buried oxide) layer. The semiconductor substrate 12 may be formed by conventional means.
  • The semiconductor substrate 12 may further include a first device region 24 and a second device region 26 separated by an isolation region 28. A first gate structure 14 may be positioned in the first device region 24 of the substrate 12 and a second gate structure 16 may be positioned in the second device region 26 of the substrate 12. There may be other isolation regions 30, 32 to separate first device region 24 from a third device region (not shown) and second device region 26 from a fourth device region (not shown), respectively.
  • First device region 24 may also be referred to as an N-type device region (where an nFET device may be formed) or a P-type device region (where a pFET device may be formed), while second region 26 may also be referred to as a P-type device region or an N-type device region, in which the first device region 24 has a different conductivity than the second device region 26. For purposes of illustration and not limitation, FIG. 1 illustrates a first device region 24 where an nFET device may be formed and second device region 26 where a pFET device may be formed.
  • The isolation region 28 separates the device regions 24, 26 of the SOI layer 22 and may be in direct physical contact with an upper surface of the BOX layer 20 or may extend into BOX layer 20. Isolation region 28, as well as isolation regions 30, 32 may be formed by conventional means.
  • The first and second gate structures 14, 16 may be formed by conventional means. The first and second gate structures 14, 16 may each include a gate conductor 34 atop a gate dielectric 36. Gate conductor 34 material may be polysilicon, but may also include elemental metals, metal alloys, metal silicides, and/or other conductive materials. Gate dielectric 36 may be a dielectric material, such as silicon oxide (SiO2), silicon nitride, oxynitride, or alternatively high-k dielectrics, such as oxides of Ta, Zr, Al, Hf or combinations thereof. The first and second gate structures 14, 16 may also include a gate cap 38 such as silicon nitride.
  • A set of first spacers 40 may be conventionally formed in direct contact with the sidewalls of the first gate structure 14 and second gate structure 16. The first spacers 40 may be composed of a dielectric, such as nitride, oxide, oxynitride, or a combination thereof. The thickness of the first spacers 40 determines the proximity of the subsequently formed raised source/drain (RSD) regions to the channel of the device.
  • The first and second gate structures 14, 16 may be the real gate structures in the case of a gate-first process or may be dummy gate structures in the case of a gate-last process.
  • Referring now to FIG. 2, dummy RSD structures 42 may be formed. In an exemplary embodiment, the dummy RSD structures 42 may comprise silicon germanium (SiGe). The dummy RSD structures 42 are faceted and may be grown from the SOI layer 22 in a selective epitaxial deposition process. Faceting may be tailored during the selective epitaxial deposition process by adjusting the alloy and dopant concentration, and reactor temperature, pressure, and etchant and precursor flows. As an example, high-germanium percentage silicon germanium (>20%) favors the evolution of <111> facets at low temperatures (<6500), low pressures (<50 T, preferably UHV), and high partial pressures of HCl. Shallower facets (<220>, <113>, etc.) or flat morphologies evolve at moderate temperatures (near 650 C) but high precursor partial pressures and minimal etchant flows.
  • Silicon germanium is preferably used since it may be removed selectively to silicon later, when the dummy epitaxy is removed. Any other epitaxial material that forms facets and may be removed selectively to the silicon underneath it may be used. Silicon germanium is preferred because of its selectivity to silicon and can be easily selectively removed. Phosphorous doped silicon (Si:P) can work too, since it may be removed selectively to silicon, but not as easily as silicon germanium. The dummy RSD structures 42 will be selectively removed in a later process step but are important now for forming a facet with respect to the first and second gate structures 14, 16.
  • Referring now to FIG. 3, a dielectric layer 44 is blanket deposited so as to cover the semiconductor structure 10 including the first and second gate structures 14, 16 and dummy RSD structures 42. The dielectric layer 44 may comprise, for example, silicon nitride, silicon oxide, silicon oxynitride, boron nitride, high-k dielectric or any combination of these materials. Examples of high-k materials include but are not limited to metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • As illustrated in FIG. 4, the first device region 24 is masked off with a photoresist 46 while the second device region 26 is not masked off. The photoresist mask 46 may be conventionally formed by blanket deposition of a photoresist, exposing the photoresist to a suitable source of radiation and then developing to remove the unwanted photoresist. The semiconductor structure 10 then may undergo a reactive ion etching (RIE) process, indicated by arrows 48, to remove the dielectric layer 44 from the dummy RSD structures 42 in the second device region 26 and form second spacer 50 adjacent to second gate structure 16.
  • The photoresist mask 46 shown in FIG. 4 may be conventionally stripped such as by an oxygen plasma to result in the structure illustrated in FIG. 5. The dummy RSD structures 42 in the second device region 26 are also removed such as by a gas-based HCl etch (or any other halide-based etch, i.e. chlorine, fluorine, etc.). The gas-based etch may be performed in the epitaxial reactor, The RSD structures 42 may also be removed by a wet etch such as TMAH (Tetramethylammonium hydroxide). The dummy RSD structures 42, being made from SiGe, may be easily and selectively removed by the HCl etch in the second device region 26 without adversely affecting the underlying SOI layer 22. It is noted that with the removal of the dummy RSD structures 42 from the second device region 26, facets 52 remain in the second spacer 50. The dummy RSD structures 42 in the first device region 24 are protected by dielectric layer 44 and so are not removed.
  • Referring now to FIG. 6, an in-situ doped RSD 54 is epitaxially grown on SOI layer 22 in the second device region 26. By in-situ doped, it is meant that the RSD 54 is doped while the RSD 54 is epitaxially grown, with the dopant gas flowing at the same time as the deposition gases. It should be understood that in-situ doping is optional and the RSD 54 may be doped by other means. The RSD 54 is grown by a non-faceted epitaxial growth process so that a planar surface 56 approximately parallel with SOI layer 22 is obtained. The non-faceted epitaxially grown RSD 54 may be formed by adjusting the epitaxial deposition parameters as described previously. While the RSD 54 is grown by a non-faceted epitaxial growth process, the RSD 54 fills the facet 52 in second spacer 50 so that the RSD 54 forms a faceted interface with second gate structure 16 at the corner of the second gate structure 16 and SOI layer 22. In a preferred embodiment, the in-situ doped RSD 54 may be in-situ boron-doped silicon germanium (ISBD SiGe). The boron doping may be approximately 1×1018 to 1×1022 atoms/cm3 with 1×1020 to 4×1020 atoms/cm3 being more common.
  • Referring now to FIG. 7, a thin hardmask 58, such as 3 nanometers of silicon oxide, is selectively deposited in the second device region 26 so as to cover the second gate structure 16, second spacer 50 and RSD 54. The hardmask 58 may be removed from the first device region 24 by any etch selective to the dielectric layer 44. For example, if the dielectric layer 44 is silicon nitride and the hardmask 58 is an oxide, oxide may be etched by an aqueous etchant containing hydrofluoric acid selective to nitride. As shown in FIG. 7, the hardmask 58 may be removed from the dielectric layer 44 in the first device region 24 as just described. Then, the second device region 26 is masked off with a photoresist 60 while the first device region 24 is not masked off. The photoresist mask 60 may be conventionally formed by blanket deposition of a photoresist, exposing the photoresist to a suitable source of radiation and then developing to remove the unwanted photoresist. The semiconductor structure 10 then may undergo a reactive ion etching (RIE) process, indicated by arrows 62, to remove the dielectric layer 44 from the dummy RSD structures 42 in the first device region 24 and form second spacer 64 adjacent to first gate structure 14. In an alternative process flow, the process step of removing the hardmask 58 from the dielectric layer 44 in the first device region 24 may be skipped and then after the RIE process described above, the hardmask 58 would become part of the spacer 64 in the first device region 24.
  • The photoresist 60 shown in FIG. 7 may be conventionally stripped such as by an oxygen plasma to result in the structure illustrated in FIG. 8. The dummy RSD structures 42 in the first device region 24 are also removed such as by an HCl etch. The dummy RSD structures 42, being made from SiGe, may be easily and selectively removed by the HCl etch without affecting the underlying SOI layer 22. It is noted that with the removal of the dummy RSD structures 42 from the first device region 24, facets 66 remain in the second spacer 64. The second gate structure 16 and RSD 54 in the second device region 26 are protected by hardmask 58 and so are not affected by the etching of the dummy RSD structures 42 in the first device region 24.
  • Referring now to FIG. 9, an in-situ doped RSD 68 is epitaxially grown in the first device region 24. It should be understood that in-situ doping is optional and the RSD 68 may be doped by other means. The RSD 68 is grown by a non-faceted epitaxial growth process similar to that for RSD 54 so that a planar surface 70 approximately parallel with SOI layer 22 is obtained. While the RSD 68 is grown by a non-faceted epitaxial growth process, the RSD 68 fills the facet 66 in second spacer 64 so that the RSD 68 forms a faceted interface with first gate structure 14 at the corner of the first gate structure 14 and SOI layer 22. In a preferred embodiment, the in-situ doped RSD 68 may be in-situ phosphorus-doped silicon (ISPD Si), in-situ phosphorus-doped and carbon-doped silicon (ISPD Si:C), in-situ arsenic-doped silicon (ISAD Si) or in-situ phosphorus-doped silicon germanium (ISPD SiGe). The approximate doping of the silicon or silicon germanium may be 1×1018 to 1×1022 atoms/cm3 with 1×1020 to 7×1020 atoms/cm3 being more common.
  • The semiconductor structure 10 then may undergo a fast anneal to drive the dopants from the RSD 68 into the SOI layer 22 to form extensions 72 and the dopants from the RSD 54 into the SOI layer 22 to form extensions 74. The resulting structure is illustrated in FIG. 10. In a preferred embodiment, the fast anneal may be a spike anneal in which the semiconductor structure is rapidly heated to a peak temperature of approximately 1000-1100° C. and then immediately cooled after reaching the peak temperature. In addition, the fast anneal may also include rapid thermal anneal (RTA), laser anneal, flash anneal, furnace anneal, or any suitable combination of these techniques. The anneal temperature, depending on the anneal technique, may range from 600 C to 1300 C.
  • It should be understood that the fast anneal may be optional in those cases where it is not necessary to drive in the dopants. For example, if the extension is formed by an implant and laser anneal followed by forming of the RSD, a light anneal may just be necessary to link up the RSD with the extension.
  • If the first and second gate structures 14, 16 cannot tolerate the high temperatures of the fast anneal, then a gate-last process may be needed to replace the first and second gate structures 14, 16 (which would be dummy gate structures) after the fast anneal with the real first and second gate structures 14, 16.
  • The hardmask 58 shown in FIG. 9 may be conventionally removed either before or after the fast anneal. Conventional removal of the hardmask 58 may be by any suitable etch. For example, in the case that the hardmask 58 is silicon oxide, it may be removed by an aqueous solution containing hydrofluoric acid. However, the hardmask 58 should be in place during the formation of the in-situ doped RSD 68.
  • The first and second gate structures 14, 16 may be the real gate structures which would remain in place during further processing. These first and second gate structures 14, 16 may be formed by a gate first process. Alternatively, the first and second gate structures 14, 16 shown, for example, in FIG. 1 may be dummy structures and it may be desirable to replace the dummy first and second gate structures 14, 16 with real first and second gate structures 14, 16 after formation of the epitaxially formed RSDs 54, 68 shown, for example, in FIG. 10 in a gate last process.
  • There are at least two significant advantages to the exemplary embodiments. A first significant advantage is that the RSD that replaces the dummy RSD is grown by a non-faceted epitaxial process and yet a faceted epitaxial RSD is obtained at the corner where the RSD meets the gate structure. Another significant advantage is the first spacer is the same for both the nFET and pFET gate structures so that the replacement RSD is spaced from the channel the same amount for both the nFET and pFET gate structures.
  • While not shown, it should be understood that further processing may take place to form contacts in the first and second device regions 24, 26 as well as back end of the line processing to form the various layers of metallization so as to complete the formation of the nFET and pFET devices in the semiconductor structure 10.
  • It should be understood further that while the process flow illustrated in the Figures results in the first device region 24 being masked off while the second device region 26 is defined, the process flow may be reversed so that the second device region 26 is masked off while the first device region 24 is defined.
  • It will be apparent to those skilled in the art having regard to this disclosure that other modifications of the exemplary embodiments beyond those embodiments specifically described here may be made without departing from the spirit of the invention. Accordingly, such modifications are considered within the scope of the invention as limited solely by the appended claims.

Claims (12)

What is claimed is:
1. A semiconductor article comprising:
a semiconductor substrate;
a plurality of gate structures, each gate structure having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer at a juncture of the gate structure and the semiconductor substrate is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and
a raised source/drain (RSD) for each of the plurality of gate structures such that each RSD is adjacent to one of the gate structure wherein the RSD is an RSD that is formed above a channel of the gate structure, the RSD filling the faceted space and also having a surface parallel to the semiconductor substrate;
wherein at least one gate structure of the plurality of gate structures is for an nFET and at least one gate structure of the plurality of gate structures is for a pFET.
2. The semiconductor article of claim 1 wherein the RSD for each of the plurality of gate structures is an epitaxial layer.
3. The semiconductor article of claim 1 wherein the spacer for each of the plurality of gate structures comprises first and second spacers with the first spacer adjacent to the conducting material of the gate structure and the second spacer is adjacent to the first spacer and the second spacer has the faceted corner.
4. The semiconductor article of claim 1 wherein multiple gate structures of the plurality of gate structures are for an nFET and multiple gate structures of the plurality of gate structures are for a pFET.
5. A semiconductor article comprising:
a semiconductor substrate;
a gate structure having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer at a juncture of the gate structure and the semiconductor substrate is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and
a raised source/drain (RSD) adjacent to the gate structure wherein the RSD is an RSD that is formed above a channel of the gate structure, the RSD filling the faceted space and having a faceted surface wherein the RSD comprises two contiguous portions, the first portion having the faceted surface in the faceted space and a first height with respect to the substrate, the second portion outside the faceted space having a second height with respect to the substrate wherein the first height is less than the second height.
6. The semiconductor article of claim 5 wherein the RSD is an epitaxial layer.
7. The semiconductor article of claim 5 wherein the spacer comprises first and second spacers with the first spacer adjacent to the conducting material of the gate structure and the second spacer is adjacent to the first spacer and the second spacer has the faceted space.
8. The semiconductor article of claim 5 further comprising a plurality of gate structures and a plurality of RSDs such that there is a RSD adjacent to each of the plurality of gate structure and wherein at least one gate structure is for an nFET and at least one gate structure is for a pFET.
9. A semiconductor article comprising:
a semiconductor substrate;
a plurality of gate structures, each gate structure having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer at a juncture of the gate structure and the semiconductor substrate is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and
a raised source/drain (RSD) for each of the plurality of gate structures such that each RSD is adjacent to one of the gate structures wherein the RSD is an RSD that is formed above a channel of the gate structure, the RSD filling the faceted space and having a faceted surface wherein the RSD comprises two contiguous portions, the first portion having the faceted surface in the faceted space and a first height with respect to the substrate, the second portion outside the faceted space having a second height with respect to the substrate wherein the first height is less than the second height;
wherein at least one gate structure of the plurality of gate structures is for an nFET and at least one gate structure of the plurality of gate structures is for a pFET.
10. The semiconductor article of claim 9 wherein the RSD for each of the plurality of gate structures is an epitaxial layer.
11. The semiconductor article of claim 9 wherein the spacer for each of the plurality of gate structures comprises first and second spacers with the first spacer adjacent to the conducting material of the gate structure and the second spacer is adjacent to the first spacer and the second spacer has the faceted corner.
12. The semiconductor article of claim 9 wherein multiple gate structures of the plurality of gate structures are for an nFET and multiple gate structures of the plurality of gate structures are for a pFET.
US14/318,936 2012-01-23 2014-06-30 Epitaxial replacement of a raised source/drain Abandoned US20140312428A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/318,936 US20140312428A1 (en) 2012-01-23 2014-06-30 Epitaxial replacement of a raised source/drain

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/355,691 US8828831B2 (en) 2012-01-23 2012-01-23 Epitaxial replacement of a raised source/drain
US14/318,936 US20140312428A1 (en) 2012-01-23 2014-06-30 Epitaxial replacement of a raised source/drain

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US13/355,691 Division US8828831B2 (en) 2012-01-23 2012-01-23 Epitaxial replacement of a raised source/drain

Publications (1)

Publication Number Publication Date
US20140312428A1 true US20140312428A1 (en) 2014-10-23

Family

ID=48796532

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/355,691 Expired - Fee Related US8828831B2 (en) 2012-01-23 2012-01-23 Epitaxial replacement of a raised source/drain
US14/318,936 Abandoned US20140312428A1 (en) 2012-01-23 2014-06-30 Epitaxial replacement of a raised source/drain

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US13/355,691 Expired - Fee Related US8828831B2 (en) 2012-01-23 2012-01-23 Epitaxial replacement of a raised source/drain

Country Status (1)

Country Link
US (2) US8828831B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9711619B1 (en) * 2016-01-19 2017-07-18 Globalfoundries Inc. Stress memorization and defect suppression techniques for NMOS transistor devices
CN107452684A (en) * 2016-04-26 2017-12-08 格罗方德半导体公司 Strengthen the method for the surface dopant concentration of source/drain regions
US11289484B2 (en) * 2020-01-03 2022-03-29 International Business Machines Corporation Forming source and drain regions for sheet transistors

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8916443B2 (en) * 2012-06-27 2014-12-23 International Business Machines Corporation Semiconductor device with epitaxial source/drain facetting provided at the gate edge
US9029208B2 (en) * 2012-11-30 2015-05-12 International Business Machines Corporation Semiconductor device with replacement metal gate and method for selective deposition of material for replacement metal gate
FR3012258A1 (en) * 2013-10-23 2015-04-24 St Microelectronics Crolles 2 METHOD FOR PRODUCING NMOS AND PMOS TRANSISTORS ON A SOI-TYPE SUBSTRATE, ESPECIALLY FDSOI, AND CORRESPONDING INTEGRATED CIRCUIT
US9269626B2 (en) * 2014-02-06 2016-02-23 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structure and method for manufacturing thereof
US20160247888A1 (en) * 2015-02-19 2016-08-25 International Business Machines Corporation Non-uniform gate dielectric for u-shape mosfet

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08298328A (en) * 1995-04-27 1996-11-12 Hitachi Ltd Semiconductor device and its manufacture
US6335251B2 (en) * 1998-05-29 2002-01-01 Kabushiki Kaisha Toshiba Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor
US20080258218A1 (en) * 2007-04-20 2008-10-23 Renesas Technology Corp. Semiconductor device and method of manufacturing the same

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6127233A (en) 1997-12-05 2000-10-03 Texas Instruments Incorporated Lateral MOSFET having a barrier between the source/drain regions and the channel region
US6187641B1 (en) * 1997-12-05 2001-02-13 Texas Instruments Incorporated Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region
US6946371B2 (en) * 2002-06-10 2005-09-20 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
US6906360B2 (en) * 2003-09-10 2005-06-14 International Business Machines Corporation Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions
US6991991B2 (en) * 2003-11-12 2006-01-31 United Microelectronics Corp. Method for preventing to form a spacer undercut in SEG pre-clean process
CN100536089C (en) * 2003-12-30 2009-09-02 中芯国际集成电路制造(上海)有限公司 Method and apparatus for quickly cooling and annealing of wafer
JPWO2007077748A1 (en) * 2005-12-27 2009-06-11 日本電気株式会社 Semiconductor device and manufacturing method of semiconductor device
US8008157B2 (en) * 2006-10-27 2011-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS device with raised source and drain regions
US7943469B2 (en) * 2006-11-28 2011-05-17 Intel Corporation Multi-component strain-inducing semiconductor regions
US7883976B2 (en) * 2007-12-13 2011-02-08 International Business Machines Corporation Structure and method for manufacturing device with planar halo profile
US8084309B2 (en) 2009-08-17 2011-12-27 International Business Machines Corporation Extremely thin silicon on insulator (ETSOI) complementary metal oxide semiconductor (CMOS) with in-situ doped source and drain regions formed by a single mask
US8022488B2 (en) 2009-09-24 2011-09-20 International Business Machines Corporation High-performance FETs with embedded stressors
US8288218B2 (en) 2010-01-19 2012-10-16 International Business Machines Corporation Device structure, layout and fabrication method for uniaxially strained transistors
US8338260B2 (en) 2010-04-14 2012-12-25 International Business Machines Corporation Raised source/drain structure for enhanced strain coupling from stress liner

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08298328A (en) * 1995-04-27 1996-11-12 Hitachi Ltd Semiconductor device and its manufacture
US6335251B2 (en) * 1998-05-29 2002-01-01 Kabushiki Kaisha Toshiba Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor
US20080258218A1 (en) * 2007-04-20 2008-10-23 Renesas Technology Corp. Semiconductor device and method of manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9711619B1 (en) * 2016-01-19 2017-07-18 Globalfoundries Inc. Stress memorization and defect suppression techniques for NMOS transistor devices
US9905673B2 (en) 2016-01-19 2018-02-27 Globalfoundries Inc. Stress memorization and defect suppression techniques for NMOS transistor devices
CN107452684A (en) * 2016-04-26 2017-12-08 格罗方德半导体公司 Strengthen the method for the surface dopant concentration of source/drain regions
US11289484B2 (en) * 2020-01-03 2022-03-29 International Business Machines Corporation Forming source and drain regions for sheet transistors

Also Published As

Publication number Publication date
US8828831B2 (en) 2014-09-09
US20130187205A1 (en) 2013-07-25

Similar Documents

Publication Publication Date Title
US9502530B2 (en) Method of manufacturing semiconductor devices
US8828831B2 (en) Epitaxial replacement of a raised source/drain
US9842930B2 (en) Semiconductor device and fabrication method thereof
US9576960B2 (en) Structure for finFET CMOS
US9728641B2 (en) Semiconductor device and fabrication method thereof
US9659823B2 (en) Highly scaled tunnel FET with tight pitch and method to fabricate same
US7435657B2 (en) Method of fabricating transistor including buried insulating layer and transistor fabricated using the same
US10312155B2 (en) FinFET device and fabrication method thereof
US9385231B2 (en) Device structure with increased contact area and reduced gate capacitance
US9799750B2 (en) Semiconductor device and fabrication method thereof
US9496395B2 (en) Semiconductor device having a strain feature in a gate spacer and methods of manufacture thereof
US20210273102A1 (en) Semiconductor device and method of manufacture
US9331159B1 (en) Fabricating transistor(s) with raised active regions having angled upper surfaces
US9306033B2 (en) Semiconductor device and fabrication method thereof
KR20160005858A (en) Field effect transistor and methods for manufacturing the same
WO2014159391A1 (en) Dielectric void etched in finfet sacrificial layer
US11901235B2 (en) Ion implantation for nano-FET
CN104332399A (en) Semiconductor device manufacturing method
CN110010468B (en) Semiconductor device and method of forming the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ADAM, THOMAS N.;CHENG, KANGGUO;KHAKIFIROOZ, ALI;AND OTHERS;SIGNING DATES FROM 20140619 TO 20140627;REEL/FRAME:033209/0025

AS Assignment

Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001

Effective date: 20150629

AS Assignment

Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001

Effective date: 20150910

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION