US20140103498A1

US20140103498A1 - Selective wet etching of hafnium aluminum oxide films

Info

Publication number: US20140103498A1
Application number: US14/136,081
Authority: US
Inventors: Prashant Raghu; Yi Yang
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2007-08-16
Filing date: 2013-12-20
Publication date: 2014-04-17
Also published as: US8618000B2; US8283258B2; US20090047790A1; US20120306059A1

Abstract

Methods and etchant compositions for wet etching to selectively remove a hafnium aluminum oxide (HfAlO_x) material relative to silicon oxide (SiO_x) are provided.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No. 13/585,072, filed Aug. 14, 2012, pending, which application is a continuation of U.S. patent application Ser. No. 11/839,628, filed Aug. 16, 2007, now U.S. Pat. No. 8,283,258, issued Oct. 9, 2012, the disclosure of each of which is hereby incorporated herein in its entirety by this reference.

TECHNICAL FIELD

Embodiments of the invention relate to etchant chemistries and methods of processing a substrate and semiconductor constructions.

BACKGROUND

Conventionally, in a manufacturing process for a semiconductor device, openings such as contact holes are formed in dielectric layers by plasma etching using a patterned photoresist layer as a mask. However, as device sizes decrease, the size of features such as contact holes is reduced, requiring the replacement of conventionally used resist masks.
A hard mask formed of amorphous or transparent carbon has been used for dry etching of silicon oxide films, which offers high etch selectivity relative to a photoresist or other hard mask materials. However, the use of amorphous carbon as a mask is inapplicable for some processes when plasma etching silicon oxide, in part, because a sufficient selectivity of the silicon oxide film against the amorphous carbon mask cannot be obtained. In addition, etching features in silicon oxide that are 25 nm or less often requires the use of a very thick carbon film, which is generally not extendable for 25 nm patterning due to toppling of the mask structures, making a conventional amorphous carbon mask unsuitable.
It would be useful to provide processes that overcome these or related problems.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention are described below with reference to the following accompanying drawings, which are for illustrative purposes only. Throughout the following views, the reference numerals will be used in the drawings, and the same reference numerals will be used throughout the several views and in the description to indicate same or like parts.

FIG. 1 illustrates a diagrammatic, cross-sectional view of a portion of a substrate at a preliminary processing stage according to an embodiment of the present disclosure.

FIGS. 2-6 are cross-sectional views of the substrate depicted in FIG. 1 at subsequent processing stages.

DETAILED DESCRIPTION

The following description with reference to the drawings provides illustrative examples of devices and methods according to embodiments of the invention. Such description is for illustrative purposes only and not for purposes of limiting the same.
In the context of the current application, the term “semiconductor substrate” or “semiconductive substrate” or “semiconductive wafer fragment” or “wafer fragment” or “wafer” will be understood to mean any construction comprising semiconductor material, including but not limited to bulk semiconductive materials such as a semiconductor wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The “substrate” refers to any supporting structure including, but not limited to, the semiconductive substrates, wafer fragments or wafers described above.
Embodiments of the invention relate to the use of hafnium aluminum oxide (HfAlO_x) as a hard mask in etching silicon oxide, and solutions that provide etchant chemistry for selective removal of HfAlO_xmaterial from a structure relative to exposed doped and undoped silicon oxide materials including, but not limited to, silicon oxide deposited from tetraethylorthosilicate (TEOS), spin-on-glass (SOG), undoped SiO₂, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and borosilicate glass (BSG). By “selectively” etching or removal of the HfAlO_xmaterial, it is meant that the etch is preferential to the HfAlO_xmaterial relative to adjacent or exposed silicon oxide with little or no etching of the silicon oxide, and that the HfAlO_xmaterial is etched at a rate greater than the silicon oxide. The compositions of the invention have increased selectivity to HfAlO_xmaterial in the presence of silicon oxide materials compared to conventional wet chemistries commonly used for removing HfAlO_xmaterial. The etchant solution can be used in applications for fabricating contact openings, word lines, digit lines, among other features and structures.
An embodiment of a method according to the invention is illustrated with reference to FIGS. 1-6. FIG. 1 illustrates a substrate fragment indicated generally with reference to numeral 10 at a preliminary processing stage. The substrate fragment 10 in progress can comprise a semiconductor wafer substrate or the wafer along with various process layers formed thereon, including one or more semiconductor layers or other formations, and active or operable portions of semiconductor devices.
The substrate fragment 10 comprises a substrate 12, a dielectric (silicon oxide) layer 14 to be etched, a hafnium aluminum oxide (HfAlO_x) layer 16, a dielectric antireflective coating (DARC) layer 18, and a photoresist masking layer 20.
The substrate 12 is compositionally dissimilar to the silicon oxide layer 14, and can be composed of a silicon layer such as monocrystalline, polycrystalline or amorphous silicon, a doped silicon region, a nitride material (e.g., silicon nitride such as Si₃N₄, a refractory metal nitride such as titanium nitride (TiN), tungsten nitride (WN), etc.), a silicon oxide layer with different doping than a silicon oxide dielectric layer 14, a metal silicide such as titanium silicide (TiSi₂), a metal interconnect, or other material layer.
The dielectric layer 14 can be formed of undoped or doped silicon oxide (SiO_x), for example, silicon oxide deposited from tetraethylorthosilicate (TEOS), borophosphosilicate glass (BPSG), borosilicate glass (BSG), phosphosilicate glass (PSG), spin-on-glass (SOG), etc., in a single layer or multiple layers. In various embodiments, the dielectric (SiO_x) layer 14 will comprise, consist essentially of, or consist of silicon and oxygen. A typical thickness of the dielectric layer 14 is about 1,000-20,000 Å.
A hafnium aluminum oxide layer 16 (Hf_xAl_yO_zor HfAlO_xsuch as HfAlO₃), a high dielectric constant (high-k) material, replaces a conventional hard mask such as a carbon-based hard mask that is generally formed over a material to be etched. In embodiments of the invention, the HfAlO_xlayer 16 is formed as a hard mask over the dielectric (SiO_x) layer 14 by atomic layer deposition (ALD) processing with a concentration ratio of Hf:Al in the film at about 20:1 to about 4:1 (wt-%), or about 10:1 to about 8:1 (ALD deposition temperature of about 300° C.). The thickness of the HfAlO_x hard mask layer 16 is generally about 200-1,000 Å, or about 300-500 Å.
The HfAlO_x hard mask layer 16 can be formed by ALD processing using known techniques in the art, for example, as described in U.S. Pat. No. 7,211,492 (Forbes et al.) and U.S. Pat. No. 7,135,421 (Ahn et al.), which are commonly assigned to Micron Technology, Inc., the disclosures of which are incorporated by reference herein. Briefly, the HfAlO_x hard mask layer 16 can be farmed using ALD processing by employing a hafnium sequence of pulsing a hafnium-containing precursor (e.g., HfCl₄) into a reaction chamber containing a substrate and pulsing a first oxygen-containing precursor (e.g., water vapor) into the reaction chamber as an oxidizing reactant to form hafnium oxide, and an aluminum sequence by pulsing an aluminum-containing precursor (e.g., trimethylaluminum, Al(CH₃)₃, or DMEAA, an adduct of alane (AlH₃) and dimethylethylamine (N(CH₃)₂(C₂H₅)), into the reaction chamber and pulsing a second oxygen containing precursor (e.g., distilled water vapor) into the reaction chamber as an oxidizing reactant to form a HfAlO_xfilm. Each precursor is pulsed into the reaction chamber for a selected time period (pulse time), typically from about 0.5 seconds to about 2-3 seconds. Between each precursor pulsing, the reaction chamber is purged with an inert gas (e.g., nitrogen or argon) or evacuated to remove precursor excess and reaction by-products. The thickness of the HfAlO_xfilm is controlled by repeating for a number of cycles the pulsing of the Hf-containing precursor, the first 0-containing precursor, the Al-containing precursor, and the second 0-containing precursor until the desired thickness is formed. In addition, the HfAlO_x hard mask layer 16 can be engineered with selected characteristics by controlling precursor materials for each sequence, processing temperatures and pressures for each sequence, individual precursor pulsing times, and heat treatment at the end of the process, at the end of each cycle, and at the end of each sequence.
A dielectric antireflective coating layer (DARC) 18 overlies the HfAlO_x hard mask layer 16 and is generally a silicon oxynitride (Si_xO_yN_z, e.g., where x=10-60, y=20-50, z=10-20, for example, Si₅₀O₃₇N₁₃). The DARC layer 18 can serve as an intermediate hard mask to reduce light reflections during lithography. The DARC layer 18 can be deposited onto the HfAlO_x hard mask layer 16 by known processes, such as chemical vapor deposition (CVD) or plasma enhanced CVD (PECVD) including, for example, electron cyclotron resonance (ECR) PECVD, and bias ECR PECVD processes, for example, using a feed gas that comprises SiH₄, N₂, O₂, and argon. A typical thickness of the DARC layer 18 is about 200-1,000 Å, or about 300-400 Å.
A photoresist mask layer 20, typically an organic polymeric material (e.g., a novolac resin), is formed over the DARC layer 18 and, as depicted, exposed and developed using conventional photolithographic techniques as known in the art, to provide a desired pattern with openings 22 that expose portions of the DARC layer 18.
The pattern in the photoresist mask layer 20 can be transferred to the DARC layer 18 by a standard dry etch (arrows ↓↓↓) using, for example, a fluorine-based gas plasma chemistry to expose the underlying HfAlO_x hard mask layer 16, as shown in FIG. 2.
Then, as illustrated in FIG. 3, the HfAlO_x hard mask layer 16 can be dry etched (arrows ↓↓↓) using a standard chemistry to expose portions of the silicon oxide layer 14. An etchant gas is used, for example, a mixture of boron trichloride (BCl₃) and chlorine (Cl₂) gases, which provides good selectivity to etch HfAlO_xand stop on TEOS or other silicon oxide material (e.g., substrate 12).
Referring now to FIG. 4, the dielectric (SiO_x) layer 14 is then dry etched to form a contact opening 24 (i.e., contact hole, via, or other opening such as a trench) extending to the underlying substrate layer 12 for forming, for example, a contact hole for an interconnect level, a gate electrode, a capacitor electrode, a via, etc. A silicon oxide dry etch can be conducted according to known methods using a standard fluorocarbon-based dry etch chemistry (e.g., CF₄, CHF₃, CH₂F₂, CH₃F, C₂F₆, C₃F₈, C₄F₆, etc.). Typically, the contact opening 24 is etched to a high aspect ratio of about 1:1 to about 20:1 with a width of about 15-65 nm and a depth of about 100 nm-2,000 nm, for example.
After the etch of the contact opening 24 is completed, the photoresist mask layer 20 is selectively removed (dry stripped) as shown in FIG. 5, for example, by a standard dry etch process using an oxygen (O₂) plasma ashing step.
Then, in accordance with the invention, the DARC layer 18 and the HfAlO_x hard mask layer 16 are removed (stripped) selective to the dielectric (SiO_x) layer 14 and the substrate 12, as illustrated in FIG. 6.
Conventional processes for removing HfAlO_x(and DARC) materials typically use hydrofluoric acid (HF) based chemistries, e.g., a dilute HF/water wet etch. However, standard dilute HF etch chemistries are not selective to and will attack and rapidly etch silicon oxides such as BPSG, PSG and TEOS. This necessitates the use of different etch chemistries for stripping HfAlO_xmaterials in the presence of oxides.
The etchant compositions of the invention are aqueous solutions of phosphoric acid (H₃PO₄) and water (H₂O) that etch HfAlO_xmaterial selective to silicon oxide (e.g., BPSG, PSG, TEOS, etc.). Embodiments of the etchant compositions are formulated with a H₃PO₄:H₂O volume ratio of about 50:50 to about 90:10, or about 80:20 to about 85:15, based on the total volume of the solution. A temperature range of about 100-185° C. is typical for most applications. The H₃PO₄:H₂O etchant compositions are maintained at a pH level <2, which can be manipulated by adding an additional acid such HCl, H₂SO₄, HNO₃, HCOOH and CH₃COOH, among others. In some embodiments, the etchant composition consists essentially of or consists of phosphoric acid and water, optionally with an additional acid in a minor but effective amount to modify the pH of the solution.
The H₃PO₄/H₂O etchant solution can be applied to the material layers, e.g., the HfAlO_xlayer 16 and DARC layer 18, to be stripped in various ways. For example, the etchant solution can be sprayed onto the substrate 10, or the substrate can be dipped or immersed into a bath of the etchant solution (e.g., a megasonic bath), or the etchant solution can be flowed over the substrate, among other applications.
The H₃PO₄/H₂O etchant compositions provide a wet etch of HfAlO_x(about 10:1 Hf:Al ratio) and DARC materials selective to the SiO_xmaterial layer 14 at an etch rate (or selectivity) of greater than 1, or an etch selectivity of about 2:1 to about 20:1 (HfAlO_x:SiO_x), with little or no etching of the SiO_xlayer. Etchant compositions having a H₃PO₄:H₂O volume ratio of about 50:50 to about 90:10 (temperature of about 100-185° C.) provide an etch of ALD HfAlO_x(Hf:Al ratio of about 20:1 to about 4:1) at a rate about 50-400 Å/minute, an etch of a DARC material layer 18 at a rate of about 5-40 Å/minute or about 20-40 Å/minute, and minimal etching of a SiO_xmaterial layer 14 at about 5-40 Å/minute or about 5-15 Å/minute. For example, the application of an etchant solution of H₃PO₄:H₂O at a ratio of about 80:20 to about 85:15 (v/v) (temperature of about 100-185° C.) will etch ALD HfAlOx (about 10:1 Hf:Al ratio) at an etch selectivity of about 8:1 to about 12:1. The application of an about 10:1 (v/v) H₃PO₄:H₂O etchant solution at about 145° C. will provide an etch of an ALD HfAlO_xfilm 16 (about 10:1 Hf:Al ratio) at a rate of about 300 Å/minute.
Materials such as PSG, TiN, Si_xN_y, etc., can be exposed as the substrate layer 12 or at different levels in a material stack during the wet etch of the HfAlO_xmaterial layer 16. The H₃PO₄:H₂O etchant compositions have a selectivity (or etch rate) to PSG of about 10:1 (HfAlO_x:PSG), a selectivity to titanium nitride (TiN) of about 43:1 (HfAlO_x:TiN), and a selectivity to silicon nitride (Si_xN_y, e.g., such as Si₃N₄) of about 6:1 (HfAlO_x: Si_xN_y).
The etchant solution can be used in applications for fabricating contact openings as illustrated, or other features such as word lines, digit lines, etc. The substrate 10 can then undergo post-etch processing steps that are known in the art to fabricate desired components. For example, the resulting contact openings 24 can be further processed, for example, by filling with a metal or conductive material such as copper, aluminum, silicon, Ti₃N₄, among others, to form contacts or conductive lines, for example, to an underlying active area, contact, or conductive line, or with a metal-insulator-metal-stack to form capacitors with a dielectric material such as Al₂O₃, HfO₂, ZrO₂, SrTiO₃, and the like, in the fabrication of integrated circuit devices such as memory devices. Finished semiconductor wafers can be cut into dies, which may then be further processed into integrated circuit chips and incorporated in electronic devices.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover any adaptations or variations that operate according to the principles of the invention as described. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof. The disclosures of patents, references and publications cited in the application are incorporated by reference herein.

Claims

1. A semiconductor device structure, comprising:

a dielectric material on a substrate;

a hafnium aluminum oxide material overlying and in contact with the dielectric material; and

a dielectric antireflective coating material overlying and in contact with the hafnium aluminum oxide material,

wherein the dielectric material, hafnium aluminum oxide material, and dielectric antireflective coating material comprises a plurality of openings therein, each of the plurality of openings comprising an aspect ratio of from about 1:1 to about 20:1.

2. The semiconductor structure of claim 1, wherein the dielectric material has a thickness of from about 1,000 Å to 20,000 Å.

3. The semiconductor structure of claim 1, wherein the hafnium aluminum oxide material has a thickness of from about 200 Å to 1,000 Å.

4. The semiconductor structure of claim 1, wherein the dielectric antireflective coating material has a thickness of from about 200 Å to about 1,000 Å.

5. The semiconductor structure of claim 1, further comprising a conductive material in the plurality of openings.

6. The semiconductor structure of claim 1, wherein the dielectric material comprises silicon oxide material.

7. The semiconductor structure of claim 1, further comprising a metal-insulator-metal-stack in the plurality of openings.

8. A semiconductor structure, comprising:

a silicon oxide material on a substrate;

a hafnium aluminum oxide material over the silicon oxide material;

a dielectric antireflective coating material over the hafnium aluminum oxide material; and

at least one opening extending through the silicon oxide material, hafnium aluminum oxide material, and dielectric antireflective coating material.

9. The semiconductor structure of claim 8, wherein the hafnium aluminum oxide material has a Hf:Al ratio of about 20:1 to about 4:1.

10. The semiconductor structure of claim 8, wherein the silicon oxide material comprises an oxide selected from the group consisting of tetraethylorthosilicate, spin-on-glass, undoped silicon dioxide, phosphosilicate glass, borophosphosilicate glass, and borosilicate glass.

11. The semiconductor structure of claim 8, wherein the dielectric antireflective coating material comprises a silicon oxynitride of chemical formula Si_xO_yN_z, wherein x is from 10 to 60, y is from 20 to 50, and z is from 10 to 20.

12. A semiconductor structure, comprising:

a dielectric material on a substrate;

a hafnium aluminum oxide material over the dielectric material; and

at least one opening extending through the dielectric material and hafnium aluminum oxide material.

13. The semiconductor structure of claim 12, wherein the at least one opening comprises an aspect ratio of from about 1:1 to about 20:1.

14. The semiconductor structure of claim 12, wherein the at least one opening has a width of from about 15 nm to 65 nm and a depth of from about 100 nm to 2,000 nm.

15. The semiconductor structure of claim 12, further comprising an antireflective coating material over the hafnium aluminum oxide material, wherein the at least one opening extends through the dielectric material, hafnium aluminum oxide material, and dielectric antireflective coating material.

16. The semiconductor structure of claim 12, wherein the dielectric material is a silicon oxide material consisting essentially of silicon and oxygen.

17. The semiconductor structure of claim 12, wherein the dielectric antireflective coating material comprises a silicon oxynitride material.