US20130277767A1 - Etch stop layer formation in metal gate process - Google Patents
Etch stop layer formation in metal gate process Download PDFInfo
- Publication number
- US20130277767A1 US20130277767A1 US13/780,957 US201313780957A US2013277767A1 US 20130277767 A1 US20130277767 A1 US 20130277767A1 US 201313780957 A US201313780957 A US 201313780957A US 2013277767 A1 US2013277767 A1 US 2013277767A1
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- United States
- Prior art keywords
- gate
- semiconductor device
- metal
- gate dielectric
- dielectric cap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Definitions
- the present disclosure relates generally to semiconductor integrated circuits. More particularly, the present disclosure relates to scaling of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs).
- MOSFETs metal oxide semiconductor field effect transistors
- FETs field effect transistors
- CMOS complementary metal oxide semiconductors
- a semiconductor device is formed by a method that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate, wherein the metal gate conductor is comprised of a catalytic metal.
- a gate dielectric cap comprising at least silicon and oxygen is formed on the metal gate conductor.
- the gate dielectric cap is catalyzed by the catalytic metal so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor.
- Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.
- a semiconductor device in another aspect, includes a gate structure on a channel portion of a semiconductor substrate.
- the gate structure includes at least one gate dielectric in contact with the channel portion of the semiconductor substrate and a gate conductor comprised of a catalytic metal.
- the at least one gate dielectric has a U-shaped geometry.
- a gate dielectric cap is present on the gate conductor, wherein the gate dielectric cap has edges that are substantially self-aligned to sidewalls of the gate conductor.
- the gate dielectric cap comprises at least silicon and oxygen and has a self-limited thickness of less than 20 nm.
- a source region and a drain region are present on opposing sides of the gate structure.
- a contact is present to each of the source region and the drain region. The contact is separated from the gate conductor by at least the gate conductor.
- FIG. 1 is a side cross-sectional view depicting one embodiment of an initial structure of the disclosed method including a replacement gate structure on a semiconductor substrate, a source region and a drain region present in the semiconductor substrate on opposing sides of the sacrificial gate structure, and a spacer adjacent to the sacrificial gate structure, in accordance with the present disclosure.
- FIG. 2 is a side cross-sectional view depicting one embodiment of removing the replacement gate structure to provide an opening to a channel portion of the semiconductor substrate, and forming a functional gate structure in the opening, wherein the functional gate structure includes at least one gate dielectric and at least one gate conductor.
- FIG. 3 is a side cross-sectional view depicting one embodiment of forming a gate dielectric cap on the metal gate conductor, wherein the gate dielectric cap is a silicon oxide, or doped silicon oxide, with dopants being carbon, nitrogen, hydrogen or combined mixtures that is catalyzed by a metal element from the catalytic metal so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor.
- the gate dielectric cap is a silicon oxide, or doped silicon oxide, with dopants being carbon, nitrogen, hydrogen or combined mixtures that is catalyzed by a metal element from the catalytic metal so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor.
- FIG. 4 is a side cross-sectional view depicting one embodiment of forming a contact to the source and drain regions of the semiconductor device.
- the present disclosure provides a process sequence for manufacturing a semiconductor device that forms a dielectric gate cap atop a metal gate conductor composed of a catalytic metal, in which the catalytic metal functions as a catalyst to selective deposition of the dielectric material of the dielectric gate cap on only the metal gate conductor in a self-aligned manner.
- self-aligned it is meant that the deposited material of the dielectric gate cap is deposited continuously atop the entire upper surface of the metal gate conductor, wherein the edges of the dielectric gate cap are aligned to the sidewalls of the metal gate conductor.
- the catalytic metal that dictates the self-aligned characteristics of the dielectric gate cap also provides that the dielectric gate cap has a self-limiting thickness.
- FIG. 1 illustrates the results of initial processing steps of the present disclosure that produce a replacement gate structure 10 on a semiconductor substrate 5 including a source region 20 and a drain region 25 present in the semiconductor substrate 5 on opposing sides of the replacement gate structure 10 , at least one dielectric spacer 15 adjacent to the replacement gate structure 10 , and an interlevel dielectric layer 30 adjoining the replacement gate structure 10 and located on the exposed surface of the semiconductor substrate 5 .
- the semiconductor substrate 5 may be composed of a silicon containing material. Silicon containing materials include, but are not limited to, Si, single crystal Si, polycrystalline Si, SiGe, single crystal silicon germanium, polycrystalline silicon germanium, or silicon doped with carbon, amorphous Si and combinations and multi-layers thereof.
- the semiconductor substrate 5 may also be composed of other semiconductor materials, such as germanium, and compound semiconductor substrates, such as type III/V semiconductor substrates, e.g., GaAs. Although the semiconductor substrate 5 is depicted as a bulk semiconductor substrate, semiconductor on insulator (SOI) substrate arrangements, such as silicon on insulator substrates, are also suitable for the semiconductor substrate 5 .
- SOI semiconductor on insulator
- the replacement gate structure 10 is formed on the channel portion of the semiconductor substrate 5 .
- the term “replacement gate structure 10 ” denotes a sacrificial structure that dictates the geometry and location of the later formed functioning gate structure.
- the functional gate structure controls output current, i.e., flow of carriers in the channel region of the semiconductor device.
- the channel region is the region between the source region and the drain region of the semiconductor device that becomes conductive when the transistor is turned on.
- the sacrificial material that provides the replacement gate structure 10 may be composed of any material that can be etched selectively to the bottom dielectric films or semiconductor substrate 5 .
- the sacrificial material that provides the replacement gate structure 10 may be composed of a silicon-containing material, such as polysilicon.
- the replacement gate structure 10 is typically composed of a semiconductor material, the replacement gate structure 10 may also be composed of doped Si layers with Ge, or a dielectric material, such as amorphous carbon.
- the sacrificial material may be patterned and etched to provide the replacement gate structure 10 . Specifically, and in one example, a pattern is produced by applying a photoresist to the surface to be etched, exposing the photoresist to a pattern of radiation, and then developing the pattern into the photoresist utilizing a resist developer.
- the sections of the sacrificial material covered by the photoresist are protected to provide the replacement gate structure 10 , while the exposed regions are removed using a selective etching process that removes the unprotected regions.
- the photoresist may be removed.
- At least one dielectric gate spacer 15 may then be formed adjacent to the replacement gate structure 10 , i.e., in direct contact with the sidewall of the replacement gate structure 10 .
- the at last one dielectric gate spacer 15 may be formed by using a blanket layer deposition, such as chemical vapor deposition, and an anisotropic etchback method.
- the at least one dielectric gate spacer 15 may have a width ranging from 2.0 nm to 15.0 nm, and may be composed of a dielectric, such as a nitride, oxide, oxynitride, or a combination thereof.
- the dielectric gate spacer 15 is optional, and may be omitted.
- a source region 20 and a drain region 25 may then be formed in the portions of the semiconductor substrate 5 that are present on opposing sides of replacement gate structure 10 .
- the source region 20 and the drain region 25 are formed using an ion implantation process.
- the conductivity type, e.g., n-type or p-type, of the source region 20 and the drain region 25 typically dictates the conductivity type of the semiconductor device, e.g., nFET or pFET.
- examples of p-type dopants include but are not limited to, boron, aluminum, gallium and indium
- examples of n-type dopants, i.e., impurities include but are not limited to antimony, arsenic and phosphorous.
- a first interlevel dielectric layer 30 is formed atop the source region 20 and the drain region 25 , wherein the upper surface of the interlevel dielectric layer 30 is coplanar with an upper surface of the replacement gate structure 10 .
- the composition of the first interlevel dielectric layer 30 may be selected from the group consisting of silicon-containing materials such as SiO 2 , Si 3 N 4 , SiO x N y , SiC, SiCO, SiCOH, SiCBN and SiCH compounds, the above-mentioned silicon-containing materials with some or all of the Si replaced by Ge, carbon-doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLKTM, other carbon-containing materials, organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials, and diamond-like carbon (DLC, also known as amorphous hydrogenated carbon, ⁇ -C:H).
- silicon-containing materials such as SiO 2 , Si 3 N 4 , SiO x N y , SiC, SiCO, SiCOH, SiCBN and SiCH compounds
- the above-mentioned silicon-containing materials with some or all of the Si replaced by Ge carbon-do
- the first interlevel dielectric layer 30 may be formed using a deposition method such as chemical vapor deposition (CVD) or spin on deposition. Following deposition the first interlevel dielectric layer 30 may be planarized, e.g., planarized by chemical mechanical planarization (CMP), so that an upper surface of the first interlevel dielectric layer 30 is coplanar with an upper surface of the replacement gate structure 10 .
- CVD chemical vapor deposition
- CMP chemical mechanical planarization
- FIG. 2 depicts one embodiment of removing the replacement gate structure 10 to provide an opening to a channel portion of the semiconductor substrate 5 , and forming a functional gate structure 45 in the opening.
- the etch process for removing the replacement gate structure 10 may be a selective etch.
- the term “selective” in reference to a material removal process denotes that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied.
- a selective etch may include an etch chemistry that removes a first material selectively to a second material by a ratio of 2:1 or greater, such as 5:1.
- the replacement gate structure 10 may be removed using a wet or dry etch process, such as reactive ion etch (RIE), or combination of these techniques thereof.
- RIE reactive ion etch
- an etch step for removing the replacement gate structure 10 can include an etch chemistry for removing the replacement gate structure 10 selective to the substrate dielectrics or semiconductor substrate 5 .
- the functional gate structure 45 includes at least one gate dielectric 46 and at least one gate conductor 47 .
- the at least one gate dielectric 46 may be composed of any dielectric material including oxides, nitrides and oxynitrides.
- the at least one gate dielectric 46 may be provided by a high-k dielectric material.
- the term “high-k” as used to describe the material of the at least one gate dielectric 46 denotes a dielectric material having a dielectric constant greater than silicon oxide (SiO 2 ) at room temperature (20° C. to 25° C.) and atmospheric pressure (1 atm).
- a high-k dielectric material may have a dielectric constant greater than 4.0.
- the dielectric constant of the high-k dielectric material may be greater than 10.0.
- the at least one gate dielectric 46 is composed of a high-k oxide such as, for example, HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , Y 2 O 3 and mixtures thereof.
- the at least one gate dielectric 46 may be deposited by chemical vapor deposition (CVD), such as plasma enhanced CVD (PECVD). In one embodiment, the at least one gate dielectric 46 may be deposited using a conformal deposition method.
- CVD chemical vapor deposition
- PECVD plasma enhanced CVD
- the at least one gate dielectric 46 may be deposited using a conformal deposition method.
- conformal denotes a layer having a thickness that does not deviate from greater than or less than 20% of an average value for the thickness of the layer. In one embodiment, the thickness of the at least one gate dielectric 46 ranges from 0.8 nm to 6.0 nm.
- the side cross-section of at least one gate dielectric 46 has a U-shaped geometry, as depicted in FIG.
- a portion of the at least one gate dielectric 46 extends along an entire height of the interior sidewalls of the dielectric spacer 15 and a portion of the at least one gate dielectric 46 is present on the surface of the semiconductor substrate 5 that includes the device channel.
- the at least one metal gate conductor 47 is formed on the at least one gate dielectric 46 .
- the at least one metal gate conductor 47 is composed of a catalytic metal.
- a “catalytic metal” is a metal that provides for a polymerization reaction with the precursor of the atomic layer deposition (ALD) half reaction for forming the gate dielectric cap that is self-aligned to the metal gate conductor.
- the catalytic metal is a Lewis-acid type metal.
- a “Lewis-acid type metal” is a metal ion that functions as an electron pair acceptor in the formation of a stable substance.
- catalytic metals examples include aluminum (Al), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), tungsten (W) and a combination thereof.
- the at least one metal gate conductor 47 may be formed by a deposition process, such as CVD, plasma-assisted CVD, plating, and/or sputtering, followed by planarization. More specifically, in one embodiment, the at least one metal gate conductor 47 may be deposited filling the opening produced by removing the replacement gate structure 10 .
- FIG. 3 depicts one embodiment of forming a gate dielectric cap 50 on the at least one metal gate conductor 47 , wherein the gate dielectric cap 50 is a silicon and oxygen containing dielectric that is catalyzed by the catalytic metal of the gate conductor 471 so that edges E 1 of the gate dielectric cap 50 are substantially aligned with a sidewall of the at least one metal gate conductor 47 .
- substantially aligned it is mean that the sidewall of edge E 1 of the gate dielectric cap 50 may extend from the sidewall of the at least one metal gate conductor 47 by a dimension of 20 nm or less.
- the catalytic effect provided by the catalytic metal means that there is substantially no deposition of the material for the gate dielectric cap 50 grown on the first interlevel dielectric layer 30 and the semiconductor substrate.
- the material for the gate dielectric cap 50 is only deposited on the upper surface of the at least one metal gate conductor 47 of the catalytic metal. More specifically, in some embodiments, the ALD half reaction deposition process, which will be described in more detail below, provides for a self limiting thickness of 20 nm or less.
- the maximum amount of lateral growth of the gate dielectric cap 50 can be 20 nm, which allows for some overlap of the dielectric spacers 15 or lateral extension to first interlevel dielectric layer 30 .
- the material of the gate dielectric cap 50 is not grown on an exterior surface of the first interlevel dielectric layer 30 .
- the gate dielectric cap 50 may provide an etch stop layer to protect the at least one metal gate conductor 47 during subsequent etch steps to form vias to the source region 20 and drain region 25 , for the subsequently formed contacts; i.e., interconnects.
- the gate dielectric cap 50 may be formed using an atomic layer deposition (ALD) half reaction.
- Atomic Layer Deposition (ALD) uses self-limiting surface reactions to deposit material layers in the monolayer or sub-monolayer thickness regime.
- ALD is similar in chemistry to chemical vapor deposition (CVD), except that the ALD reaction breaks the CVD reaction into two half-reactions, keeping the precursor materials separate during the reaction.
- the atomic layer depsoition (ALD) process of the present disclosure uses only half reactions to deposit the gate dielectric cap 50 .
- the precusor of the atomic layer deposition process may be a silicon containing precursor.
- the percursor may have the following chemical formulation:
- the precursor in one embodiment, in which R in the above chemical formula is equal to an alkyloxy group, the precursor may be tris (tert-butyloxyl) silanol. In another embodiment, in which R in the above chemical formula is a butyl group, such as tert-butyl, the precursor may be at least one of bis(tert-butyloxyl) alkyl silanol, and mono-tert-butyloxyl alkyl silanol. Other butyl groups that are suitable for R in the above chemical formula include n-butyl, iso-butyl, and sec-butyl.
- the R group in the above chemical formula for the precursor of the ALD half reaction may be any group having a carbon chain.
- the R group in the above chemical formula may be an alkyl group, such as methyl group, ethyl group, propyl group, n-propyl group, isopropyl group, pentyl group, hexyl group, octyl group and combinations thereof.
- the deposited gate dielectric cap 50 is composed of silicon oxide (SiO 2 ). In another example, in which the silicon precursor of the ALD half reaction process is bis(tert-butyloxyl) alkyl silanol, the deposited gate dielectric cap 50 is silicon-oxycarbide (SiCO). In another example, in which the silicon precursor of the ALD half reaction process is bis-tert-butyloxyl-aminoalkyl silanol, the gate dielectric cap 50 comprises silicon carbon nitro-oxide (SiCNO).
- the ALD half reaction using one of the above described precursors is a self-aligned and self-limiting deposition process.
- the above described precursor gasses are chemisorbed by the catalytic metal of the at least one metal gate conductor 47 , wherein the silanol molecules can then diffuse into the catalytic metal.
- Repeated insertion of the silanol molecules into the catalytic metal of the at least one metal gate conductor 47 form a siloxane polymer bound to the surface of the at least one metal gate conductor 47 through the catalytic metal, e.g., aluminum.
- This siloxane polymer is attached to the surface by strong chemical bonds and is thus non-volatile, i.e., a chemisorbed material.
- the catalytic metal remains available to catalyze the polymerization of the silanol molecules.
- the self-aligned and rate-limiting mechanism in this process is the catalytic conversion of silanol to siloxane, provided that the concentration of silanol vapor is sufficiently high to keep the catalytic aluminum atoms fully occupied.
- the chemisorption rate does not depend on the rate at which silanol arrives at the surface of the siloxane layer. In the language of chemical kinetics, the chemisorption rate is zero order in the vapor concentration of silanol.
- the self aligned and self-limiting nature of the ALD half reaction results from cross-linking of the siloxane polymer.
- the cross-linking reactions connect the siloxane polymer chains, causing the polymer layer to gel and eventually solidify.
- the polymer layer may solidify to form silica (SiO 2 ).
- the precursor of the ALD half reaction is bis(tert-butyloxyl) alkyl silanol
- the polymer layer may solidify to form silicon-oxycarbide (SiCO).
- the polymer layer may solidify to form silicon carbon nitro-oxide (SiCNO). Because the silanol presumably has a negligible rate of diffusion through solid silica, silicon-oxycarbide (SiCO) or silicon carbon nitro-oxide (SiCNO), additional silanol can no longer reach the catalytic metal, e.g., aluminum, so the chemisorption stops, i.e., becomes self-limited.
- self-limiting or self-limited it is meant that the amount of film material deposited in each reaction cycle of the ALD deposition is constant.
- One ALD half reaction may take from 0.5 seconds to a few seconds and may deposit a gate dielectric cap 50 having a self limited thickness between 1.0 nm and 20 nm.
- the gate dielectric cap 50 has a self limited thickness that ranges from 1.0 nm to 10 nm.
- the self-limited thickness may be provided by one ALD half reaction cycle. Further details regarding one embodiment of the ALD half reaction process that provides the self-aligned and self-limited gate dielectric cap 50 may be found in Hausmann et al. “Rapid Vapor Deposition of Highly Conformal Silica Nanolaminates”, Science, Vol. 498, p. 402 (Oct. 11, 2002).
- FIG. 4 depicts one embodiment of forming a contact 60 to the source region 20 and the drain region 25 of the semiconductor device 100 .
- a second interlevel dielectric layer 55 is deposited over the structure depicted in FIG. 3 , and contacts 60 are formed to the source regions 20 and drain regions 25 of the semiconductor device 100 .
- the composition of the second interlevel dielectric layer 55 may be similar to the first interlevel dielectric layer 30 that is described above with reference to FIG. 1 . Therefore, the description of the first interlevel dielectric layer 30 that is described above with respect to FIG. 1 is suitable for the second interlevel dielectric layer 55 that is depicted in FIG. 4 .
- Via openings may be formed to expose an upper surface of the source region 20 and the drain region 25 .
- the via openings may be formed using photolithography and etch processes.
- a photoresist etch mask can be produced by applying a photoresist layer to the upper surface of the second interlevel dielectric layer 55 , exposing the photoresist layer to a pattern of radiation, and then developing the pattern into the photoresist layer utilizing a resist developer.
- the photoresist etch mask may be positioned so that the portions of the second interlevel dielectric layer 55 that are not protected by the photoresist etch mask may be etched in order to provide the via openings.
- the exposed portion of the second interlevel dielectric layer 55 is then removed by a selective etch.
- the etch that removes the exposed portions of the second interlevel dielectric layer 55 is selective to at least the gate dielectric cap 50 , and may also be selective to the dielectric spacers 15 and the semiconductor substrate 5 .
- the etch that removes the exposed portion of the second interlevel dielectric layer 55 may be an anisotropic etch. Examples of anisotropic etch process suitable for forming the via openings include, but are not limited to, reactive-ion etching (RIE), ion beam etching, plasma etching and/or laser ablation.
- RIE reactive-ion etching
- Contacts 60 may be formed in the via openings, in which the contacts 60 are in direct contact with the upper surface of the source region 20 and the drain region 25 .
- Contacts 60 are formed by depositing a conductive metal into the via openings using a deposition process, such as physical vapor deposition (PVD), such as sputtering and plating.
- the contact 60 may be composed of conductive metals, such as titanium/titanium nitride/tungsten, tantalum nitride/tantalum/copper, manganese, aluminum, silver, gold, and alloys thereof.
- PVD physical vapor deposition
- a separate contact may be formed to the at least one metal gate conductor 47 .
- a semiconductor device 100 includes a functional gate structure 45 on a channel portion of a semiconductor substrate 5 .
- the gate structure 45 includes at least one gate dielectric 46 having a U-shaped geometry in contact with the channel portion of the semiconductor substrate 5 and a metal gate conductor 47 comprised of a catalytic metal.
- the gate dielectric cap 50 has edges E 1 that are self-aligned to sidewalls of the gate conductor 47 .
- the gate dielectric cap 50 typically has a self-limiting thickness of less than 20 nm. In one embodiment, the gate dielectric cap 50 has a thickness ranging from 1 nm to 15 nm.
- an interface oxide may be present between the gate dielectric cap 5 and the catalytic metal of the metal gate conductor 47 .
- the interface oxide 51 includes a metal element from the catalytic metal.
- the interface oxide 51 is comprised of aluminum oxide (Al 2 O 3 ).
- the gate dielectric cap 50 protects the gate conductor 47 from being shorted to the source region 25 and the drain region 30 by the contact 60 , because the gate dielectric cap 50 separates the contact 60 from the metal gate conductor 47 . Therefore, the gate dielectric cap 50 prevents shorting between the contact 60 to the source region 25 and the drain region 30 and the metal gate conductor 47 with increased scaling of the semiconductor device 100 .
- the methods and structures disclosed herein may be applicable to semiconductor devices 100 , 110 separated by a pitch between adjacent gate structures 45 , 45 a ranging from 30 nm to 100 nm.
Abstract
Description
- This application is a continuation of U.S. patent application Ser. No. 13/449,433, filed Apr. 18, 2012 the entire content and disclosure of which is incorporated herein by reference.
- The present disclosure relates generally to semiconductor integrated circuits. More particularly, the present disclosure relates to scaling of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs). In order to be able to make integrated circuits, such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as MOSFETs and complementary metal oxide semiconductors (CMOS). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions of the device.
- In one embodiment, a semiconductor device is formed by a method that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate, wherein the metal gate conductor is comprised of a catalytic metal. A gate dielectric cap comprising at least silicon and oxygen is formed on the metal gate conductor. The gate dielectric cap is catalyzed by the catalytic metal so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.
- In another aspect, a semiconductor device is provided that includes a gate structure on a channel portion of a semiconductor substrate. The gate structure includes at least one gate dielectric in contact with the channel portion of the semiconductor substrate and a gate conductor comprised of a catalytic metal. The at least one gate dielectric has a U-shaped geometry. A gate dielectric cap is present on the gate conductor, wherein the gate dielectric cap has edges that are substantially self-aligned to sidewalls of the gate conductor. The gate dielectric cap comprises at least silicon and oxygen and has a self-limited thickness of less than 20 nm. A source region and a drain region are present on opposing sides of the gate structure. A contact is present to each of the source region and the drain region. The contact is separated from the gate conductor by at least the gate conductor.
- The following detailed description, given by way of example and not intended to limit the disclosure solely thereto, will best be appreciated in conjunction with the accompanying drawings, wherein like reference numerals denote like elements and parts, in which:
-
FIG. 1 is a side cross-sectional view depicting one embodiment of an initial structure of the disclosed method including a replacement gate structure on a semiconductor substrate, a source region and a drain region present in the semiconductor substrate on opposing sides of the sacrificial gate structure, and a spacer adjacent to the sacrificial gate structure, in accordance with the present disclosure. -
FIG. 2 is a side cross-sectional view depicting one embodiment of removing the replacement gate structure to provide an opening to a channel portion of the semiconductor substrate, and forming a functional gate structure in the opening, wherein the functional gate structure includes at least one gate dielectric and at least one gate conductor. -
FIG. 3 is a side cross-sectional view depicting one embodiment of forming a gate dielectric cap on the metal gate conductor, wherein the gate dielectric cap is a silicon oxide, or doped silicon oxide, with dopants being carbon, nitrogen, hydrogen or combined mixtures that is catalyzed by a metal element from the catalytic metal so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. -
FIG. 4 is a side cross-sectional view depicting one embodiment of forming a contact to the source and drain regions of the semiconductor device. - Detailed embodiments of the methods and structures of the present disclosure are described herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the disclosed methods and structures that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments of the disclosure are intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present disclosure. For purposes of the description hereinafter, the terms “upper”, “lower”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures, as they are oriented in the drawing figures.
- It has been determined that one consequence of scaling semiconductor devices, such as field effect transistors (FETs), is that as the distance between adjacent semiconductor devices is decreased it is becomes increasingly difficult to form interconnects to the source region and the drain region without shorting the gate structures. In one aspect, the present disclosure provides a process sequence for manufacturing a semiconductor device that forms a dielectric gate cap atop a metal gate conductor composed of a catalytic metal, in which the catalytic metal functions as a catalyst to selective deposition of the dielectric material of the dielectric gate cap on only the metal gate conductor in a self-aligned manner. More specifically, by self-aligned it is meant that the deposited material of the dielectric gate cap is deposited continuously atop the entire upper surface of the metal gate conductor, wherein the edges of the dielectric gate cap are aligned to the sidewalls of the metal gate conductor. In one embodiment, the catalytic metal that dictates the self-aligned characteristics of the dielectric gate cap also provides that the dielectric gate cap has a self-limiting thickness.
-
FIG. 1 illustrates the results of initial processing steps of the present disclosure that produce areplacement gate structure 10 on asemiconductor substrate 5 including asource region 20 and adrain region 25 present in thesemiconductor substrate 5 on opposing sides of thereplacement gate structure 10, at least onedielectric spacer 15 adjacent to thereplacement gate structure 10, and an interleveldielectric layer 30 adjoining thereplacement gate structure 10 and located on the exposed surface of thesemiconductor substrate 5. Thesemiconductor substrate 5 may be composed of a silicon containing material. Silicon containing materials include, but are not limited to, Si, single crystal Si, polycrystalline Si, SiGe, single crystal silicon germanium, polycrystalline silicon germanium, or silicon doped with carbon, amorphous Si and combinations and multi-layers thereof. Thesemiconductor substrate 5 may also be composed of other semiconductor materials, such as germanium, and compound semiconductor substrates, such as type III/V semiconductor substrates, e.g., GaAs. Although thesemiconductor substrate 5 is depicted as a bulk semiconductor substrate, semiconductor on insulator (SOI) substrate arrangements, such as silicon on insulator substrates, are also suitable for thesemiconductor substrate 5. - Still referring to
FIG. 1 , thereplacement gate structure 10 is formed on the channel portion of thesemiconductor substrate 5. As used herein, the term “replacement gate structure 10” denotes a sacrificial structure that dictates the geometry and location of the later formed functioning gate structure. The functional gate structure controls output current, i.e., flow of carriers in the channel region of the semiconductor device. The channel region is the region between the source region and the drain region of the semiconductor device that becomes conductive when the transistor is turned on. The sacrificial material that provides thereplacement gate structure 10 may be composed of any material that can be etched selectively to the bottom dielectric films orsemiconductor substrate 5. In one embodiment, the sacrificial material that provides thereplacement gate structure 10 may be composed of a silicon-containing material, such as polysilicon. Although, thereplacement gate structure 10 is typically composed of a semiconductor material, thereplacement gate structure 10 may also be composed of doped Si layers with Ge, or a dielectric material, such as amorphous carbon. The sacrificial material may be patterned and etched to provide thereplacement gate structure 10. Specifically, and in one example, a pattern is produced by applying a photoresist to the surface to be etched, exposing the photoresist to a pattern of radiation, and then developing the pattern into the photoresist utilizing a resist developer. Once the patterning of the photoresist is completed, the sections of the sacrificial material covered by the photoresist are protected to provide thereplacement gate structure 10, while the exposed regions are removed using a selective etching process that removes the unprotected regions. Following formation of thereplacement gate structure 10, the photoresist may be removed. - At least one
dielectric gate spacer 15 may then be formed adjacent to thereplacement gate structure 10, i.e., in direct contact with the sidewall of thereplacement gate structure 10. In one embodiment, the at last onedielectric gate spacer 15 may be formed by using a blanket layer deposition, such as chemical vapor deposition, and an anisotropic etchback method. The at least onedielectric gate spacer 15 may have a width ranging from 2.0 nm to 15.0 nm, and may be composed of a dielectric, such as a nitride, oxide, oxynitride, or a combination thereof. Thedielectric gate spacer 15 is optional, and may be omitted. - In some embodiments, a
source region 20 and adrain region 25 may then be formed in the portions of thesemiconductor substrate 5 that are present on opposing sides ofreplacement gate structure 10. In one embodiment, thesource region 20 and thedrain region 25 are formed using an ion implantation process. The conductivity type, e.g., n-type or p-type, of thesource region 20 and thedrain region 25 typically dictates the conductivity type of the semiconductor device, e.g., nFET or pFET. In a silicon-containingsemiconductor substrate 5, examples of p-type dopants, i.e., impurities, include but are not limited to, boron, aluminum, gallium and indium, and examples of n-type dopants, i.e., impurities, include but are not limited to antimony, arsenic and phosphorous. - Still referring to
FIG. 1 , in one embodiment, a first interleveldielectric layer 30 is formed atop thesource region 20 and thedrain region 25, wherein the upper surface of the interleveldielectric layer 30 is coplanar with an upper surface of thereplacement gate structure 10. The composition of the first interleveldielectric layer 30 may be selected from the group consisting of silicon-containing materials such as SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, SiCBN and SiCH compounds, the above-mentioned silicon-containing materials with some or all of the Si replaced by Ge, carbon-doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK™, other carbon-containing materials, organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials, and diamond-like carbon (DLC, also known as amorphous hydrogenated carbon, α-C:H). The first interleveldielectric layer 30 may be formed using a deposition method such as chemical vapor deposition (CVD) or spin on deposition. Following deposition the first interleveldielectric layer 30 may be planarized, e.g., planarized by chemical mechanical planarization (CMP), so that an upper surface of the first interleveldielectric layer 30 is coplanar with an upper surface of thereplacement gate structure 10. -
FIG. 2 depicts one embodiment of removing thereplacement gate structure 10 to provide an opening to a channel portion of thesemiconductor substrate 5, and forming afunctional gate structure 45 in the opening. The etch process for removing thereplacement gate structure 10 may be a selective etch. As used herein, the term “selective” in reference to a material removal process denotes that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied. For example and in one embodiment, a selective etch may include an etch chemistry that removes a first material selectively to a second material by a ratio of 2:1 or greater, such as 5:1. Thereplacement gate structure 10 may be removed using a wet or dry etch process, such as reactive ion etch (RIE), or combination of these techniques thereof. In one example, an etch step for removing thereplacement gate structure 10 can include an etch chemistry for removing thereplacement gate structure 10 selective to the substrate dielectrics orsemiconductor substrate 5. - Still referring to
FIG. 2 , thefunctional gate structure 45 includes at least onegate dielectric 46 and at least onegate conductor 47. The at least onegate dielectric 46 may be composed of any dielectric material including oxides, nitrides and oxynitrides. In one embodiment, the at least onegate dielectric 46 may be provided by a high-k dielectric material. The term “high-k” as used to describe the material of the at least onegate dielectric 46 denotes a dielectric material having a dielectric constant greater than silicon oxide (SiO2) at room temperature (20° C. to 25° C.) and atmospheric pressure (1 atm). For example, a high-k dielectric material may have a dielectric constant greater than 4.0. In another example, the dielectric constant of the high-k dielectric material may be greater than 10.0. In one embodiment, the at least onegate dielectric 46 is composed of a high-k oxide such as, for example, HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3 and mixtures thereof. - In one embodiment, the at least one
gate dielectric 46 may be deposited by chemical vapor deposition (CVD), such as plasma enhanced CVD (PECVD). In one embodiment, the at least onegate dielectric 46 may be deposited using a conformal deposition method. The term “conformal” denotes a layer having a thickness that does not deviate from greater than or less than 20% of an average value for the thickness of the layer. In one embodiment, the thickness of the at least onegate dielectric 46 ranges from 0.8 nm to 6.0 nm. In one embodiment, the side cross-section of at least onegate dielectric 46 has a U-shaped geometry, as depicted inFIG. 2 , in which a portion of the at least onegate dielectric 46 extends along an entire height of the interior sidewalls of thedielectric spacer 15 and a portion of the at least onegate dielectric 46 is present on the surface of thesemiconductor substrate 5 that includes the device channel. - The at least one
metal gate conductor 47 is formed on the at least onegate dielectric 46. The at least onemetal gate conductor 47 is composed of a catalytic metal. A “catalytic metal” is a metal that provides for a polymerization reaction with the precursor of the atomic layer deposition (ALD) half reaction for forming the gate dielectric cap that is self-aligned to the metal gate conductor. In one embodiment, the catalytic metal is a Lewis-acid type metal. As used herein, a “Lewis-acid type metal” is a metal ion that functions as an electron pair acceptor in the formation of a stable substance. Examples of catalytic metals include aluminum (Al), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), tungsten (W) and a combination thereof. The at least onemetal gate conductor 47 may be formed by a deposition process, such as CVD, plasma-assisted CVD, plating, and/or sputtering, followed by planarization. More specifically, in one embodiment, the at least onemetal gate conductor 47 may be deposited filling the opening produced by removing thereplacement gate structure 10. -
FIG. 3 depicts one embodiment of forming a gatedielectric cap 50 on the at least onemetal gate conductor 47, wherein the gatedielectric cap 50 is a silicon and oxygen containing dielectric that is catalyzed by the catalytic metal of the gate conductor 471 so that edges E1 of the gatedielectric cap 50 are substantially aligned with a sidewall of the at least onemetal gate conductor 47. By “substantially aligned” it is mean that the sidewall of edge E1 of the gatedielectric cap 50 may extend from the sidewall of the at least onemetal gate conductor 47 by a dimension of 20 nm or less. The catalytic effect provided by the catalytic metal means that there is substantially no deposition of the material for the gatedielectric cap 50 grown on the firstinterlevel dielectric layer 30 and the semiconductor substrate. The material for the gatedielectric cap 50 is only deposited on the upper surface of the at least onemetal gate conductor 47 of the catalytic metal. More specifically, in some embodiments, the ALD half reaction deposition process, which will be described in more detail below, provides for a self limiting thickness of 20 nm or less. Therefore, because the material of the gatedielectric cap 50 can only extend from the catalytic metal that provides the at least onemetal gate conductor 47, the maximum amount of lateral growth of the gatedielectric cap 50 can be 20 nm, which allows for some overlap of thedielectric spacers 15 or lateral extension to firstinterlevel dielectric layer 30. The material of the gatedielectric cap 50 is not grown on an exterior surface of the firstinterlevel dielectric layer 30. The gatedielectric cap 50 may provide an etch stop layer to protect the at least onemetal gate conductor 47 during subsequent etch steps to form vias to thesource region 20 and drainregion 25, for the subsequently formed contacts; i.e., interconnects. - The gate dielectric cap 50 may be formed using an atomic layer deposition (ALD) half reaction. Atomic Layer Deposition (ALD) uses self-limiting surface reactions to deposit material layers in the monolayer or sub-monolayer thickness regime. ALD is similar in chemistry to chemical vapor deposition (CVD), except that the ALD reaction breaks the CVD reaction into two half-reactions, keeping the precursor materials separate during the reaction. The atomic layer depsoition (ALD) process of the present disclosure uses only half reactions to deposit the gate dielectric cap 50. The precusor of the atomic layer deposition process may be a silicon containing precursor. In some embodiments, the percursor may have the following chemical formulation:
- In one embodiment, in which R in the above chemical formula is equal to an alkyloxy group, the precursor may be tris (tert-butyloxyl) silanol. In another embodiment, in which R in the above chemical formula is a butyl group, such as tert-butyl, the precursor may be at least one of bis(tert-butyloxyl) alkyl silanol, and mono-tert-butyloxyl alkyl silanol. Other butyl groups that are suitable for R in the above chemical formula include n-butyl, iso-butyl, and sec-butyl. It is noted that the above examples are provided for illustrative purposes only, as the R group in the above chemical formula for the precursor of the ALD half reaction may be any group having a carbon chain. For example, the R group in the above chemical formula may be an alkyl group, such as methyl group, ethyl group, propyl group, n-propyl group, isopropyl group, pentyl group, hexyl group, octyl group and combinations thereof.
- In one example, in which the silicon precursor of the ALD half reaction process is tris (tert-butyloxyl) silanol, the deposited gate
dielectric cap 50 is composed of silicon oxide (SiO2). In another example, in which the silicon precursor of the ALD half reaction process is bis(tert-butyloxyl) alkyl silanol, the deposited gatedielectric cap 50 is silicon-oxycarbide (SiCO). In another example, in which the silicon precursor of the ALD half reaction process is bis-tert-butyloxyl-aminoalkyl silanol, the gatedielectric cap 50 comprises silicon carbon nitro-oxide (SiCNO). - The ALD half reaction using one of the above described precursors is a self-aligned and self-limiting deposition process. For example, in some embodiments, the above described precursor gasses are chemisorbed by the catalytic metal of the at least one
metal gate conductor 47, wherein the silanol molecules can then diffuse into the catalytic metal. Repeated insertion of the silanol molecules into the catalytic metal of the at least onemetal gate conductor 47 form a siloxane polymer bound to the surface of the at least onemetal gate conductor 47 through the catalytic metal, e.g., aluminum. This siloxane polymer is attached to the surface by strong chemical bonds and is thus non-volatile, i.e., a chemisorbed material. Because silanol can diffuse through this soft, surface bound siloxane polymer, the catalytic metal remains available to catalyze the polymerization of the silanol molecules. The self-aligned and rate-limiting mechanism in this process is the catalytic conversion of silanol to siloxane, provided that the concentration of silanol vapor is sufficiently high to keep the catalytic aluminum atoms fully occupied. In this case, the chemisorption rate does not depend on the rate at which silanol arrives at the surface of the siloxane layer. In the language of chemical kinetics, the chemisorption rate is zero order in the vapor concentration of silanol. The self aligned and self-limiting nature of the ALD half reaction results from cross-linking of the siloxane polymer. - More specifically, the cross-linking reactions connect the siloxane polymer chains, causing the polymer layer to gel and eventually solidify. For example, in the embodiments in which the precursor of the ALD half reaction is tris (tert-butyloxyl) silanol, the polymer layer may solidify to form silica (SiO2). In another example, in which the precursor of the ALD half reaction is bis(tert-butyloxyl) alkyl silanol, the polymer layer may solidify to form silicon-oxycarbide (SiCO). In yet another example, in which the precursor of the ALD half reaction is mono-tert-butyloxyl alkyl silanol, the polymer layer may solidify to form silicon carbon nitro-oxide (SiCNO). Because the silanol presumably has a negligible rate of diffusion through solid silica, silicon-oxycarbide (SiCO) or silicon carbon nitro-oxide (SiCNO), additional silanol can no longer reach the catalytic metal, e.g., aluminum, so the chemisorption stops, i.e., becomes self-limited. By “self-limiting” or “self-limited” it is meant that the amount of film material deposited in each reaction cycle of the ALD deposition is constant. One ALD half reaction may take from 0.5 seconds to a few seconds and may deposit a gate
dielectric cap 50 having a self limited thickness between 1.0 nm and 20 nm. In another embodiment, the gatedielectric cap 50 has a self limited thickness that ranges from 1.0 nm to 10 nm. The self-limited thickness may be provided by one ALD half reaction cycle. Further details regarding one embodiment of the ALD half reaction process that provides the self-aligned and self-limited gatedielectric cap 50 may be found in Hausmann et al. “Rapid Vapor Deposition of Highly Conformal Silica Nanolaminates”, Science, Vol. 498, p. 402 (Oct. 11, 2002). -
FIG. 4 depicts one embodiment of forming acontact 60 to thesource region 20 and thedrain region 25 of thesemiconductor device 100. In one embodiment, a second interleveldielectric layer 55 is deposited over the structure depicted inFIG. 3 , andcontacts 60 are formed to thesource regions 20 anddrain regions 25 of thesemiconductor device 100. The composition of the second interleveldielectric layer 55 may be similar to the firstinterlevel dielectric layer 30 that is described above with reference toFIG. 1 . Therefore, the description of the firstinterlevel dielectric layer 30 that is described above with respect toFIG. 1 is suitable for the second interleveldielectric layer 55 that is depicted inFIG. 4 . - Via openings may be formed to expose an upper surface of the
source region 20 and thedrain region 25. The via openings may be formed using photolithography and etch processes. For example, a photoresist etch mask can be produced by applying a photoresist layer to the upper surface of the second interleveldielectric layer 55, exposing the photoresist layer to a pattern of radiation, and then developing the pattern into the photoresist layer utilizing a resist developer. The photoresist etch mask may be positioned so that the portions of the second interleveldielectric layer 55 that are not protected by the photoresist etch mask may be etched in order to provide the via openings. The exposed portion of the second interleveldielectric layer 55 is then removed by a selective etch. The etch that removes the exposed portions of the second interleveldielectric layer 55 is selective to at least the gatedielectric cap 50, and may also be selective to thedielectric spacers 15 and thesemiconductor substrate 5. The etch that removes the exposed portion of the second interleveldielectric layer 55 may be an anisotropic etch. Examples of anisotropic etch process suitable for forming the via openings include, but are not limited to, reactive-ion etching (RIE), ion beam etching, plasma etching and/or laser ablation.Contacts 60 may be formed in the via openings, in which thecontacts 60 are in direct contact with the upper surface of thesource region 20 and thedrain region 25.Contacts 60 are formed by depositing a conductive metal into the via openings using a deposition process, such as physical vapor deposition (PVD), such as sputtering and plating. Thecontact 60 may be composed of conductive metals, such as titanium/titanium nitride/tungsten, tantalum nitride/tantalum/copper, manganese, aluminum, silver, gold, and alloys thereof. Following the formation of thecontacts 60, a separate contact may be formed to the at least onemetal gate conductor 47. - Referring to
FIG. 4 , in one embodiment asemiconductor device 100 is provided that includes afunctional gate structure 45 on a channel portion of asemiconductor substrate 5. Thegate structure 45 includes at least onegate dielectric 46 having a U-shaped geometry in contact with the channel portion of thesemiconductor substrate 5 and ametal gate conductor 47 comprised of a catalytic metal. The gatedielectric cap 50 has edges E1 that are self-aligned to sidewalls of thegate conductor 47. The gatedielectric cap 50 typically has a self-limiting thickness of less than 20 nm. In one embodiment, the gatedielectric cap 50 has a thickness ranging from 1 nm to 15 nm. In one embodiment, an interface oxide may be present between the gatedielectric cap 5 and the catalytic metal of themetal gate conductor 47. Theinterface oxide 51 includes a metal element from the catalytic metal. In one embodiment, in which the catalytic metal is composed of aluminum (Al), theinterface oxide 51 is comprised of aluminum oxide (Al2O3). - Still referring to
FIG. 4 , the gatedielectric cap 50 protects thegate conductor 47 from being shorted to thesource region 25 and thedrain region 30 by thecontact 60, because the gatedielectric cap 50 separates thecontact 60 from themetal gate conductor 47. Therefore, the gatedielectric cap 50 prevents shorting between thecontact 60 to thesource region 25 and thedrain region 30 and themetal gate conductor 47 with increased scaling of thesemiconductor device 100. For example, the methods and structures disclosed herein may be applicable tosemiconductor devices adjacent gate structures - While the claimed methods and structures has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the presently claimed methods and structures.
Claims (13)
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