Sök Bilder Maps Play YouTube Nyheter Gmail Drive Mer »
Logga in
Använder du ett skärmläsningsprogram? Öppna boken i tillgänglighetsläge genom att klicka här. Tillgänglighetsläget har samma grundläggande funktioner men fungerar bättre ihop med skärmläsningsprogrammet.

Patent

  1. Avancerad patentsökning
PublikationsnummerUS20130277767 A1
Typ av kungörelseAnsökan
AnsökningsnummerUS 13/780,957
Publiceringsdatum24 okt 2013
Registreringsdatum28 feb 2013
Prioritetsdatum18 apr 2012
Även publicerat somUS8759172, US20130277764
Publikationsnummer13780957, 780957, US 2013/0277767 A1, US 2013/277767 A1, US 20130277767 A1, US 20130277767A1, US 2013277767 A1, US 2013277767A1, US-A1-20130277767, US-A1-2013277767, US2013/0277767A1, US2013/277767A1, US20130277767 A1, US20130277767A1, US2013277767 A1, US2013277767A1
UppfinnareZhengwen Li, Michael P. Chudzik, Ramachandra Divakaruni, Siddarth A. Krishnan, Unoh Kwon, Richard S. Wise
Ursprunglig innehavareInternational Business Machines Corporation
Exportera citatBiBTeX, EndNote, RefMan
Externa länkar: USPTO, Överlåtelse av äganderätt till patent som har registrerats av USPTO, Espacenet
Etch stop layer formation in metal gate process
US 20130277767 A1
Sammanfattning
A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.
Bilder(2)
Previous page
Next page
Anspråk(13)
What is claimed is:
1. A semiconductor device comprising:
a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric layer having a U-shaped geometry in contact with the channel portion of the semiconductor substrate and a metal gate conductor comprised of a catalytic metal;
a gate dielectric cap having edges that are substantially self-aligned to sidewalls of the metal gate conductor, wherein the gate dielectric cap is an oxide-containing dielectric having a self-limited thickness of less than 20 nm;
a source region and a drain region on opposing sides of the gate structure; and
a contact to each of the source region and the drain region, wherein the contact is separated from the metal gate conductor by at least the gate dielectric cap.
2. The semiconductor device of claim 1, wherein the at least one gate dielectric layer is comprised of a high-k dielectric material.
3. The semiconductor device of claim 1, wherein the at least one gate dielectric layer has a thickness that ranges 0.8 mm to 6.0 mm.
4. The semiconductor device of claim 2, wherein the high-k dielectric material is selected from the group consisting of HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3 and mixtures thereof.
5. The semiconductor device of claim 1, wherein the gate dielectric cap comprises at least one of silicon-oxycarbide (SiCO), silicon carbon nitro-oxide (SiCNO) and silicon oxide (SiO2).
6. The semiconductor device of claim 1, wherein the catalytic metal comprises aluminum (Al), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), tungsten (W) or a combination thereof.
7. The semiconductor device of claim 1, wherein a spacer is adjacent to the gate structure.
8. The semiconductor device of claim 4, wherein said edges of the gate dielectric cap that are substantially self-aligned to sidewalls of the metal gate conductor may extend past the metal gate conductor over the spacer by a dimension of 20 nm or less.
9. The semiconductor device of claim 1, wherein the gate structure of the semiconductor device and an adjacent gate structure of an adjacent semiconductor device are separated by a pitch ranging from 30 nm to 100 nm.
10. The semiconductor device of claim 1 further comprising dielectric spacers adjacent to the gate structure, wherein the material of the gate dielectric cap is not present on an exterior surface of the dielectric spacers.
11. The semiconductor device of claim 1, wherein the catalytic metal is aluminum, the interface oxide is aluminum oxide (Al2O3), and the gate dielectric cap is silicon oxide (SiO2).
12. The semiconductor device of claim 1, wherein at least one contact of said contact to each of the source region and the drain region is in direct contact with the gate dielectric cap.
13. The semiconductor device of claim 1, wherein the at least one contact is comprised of titanium/titanium nitride/tungsten, tantalum nitride/tantalum/copper, manganese, aluminum, silver, gold, or alloys thereof.
Beskrivning
    CROSS REFERENCE TO RELATED APPLICATION
  • [0001]
    This application is a continuation of U.S. patent application Ser. No. 13/449,433, filed Apr. 18, 2012 the entire content and disclosure of which is incorporated herein by reference.
  • BACKGROUND
  • [0002]
    The present disclosure relates generally to semiconductor integrated circuits. More particularly, the present disclosure relates to scaling of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs). In order to be able to make integrated circuits, such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as MOSFETs and complementary metal oxide semiconductors (CMOS). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions of the device.
  • SUMMARY
  • [0003]
    In one embodiment, a semiconductor device is formed by a method that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate, wherein the metal gate conductor is comprised of a catalytic metal. A gate dielectric cap comprising at least silicon and oxygen is formed on the metal gate conductor. The gate dielectric cap is catalyzed by the catalytic metal so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.
  • [0004]
    In another aspect, a semiconductor device is provided that includes a gate structure on a channel portion of a semiconductor substrate. The gate structure includes at least one gate dielectric in contact with the channel portion of the semiconductor substrate and a gate conductor comprised of a catalytic metal. The at least one gate dielectric has a U-shaped geometry. A gate dielectric cap is present on the gate conductor, wherein the gate dielectric cap has edges that are substantially self-aligned to sidewalls of the gate conductor. The gate dielectric cap comprises at least silicon and oxygen and has a self-limited thickness of less than 20 nm. A source region and a drain region are present on opposing sides of the gate structure. A contact is present to each of the source region and the drain region. The contact is separated from the gate conductor by at least the gate conductor.
  • DESCRIPTION OF THE DRAWINGS
  • [0005]
    The following detailed description, given by way of example and not intended to limit the disclosure solely thereto, will best be appreciated in conjunction with the accompanying drawings, wherein like reference numerals denote like elements and parts, in which:
  • [0006]
    FIG. 1 is a side cross-sectional view depicting one embodiment of an initial structure of the disclosed method including a replacement gate structure on a semiconductor substrate, a source region and a drain region present in the semiconductor substrate on opposing sides of the sacrificial gate structure, and a spacer adjacent to the sacrificial gate structure, in accordance with the present disclosure.
  • [0007]
    FIG. 2 is a side cross-sectional view depicting one embodiment of removing the replacement gate structure to provide an opening to a channel portion of the semiconductor substrate, and forming a functional gate structure in the opening, wherein the functional gate structure includes at least one gate dielectric and at least one gate conductor.
  • [0008]
    FIG. 3 is a side cross-sectional view depicting one embodiment of forming a gate dielectric cap on the metal gate conductor, wherein the gate dielectric cap is a silicon oxide, or doped silicon oxide, with dopants being carbon, nitrogen, hydrogen or combined mixtures that is catalyzed by a metal element from the catalytic metal so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor.
  • [0009]
    FIG. 4 is a side cross-sectional view depicting one embodiment of forming a contact to the source and drain regions of the semiconductor device.
  • DETAILED DESCRIPTION
  • [0010]
    Detailed embodiments of the methods and structures of the present disclosure are described herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the disclosed methods and structures that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments of the disclosure are intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present disclosure. For purposes of the description hereinafter, the terms “upper”, “lower”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures, as they are oriented in the drawing figures.
  • [0011]
    It has been determined that one consequence of scaling semiconductor devices, such as field effect transistors (FETs), is that as the distance between adjacent semiconductor devices is decreased it is becomes increasingly difficult to form interconnects to the source region and the drain region without shorting the gate structures. In one aspect, the present disclosure provides a process sequence for manufacturing a semiconductor device that forms a dielectric gate cap atop a metal gate conductor composed of a catalytic metal, in which the catalytic metal functions as a catalyst to selective deposition of the dielectric material of the dielectric gate cap on only the metal gate conductor in a self-aligned manner. More specifically, by self-aligned it is meant that the deposited material of the dielectric gate cap is deposited continuously atop the entire upper surface of the metal gate conductor, wherein the edges of the dielectric gate cap are aligned to the sidewalls of the metal gate conductor. In one embodiment, the catalytic metal that dictates the self-aligned characteristics of the dielectric gate cap also provides that the dielectric gate cap has a self-limiting thickness.
  • [0012]
    FIG. 1 illustrates the results of initial processing steps of the present disclosure that produce a replacement gate structure 10 on a semiconductor substrate 5 including a source region 20 and a drain region 25 present in the semiconductor substrate 5 on opposing sides of the replacement gate structure 10, at least one dielectric spacer 15 adjacent to the replacement gate structure 10, and an interlevel dielectric layer 30 adjoining the replacement gate structure 10 and located on the exposed surface of the semiconductor substrate 5. The semiconductor substrate 5 may be composed of a silicon containing material. Silicon containing materials include, but are not limited to, Si, single crystal Si, polycrystalline Si, SiGe, single crystal silicon germanium, polycrystalline silicon germanium, or silicon doped with carbon, amorphous Si and combinations and multi-layers thereof. The semiconductor substrate 5 may also be composed of other semiconductor materials, such as germanium, and compound semiconductor substrates, such as type III/V semiconductor substrates, e.g., GaAs. Although the semiconductor substrate 5 is depicted as a bulk semiconductor substrate, semiconductor on insulator (SOI) substrate arrangements, such as silicon on insulator substrates, are also suitable for the semiconductor substrate 5.
  • [0013]
    Still referring to FIG. 1, the replacement gate structure 10 is formed on the channel portion of the semiconductor substrate 5. As used herein, the term “replacement gate structure 10” denotes a sacrificial structure that dictates the geometry and location of the later formed functioning gate structure. The functional gate structure controls output current, i.e., flow of carriers in the channel region of the semiconductor device. The channel region is the region between the source region and the drain region of the semiconductor device that becomes conductive when the transistor is turned on. The sacrificial material that provides the replacement gate structure 10 may be composed of any material that can be etched selectively to the bottom dielectric films or semiconductor substrate 5. In one embodiment, the sacrificial material that provides the replacement gate structure 10 may be composed of a silicon-containing material, such as polysilicon. Although, the replacement gate structure 10 is typically composed of a semiconductor material, the replacement gate structure 10 may also be composed of doped Si layers with Ge, or a dielectric material, such as amorphous carbon. The sacrificial material may be patterned and etched to provide the replacement gate structure 10. Specifically, and in one example, a pattern is produced by applying a photoresist to the surface to be etched, exposing the photoresist to a pattern of radiation, and then developing the pattern into the photoresist utilizing a resist developer. Once the patterning of the photoresist is completed, the sections of the sacrificial material covered by the photoresist are protected to provide the replacement gate structure 10, while the exposed regions are removed using a selective etching process that removes the unprotected regions. Following formation of the replacement gate structure 10, the photoresist may be removed.
  • [0014]
    At least one dielectric gate spacer 15 may then be formed adjacent to the replacement gate structure 10, i.e., in direct contact with the sidewall of the replacement gate structure 10. In one embodiment, the at last one dielectric gate spacer 15 may be formed by using a blanket layer deposition, such as chemical vapor deposition, and an anisotropic etchback method. The at least one dielectric gate spacer 15 may have a width ranging from 2.0 nm to 15.0 nm, and may be composed of a dielectric, such as a nitride, oxide, oxynitride, or a combination thereof. The dielectric gate spacer 15 is optional, and may be omitted.
  • [0015]
    In some embodiments, a source region 20 and a drain region 25 may then be formed in the portions of the semiconductor substrate 5 that are present on opposing sides of replacement gate structure 10. In one embodiment, the source region 20 and the drain region 25 are formed using an ion implantation process. The conductivity type, e.g., n-type or p-type, of the source region 20 and the drain region 25 typically dictates the conductivity type of the semiconductor device, e.g., nFET or pFET. In a silicon-containing semiconductor substrate 5, examples of p-type dopants, i.e., impurities, include but are not limited to, boron, aluminum, gallium and indium, and examples of n-type dopants, i.e., impurities, include but are not limited to antimony, arsenic and phosphorous.
  • [0016]
    Still referring to FIG. 1, in one embodiment, a first interlevel dielectric layer 30 is formed atop the source region 20 and the drain region 25, wherein the upper surface of the interlevel dielectric layer 30 is coplanar with an upper surface of the replacement gate structure 10. The composition of the first interlevel dielectric layer 30 may be selected from the group consisting of silicon-containing materials such as SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, SiCBN and SiCH compounds, the above-mentioned silicon-containing materials with some or all of the Si replaced by Ge, carbon-doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK™, other carbon-containing materials, organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials, and diamond-like carbon (DLC, also known as amorphous hydrogenated carbon, α-C:H). The first interlevel dielectric layer 30 may be formed using a deposition method such as chemical vapor deposition (CVD) or spin on deposition. Following deposition the first interlevel dielectric layer 30 may be planarized, e.g., planarized by chemical mechanical planarization (CMP), so that an upper surface of the first interlevel dielectric layer 30 is coplanar with an upper surface of the replacement gate structure 10.
  • [0017]
    FIG. 2 depicts one embodiment of removing the replacement gate structure 10 to provide an opening to a channel portion of the semiconductor substrate 5, and forming a functional gate structure 45 in the opening. The etch process for removing the replacement gate structure 10 may be a selective etch. As used herein, the term “selective” in reference to a material removal process denotes that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied. For example and in one embodiment, a selective etch may include an etch chemistry that removes a first material selectively to a second material by a ratio of 2:1 or greater, such as 5:1. The replacement gate structure 10 may be removed using a wet or dry etch process, such as reactive ion etch (RIE), or combination of these techniques thereof. In one example, an etch step for removing the replacement gate structure 10 can include an etch chemistry for removing the replacement gate structure 10 selective to the substrate dielectrics or semiconductor substrate 5.
  • [0018]
    Still referring to FIG. 2, the functional gate structure 45 includes at least one gate dielectric 46 and at least one gate conductor 47. The at least one gate dielectric 46 may be composed of any dielectric material including oxides, nitrides and oxynitrides. In one embodiment, the at least one gate dielectric 46 may be provided by a high-k dielectric material. The term “high-k” as used to describe the material of the at least one gate dielectric 46 denotes a dielectric material having a dielectric constant greater than silicon oxide (SiO2) at room temperature (20° C. to 25° C.) and atmospheric pressure (1 atm). For example, a high-k dielectric material may have a dielectric constant greater than 4.0. In another example, the dielectric constant of the high-k dielectric material may be greater than 10.0. In one embodiment, the at least one gate dielectric 46 is composed of a high-k oxide such as, for example, HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3 and mixtures thereof.
  • [0019]
    In one embodiment, the at least one gate dielectric 46 may be deposited by chemical vapor deposition (CVD), such as plasma enhanced CVD (PECVD). In one embodiment, the at least one gate dielectric 46 may be deposited using a conformal deposition method. The term “conformal” denotes a layer having a thickness that does not deviate from greater than or less than 20% of an average value for the thickness of the layer. In one embodiment, the thickness of the at least one gate dielectric 46 ranges from 0.8 nm to 6.0 nm. In one embodiment, the side cross-section of at least one gate dielectric 46 has a U-shaped geometry, as depicted in FIG. 2, in which a portion of the at least one gate dielectric 46 extends along an entire height of the interior sidewalls of the dielectric spacer 15 and a portion of the at least one gate dielectric 46 is present on the surface of the semiconductor substrate 5 that includes the device channel.
  • [0020]
    The at least one metal gate conductor 47 is formed on the at least one gate dielectric 46. The at least one metal gate conductor 47 is composed of a catalytic metal. A “catalytic metal” is a metal that provides for a polymerization reaction with the precursor of the atomic layer deposition (ALD) half reaction for forming the gate dielectric cap that is self-aligned to the metal gate conductor. In one embodiment, the catalytic metal is a Lewis-acid type metal. As used herein, a “Lewis-acid type metal” is a metal ion that functions as an electron pair acceptor in the formation of a stable substance. Examples of catalytic metals include aluminum (Al), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), tungsten (W) and a combination thereof. The at least one metal gate conductor 47 may be formed by a deposition process, such as CVD, plasma-assisted CVD, plating, and/or sputtering, followed by planarization. More specifically, in one embodiment, the at least one metal gate conductor 47 may be deposited filling the opening produced by removing the replacement gate structure 10.
  • [0021]
    FIG. 3 depicts one embodiment of forming a gate dielectric cap 50 on the at least one metal gate conductor 47, wherein the gate dielectric cap 50 is a silicon and oxygen containing dielectric that is catalyzed by the catalytic metal of the gate conductor 471 so that edges E1 of the gate dielectric cap 50 are substantially aligned with a sidewall of the at least one metal gate conductor 47. By “substantially aligned” it is mean that the sidewall of edge E1 of the gate dielectric cap 50 may extend from the sidewall of the at least one metal gate conductor 47 by a dimension of 20 nm or less. The catalytic effect provided by the catalytic metal means that there is substantially no deposition of the material for the gate dielectric cap 50 grown on the first interlevel dielectric layer 30 and the semiconductor substrate. The material for the gate dielectric cap 50 is only deposited on the upper surface of the at least one metal gate conductor 47 of the catalytic metal. More specifically, in some embodiments, the ALD half reaction deposition process, which will be described in more detail below, provides for a self limiting thickness of 20 nm or less. Therefore, because the material of the gate dielectric cap 50 can only extend from the catalytic metal that provides the at least one metal gate conductor 47, the maximum amount of lateral growth of the gate dielectric cap 50 can be 20 nm, which allows for some overlap of the dielectric spacers 15 or lateral extension to first interlevel dielectric layer 30. The material of the gate dielectric cap 50 is not grown on an exterior surface of the first interlevel dielectric layer 30. The gate dielectric cap 50 may provide an etch stop layer to protect the at least one metal gate conductor 47 during subsequent etch steps to form vias to the source region 20 and drain region 25, for the subsequently formed contacts; i.e., interconnects.
  • [0022]
    The gate dielectric cap 50 may be formed using an atomic layer deposition (ALD) half reaction. Atomic Layer Deposition (ALD) uses self-limiting surface reactions to deposit material layers in the monolayer or sub-monolayer thickness regime. ALD is similar in chemistry to chemical vapor deposition (CVD), except that the ALD reaction breaks the CVD reaction into two half-reactions, keeping the precursor materials separate during the reaction. The atomic layer depsoition (ALD) process of the present disclosure uses only half reactions to deposit the gate dielectric cap 50. The precusor of the atomic layer deposition process may be a silicon containing precursor. In some embodiments, the percursor may have the following chemical formulation:
  • [0000]
  • [0023]
    In one embodiment, in which R in the above chemical formula is equal to an alkyloxy group, the precursor may be tris (tert-butyloxyl) silanol. In another embodiment, in which R in the above chemical formula is a butyl group, such as tert-butyl, the precursor may be at least one of bis(tert-butyloxyl) alkyl silanol, and mono-tert-butyloxyl alkyl silanol. Other butyl groups that are suitable for R in the above chemical formula include n-butyl, iso-butyl, and sec-butyl. It is noted that the above examples are provided for illustrative purposes only, as the R group in the above chemical formula for the precursor of the ALD half reaction may be any group having a carbon chain. For example, the R group in the above chemical formula may be an alkyl group, such as methyl group, ethyl group, propyl group, n-propyl group, isopropyl group, pentyl group, hexyl group, octyl group and combinations thereof.
  • [0024]
    In one example, in which the silicon precursor of the ALD half reaction process is tris (tert-butyloxyl) silanol, the deposited gate dielectric cap 50 is composed of silicon oxide (SiO2). In another example, in which the silicon precursor of the ALD half reaction process is bis(tert-butyloxyl) alkyl silanol, the deposited gate dielectric cap 50 is silicon-oxycarbide (SiCO). In another example, in which the silicon precursor of the ALD half reaction process is bis-tert-butyloxyl-aminoalkyl silanol, the gate dielectric cap 50 comprises silicon carbon nitro-oxide (SiCNO).
  • [0025]
    The ALD half reaction using one of the above described precursors is a self-aligned and self-limiting deposition process. For example, in some embodiments, the above described precursor gasses are chemisorbed by the catalytic metal of the at least one metal gate conductor 47, wherein the silanol molecules can then diffuse into the catalytic metal. Repeated insertion of the silanol molecules into the catalytic metal of the at least one metal gate conductor 47 form a siloxane polymer bound to the surface of the at least one metal gate conductor 47 through the catalytic metal, e.g., aluminum. This siloxane polymer is attached to the surface by strong chemical bonds and is thus non-volatile, i.e., a chemisorbed material. Because silanol can diffuse through this soft, surface bound siloxane polymer, the catalytic metal remains available to catalyze the polymerization of the silanol molecules. The self-aligned and rate-limiting mechanism in this process is the catalytic conversion of silanol to siloxane, provided that the concentration of silanol vapor is sufficiently high to keep the catalytic aluminum atoms fully occupied. In this case, the chemisorption rate does not depend on the rate at which silanol arrives at the surface of the siloxane layer. In the language of chemical kinetics, the chemisorption rate is zero order in the vapor concentration of silanol. The self aligned and self-limiting nature of the ALD half reaction results from cross-linking of the siloxane polymer.
  • [0026]
    More specifically, the cross-linking reactions connect the siloxane polymer chains, causing the polymer layer to gel and eventually solidify. For example, in the embodiments in which the precursor of the ALD half reaction is tris (tert-butyloxyl) silanol, the polymer layer may solidify to form silica (SiO2). In another example, in which the precursor of the ALD half reaction is bis(tert-butyloxyl) alkyl silanol, the polymer layer may solidify to form silicon-oxycarbide (SiCO). In yet another example, in which the precursor of the ALD half reaction is mono-tert-butyloxyl alkyl silanol, the polymer layer may solidify to form silicon carbon nitro-oxide (SiCNO). Because the silanol presumably has a negligible rate of diffusion through solid silica, silicon-oxycarbide (SiCO) or silicon carbon nitro-oxide (SiCNO), additional silanol can no longer reach the catalytic metal, e.g., aluminum, so the chemisorption stops, i.e., becomes self-limited. By “self-limiting” or “self-limited” it is meant that the amount of film material deposited in each reaction cycle of the ALD deposition is constant. One ALD half reaction may take from 0.5 seconds to a few seconds and may deposit a gate dielectric cap 50 having a self limited thickness between 1.0 nm and 20 nm. In another embodiment, the gate dielectric cap 50 has a self limited thickness that ranges from 1.0 nm to 10 nm. The self-limited thickness may be provided by one ALD half reaction cycle. Further details regarding one embodiment of the ALD half reaction process that provides the self-aligned and self-limited gate dielectric cap 50 may be found in Hausmann et al. “Rapid Vapor Deposition of Highly Conformal Silica Nanolaminates”, Science, Vol. 498, p. 402 (Oct. 11, 2002).
  • [0027]
    FIG. 4 depicts one embodiment of forming a contact 60 to the source region 20 and the drain region 25 of the semiconductor device 100. In one embodiment, a second interlevel dielectric layer 55 is deposited over the structure depicted in FIG. 3, and contacts 60 are formed to the source regions 20 and drain regions 25 of the semiconductor device 100. The composition of the second interlevel dielectric layer 55 may be similar to the first interlevel dielectric layer 30 that is described above with reference to FIG. 1. Therefore, the description of the first interlevel dielectric layer 30 that is described above with respect to FIG. 1 is suitable for the second interlevel dielectric layer 55 that is depicted in FIG. 4.
  • [0028]
    Via openings may be formed to expose an upper surface of the source region 20 and the drain region 25. The via openings may be formed using photolithography and etch processes. For example, a photoresist etch mask can be produced by applying a photoresist layer to the upper surface of the second interlevel dielectric layer 55, exposing the photoresist layer to a pattern of radiation, and then developing the pattern into the photoresist layer utilizing a resist developer. The photoresist etch mask may be positioned so that the portions of the second interlevel dielectric layer 55 that are not protected by the photoresist etch mask may be etched in order to provide the via openings. The exposed portion of the second interlevel dielectric layer 55 is then removed by a selective etch. The etch that removes the exposed portions of the second interlevel dielectric layer 55 is selective to at least the gate dielectric cap 50, and may also be selective to the dielectric spacers 15 and the semiconductor substrate 5. The etch that removes the exposed portion of the second interlevel dielectric layer 55 may be an anisotropic etch. Examples of anisotropic etch process suitable for forming the via openings include, but are not limited to, reactive-ion etching (RIE), ion beam etching, plasma etching and/or laser ablation. Contacts 60 may be formed in the via openings, in which the contacts 60 are in direct contact with the upper surface of the source region 20 and the drain region 25. Contacts 60 are formed by depositing a conductive metal into the via openings using a deposition process, such as physical vapor deposition (PVD), such as sputtering and plating. The contact 60 may be composed of conductive metals, such as titanium/titanium nitride/tungsten, tantalum nitride/tantalum/copper, manganese, aluminum, silver, gold, and alloys thereof. Following the formation of the contacts 60, a separate contact may be formed to the at least one metal gate conductor 47.
  • [0029]
    Referring to FIG. 4, in one embodiment a semiconductor device 100 is provided that includes a functional gate structure 45 on a channel portion of a semiconductor substrate 5. The gate structure 45 includes at least one gate dielectric 46 having a U-shaped geometry in contact with the channel portion of the semiconductor substrate 5 and a metal gate conductor 47 comprised of a catalytic metal. The gate dielectric cap 50 has edges E1 that are self-aligned to sidewalls of the gate conductor 47. The gate dielectric cap 50 typically has a self-limiting thickness of less than 20 nm. In one embodiment, the gate dielectric cap 50 has a thickness ranging from 1 nm to 15 nm. In one embodiment, an interface oxide may be present between the gate dielectric cap 5 and the catalytic metal of the metal gate conductor 47. The interface oxide 51 includes a metal element from the catalytic metal. In one embodiment, in which the catalytic metal is composed of aluminum (Al), the interface oxide 51 is comprised of aluminum oxide (Al2O3).
  • [0030]
    Still referring to FIG. 4, the gate dielectric cap 50 protects the gate conductor 47 from being shorted to the source region 25 and the drain region 30 by the contact 60, because the gate dielectric cap 50 separates the contact 60 from the metal gate conductor 47. Therefore, the gate dielectric cap 50 prevents shorting between the contact 60 to the source region 25 and the drain region 30 and the metal gate conductor 47 with increased scaling of the semiconductor device 100. For example, the methods and structures disclosed herein may be applicable to semiconductor devices 100, 110 separated by a pitch between adjacent gate structures 45, 45 a ranging from 30 nm to 100 nm.
  • [0031]
    While the claimed methods and structures has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the presently claimed methods and structures.
Citat från patent
citerade patent Registreringsdatum Publiceringsdatum Sökande Titel
US7759262 *30 jun 200820 jul 2010Intel CorporationSelective formation of dielectric etch stop layers
US8043907 *14 jan 201025 okt 2011Applied Materials, Inc.Atomic layer deposition processes for non-volatile memory devices
US20100041193 *23 okt 200918 feb 2010Kabushiki Kaisha ToshibaNonvolatile semiconductor memory device and method of manufacturing the same
US20110156107 *30 dec 200930 jun 2011Bohr Mark TSelf-aligned contacts
US20120217591 *14 dec 201130 aug 2012Fujitsu LimitedSemiconductor device and method of manufacturing the same, and power supply apparatus
US20130009253 *3 jul 201210 jan 2013Texas Instruments IncorporatedPower mosfet with integrated gate resistor and diode-connected mosfet
US20130015509 *15 jul 201117 jan 2013International Business Machines CorporationLow resistance source and drain extensions for etsoi
US20130043592 *19 aug 201121 feb 2013Globalfoundries Inc.Methods of Forming a Replacement Gate Comprised of Silicon and a Device Including Same
US20130078791 *28 sep 201128 mar 2013Globalfoundries Inc.Semiconductor device fabrication methods with enhanced control in recessing processes
US20140203355 *24 mar 201424 jul 2014Fairchild Semiconductor CorporationField effect transistor and schottky diode structures
Hänvisningar finns i följande patent
citeras i Registreringsdatum Publiceringsdatum Sökande Titel
US9105578 *15 mar 201311 aug 2015Taiwan Semiconductor Manufacturing Company, Ltd.Interface for metal gate integration
US9190488 *13 aug 201417 nov 2015Globalfoundries Inc.Methods of forming gate structure of semiconductor devices and the resulting devices
US926327512 mar 201316 feb 2016Taiwan Semiconductor Manufacturing Company, Ltd.Interface for metal gate integration
US9698255 *8 apr 20154 jul 2017United Microelectronics Corp.Semiconductor device having gate structure with doped hard mask
US20140264480 *14 mar 201318 sep 2014United Microelectronics Corp.Semiconductor device and method of forming the same
US20140273385 *15 mar 201318 sep 2014Taiwan Semiconductor Manufacturing Company, Ltd.Interface for metal gate integration
Klassificeringar
USA-klassificering257/411
Internationell klassificeringH01L29/51
Kooperativ klassningH01L29/517, H01L29/66545, H01L29/495, H01L21/76834, H01L21/76897, H01L21/02164, H01L21/02208, H01L21/31116, H01L21/02126, H01L21/0228
Juridiska händelser
DatumKodHändelseBeskrivning
3 sep 2015ASAssignment
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001
Effective date: 20150629
5 okt 2015ASAssignment
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001
Effective date: 20150910