US20130009215A1 - Vertical diode using silicon formed by selective epitaxial growth - Google Patents
Vertical diode using silicon formed by selective epitaxial growth Download PDFInfo
- Publication number
- US20130009215A1 US20130009215A1 US13/618,738 US201213618738A US2013009215A1 US 20130009215 A1 US20130009215 A1 US 20130009215A1 US 201213618738 A US201213618738 A US 201213618738A US 2013009215 A1 US2013009215 A1 US 2013009215A1
- Authority
- US
- United States
- Prior art keywords
- film
- epitaxial
- semiconductive
- disposed
- doping region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title description 5
- 229910052710 silicon Inorganic materials 0.000 title description 5
- 239000010703 silicon Substances 0.000 title description 5
- 238000000034 method Methods 0.000 claims abstract description 50
- 230000000694 effects Effects 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 74
- 229910021332 silicide Inorganic materials 0.000 claims description 71
- 239000000758 substrate Substances 0.000 claims description 45
- 230000008878 coupling Effects 0.000 claims description 8
- 238000010168 coupling process Methods 0.000 claims description 8
- 238000005859 coupling reaction Methods 0.000 claims description 8
- 238000011065 in-situ storage Methods 0.000 claims description 7
- 125000006850 spacer group Chemical group 0.000 claims description 7
- 230000000903 blocking effect Effects 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 9
- 238000002513 implantation Methods 0.000 description 13
- 150000004767 nitrides Chemical class 0.000 description 7
- 230000000873 masking effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000004377 microelectronic Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
Definitions
- Embodiments described herein relate generally to diodes and to gated diodes.
- Diodes are used with microelectronic devices such as for electrostatic discharge protectants in sensitive solid-state circuits. Miniaturization is the process of crowding more devices, both passive and active, onto the same or an even smaller footprint of a microelectronic device. The crowding of more diodes into even smaller areas, poses significant challenges.
- FIG. 1 is a cross-section elevation of an apparatus according to an embodiment.
- FIGS. 2 a - 2 f represent cross-section elevations of an apparatus during processing according to an embodiment.
- FIG. 3 is a cross-sectional elevation of an apparatus that can exhibit vertical-diode activity according to an embodiment.
- FIG. 4 is a cross-sectional elevation of an apparatus that can exhibit lateral- and vertical-diode activity according to an embodiment.
- FIG. 5 is a top plan of an apparatus that can exhibit vertical-diode activity according to an embodiment.
- FIG. 6 is a cross-sectional elevation of the apparatus depicted in FIG. 5 , taken along the section line 6 - 6 according to an embodiment.
- FIG. 7 is a cross-sectional elevation of the apparatus depicted in FIG. 5 , taken along the section line 7 - 7 according to an embodiment.
- FIG. 8 is a cross-sectional elevation of an apparatus that can exhibit vertical-diode activity according to an embodiment.
- FIG. 9 is a cross-sectional elevation of an apparatus that can exhibit vertical-diode activity according to an embodiment.
- FIG. 10 is a process-flow diagram according to some embodiments.
- FIG. 11 is a process-flow diagram according to some embodiments.
- FIG. 12 is a illustrates an electronic device that includes vertical-diode apparatus embodiment such described herein.
- FIG. 1 is a cross-section elevation of an apparatus 100 , according to an embodiment.
- a substrate 110 may include a dielectric substrate 112 such as a buried oxide (BOX) layer on a semiconductive substrate 114 to form a semiconductor on insulator (SOI) substrate in an embodiment.
- a semiconductive body 116 is disposed on the BOX layer 112 , and the semiconductive body 116 includes a first section 118 and a second section 120 .
- the semiconductive body 116 is disposed upon the dielectric substrate 112 .
- the semiconductive body 116 is disposed upon a bulk semiconductor, in which case both the structure 112 and the structure 114 are semiconductor materials, and they may be integral.
- the semiconductive body 116 may also be referred to as a semiconductive fin, or just a fin as understood within this disclosure.
- the first section 118 and the second section 120 may be differently doped, such as the first section 118 being undoped and the second section 120 being P+ doped.
- the first section 118 is slightly P-doped to the second section 120 being P+ doped.
- the first section 118 is slightly N-doped to the second section 120 being P+ doped.
- Other doping-difference schemes may be selected depending upon an application.
- An epitaxial film 122 is disposed above and on the semiconductive body 116 at the first section 118 .
- epitaxial film 122 is grown upon selected regions of the semiconductive body 116 .
- the semiconductive body 116 can therefore be referred to as a semiconductive seed layer 116
- the epitaxial film 122 can be referred to as a selective-growth (SEG) epitaxial film 122 .
- a diode junction 124 (represented by a dashed line) is formed at the semiconductive body 116 .
- a diode junction boundary 126 exists at the diode junction 124 in relation to the semiconductive body 116 .
- the diode junction 124 is configured to allow vertical-diode (z-direction) activity between the semiconductive body 116 at the first section 118 and the epitaxial film 122 .
- the epitaxial film 122 also exhibits a top surface 128 and a lateral surface 130 .
- the apparatus 100 communicates to the outside world by a first contact 132 , disposed on the epitaxial film 122 at the top surface 128 , and by a second contact 134 , disposed upon the semiconductive body 116 at the second section 120 . Consequently, the contacts are coupleable to external structures.
- a diode distance 136 represents the electrical length of the diode that is formed by the apparatus 100 .
- the second contact 134 is vertically closer to the semiconductive body 116 than the first contact 132 . This is because the second contact 134 is disposed directly upon the semiconductive body 116 , and the first contact 132 is disposed upon the epitaxial film 122 .
- FIGS. 2 a - 2 f represent a cross-section elevation of an apparatus during processing according to an embodiment.
- FIG. 2 f is a cross-section elevation of an apparatus 205 that can exhibit vertical diode activity according to an embodiment.
- FIG. 2 f represents a processed apparatus that is process-illustrated in FIGS. 2 a , 2 b , 2 c , 2 d , 2 e , and 2 f.
- a substrate 210 may include a dielectric substrate 212 such as a BOX layer that is formed on a semiconductive layer 214 to form an SOI substrate in an embodiment.
- a semiconductive body 216 is disposed on the dielectric substrate 212 , and the semiconductive body 216 includes a first section 218 and a second section 220 .
- the semiconductive body 216 may also be referred to as a semiconductive fin, or just a fin as understood within this disclosure.
- the semiconductive body 216 is a silicon seed layer 216 .
- the first section 218 and the second section 220 may be differently doped, such as is set forth for the embodiments described in FIG. 1 . In other embodiments, the semiconductive body 216 is doped differently depending upon the specific application.
- An epitaxial film 222 is disposed above and on the semiconductive body 216 at the first section 218 .
- the epitaxial film 222 may be an SEG film 222 according to process embodiments.
- a diode junction 224 (represented by a dashed line) is formed at the semiconductive body 216 .
- a diode junction boundary 226 exists at the diode junction 224 in relation to the semiconductive body 216 .
- the epitaxial film 222 also exhibits a top surface 228 and a lateral surface.
- the lateral surface has been consumed, however, by a silicide first region 238 , but some of the top surface 228 remains exposed adjacent to the silicide first region 238 .
- the silicide first region 238 is formed in the epitaxial film 222 above the first section 218 , and a silicide second region 240 is formed in semiconductive body 216 at the second section 220 .
- the diode junction 224 is configured to allow vertical-diode activity and lateral-diode activity between the semiconductive body 216 at the first section 218 and the epitaxial film 222 .
- the apparatus 205 communicates to the outside world by a first contact 232 , disposed on the silicide first region 238 of the epitaxial film 222 at the top surface 228 , and by a second contact 234 , disposed upon the silicide second region 240 of the semiconductive body 216 at the second section 220 .
- a diode distance 236 represents the electrical length of the diode that is formed by the apparatus 205 .
- the silicide-blocking distance 242 represents the effect of masking during silicide formation, to obtain the spaced-apart silicide first region 238 and silicide second region 240 , respectively.
- the second contact 234 is vertically (z-direction) closer to the semiconductive body 216 than the first contact 232 . This is because the second contact 234 is disposed directly upon the semiconductive body 216 at the silicide second region 240 , and the first contact 232 is disposed upon the silicide first region 238 , which was formed from the epitaxial film 222 .
- FIG. 2 a is a cross-section elevation of an apparatus 200 during fabrication according to an embodiment.
- the apparatus 200 depicted in FIG. 2 a will be processed and described through FIG. 2 f to attain the apparatus 205 .
- the substrate 210 includes a dielectric substrate 212 such as a BOX layer that is formed on a semiconductive layer 214 to form an SOI substrate in an embodiment.
- FIG. 2 b is a cross-section elevation of the apparatus depicted in FIG. 2 a after further processing according to an embodiment.
- the apparatus 201 is further processed by the placement of a semiconductive body 216 on the dielectric substrate 212 .
- the semiconductive body 216 can be silicon, and can be referred to as a “seed silicon”, or more generally, a “seed semiconductor” to facilitate the formation of an epitaxial film upon the semiconductive body 216 .
- the semiconductive body 216 has been patterned to exhibit the lateral (x-dimension) footprint of a diode device that is being fabricated.
- the semiconductive body 216 exhibits both an upper surface 228 and lateral surfaces 230 .
- FIG. 2 c is a cross-section elevation of the apparatus depicted in FIG. 2 b after further processing according to an embodiment.
- the apparatus 202 is further processed by implantation of a portion of the semiconductive body 216 .
- a first mask 216 c allows for a first section 218 of the semiconductive body 216 to be protected during ion implantation, and a second section 220 of the semiconductive body 216 is implanted.
- the directional arrows 208 represent ion implantation.
- the first mask 216 c allows the first section 218 to be differently doped from the second section 220 , such as is set forth for the embodiments described in FIG. 1 .
- Other doping-difference schemes may be carried out depending upon a given application.
- FIG. 2 d is a cross-section elevation of the apparatus depicted in FIG. 2 c after further processing according to an embodiment.
- the apparatus 203 is further processed by the selective epitaxial growth (SEG) of the epitaxial film 222 .
- a second mask 216 d blocks a portion of the semiconductive body 216 , such that the epitaxial film 222 forms opposite the second mask 216 d .
- the epitaxial film 222 is doped in situ during SEG-film growth.
- the epitaxial film 222 is first grown such as by SEG processing, and the second mask 216 d may be used as a blocking second mask, to allow for ion implantation of the epitaxial film 222 .
- some or all of the lateral portion of the epitaxial film 222 is doped to a higher concentration as compared to the exposed upper portion at the top surface 228 .
- FIG. 2 e is a cross-section elevation of the apparatus depicted in FIG. 2 d after further processing according to an embodiment.
- the apparatus 204 is further processed by formation of a third mask 216 e that facilitates a silicide block of a portion of the apparatus 204 , during the growth of the silicide first region 238 and the silicide second region 240 .
- the third mask 216 e is a hard nitride mask such as a silicon nitride material, that resists the growth of silicides. It can be seen that the silicide first region 238 has formed on the upper surface 228 and has consumed a part of the lateral surface and the vertical surface of the epitaxial film 222 .
- the third mask 216 e has left a spaced-apart silicide first region 238 , from the silicide second region 240 .
- the presence of silicide can lower resistance for the diode apparatus 205 .
- a silicide-blocking distance 242 represents the effect of masking during silicide formation, to obtain the spaced-apart silicide first region 238 and silicide second region 240 , respectively.
- FIG. 3 is a cross-sectional elevation of an apparatus 300 that can exhibit vertical-diode activity according to an embodiment.
- a substrate 310 may include a dielectric substrate 312 upon a semiconductive substrate 314 , to form a BOX layer 312 to form an SOI substrate in an embodiment.
- a semiconductive body 316 is disposed on the BOX layer 314 .
- the semiconductive body 316 may also be referred to as a semiconductive fin, or just a fin as understood within this disclosure.
- An epitaxial film 322 is disposed above and on the semiconductive body 316 , where the semiconductive body 316 has acted as a seed layer.
- the epitaxial film 322 is referred to as an epitaxial first film 322 .
- An epitaxial second film 344 is also disposed above and on the semiconductive body 316 .
- a first diode junction 324 (represented by a dashed line) is formed at the semiconductive body 316 .
- a diode first boundary 326 is also indicated.
- a second diode junction 346 is also exhibited between the epitaxial first film 322 and the epitaxial second film 344 .
- the epitaxial first film 322 also exhibits a top surface 328 and a lateral surface.
- the lateral surface has been in part consumed, however, by a silicide first region 338 , but some of the top surface 328 remains exposed adjacent to the silicide first region 338 .
- the epitaxial second film 344 also exhibits the top surface 328 and a lateral surface.
- the lateral surface has also been in part consumed, however, by a silicide second region 340 , but some of the top surface 328 remains exposed adjacent to the silicide second region 340 .
- the silicide first region 338 is formed in the epitaxial first film 322 above the semiconductive body 316 and the silicide second region 340 is formed in the epitaxial second film 344 above semiconductive body 316 .
- a silicide-blocking distance 342 represents the effect of masking during silicide formation, to obtain the spaced-apart silicide first region 338 and silicide second region 340 , respectively.
- the first diode junction 324 is configured to allow vertical-diode activity and lateral-diode activity between the semiconductive body 316 and the epitaxial first film 322 .
- the first diode junction 324 is locatable below the epitaxial second film 344 , between the epitaxial second film 344 and the semiconductive body 316 .
- the location of the first diode junction, however, whether it is below the epitaxial first film 322 or the epitaxial second film 344 will be selected based upon a given application and doping rules.
- a second diode junction 346 can also occur between the epitaxial first film 322 and the epitaxial second film 344 .
- the apparatus 300 can exhibit two diode activities; one at the first diode junction 324 , and another at the second diode junction 346 . Consequently, forward- and reverse breakdown can be tailored with the first- and second diode junctions 324 and 346 , respectively.
- the apparatus 300 communicates to the outside world by a first contact 332 , disposed on the epitaxial first film 322 at the top surface 328 , and by a second contact 334 , disposed upon the epitaxial second film 344 , also at the top surface 328 . Consequently, the contacts are coupleable to external structures.
- FIG. 4 is a cross-sectional elevation of an apparatus 400 that can exhibit lateral- and vertical-diode activity according to an embodiment.
- a substrate 410 may include a dielectric substrate 412 upon a semiconductive substrate 414 , to form a BOX layer 412 to form an SOI substrate in an embodiment.
- a semiconductive body 416 is disposed on the BOX layer 412 .
- the semiconductive body 416 may also be referred to as a semiconductive fin, or just a fin as understood within this disclosure.
- An epitaxial film 422 is disposed above and on the semiconductive body 416 .
- the epitaxial film 422 is referred to as an epitaxial first film 422 .
- An epitaxial second film 444 is also disposed above and on the semiconductiv body 416 .
- the epitaxial first film 422 and the epitaxial second film 444 are formed during distinct SEG processes, such as an in situ N+ SEG process for the epitaxial first film 422 and an in situ P+ process for the epitaxial second film 444 .
- the fin 416 is a semiconductive body 416 that is one of P ⁇ , N ⁇ , seed silicon.
- a diode junction 424 (represented by a dashed line) is formed at the semiconductive body 416 .
- a diode first boundary 426 is also indicated.
- the epitaxial first film 422 also exhibits a top surface 428 and a lateral surface. The lateral surface has been consumed, however, by a silicide first region 438 , but some of the top surface 428 remains exposed adjacent to the silicide first region 438 .
- the epitaxial second film 444 also exhibits the top surface 448 and a lateral surface. The lateral surface has also been consumed, however, by a silicide second region 440 , but some of the top surface 448 remains exposed adjacent to the silicide second region 440 .
- the diode junction 424 is configured to allow vertical-diode activity and lateral-diode activity between the semiconductive body 416 and the epitaxial second film 444 .
- the diode junction 424 may be locatable below the epitaxial first film 444 , between the epitaxial first film 444 and the semiconductive body 416 .
- the diode junction location, whether below the epitaxial first film 422 or the epitaxial second film 444 will be selected based upon a given application and doping rules.
- the apparatus 400 communicates to the outside world by a first contact 432 , disposed on the silicide first region 438 of the epitaxial first film 422 at the top surface 428 , and by a second contact 434 , disposed upon the epitaxial second film 444 , also at the top surface 448 . Consequently, the contacts are coupleable to external structures.
- a diode distance 426 represents the electrical length of the diode that is formed by the apparatus 400 .
- An epitaxial-film blocking distance 426 represents the effect of masking during epitaxial film formation, to obtain the spaced-apart epitaxial first film 422 and the epitaxial second film 444 .
- a silicide blocking distance 442 represents the effect of masking during silicide formation.
- FIG. 5 is a top plan of an apparatus 500 according to an embodiment. A portion of the structures are removed and others are presented in phantom lines for clarity.
- a substrate may include a dielectric substrate 512 upon a semiconductive substrate that is obscured in this illustration (see FIGS. 6 and 7 ), to form a BOX layer 512 that in turn can form an SOI substrate in an embodiment.
- a semiconductive body 516 is represented with recesses 515 formed therein between rows of contacts 532 and 534 . The contacts 532 and 534 , however, are depicted only as projections upon the epitaxial second film 544 .
- the semiconductive body 516 is disposed on the BOX layer 512 and the semiconductive body 516 has been etched to form fins 516 that are defined in part by the recesses 515 .
- the semiconductive body 516 may include sections that are not in a fin shape, the reference to the fin 516 is that portion between two recesses 515 , and consequently that fin portion 516 that is used as a diode structure.
- multiple semiconductor bodies are connected in parallel as illustrated, by coupling a first section to a first group of contacts 532 , and a second section to a second group of contacts 534 .
- This configuration allows for adjusting the current drivability of a diode that includes multiple fin bodies 516 .
- An epitaxial first film 522 is disposed above and on the semiconductive body 516 .
- the epitaxial second film 544 is also disposed above and on the semiconductive body 512 . These films are exposed such that the silicide films have been omitted from the illustration.
- the epitaxial first film 522 also exhibits a top surface and a lateral surface, although the top- and lateral surfaces are partly consumed during silicidation.
- the epitaxial second film 544 also exhibits a top surface and a lateral surface.
- FIG. 5 also illustrates a gate 550 and spacers 552 and 554 .
- FIG. 6 is a cross-sectional elevation of the apparatus depicted in FIG. 5 , taken along the section line 6 - 6 according to an embodiment.
- the substrate 510 is illustrated with a dielectric substrate 512 upon a semiconductive substrate 514 .
- the semiconductive body 516 is disposed on the BOX layer 512 in this embodiment.
- the semiconductive body 516 may also be referred to as a semiconductive fin, or just a fin as understood within this disclosure.
- the epitaxial first film 522 is disposed above and on the semiconductive body 516 , as well as the epitaxial second film 544 .
- a diode junction 524 (represented by a dashed line) is formed at the semiconductive body 516 below the epitaxial first film 522 .
- the diode junction 524 is configured to allow vertical-diode activity and lateral-diode activity between the semiconductive body 516 and the epitaxial first film 522 .
- a diode first boundary 526 is also indicated.
- the diode junction 524 is locatable below the epitaxial second film 544 .
- the diode junction location, whether below the epitaxial first film 522 or the epitaxial second film 544 , will be selected based upon a given application and doping rules.
- the apparatus 500 communicates to the outside world by a group of contacts, one of which is the first contact 532 .
- the first contact is disposed on the silicide first region 538 of the epitaxial first film 522 , and by a group of contacts, one of which is the second contact 534 .
- the second contact is disposed on the silicide second region 540 of upon the epitaxial second film 544 . Consequently, the contacts are coupleable to external structures.
- the apparatus 500 also communicates to the outside world by the gate silicide 550 and a gate layer 560 .
- a gate length 536 represents the approximate electrical length of the silicided-gate diode that is formed by the apparatus 500 .
- the gate silicide 550 is part of a gate-stack structure with the spacers 552 and 554 and the gate layer 560 that is disposed above and on the semiconductive body 516 .
- the gate silicide 550 is formed above the gate layer 560 , which has been grown according to an embodiment.
- the gate layer 560 is a metal.
- the gate layer 560 is a thin layer of metal adjacent to the gate dielectric layer 558 .
- the gate layer 560 is a polycrystalline silicon that is grown upon the gate dielectric layer 558 , which may be formed by oxidation.
- the gate dielectric layer 558 is disposed above and on the fin-shaped semiconductive body 556 .
- the gate dielectric layer 558 is an oxide.
- the gate dielectric layer 558 is an oxynitride.
- the semiconductive body 516 can be seen to be sectioned according to doping, into a first doping region 518 , a second doping region 520 , and the fin-shaped (finned) semiconductive body 556 , which together can also be referred to as a FINFET doping region 556 .
- the first doping region 518 and the second doping region 520 of the semiconductive body 516 may be differently doped, such as in an embodiment, the first doping region 518 is N ⁇ extension implanted and the second doping region 520 is P ⁇ extension implanted.
- the first contact 532 is referred to as a cathode and the second contact 534 is referred to as an anode.
- the FINFET doping region 556 may also be differently doped from the first doping region 518 and the second doping region 520 .
- the FINFET doping region 556 may also be similarly doped with respect to one of the first doping region 518 or the second doping region 520 or it may be undoped.
- FIG. 7 is a cross-sectional elevation of the apparatus depicted in FIG. 5 , taken along the section line 7 - 7 according to an embodiment.
- the substrate 510 includes the dielectric substrate 512 upon the semiconductive substrate 514 .
- the semiconductive body 516 is disposed on the BOX layer 514 .
- the epitaxial first film 522 and the epitaxial second film 544 are also disposed above and on the semiconductive body 516 .
- the epitaxial first film 522 as well as the epitaxial second film 544 have been covered with the respective silicide first region 538 and silicide second region 540 .
- the gate structure has acted as a blocking structure to prevent a shorting merger between the silicide first region 538 and silicide second region 540 .
- FIG. 8 is a cross-sectional elevation of an apparatus according to an embodiment.
- a substrate 810 is illustrated with a dielectric substrate 812 upon a semiconductive substrate 814 .
- a semiconductive body 816 is disposed on the BOX layer 812 .
- the semiconductive body 816 may also be referred to as a semiconductive fin, or just a fin as understood within this disclosure.
- An epitaxial first film 822 is disposed above and on the semiconductive body 816 , as well as an epitaxial second film 844 .
- a diode junction 824 (represented by a dashed line) is formed at the semiconductive body 816 below the epitaxial first film 822 .
- a diode first boundary 826 is also indicated.
- the diode junction 824 is configured to allow vertical-diode activity and lateral-diode activity between the semiconductive body 816 and the epitaxial first film 822 .
- the diode junction 824 is locatable below the epitaxial second film 844 . The diode junction location, whether below the epitaxial first film 822 or the epitaxial second film 844 , will be selected based upon a given application and doping rules.
- both the epitaxial first film 822 and the epitaxial second film 844 are grown at the same time.
- a nitride mask 860 is used to block the growth of silicide, and it also is used to facilitate a self-aligned growth of the SEG films 822 and 844 .
- the N+ and P+ source/drain masks are alternatively used to implant each of the epitaxial first film 822 and the epitaxial second film 844 .
- the implantation process 862 therefore may be two separate implantation processes, and implantation processes are used to dope the SEG films 822 and 844 as well as selected parts of the semiconductive body 816 disposed upon the dielectric substrate 812 .
- the nitride mask 860 also prevents unplanned implantation doping 862 of the FINFET doping region 856 .
- the first doping region 818 and the second doping region 820 of the semiconductive body 816 may be differently doped.
- the FINFET doping region 856 may also be differently doped from the first doping region 818 or the second doping region 820 .
- the FINFET doping region 856 may also be similarly doped with respect to one of the first doping region 818 or the second doping region 820 .
- the apparatus 800 communicates to the outside world by a first contact 832 , disposed on the silicide first region 838 of the epitaxial first film 822 , and by a second contact 834 , disposed on the silicide second region 840 of the epitaxial second film 844 . Consequently, the contacts are coupleable to external structures. It can now be appreciated that the semiconductive body 816 can be configured as a semiconductive fin.
- FIG. 9 is a cross-sectional elevation of an apparatus that can exhibit vertical-diode activity according to an embodiment.
- a substrate 910 is illustrated with a dielectric substrate 912 upon a semiconductive substrate 914 .
- a semiconductive body 916 is disposed on the BOX layer 912 .
- the semiconductive body 916 may also be referred to as a semiconductive fin, or just a fin as understood within this disclosure.
- An epitaxial first film 922 is disposed above and on the semiconductive body 916 , as well as an epitaxial second film 944 .
- a diode first boundary 926 is also indicated.
- a diode junction 924 (represented by a dashed line) is formed at the semiconductive body 916 below the epitaxial first film 922 .
- the diode junction 924 is configured to allow vertical-diode activity and lateral-diode activity between the semiconductive body 916 and the epitaxial first film 922 .
- the diode junction 924 may be locatable below the epitaxial second film 944 . The diode junction location, whether below the epitaxial first film 922 or the epitaxial second film 944 , will be selected based upon a given application and doping rules.
- the gate spacers 952 and 954 and a gate dielectric layer 958 are part of the gate structure.
- the gate dielectric layer 958 is disposed above and on the FINFET doping region 956 .
- the semiconductive body 916 can be seen to be sectioned according to doping, into a first doping region 918 , a second doping region 920 , and the FINFET doping region 956 of the semiconductive body 916 .
- a gate layer 960 is first formed, followed by extension implantation of the semiconductive body 916 on each side of the gate layer 960 .
- gate spacers 952 and 954 are formed, such as nitride materials, as well as the hard mask 961 . Growth of the SEG films 922 and 944 may follow, such that the hard mask 961 acts as a blocking mask to prevent SEG film formation.
- Doping of regions not protected by the hard mask 961 may next be carried out such as N+ doping of the first doping region 918 a , and P+ doping of the second doping region 920 a . These doping processes may be done by alternatively photomasking each of the first doping region 918 a and the second region 920 a.
- silicide first region 938 and of the silicide second region 940 may be carried out.
- both the epitaxial first film 922 and the epitaxial second film 944 are grown at the same time.
- Nitride hard masks may be used to block the growth of silicide above what becomes the first doping region 918 b and the second doping region 920 b .
- the masks may also be used to facilitate a self-aligned growth of the SEG films 922 and 944 .
- the N+ and P+ source/drain masks are alternatively used to implant each of the epitaxial first film 922 and the epitaxial second film 944 .
- the implantation process 962 therefore may be two separate implantation processes, and implantation processes are used to dope the SEG films 922 and 944 as well as selected parts of the semiconductive body 916 disposed upon the dielectric substrate 912 .
- the FINFET doping region 956 exhibits multiple electrical properties similarly to the gate structure depicted in FIG. 6 . Consequently, a multiple-fin FET apparatus 900 is formed of the various structures of the apparatus 600 when they are used in concert to act upon the FINFET doping region 956 of the semiconductive body 916 .
- both the epitaxial first film 922 and the epitaxial second film 944 are grown at the same time.
- the N+ and P+ source/drain masks and implantation processes are used to dope parts of the SEG films 922 and 944 as well as parts of the semiconductive body 916 disposed upon the dielectric substrate 912 .
- the nitride hard mask 961 is used to block the growth of silicide, and it also is used to facilitate a self-aligned SEG growth of the SEG films 922 and 944 . Further, the nitride hard mask 961 also prevents unplanned implantation dopings 962 of the FINFET doping region 956 .
- a diode distance 936 represents the electrical length of the diode that is formed by the FINFET diode apparatus 900 .
- the first doping region 918 and the second doping region 920 of the semiconductive body 916 may be differently doped.
- the first doping region 918 is doped differently as a first doping region 918 a and a first doping region 918 b .
- the different doping may arise due to fabrication with the presence or absence of various structures including the gate spacers 952 and 954 and the mask 961 .
- the second doping region 920 is doped differently as a second doping region 920 a and a second doping region 920 b .
- the FINFET doping region 956 may also be differently doped from the first doping region 918 and the second doping region 920 .
- the FINFET doping region 956 may also be similarly doped with respect to one of the first doping region 918 or the second doping region 920 .
- a FINFET diode apparatus 900 of this type may be used to provide long and quasi-graded anode and cathode regions for lowered leakage and increased reverse breakdown voltages, while still making use of the low resistivity and thermally useful SEG films.
- the apparatus 900 communicates to the outside world by the first contact 932 , disposed on the silicide first region 938 of the epitaxial first film 922 , and by a second contact 934 , disposed on the silicide second region 940 of the epitaxial second film 944 . Consequently, the contacts are coupleable to external structures.
- the apparatus 900 also communicates to the outside world through a gate structure that includes the gate layer 960 that exhibits a gate length 959 . It can now be appreciated that the semiconductive body 916 can be configured as a semiconductive fin.
- FIG. 10 is a process-flow diagram according to some embodiments.
- the process includes patterning a semiconductive body upon a dielectric substrate.
- the process includes imposing a doping differential between a first doping region of the semiconductive body and a second doping region of the semiconductive body.
- the process includes forming an in situ doped SEG film upon the first doping region or upon the second doping region of the semiconductive body.
- the process includes forming a silicide first region to make contact to the SEG first film.
- the process includes forming a silicide second region to make contact to the SEG second film.
- the process includes coupling the SEG first film to an external structure.
- the process includes coupling the SEG second film to an external structure.
- FIG. 11 is a process-flow diagram according to some embodiments.
- the process includes patterning a semiconductive body, also referred to as a fin, upon a dielectric substrate.
- the process includes forming a gate above and on the fin.
- the process includes extension implanting the fin about the gate.
- the process includes forming a gate spacer about the gate.
- the process includes forming a hard mask above and on the semiconductive fin.
- a first photo mask and resist covers the semiconductive body at the second doping region while implantation is carried out in the semiconductive body at the first section.
- a subsequent photo mask and resist covers the semiconductive body at the first doping region while implantation is carried out in the semiconductive body at the second section.
- processing may proceed directly from 1110 to 1130 as is illustrated in FIG. 8
- the process includes forming an SEG film upon the first doping region or upon the second doping region of the semiconductive body.
- the process includes implanting the first SEG film.
- the process includes implanting the second SEG film.
- the process includes forming a silicide first region to make contact to the SEG first film.
- the process includes forming a silicide second region to make contact to the SEG second film.
- the process includes coupling the SEG first film to an external structure.
- the process includes coupling the SEG second film to an external structure.
- FIG. 12 illustrates an electronic device 1200 that includes a vertical-diode apparatus embodiment such described above.
- the electronic device 1200 can be referred to as an external structure.
- Components of the electronic device 1200 can also be referred to as an external structure.
- sub-components, such as first area of a semiconductive device that on the same chip of a vertical-diode apparatus embodiment can also be referred to as an external structure.
- the electronic device 1200 includes a first component 1220 that benefits from coupling to a vertical-diode apparatus.
- first component 1220 include electrostatic discharge (ESD) functionalities such as in an output driver.
- ESD electrostatic discharge
- Another example of the first component 1220 includes an ESD functionality in a logic circuit. In these examples, device operation is improved with the presence of a vertical-diode apparatus.
- the device 1200 further includes a power source 1230 .
- the power source 1230 is electrically connected to the first device component 1220 using interconnecting circuitry 1240 .
- the interconnecting circuitry 1240 includes a vertical-diode apparatus embodiment.
- the device 1200 further includes a second device component 1210 .
- the second component is electrically connected to the first component 1220 using interconnecting circuitry 1242 .
- the interconnecting circuitry 1242 includes a vertical-diode apparatus embodiment.
- second device components 1210 include signal amplifiers, memory structures, logic circuitry, output circuits, ESD circuits, or other microprocessing apparatus.
- the first device component 1220 and/or the second device component 1210 includes vertical-diode apparatus embodiment formed according to process embodiments described above.
- Embodiments disclosed herein are suitable for application in embodiments of microelectronic devices that require passive devices near the microelectronic portions.
- embodiments of the system discussed may be used in a wide range of wireless communication devices such as cellular phone, mobile computers, and other handheld wireless digital devices.
- inventive subject matter may be referred to herein, individually and/or collectively, by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed.
- inventive concept merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed.
- inventive subject matter is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description.
- the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ”.
Abstract
Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.
Description
- This application is a Divisional of U.S. application Ser. No. 12/986,875, filed on Jan. 7, 2011, which is a Divisional of U.S. application Ser. No. 11/862,964, filed on Sep. 27, 2007, which applications are incorporated herein by reference in their entirety.
- Embodiments described herein relate generally to diodes and to gated diodes.
- Diodes are used with microelectronic devices such as for electrostatic discharge protectants in sensitive solid-state circuits. Miniaturization is the process of crowding more devices, both passive and active, onto the same or an even smaller footprint of a microelectronic device. The crowding of more diodes into even smaller areas, poses significant challenges.
-
FIG. 1 is a cross-section elevation of an apparatus according to an embodiment. -
FIGS. 2 a-2 f represent cross-section elevations of an apparatus during processing according to an embodiment. -
FIG. 3 is a cross-sectional elevation of an apparatus that can exhibit vertical-diode activity according to an embodiment. -
FIG. 4 is a cross-sectional elevation of an apparatus that can exhibit lateral- and vertical-diode activity according to an embodiment. -
FIG. 5 is a top plan of an apparatus that can exhibit vertical-diode activity according to an embodiment. -
FIG. 6 is a cross-sectional elevation of the apparatus depicted inFIG. 5 , taken along the section line 6-6 according to an embodiment. -
FIG. 7 is a cross-sectional elevation of the apparatus depicted inFIG. 5 , taken along the section line 7-7 according to an embodiment. -
FIG. 8 is a cross-sectional elevation of an apparatus that can exhibit vertical-diode activity according to an embodiment. -
FIG. 9 is a cross-sectional elevation of an apparatus that can exhibit vertical-diode activity according to an embodiment. -
FIG. 10 is a process-flow diagram according to some embodiments. -
FIG. 11 is a process-flow diagram according to some embodiments. -
FIG. 12 is a illustrates an electronic device that includes vertical-diode apparatus embodiment such described herein. - The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which embodiments may be practiced. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the disclosed embodiments. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. Like structures may be seen in the various figures with like reference numerals.
-
FIG. 1 is a cross-section elevation of anapparatus 100, according to an embodiment. Asubstrate 110 may include adielectric substrate 112 such as a buried oxide (BOX) layer on asemiconductive substrate 114 to form a semiconductor on insulator (SOI) substrate in an embodiment. Asemiconductive body 116 is disposed on theBOX layer 112, and thesemiconductive body 116 includes afirst section 118 and asecond section 120. In an embodiment, thesemiconductive body 116 is disposed upon thedielectric substrate 112. In an embodiment, thesemiconductive body 116 is disposed upon a bulk semiconductor, in which case both thestructure 112 and thestructure 114 are semiconductor materials, and they may be integral. - The
semiconductive body 116 may also be referred to as a semiconductive fin, or just a fin as understood within this disclosure. Thefirst section 118 and thesecond section 120 may be differently doped, such as thefirst section 118 being undoped and thesecond section 120 being P+ doped. In an embodiment, thefirst section 118 is slightly P-doped to thesecond section 120 being P+ doped. In an embodiment, thefirst section 118 is slightly N-doped to thesecond section 120 being P+ doped. Other doping-difference schemes may be selected depending upon an application. - An
epitaxial film 122 is disposed above and on thesemiconductive body 116 at thefirst section 118. In an embodiment,epitaxial film 122 is grown upon selected regions of thesemiconductive body 116. Thesemiconductive body 116 can therefore be referred to as asemiconductive seed layer 116, and theepitaxial film 122 can be referred to as a selective-growth (SEG)epitaxial film 122. - A diode junction 124 (represented by a dashed line) is formed at the
semiconductive body 116. Adiode junction boundary 126 exists at thediode junction 124 in relation to thesemiconductive body 116. Thediode junction 124 is configured to allow vertical-diode (z-direction) activity between thesemiconductive body 116 at thefirst section 118 and theepitaxial film 122. - The
epitaxial film 122 also exhibits atop surface 128 and alateral surface 130. Theapparatus 100 communicates to the outside world by afirst contact 132, disposed on theepitaxial film 122 at thetop surface 128, and by asecond contact 134, disposed upon thesemiconductive body 116 at thesecond section 120. Consequently, the contacts are coupleable to external structures. Adiode distance 136 represents the electrical length of the diode that is formed by theapparatus 100. - It can be seen that the
second contact 134 is vertically closer to thesemiconductive body 116 than thefirst contact 132. This is because thesecond contact 134 is disposed directly upon thesemiconductive body 116, and thefirst contact 132 is disposed upon theepitaxial film 122. -
FIGS. 2 a-2 f represent a cross-section elevation of an apparatus during processing according to an embodiment.FIG. 2 f is a cross-section elevation of anapparatus 205 that can exhibit vertical diode activity according to an embodiment. FIG. 2 f represents a processed apparatus that is process-illustrated inFIGS. 2 a, 2 b, 2 c, 2 d, 2 e, and 2 f. - A
substrate 210 may include adielectric substrate 212 such as a BOX layer that is formed on asemiconductive layer 214 to form an SOI substrate in an embodiment. Asemiconductive body 216 is disposed on thedielectric substrate 212, and thesemiconductive body 216 includes afirst section 218 and asecond section 220. Thesemiconductive body 216 may also be referred to as a semiconductive fin, or just a fin as understood within this disclosure. In an embodiment, thesemiconductive body 216 is asilicon seed layer 216. Thefirst section 218 and thesecond section 220 may be differently doped, such as is set forth for the embodiments described inFIG. 1 . In other embodiments, thesemiconductive body 216 is doped differently depending upon the specific application. - An
epitaxial film 222 is disposed above and on thesemiconductive body 216 at thefirst section 218. Theepitaxial film 222 may be anSEG film 222 according to process embodiments. A diode junction 224 (represented by a dashed line) is formed at thesemiconductive body 216. Adiode junction boundary 226 exists at thediode junction 224 in relation to thesemiconductive body 216. - The
epitaxial film 222 also exhibits atop surface 228 and a lateral surface. The lateral surface has been consumed, however, by a silicidefirst region 238, but some of thetop surface 228 remains exposed adjacent to the silicidefirst region 238. The silicidefirst region 238 is formed in theepitaxial film 222 above thefirst section 218, and a silicidesecond region 240 is formed insemiconductive body 216 at thesecond section 220. - The
diode junction 224 is configured to allow vertical-diode activity and lateral-diode activity between thesemiconductive body 216 at thefirst section 218 and theepitaxial film 222. - The
apparatus 205 communicates to the outside world by afirst contact 232, disposed on the silicidefirst region 238 of theepitaxial film 222 at thetop surface 228, and by asecond contact 234, disposed upon the silicidesecond region 240 of thesemiconductive body 216 at thesecond section 220. Adiode distance 236 represents the electrical length of the diode that is formed by theapparatus 205. The silicide-blocking distance 242 represents the effect of masking during silicide formation, to obtain the spaced-apart silicidefirst region 238 and silicidesecond region 240, respectively. - It can be seen that the
second contact 234 is vertically (z-direction) closer to thesemiconductive body 216 than thefirst contact 232. This is because thesecond contact 234 is disposed directly upon thesemiconductive body 216 at the silicidesecond region 240, and thefirst contact 232 is disposed upon the silicidefirst region 238, which was formed from theepitaxial film 222. -
FIG. 2 a is a cross-section elevation of anapparatus 200 during fabrication according to an embodiment. Theapparatus 200 depicted inFIG. 2 a will be processed and described throughFIG. 2 f to attain theapparatus 205. Thesubstrate 210 includes adielectric substrate 212 such as a BOX layer that is formed on asemiconductive layer 214 to form an SOI substrate in an embodiment. -
FIG. 2 b is a cross-section elevation of the apparatus depicted inFIG. 2 a after further processing according to an embodiment. Theapparatus 201 is further processed by the placement of asemiconductive body 216 on thedielectric substrate 212. Thesemiconductive body 216 can be silicon, and can be referred to as a “seed silicon”, or more generally, a “seed semiconductor” to facilitate the formation of an epitaxial film upon thesemiconductive body 216. Thesemiconductive body 216 has been patterned to exhibit the lateral (x-dimension) footprint of a diode device that is being fabricated. Thesemiconductive body 216 exhibits both anupper surface 228 andlateral surfaces 230. -
FIG. 2 c is a cross-section elevation of the apparatus depicted inFIG. 2 b after further processing according to an embodiment. Theapparatus 202 is further processed by implantation of a portion of thesemiconductive body 216. Afirst mask 216 c allows for afirst section 218 of thesemiconductive body 216 to be protected during ion implantation, and asecond section 220 of thesemiconductive body 216 is implanted. Thedirectional arrows 208 represent ion implantation. In any event, thefirst mask 216 c allows thefirst section 218 to be differently doped from thesecond section 220, such as is set forth for the embodiments described inFIG. 1 . Other doping-difference schemes may be carried out depending upon a given application. -
FIG. 2 d is a cross-section elevation of the apparatus depicted inFIG. 2 c after further processing according to an embodiment. Theapparatus 203 is further processed by the selective epitaxial growth (SEG) of theepitaxial film 222. Asecond mask 216 d blocks a portion of thesemiconductive body 216, such that theepitaxial film 222 forms opposite thesecond mask 216 d. In an embodiment, theepitaxial film 222 is doped in situ during SEG-film growth. In an embodiment, theepitaxial film 222 is first grown such as by SEG processing, and thesecond mask 216 d may be used as a blocking second mask, to allow for ion implantation of theepitaxial film 222. When ion implantation is carried out, however, some or all of the lateral portion of theepitaxial film 222 is doped to a higher concentration as compared to the exposed upper portion at thetop surface 228. -
FIG. 2 e is a cross-section elevation of the apparatus depicted inFIG. 2 d after further processing according to an embodiment. Theapparatus 204 is further processed by formation of athird mask 216 e that facilitates a silicide block of a portion of theapparatus 204, during the growth of the silicidefirst region 238 and the silicidesecond region 240. In an embodiment, thethird mask 216 e is a hard nitride mask such as a silicon nitride material, that resists the growth of silicides. It can be seen that the silicidefirst region 238 has formed on theupper surface 228 and has consumed a part of the lateral surface and the vertical surface of theepitaxial film 222. - Reference is again made to
FIG. 2 f. It can be seen that thethird mask 216 e has left a spaced-apart silicidefirst region 238, from the silicidesecond region 240. The presence of silicide can lower resistance for thediode apparatus 205. A silicide-blocking distance 242 represents the effect of masking during silicide formation, to obtain the spaced-apart silicidefirst region 238 and silicidesecond region 240, respectively. -
FIG. 3 is a cross-sectional elevation of anapparatus 300 that can exhibit vertical-diode activity according to an embodiment. Asubstrate 310 may include adielectric substrate 312 upon asemiconductive substrate 314, to form aBOX layer 312 to form an SOI substrate in an embodiment. Asemiconductive body 316 is disposed on theBOX layer 314. Thesemiconductive body 316 may also be referred to as a semiconductive fin, or just a fin as understood within this disclosure. Anepitaxial film 322 is disposed above and on thesemiconductive body 316, where thesemiconductive body 316 has acted as a seed layer. Hereinafter, theepitaxial film 322 is referred to as an epitaxialfirst film 322. An epitaxialsecond film 344 is also disposed above and on thesemiconductive body 316. A first diode junction 324 (represented by a dashed line) is formed at thesemiconductive body 316. A diodefirst boundary 326 is also indicated. Asecond diode junction 346 is also exhibited between the epitaxialfirst film 322 and the epitaxialsecond film 344. - The epitaxial
first film 322 also exhibits atop surface 328 and a lateral surface. The lateral surface has been in part consumed, however, by a silicidefirst region 338, but some of thetop surface 328 remains exposed adjacent to the silicidefirst region 338. The epitaxialsecond film 344 also exhibits thetop surface 328 and a lateral surface. The lateral surface has also been in part consumed, however, by a silicidesecond region 340, but some of thetop surface 328 remains exposed adjacent to the silicidesecond region 340. The silicidefirst region 338 is formed in the epitaxialfirst film 322 above thesemiconductive body 316 and the silicidesecond region 340 is formed in the epitaxialsecond film 344 abovesemiconductive body 316. A silicide-blocking distance 342 represents the effect of masking during silicide formation, to obtain the spaced-apart silicidefirst region 338 and silicidesecond region 340, respectively. - The
first diode junction 324 is configured to allow vertical-diode activity and lateral-diode activity between thesemiconductive body 316 and the epitaxialfirst film 322. In an embodiment, thefirst diode junction 324 is locatable below the epitaxialsecond film 344, between the epitaxialsecond film 344 and thesemiconductive body 316. The location of the first diode junction, however, whether it is below the epitaxialfirst film 322 or the epitaxialsecond film 344, will be selected based upon a given application and doping rules. - A
second diode junction 346 can also occur between the epitaxialfirst film 322 and the epitaxialsecond film 344. In an embodiment, theapparatus 300 can exhibit two diode activities; one at thefirst diode junction 324, and another at thesecond diode junction 346. Consequently, forward- and reverse breakdown can be tailored with the first- andsecond diode junctions - The
apparatus 300 communicates to the outside world by afirst contact 332, disposed on the epitaxialfirst film 322 at thetop surface 328, and by asecond contact 334, disposed upon the epitaxialsecond film 344, also at thetop surface 328. Consequently, the contacts are coupleable to external structures. -
FIG. 4 is a cross-sectional elevation of anapparatus 400 that can exhibit lateral- and vertical-diode activity according to an embodiment. Asubstrate 410 may include adielectric substrate 412 upon asemiconductive substrate 414, to form aBOX layer 412 to form an SOI substrate in an embodiment. Asemiconductive body 416 is disposed on theBOX layer 412. Thesemiconductive body 416 may also be referred to as a semiconductive fin, or just a fin as understood within this disclosure. - An
epitaxial film 422 is disposed above and on thesemiconductive body 416. Hereinafter, theepitaxial film 422 is referred to as an epitaxialfirst film 422. An epitaxialsecond film 444 is also disposed above and on thesemiconductiv body 416. In an embodiment, the epitaxialfirst film 422 and the epitaxialsecond film 444 are formed during distinct SEG processes, such as an in situ N+ SEG process for the epitaxialfirst film 422 and an in situ P+ process for the epitaxialsecond film 444. In an embodiment, where the epitaxialfirst film 422 is in situ N+ SEG processed, and where the epitaxialsecond film 444 is in situ P+ processed, thefin 416 is asemiconductive body 416 that is one of P−, N−, seed silicon. - A diode junction 424 (represented by a dashed line) is formed at the
semiconductive body 416. A diodefirst boundary 426 is also indicated. The epitaxialfirst film 422 also exhibits atop surface 428 and a lateral surface. The lateral surface has been consumed, however, by a silicidefirst region 438, but some of thetop surface 428 remains exposed adjacent to the silicidefirst region 438. The epitaxialsecond film 444 also exhibits thetop surface 448 and a lateral surface. The lateral surface has also been consumed, however, by a silicidesecond region 440, but some of thetop surface 448 remains exposed adjacent to the silicidesecond region 440. - The
diode junction 424 is configured to allow vertical-diode activity and lateral-diode activity between thesemiconductive body 416 and the epitaxialsecond film 444. In an embodiment, thediode junction 424 may be locatable below the epitaxialfirst film 444, between the epitaxialfirst film 444 and thesemiconductive body 416. The diode junction location, whether below the epitaxialfirst film 422 or the epitaxialsecond film 444, will be selected based upon a given application and doping rules. - The
apparatus 400 communicates to the outside world by afirst contact 432, disposed on the silicidefirst region 438 of the epitaxialfirst film 422 at thetop surface 428, and by asecond contact 434, disposed upon the epitaxialsecond film 444, also at thetop surface 448. Consequently, the contacts are coupleable to external structures. Adiode distance 426 represents the electrical length of the diode that is formed by theapparatus 400. An epitaxial-film blocking distance 426 represents the effect of masking during epitaxial film formation, to obtain the spaced-apart epitaxialfirst film 422 and the epitaxialsecond film 444. Asilicide blocking distance 442 represents the effect of masking during silicide formation. -
FIG. 5 is a top plan of anapparatus 500 according to an embodiment. A portion of the structures are removed and others are presented in phantom lines for clarity. A substrate may include adielectric substrate 512 upon a semiconductive substrate that is obscured in this illustration (seeFIGS. 6 and 7 ), to form aBOX layer 512 that in turn can form an SOI substrate in an embodiment. Asemiconductive body 516 is represented withrecesses 515 formed therein between rows ofcontacts contacts second film 544. - The
semiconductive body 516 is disposed on theBOX layer 512 and thesemiconductive body 516 has been etched to formfins 516 that are defined in part by therecesses 515. As thesemiconductive body 516 may include sections that are not in a fin shape, the reference to thefin 516 is that portion between tworecesses 515, and consequently thatfin portion 516 that is used as a diode structure. - In an embodiment, multiple semiconductor bodies are connected in parallel as illustrated, by coupling a first section to a first group of
contacts 532, and a second section to a second group ofcontacts 534. This configuration allows for adjusting the current drivability of a diode that includesmultiple fin bodies 516. - An epitaxial
first film 522 is disposed above and on thesemiconductive body 516. The epitaxialsecond film 544 is also disposed above and on thesemiconductive body 512. These films are exposed such that the silicide films have been omitted from the illustration. - The epitaxial
first film 522 also exhibits a top surface and a lateral surface, although the top- and lateral surfaces are partly consumed during silicidation. The epitaxialsecond film 544 also exhibits a top surface and a lateral surface.FIG. 5 also illustrates agate 550 andspacers -
FIG. 6 is a cross-sectional elevation of the apparatus depicted inFIG. 5 , taken along the section line 6-6 according to an embodiment. Thesubstrate 510 is illustrated with adielectric substrate 512 upon asemiconductive substrate 514. Thesemiconductive body 516 is disposed on theBOX layer 512 in this embodiment. Thesemiconductive body 516 may also be referred to as a semiconductive fin, or just a fin as understood within this disclosure. The epitaxialfirst film 522 is disposed above and on thesemiconductive body 516, as well as the epitaxialsecond film 544. A diode junction 524 (represented by a dashed line) is formed at thesemiconductive body 516 below the epitaxialfirst film 522. Thediode junction 524 is configured to allow vertical-diode activity and lateral-diode activity between thesemiconductive body 516 and the epitaxialfirst film 522. A diodefirst boundary 526 is also indicated. - In an embodiment, the
diode junction 524 is locatable below the epitaxialsecond film 544. The diode junction location, whether below the epitaxialfirst film 522 or the epitaxialsecond film 544, will be selected based upon a given application and doping rules. - Now referring to
FIG. 7 , theapparatus 500 communicates to the outside world by a group of contacts, one of which is thefirst contact 532. The first contact is disposed on the silicidefirst region 538 of the epitaxialfirst film 522, and by a group of contacts, one of which is thesecond contact 534. The second contact is disposed on the silicidesecond region 540 of upon the epitaxialsecond film 544. Consequently, the contacts are coupleable to external structures. Theapparatus 500 also communicates to the outside world by thegate silicide 550 and agate layer 560. Agate length 536 represents the approximate electrical length of the silicided-gate diode that is formed by theapparatus 500. - The
gate silicide 550 is part of a gate-stack structure with thespacers gate layer 560 that is disposed above and on thesemiconductive body 516. Thegate silicide 550 is formed above thegate layer 560, which has been grown according to an embodiment. In an embodiment, thegate layer 560 is a metal. In an embodiment, thegate layer 560 is a thin layer of metal adjacent to thegate dielectric layer 558. In an embodiment, thegate layer 560 is a polycrystalline silicon that is grown upon thegate dielectric layer 558, which may be formed by oxidation. - The
gate dielectric layer 558 is disposed above and on the fin-shapedsemiconductive body 556. In an embodiment, thegate dielectric layer 558 is an oxide. In an embodiment, thegate dielectric layer 558 is an oxynitride. - Further to
FIG. 6 , thesemiconductive body 516 can be seen to be sectioned according to doping, into afirst doping region 518, asecond doping region 520, and the fin-shaped (finned)semiconductive body 556, which together can also be referred to as aFINFET doping region 556. Thefirst doping region 518 and thesecond doping region 520 of thesemiconductive body 516 may be differently doped, such as in an embodiment, thefirst doping region 518 is N− extension implanted and thesecond doping region 520 is P− extension implanted. In this embodiment thefirst contact 532 is referred to as a cathode and thesecond contact 534 is referred to as an anode. - The
FINFET doping region 556 may also be differently doped from thefirst doping region 518 and thesecond doping region 520. TheFINFET doping region 556 may also be similarly doped with respect to one of thefirst doping region 518 or thesecond doping region 520 or it may be undoped. -
FIG. 7 is a cross-sectional elevation of the apparatus depicted inFIG. 5 , taken along the section line 7-7 according to an embodiment. Thesubstrate 510 includes thedielectric substrate 512 upon thesemiconductive substrate 514. Thesemiconductive body 516 is disposed on theBOX layer 514. The epitaxialfirst film 522 and the epitaxialsecond film 544 are also disposed above and on thesemiconductive body 516. - The epitaxial
first film 522 as well as the epitaxialsecond film 544 have been covered with the respective silicidefirst region 538 and silicidesecond region 540. The gate structure has acted as a blocking structure to prevent a shorting merger between the silicidefirst region 538 and silicidesecond region 540. -
FIG. 8 is a cross-sectional elevation of an apparatus according to an embodiment. Asubstrate 810 is illustrated with adielectric substrate 812 upon asemiconductive substrate 814. A semiconductive body 816 is disposed on theBOX layer 812. The semiconductive body 816 may also be referred to as a semiconductive fin, or just a fin as understood within this disclosure. An epitaxialfirst film 822 is disposed above and on the semiconductive body 816, as well as an epitaxialsecond film 844. A diode junction 824 (represented by a dashed line) is formed at the semiconductive body 816 below the epitaxialfirst film 822. A diodefirst boundary 826 is also indicated. Thediode junction 824 is configured to allow vertical-diode activity and lateral-diode activity between the semiconductive body 816 and the epitaxialfirst film 822. In an embodiment, thediode junction 824 is locatable below the epitaxialsecond film 844. The diode junction location, whether below the epitaxialfirst film 822 or the epitaxialsecond film 844, will be selected based upon a given application and doping rules. - In a process embodiment, both the epitaxial
first film 822 and the epitaxialsecond film 844 are grown at the same time. Anitride mask 860 is used to block the growth of silicide, and it also is used to facilitate a self-aligned growth of theSEG films - In an embodiment, the N+ and P+ source/drain masks are alternatively used to implant each of the epitaxial
first film 822 and the epitaxialsecond film 844. Theimplantation process 862 therefore may be two separate implantation processes, and implantation processes are used to dope theSEG films dielectric substrate 812. Further, thenitride mask 860 also preventsunplanned implantation doping 862 of theFINFET doping region 856. Thefirst doping region 818 and thesecond doping region 820 of the semiconductive body 816 may be differently doped. TheFINFET doping region 856 may also be differently doped from thefirst doping region 818 or thesecond doping region 820. TheFINFET doping region 856 may also be similarly doped with respect to one of thefirst doping region 818 or thesecond doping region 820. - The
apparatus 800 communicates to the outside world by afirst contact 832, disposed on the silicidefirst region 838 of the epitaxialfirst film 822, and by asecond contact 834, disposed on the silicidesecond region 840 of the epitaxialsecond film 844. Consequently, the contacts are coupleable to external structures. It can now be appreciated that the semiconductive body 816 can be configured as a semiconductive fin. -
FIG. 9 is a cross-sectional elevation of an apparatus that can exhibit vertical-diode activity according to an embodiment. Asubstrate 910 is illustrated with adielectric substrate 912 upon a semiconductive substrate 914. Asemiconductive body 916 is disposed on theBOX layer 912. Thesemiconductive body 916 may also be referred to as a semiconductive fin, or just a fin as understood within this disclosure. An epitaxialfirst film 922 is disposed above and on thesemiconductive body 916, as well as an epitaxialsecond film 944. A diodefirst boundary 926 is also indicated. - A diode junction 924 (represented by a dashed line) is formed at the
semiconductive body 916 below the epitaxialfirst film 922. Thediode junction 924 is configured to allow vertical-diode activity and lateral-diode activity between thesemiconductive body 916 and the epitaxialfirst film 922. In an embodiment, thediode junction 924 may be locatable below the epitaxialsecond film 944. The diode junction location, whether below the epitaxialfirst film 922 or the epitaxialsecond film 944, will be selected based upon a given application and doping rules. - The gate spacers 952 and 954 and a
gate dielectric layer 958 are part of the gate structure. Thegate dielectric layer 958 is disposed above and on theFINFET doping region 956. - Further to
FIG. 9 , thesemiconductive body 916 can be seen to be sectioned according to doping, into a first doping region 918, a second doping region 920, and theFINFET doping region 956 of thesemiconductive body 916. - In a process embodiment, a
gate layer 960 is first formed, followed by extension implantation of thesemiconductive body 916 on each side of thegate layer 960. Next,gate spacers hard mask 961. Growth of theSEG films hard mask 961 acts as a blocking mask to prevent SEG film formation. - Doping of regions not protected by the
hard mask 961 may next be carried out such as N+ doping of thefirst doping region 918 a, and P+ doping of thesecond doping region 920 a. These doping processes may be done by alternatively photomasking each of thefirst doping region 918 a and thesecond region 920 a. - Thereafter, silicidation of the silicide
first region 938 and of the silicidesecond region 940 may be carried out. - In a process embodiment, both the epitaxial
first film 922 and the epitaxialsecond film 944 are grown at the same time. Nitride hard masks may be used to block the growth of silicide above what becomes thefirst doping region 918 b and thesecond doping region 920 b. The masks may also be used to facilitate a self-aligned growth of theSEG films - In an embodiment, the N+ and P+ source/drain masks are alternatively used to implant each of the epitaxial
first film 922 and the epitaxialsecond film 944. Theimplantation process 962 therefore may be two separate implantation processes, and implantation processes are used to dope theSEG films semiconductive body 916 disposed upon thedielectric substrate 912. - The
FINFET doping region 956 exhibits multiple electrical properties similarly to the gate structure depicted inFIG. 6 . Consequently, a multiple-fin FET apparatus 900 is formed of the various structures of theapparatus 600 when they are used in concert to act upon theFINFET doping region 956 of thesemiconductive body 916. - In a process embodiment, both the epitaxial
first film 922 and the epitaxialsecond film 944 are grown at the same time. The N+ and P+ source/drain masks and implantation processes are used to dope parts of theSEG films semiconductive body 916 disposed upon thedielectric substrate 912. The nitridehard mask 961 is used to block the growth of silicide, and it also is used to facilitate a self-aligned SEG growth of theSEG films hard mask 961 also prevents unplanned implantation dopings 962 of theFINFET doping region 956. Adiode distance 936 represents the electrical length of the diode that is formed by theFINFET diode apparatus 900. - The first doping region 918 and the second doping region 920 of the
semiconductive body 916 may be differently doped. The first doping region 918 is doped differently as afirst doping region 918 a and afirst doping region 918 b. The different doping may arise due to fabrication with the presence or absence of various structures including thegate spacers mask 961. Similarly, the second doping region 920 is doped differently as asecond doping region 920 a and asecond doping region 920 b. TheFINFET doping region 956 may also be differently doped from the first doping region 918 and the second doping region 920. TheFINFET doping region 956 may also be similarly doped with respect to one of the first doping region 918 or the second doping region 920. AFINFET diode apparatus 900 of this type may be used to provide long and quasi-graded anode and cathode regions for lowered leakage and increased reverse breakdown voltages, while still making use of the low resistivity and thermally useful SEG films. - The
apparatus 900 communicates to the outside world by thefirst contact 932, disposed on the silicidefirst region 938 of the epitaxialfirst film 922, and by asecond contact 934, disposed on the silicidesecond region 940 of the epitaxialsecond film 944. Consequently, the contacts are coupleable to external structures. Theapparatus 900 also communicates to the outside world through a gate structure that includes thegate layer 960 that exhibits agate length 959. It can now be appreciated that thesemiconductive body 916 can be configured as a semiconductive fin. -
FIG. 10 is a process-flow diagram according to some embodiments. - At 1010, the process includes patterning a semiconductive body upon a dielectric substrate.
- At 1020, the process includes imposing a doping differential between a first doping region of the semiconductive body and a second doping region of the semiconductive body.
- At 1030, the process includes forming an in situ doped SEG film upon the first doping region or upon the second doping region of the semiconductive body.
- At 1040, the process includes forming a silicide first region to make contact to the SEG first film. Alternatively or additionally, at 1042, the process includes forming a silicide second region to make contact to the SEG second film.
- At 1050, the process includes coupling the SEG first film to an external structure. At 1052, the process includes coupling the SEG second film to an external structure.
-
FIG. 11 is a process-flow diagram according to some embodiments. - At 1110, the process includes patterning a semiconductive body, also referred to as a fin, upon a dielectric substrate.
- At 1120, the process includes forming a gate above and on the fin.
- At 1122, the process includes extension implanting the fin about the gate.
- At 1124, the process includes forming a gate spacer about the gate.
- At 1130, the process includes forming a hard mask above and on the semiconductive fin. In a non-limiting example embodiment, a first photo mask and resist covers the semiconductive body at the second doping region while implantation is carried out in the semiconductive body at the first section. Similarly, a subsequent photo mask and resist covers the semiconductive body at the first doping region while implantation is carried out in the semiconductive body at the second section.
- It can also be seen at 1130 that processing may proceed directly from 1110 to 1130 as is illustrated in
FIG. 8 - At 1140, the process includes forming an SEG film upon the first doping region or upon the second doping region of the semiconductive body.
- At 1150, the process includes implanting the first SEG film. Alternatively or additionally, at 1152, the process includes implanting the second SEG film.
- At 1160, the process includes forming a silicide first region to make contact to the SEG first film. Alternatively or additionally, at 1162, the process includes forming a silicide second region to make contact to the SEG second film.
- At 1170, the process includes coupling the SEG first film to an external structure. At 1172, the process includes coupling the SEG second film to an external structure.
-
FIG. 12 illustrates anelectronic device 1200 that includes a vertical-diode apparatus embodiment such described above. Theelectronic device 1200 can be referred to as an external structure. Components of theelectronic device 1200 can also be referred to as an external structure. Further, sub-components, such as first area of a semiconductive device that on the same chip of a vertical-diode apparatus embodiment can also be referred to as an external structure. - The
electronic device 1200 includes afirst component 1220 that benefits from coupling to a vertical-diode apparatus. Examples of thefirst component 1220 include electrostatic discharge (ESD) functionalities such as in an output driver. Another example of thefirst component 1220 includes an ESD functionality in a logic circuit. In these examples, device operation is improved with the presence of a vertical-diode apparatus. - In an embodiment, the
device 1200 further includes apower source 1230. Thepower source 1230 is electrically connected to thefirst device component 1220 using interconnectingcircuitry 1240. In an embodiment, the interconnectingcircuitry 1240 includes a vertical-diode apparatus embodiment. - In an embodiment, the
device 1200 further includes asecond device component 1210. The second component is electrically connected to thefirst component 1220 using interconnectingcircuitry 1242. Likewise, in one embodiment, the interconnectingcircuitry 1242 includes a vertical-diode apparatus embodiment. Examples ofsecond device components 1210 include signal amplifiers, memory structures, logic circuitry, output circuits, ESD circuits, or other microprocessing apparatus. Aside from interconnecting circuitry, in an embodiment, thefirst device component 1220 and/or thesecond device component 1210 includes vertical-diode apparatus embodiment formed according to process embodiments described above. - Embodiments disclosed herein are suitable for application in embodiments of microelectronic devices that require passive devices near the microelectronic portions. In addition, embodiments of the system discussed may be used in a wide range of wireless communication devices such as cellular phone, mobile computers, and other handheld wireless digital devices.
- The accompanying drawings that form a part hereof show by way of illustration, and not of limitation, specific embodiments in which the subject matter may be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. This Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.
- Such embodiments of the inventive subject matter may be referred to herein, individually and/or collectively, by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed. Thus, although specific embodiments have been illustrated and described herein, it should be appreciated that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description. In the previous discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ”.
- The Abstract of the Disclosure is provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.
Claims (20)
1. An apparatus comprising:
a semiconductive body, wherein the semiconductive body defines a first lateral dimension;
an epitaxial first film disposed above and on a first doping region of the semiconductive body;
a diode junction configured to allow vertically directed diode activity between the semiconductive body and the epitaxial first film;
an epitaxial second film disposed above and on a second doping region of the semiconductive body; and
a gate structure disposed above the semiconductive body, and also disposed between the epitaxial first film and the epitaxial second film.
2. The apparatus of claim 1 , wherein the epitaxial first film and the epitaxial second film are spaced apart on the semiconductive body, the apparatus further including:
a third doping region of the semiconductive body is disposed below the gate structure.
3. The apparatus of claim 1 , further including:
a silicide first layer disposed on the epitaxial first film;
a first contact disposed on the silicide first layer;
a silicide second layer disposed on the epitaxial second film; and
a second contact disposed on the silicide second layer.
4. The apparatus of claim 1 , wherein the semiconductor body is one of multiple semiconductor bodies coupled in parallel, wherein a first doping region is coupled to a first contact, and a second doping region is coupled to a second contact.
5. The apparatus of claim 1 , further including a hard mask disposed between the epitaxial first film and the epitaxial second film.
6. An apparatus comprising:
a semiconductive fin disposed above and on one of a dielectric substrate and a bulk semiconductor;
an epitaxial first film disposed above and on the semiconductive fin at a first doping region thereof, wherein the epitaxial first film includes a top surface and a lateral surface, and wherein the epitaxial first film includes a diode junction boundary with the semiconductive fin; and
a vertical diode junction formed at the semiconductive fin and the diode boundary.
7. The apparatus of claim 6 , further including an epitaxial second film disposed above and on the semiconductive fin at a second doping region thereof, and wherein the diode junction is disposed between the epitaxial first film and the epitaxial second film.
8. The apparatus of claim 6 , further including a gate disposed above the semiconductive fin, and further disposed between the first doping region and the second doping region.
9. The apparatus of claim 7 , further including:
a silicide first layer disposed on the epitaxial first film;
a first contact disposed on the silicide first layer;
a silicide second layer disposed on the epitaxial second film; and
a second contact disposed on the silicide second layer.
10. The apparatus of claim 7 , wherein:
the semiconductive fin is one of multiple semiconductive fins coupled in parallel;
the first doping region is coupled to a first contact; and
the second doping region is coupled to a second contact.
11. A process comprising:
patterning a semiconductive body upon a substrate, wherein the semiconductive body includes a first doping region and a second doping region;
forming a hard mask over a portion of the semiconductive body, and using the hard mask as a blocking structure;
growing a selective-growth (SEG) first film above the first doping region;
growing a SEG second film above the second region;
forming a self-aligned silicide first region from a portion of the SEG first film; and
forming a self-aligned silicide second region from a portion of the SEG second film.
12. The process of claim 11 , wherein growing at least one of the SEG first film and the SEG second film is done with in situ doping thereof.
13. The process of claim 11 , wherein the hard mask is disposed over a gate stack, the SEG first film, and the SEG second film, the process further including:
implanting a portion of the first doping region that is exposed between the hard mask and the SEG first film, wherein implanting is carried out with one of a P or an N-type dopant; and
implanting a portion of the second doping region that is exposed between the hard mask and the SEG second film, wherein implanting is carried out with the other of the P or the N-type dopant.
14. The process of claim 11 , further including:
coupling the SEG first film to an external structure; and
coupling the SEG second film to the external structure.
15. The process of claim 11 , further including:
forming a gate above and on the semiconductive body.
16. The process of claim 15 , further including:
extension implanting the semiconductive body about the gate.
17. The process of claim 16 , further including:
forming a gate spacer about the gate.
18. The process of claim 11 , further including:
implanting the SEG first film.
19. The process of claim 18 , further including:
implanting the SEG second film.
20. The process of claim 11 , wherein:
the semiconductive body comprises a fin;
the substrate comprises a dielectric; and
the hard mask comprises a photomask and resist.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/618,738 US20130009215A1 (en) | 2007-09-27 | 2012-09-14 | Vertical diode using silicon formed by selective epitaxial growth |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/862,964 US7888775B2 (en) | 2007-09-27 | 2007-09-27 | Vertical diode using silicon formed by selective epitaxial growth |
US12/986,875 US8318553B2 (en) | 2007-09-27 | 2011-01-07 | Vertical diode using silicon formed by selective epitaxial growth |
US13/618,738 US20130009215A1 (en) | 2007-09-27 | 2012-09-14 | Vertical diode using silicon formed by selective epitaxial growth |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/986,875 Division US8318553B2 (en) | 2007-09-27 | 2011-01-07 | Vertical diode using silicon formed by selective epitaxial growth |
Publications (1)
Publication Number | Publication Date |
---|---|
US20130009215A1 true US20130009215A1 (en) | 2013-01-10 |
Family
ID=40435626
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/862,964 Expired - Fee Related US7888775B2 (en) | 2007-09-27 | 2007-09-27 | Vertical diode using silicon formed by selective epitaxial growth |
US12/986,875 Active 2027-12-29 US8318553B2 (en) | 2007-09-27 | 2011-01-07 | Vertical diode using silicon formed by selective epitaxial growth |
US13/618,738 Abandoned US20130009215A1 (en) | 2007-09-27 | 2012-09-14 | Vertical diode using silicon formed by selective epitaxial growth |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/862,964 Expired - Fee Related US7888775B2 (en) | 2007-09-27 | 2007-09-27 | Vertical diode using silicon formed by selective epitaxial growth |
US12/986,875 Active 2027-12-29 US8318553B2 (en) | 2007-09-27 | 2011-01-07 | Vertical diode using silicon formed by selective epitaxial growth |
Country Status (2)
Country | Link |
---|---|
US (3) | US7888775B2 (en) |
DE (1) | DE102008038552B4 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140367782A1 (en) * | 2013-06-13 | 2014-12-18 | International Business Machines Corporation | Lateral Diode Compatible with FinFET and Method to Fabricate Same |
US20150041897A1 (en) * | 2013-08-07 | 2015-02-12 | International Business Machines Corporation | Anchored stress-generating active semiconductor regions for semiconductor-on-insulator finfet |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100814417B1 (en) * | 2006-10-02 | 2008-03-18 | 삼성전자주식회사 | Method of forming a silicon pattern having a single crystal and method of forming a non-volatile memory device using the same |
US7888775B2 (en) | 2007-09-27 | 2011-02-15 | Infineon Technologies Ag | Vertical diode using silicon formed by selective epitaxial growth |
US8587074B2 (en) * | 2011-05-05 | 2013-11-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device having a gate stack |
US8482078B2 (en) * | 2011-05-10 | 2013-07-09 | International Business Machines Corporation | Integrated circuit diode |
US8502320B2 (en) * | 2011-09-30 | 2013-08-06 | Broadcom Corporation | Zener diode structure and process |
US9012997B2 (en) | 2012-10-26 | 2015-04-21 | International Business Machines Corporation | Semiconductor device including ESD protection device |
US20140191319A1 (en) * | 2013-01-04 | 2014-07-10 | GlobalFoundries, Inc. | Finfet compatible diode for esd protection |
US9006087B2 (en) | 2013-02-07 | 2015-04-14 | International Business Machines Corporation | Diode structure and method for wire-last nanomesh technologies |
US8927397B2 (en) | 2013-02-07 | 2015-01-06 | International Business Machines Corporation | Diode structure and method for gate all around silicon nanowire technologies |
US9190419B2 (en) | 2013-02-07 | 2015-11-17 | International Business Machines Corporation | Diode structure and method for FINFET technologies |
US9620502B2 (en) * | 2013-04-10 | 2017-04-11 | Samsung Electronics Co., Ltd. | Semiconductor device including an extended impurity region |
US8941161B2 (en) | 2013-05-07 | 2015-01-27 | International Business Machines Corporation | Semiconductor device including finFET and diode having reduced defects in depletion region |
JP2014229713A (en) * | 2013-05-21 | 2014-12-08 | 独立行政法人産業技術総合研究所 | Semiconductor device and method for manufacturing semiconductor device |
KR102330757B1 (en) | 2015-03-30 | 2021-11-25 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing the same |
US9711533B2 (en) * | 2015-10-16 | 2017-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET devices having different source/drain proximities for input/output devices and non-input/output devices and the method of fabrication thereof |
US9793262B1 (en) | 2016-04-27 | 2017-10-17 | Globalfoundries Inc. | Fin diode with increased junction area |
US10319662B2 (en) | 2017-02-01 | 2019-06-11 | Indian Institute Of Science | Non-planar electrostatic discharge (ESD) protection devices with nano heat sinks |
US10483258B2 (en) | 2017-02-25 | 2019-11-19 | Indian Institute Of Science | Semiconductor devices and methods to enhance electrostatic discharge (ESD) robustness, latch-up, and hot carrier immunity |
US9991359B1 (en) | 2017-06-15 | 2018-06-05 | International Business Machines Corporation | Vertical transistor gated diode |
US10600774B2 (en) | 2018-04-06 | 2020-03-24 | Qualcomm Incorporated | Systems and methods for fabrication of gated diodes with selective epitaxial growth |
WO2020062275A1 (en) | 2018-09-30 | 2020-04-02 | 华为技术有限公司 | Gated diode and chip |
US11101374B1 (en) | 2020-06-13 | 2021-08-24 | International Business Machines Corporation | Nanosheet gated diode |
CN113035957A (en) * | 2021-03-01 | 2021-06-25 | 泉芯集成电路制造(济南)有限公司 | Fin type field effect transistor and semiconductor device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060131656A1 (en) * | 2004-12-17 | 2006-06-22 | Samsung Electronics Co., Ltd. | CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same |
US20080093674A1 (en) * | 2004-12-03 | 2008-04-24 | Samsung Electronics Co., Ltd. | Fin field effect transistor and method of manufacturing the same |
US20080138964A1 (en) * | 2006-12-12 | 2008-06-12 | Zhiyuan Ye | Formation of Epitaxial Layer Containing Silicon and Carbon |
US20080290370A1 (en) * | 2007-05-21 | 2008-11-27 | Jin-Ping Han | Semiconductor devices and methods of manufacturing thereof |
US20090087967A1 (en) * | 2005-11-14 | 2009-04-02 | Todd Michael A | Precursors and processes for low temperature selective epitaxial growth |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4373255A (en) * | 1979-06-19 | 1983-02-15 | The United States Of America As Represented By The Secretary Of The Air Force | Method of making oxide passivated mesa epitaxial diodes with integral plated heat sink |
FR2693314B1 (en) * | 1992-07-02 | 1994-10-07 | Alain Chantre | Vertical JFET transistor with optimized bipolar operating mode and corresponding manufacturing process. |
US5811857A (en) * | 1996-10-22 | 1998-09-22 | International Business Machines Corporation | Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications |
KR100347544B1 (en) * | 1999-02-13 | 2002-08-07 | 주식회사 하이닉스반도체 | Method of manufacturing a junction in a semiconductor device |
US6448160B1 (en) * | 1999-04-01 | 2002-09-10 | Apd Semiconductor, Inc. | Method of fabricating power rectifier device to vary operating parameters and resulting device |
US6617649B2 (en) * | 2000-12-28 | 2003-09-09 | Industrial Technology Research Institute | Low substrate-noise electrostatic discharge protection circuits with bi-directional silicon diodes |
US6690065B2 (en) * | 2000-12-28 | 2004-02-10 | Industrial Technology Research Institute | Substrate-biased silicon diode for electrostatic discharge protection and fabrication method |
US7183575B2 (en) * | 2002-02-19 | 2007-02-27 | Nissan Motor Co., Ltd. | High reverse voltage silicon carbide diode and method of manufacturing the same high reverse voltage silicon carbide diode |
US6645820B1 (en) * | 2002-04-09 | 2003-11-11 | Taiwan Semiconductor Manufacturing Company | Polycrystalline silicon diode string for ESD protection of different power supply connections |
DE10308313B4 (en) | 2003-02-26 | 2010-08-19 | Siemens Ag | Semiconductor diode, electronic component, voltage source inverter and control method |
DE10361134B4 (en) * | 2003-12-23 | 2014-10-23 | Infineon Technologies Ag | A method for producing a p-type emitter of an IGBT, an anode, a diode and an anode of an asymmetric thyristor. |
WO2005091988A2 (en) * | 2004-03-19 | 2005-10-06 | Fairchild Semiconductor Corporation | Method and device with durable contact on silicon carbide |
US7138313B2 (en) * | 2004-03-31 | 2006-11-21 | International Business Machines Corporation | Method for creating a self-aligned SOI diode by removing a polysilicon gate during processing |
DE102004036278B4 (en) | 2004-07-27 | 2006-07-06 | Siemens Ag | Semiconductor device and method for operating the semiconductor device as an electronic switch |
KR20080028858A (en) * | 2005-04-22 | 2008-04-02 | 아이스모스 테크날러지 코포레이션 | Superjunction device having oxide lined trenches and method for manufacturing a superjunction device having oxide lined trenches |
US7341932B2 (en) * | 2005-09-30 | 2008-03-11 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Schottky barrier diode and method thereof |
US20080128762A1 (en) * | 2006-10-31 | 2008-06-05 | Vora Madhukar B | Junction isolated poly-silicon gate JFET |
EP2040300B1 (en) * | 2007-09-20 | 2016-07-06 | Imec | MOSFET devices and method to fabricate them |
US7888775B2 (en) | 2007-09-27 | 2011-02-15 | Infineon Technologies Ag | Vertical diode using silicon formed by selective epitaxial growth |
-
2007
- 2007-09-27 US US11/862,964 patent/US7888775B2/en not_active Expired - Fee Related
-
2008
- 2008-08-20 DE DE102008038552A patent/DE102008038552B4/en not_active Expired - Fee Related
-
2011
- 2011-01-07 US US12/986,875 patent/US8318553B2/en active Active
-
2012
- 2012-09-14 US US13/618,738 patent/US20130009215A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080093674A1 (en) * | 2004-12-03 | 2008-04-24 | Samsung Electronics Co., Ltd. | Fin field effect transistor and method of manufacturing the same |
US20060131656A1 (en) * | 2004-12-17 | 2006-06-22 | Samsung Electronics Co., Ltd. | CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same |
US20090087967A1 (en) * | 2005-11-14 | 2009-04-02 | Todd Michael A | Precursors and processes for low temperature selective epitaxial growth |
US20080138964A1 (en) * | 2006-12-12 | 2008-06-12 | Zhiyuan Ye | Formation of Epitaxial Layer Containing Silicon and Carbon |
US20080290370A1 (en) * | 2007-05-21 | 2008-11-27 | Jin-Ping Han | Semiconductor devices and methods of manufacturing thereof |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140367782A1 (en) * | 2013-06-13 | 2014-12-18 | International Business Machines Corporation | Lateral Diode Compatible with FinFET and Method to Fabricate Same |
US20140367781A1 (en) * | 2013-06-13 | 2014-12-18 | International Business Machines Corporation | Lateral diode compatible with finfet and method to fabricate same |
US9006054B2 (en) * | 2013-06-13 | 2015-04-14 | International Business Machines Corporation | Lateral diode compatible with FinFET and method to fabricate same |
US9058992B2 (en) * | 2013-06-13 | 2015-06-16 | International Business Machines Corporation | Lateral diode compatible with FinFET and method to fabricate same |
US20150041897A1 (en) * | 2013-08-07 | 2015-02-12 | International Business Machines Corporation | Anchored stress-generating active semiconductor regions for semiconductor-on-insulator finfet |
US9349863B2 (en) * | 2013-08-07 | 2016-05-24 | Globalfoundries Inc. | Anchored stress-generating active semiconductor regions for semiconductor-on-insulator finfet |
US9991366B2 (en) | 2013-08-07 | 2018-06-05 | Globalfoundries Inc. | Anchored stress-generating active semiconductor regions for semiconductor-on-insulator FinFET |
Also Published As
Publication number | Publication date |
---|---|
US20090085163A1 (en) | 2009-04-02 |
US8318553B2 (en) | 2012-11-27 |
US20110095347A1 (en) | 2011-04-28 |
DE102008038552A1 (en) | 2009-04-16 |
DE102008038552B4 (en) | 2013-07-18 |
US7888775B2 (en) | 2011-02-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8318553B2 (en) | Vertical diode using silicon formed by selective epitaxial growth | |
US7208386B2 (en) | Drain extended MOS transistor with improved breakdown robustness | |
US8310027B2 (en) | Electronic device and manufacturing method thereof | |
KR100586737B1 (en) | NMOS DEVICE, PMOS DEVICE AND SiGe BiCMOS DEVICE ON SOI SUBSTRATE AND METHOD OF FABRICATING THE SAME | |
US6015993A (en) | Semiconductor diode with depleted polysilicon gate structure and method | |
US7741659B2 (en) | Semiconductor device | |
US6706571B1 (en) | Method for forming multiple structures in a semiconductor device | |
US9058992B2 (en) | Lateral diode compatible with FinFET and method to fabricate same | |
US20060063334A1 (en) | Fin FET diode structures and methods for building | |
US20150236116A1 (en) | Method of forming a fin-like bjt | |
US7410875B2 (en) | Semiconductor structure and fabrication thereof | |
JP5378635B2 (en) | Metal oxide semiconductor device formed in silicon-on-insulator | |
US20090236662A1 (en) | Guard ring structures for high voltage cmos/low voltage cmos technology using ldmos (lateral double-diffused metal oxide semiconductor) device fabrication | |
US10475791B1 (en) | Transistor fins with different thickness gate dielectric | |
KR100554465B1 (en) | SiGe BiCMOS DEVICE ON SOI SUBSTRATE AND METHOD OF FABRICATING THE SAME | |
US20200119000A1 (en) | Finfet having upper spacers adjacent gate and source/drain contacts | |
US5683918A (en) | Method of making semiconductor-on-insulator device with closed-gate electrode | |
US20220367714A1 (en) | Integrated Assemblies having Transistors Configured for High-Voltage Applications, and Methods of Forming Integrated Assemblies | |
US10319827B2 (en) | High voltage transistor using buried insulating layer as gate dielectric | |
US20220376039A1 (en) | Low leakage esd mosfet | |
JP2000299462A (en) | Semiconductor device and its manufacture | |
US10325908B2 (en) | Compact source ballast trench MOSFET and method of manufacturing | |
KR20080006268A (en) | Method of manufcaturing a tunneling field effect transistor | |
US20230307238A1 (en) | Carbon implantation for thicker gate silicide | |
KR20050015714A (en) | MOS transistor and fabrication method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |