US20120080318A1 - Forming Through-Substrate Vias by Electrofilling - Google Patents

Forming Through-Substrate Vias by Electrofilling Download PDF

Info

Publication number
US20120080318A1
US20120080318A1 US13/248,225 US201113248225A US2012080318A1 US 20120080318 A1 US20120080318 A1 US 20120080318A1 US 201113248225 A US201113248225 A US 201113248225A US 2012080318 A1 US2012080318 A1 US 2012080318A1
Authority
US
United States
Prior art keywords
workpiece
holes
plating base
conductive plating
seal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/248,225
Inventor
James R. Gillen
Adam Rowen
Christian Arrington
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Technology and Engineering Solutions of Sandia LLC
Original Assignee
Sandia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandia Corp filed Critical Sandia Corp
Priority to US13/248,225 priority Critical patent/US20120080318A1/en
Assigned to SANDIA CORPORATION reassignment SANDIA CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ARRINGTON, CHRISTIAN, GILLEN, JAMES R., ROWEN, ADAM
Assigned to U.S. DEPARTMENT OF ENERGY reassignment U.S. DEPARTMENT OF ENERGY CONFIRMATORY LICENSE (SEE DOCUMENT FOR DETAILS). Assignors: SANDIA CORPORATION
Publication of US20120080318A1 publication Critical patent/US20120080318A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02Electroplating of selected surface areas
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/001Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/004Sealing devices
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/06Suspending or supporting devices for articles to be coated
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate

Definitions

  • the present work relates generally to the formation of conductive vias and, more particularly, the formation of conductive vias in through holes in a substrate used as a connection layer in a multi-layer structure.
  • connection layer substrate may be, for example, an integrated circuit die, a semiconductor wafer, a printed circuit board, etc.
  • the substrate is provided with through holes that are filled with electrically conductive vias to permit the desired electrical connection between adjacent layers.
  • Some conventional approaches to via filling employ techniques that fill the through holes in the connection layer substrate with conductive pastes.
  • Other conventional approaches employ techniques for reflowing soft metals into the through holes.
  • the conventional approaches are adequate for filling vias of relatively low aspect ratio (the length-to-diameter ratio of the through holes) in a relatively thin substrate, but they present difficulties, such as bonding and hermeticity problems, as the substrate thickness and/or aspect ratio increases.
  • the conventional approaches also impose limits on via packing density (i.e., the achievable lateral spacing between vias).
  • FIG. 1 is an exploded view drawing of an example fixture for use in electrofilling through holes in a substrate to form vias according to example embodiments of the present work.
  • FIG. 2 cut-away side plan drawing illustrating an example fixture similar to the type shown in FIG. 1 , immersed in an electroplating solution for an electrofilling operation according to example embodiments of the present work.
  • FIG. 3 is a bottom plan drawing of the top plate of the example fixture of FIG. 1 according to example embodiments of the present work.
  • FIG. 4 illustrates example operations according to example embodiments of the present work.
  • Example embodiments provide for filling an array of through holes in a connection layer substrate by electroplating.
  • a conductive plating base is maintained in intimate contact with the area of the substrate that contains the array of through holes, such that the through holes are covered at one end by the conductive plating base.
  • the substrate also referred to herein as a workpiece
  • the conductive plating base is sealed from exposure to the electroplating solution except where it covers the ends of the through holes.
  • the conductive plating base remains electrically accessible externally of the electroplating solution, thereby permitting application of an electroplating voltage to the conductive plating base.
  • the conductive plating base While maintained at the electroplating voltage, the conductive plating base is cooperable with the electroplating solution to carry out an electroplating operation that deposits a solid conductive material on the conductive plating base and thereby fills the array of through holes with the solid conductive material, producing the desired vias.
  • Such via filling by electroplating operation is also referred to herein as electrofilling.
  • Electrofilling capabilities according to the present work provide manufacturable solutions that have several advantages over conventional techniques. Examples of these advantages include: acceptable quality vias packed much more densely (smaller lateral spacing between vias) than possible with conventional techniques; acceptable quality vias with much higher aspect ratios than possible with conventional techniques; and acceptable quality vias through thicker substrates than possible with conventional techniques.
  • Some example embodiments produce 100 micron diameter vias in a 675 micron thick, 6-inch silicon wafer, for an aspect ratio of nearly 7:1.
  • Some example embodiments produce 75 micron diameter vias at a 75 micron center-to-center spacing, for a pitch of 150 microns.
  • the via aspect ratios and pitches currently achievable according to the present work are limited only by the capabilities of currently available fabrication technologies to form via through holes in substrates. In general, the techniques of the present work are capable of filling vias with aspect ratios beyond 100:1 and pitches less than 5 microns.
  • Some example embodiments provide a fixture that may be used to electrofill conductive vias into densely packed arrays of high aspect ratio through holes in connection layer substrates of various thicknesses.
  • the electrofilling process provides electrical conductivity at one end of each substrate through hole, to facilitate via filling by metal deposition during an electroplating operation.
  • the fixture provides for intimate contact between a compliant, sacrificial metal foil (conductive plating base) and a surface of the substrate, in the area of the substrate that contains the through holes.
  • the metal foil covers the through holes at one end. The intimate contact is maintained by compressing the substrate and the foil together.
  • Some example embodiments include one or more shim/spacer elements to facilitate the compression, and gaskets to seal the conductive foil from all electroplating solution except that which fills the through holes. This sealing provides appropriate chemical isolation of the conductive foil from the electroplating chemistry. If the foil is exposed to the electroplating solution other than at the covered ends of the through holes, all exposed areas of the foil will plate with metal, disadvantageously inhibiting the electrofilling of the through holes.
  • the fixture includes components made of materials such as Polyvinylidene Fluoride (PVDF), Teflon and Viton. Such materials are desirably highly resistant to acids, bases and solvents, and are well suited for use in various types of conventional electroplating baths.
  • FIG. 1 diagrammatically illustrates in exploded view an example fixture assembly for use in electrofilling vias according to example embodiments of the present work.
  • the example assembly of FIG. 1 includes a top plate 11 and a base plate 12 , which may serve to function as a workpiece holder, with a stack of five distinct fixture layers sandwiched therebetween.
  • the top plate 11 and base plate 12 are made of PVDF.
  • the base plate 12 is designed to mount on a support structure 13 within a standard electroplating bath, and provides rigidity for placement of the fixture in the bath during plating, as well as during loading and unloading the fixture.
  • the base plate 12 has a groove 14 (rectangular-shaped in the example of FIG. 1 ) machined therein from the top.
  • the area of the groove 14 is larger than the area of the workpiece (i.e, the substrate with through holes to be electrofilled) 15 .
  • the base plate 12 further may include a plurality of drilled and tapped holes, located adjacent the periphery of the groove 14 as shown in FIG. 1 . These holes may desirably be used to attach the top plate 11 to the base plate 12 after the component layers of the fixture stack are placed and aligned.
  • fastening methods such as for example clamps, may be used as well.
  • the first layer in the fixture stack is a spacer 16 (made from Teflon in some example embodiments) having generally the same shape and size as the groove 14 in the base plate 12 .
  • This spacer 16 may be provided to compensate for total thickness variations of the fixture stack.
  • the spacer 16 has various thicknesses in various example embodiments, depending on the thickness of the workpiece 15 relative to the depth of the groove 14 in the base plate 12 . As such, the thicker the workpiece, the thinner the spacer 16 , and vice-a-versa.
  • the next layer in the fixture stack is bottom seal 17 (a Viton gasket in some example embodiments) having generally the same shape and size as the spacer 16 and the groove 14 .
  • This bottom seal 17 seals to the base plate 12 , and to the next layer of the stack, a conductive (in some example embodiments, copper) foil electrode 18 .
  • the bottom seal 17 desirably has sufficient flexibility to maintain sealing against the conductive foil 18 as the foil conforms to an adjoining surface of the workpiece 15 .
  • the conductive foil 18 has generally the same shape as the bottom seal 17 beneath it. Although not shown strictly to scale in FIG. 1 , the conductive foil 18 may desirably be slightly dimensionally smaller than the bottom seal 17 , to permit the seal 17 to seal around peripheral edges of the foil 18 and prevent undesired exposure of the foil to the electroplating solution.
  • the foil 18 serves as the cathode of the via electrofilling process and, as such, is desirably maintained at a suitable electroplating voltage.
  • the foil 18 may desirably include a portion (not explicitly shown in FIG. 1 ) that extends outwardly from one end of the fixture stack. This extension of the foil 18 may serve as a contact portion 21 , shown diagrammatically in FIG. 2 , which permits electrical access to the foil externally of the electroplating solution 25 .
  • a chip locator template 19 (made of Teflon in some example embodiments), with a cutout opening 22 having generally similar dimensions to the workpiece 15 , is stacked on the foil 18 .
  • the template 19 has generally the same shape and peripheral dimensions as the spacer 16 and bottom seal 17 , and generally the same thickness as the workpiece 15 .
  • the cutout 22 serves to locate the workpiece 15 on top of the foil 18 .
  • the workpiece 15 (a semiconductor die in the example of FIG. 1 ) is placed into the cutout 22 in the template 19 .
  • the template 19 is designated as a chip locator because, in this example, it locates the die (or chip) on the foil 18 .
  • the total height of the spacer 16 , the bottom seal 17 , the foil 18 , and the workpiece 15 /template 19 desirably exceeds the depth of the groove 14 by about 2-3 mm.
  • the final layer in the stack is a top seal 20 (a Viton gasket in some example embodiments).
  • This top seal 20 has generally the same shape and dimensions as the top plate 11 , and is thus dimensionally larger than the bottom seal 17 .
  • the top seal 20 provides sealing against the top plate 11 and the base plate 12 , and provides sealing against the bottom seal 17 .
  • the bottom seal 17 may be desirably dimensionally larger than the foil 18 , one skilled in the art will understand that the seals 17 and 20 may cooperate as a seal apparatus to provide a seal structure in a generally surrounding relationship to the foil 18 .
  • the top seal 20 also has a small cutout opening to expose to the electroplating solution only the area of the workpiece 15 that contains the through holes (two of which are shown at 26 in FIG.
  • the cutout in the top seal 20 may desirably be dimensionally smaller than the workpiece 15 in a number of example embodiments, as shown in FIG. 1 .
  • the top seal 20 has a plurality of through holes that respectively align with corresponding holes in the base plate 12 when the fixture stack is assembled.
  • the top plate 11 has a cutout opening 23 that cooperates with the smaller cutout in the top seal 20 to permit electroplating solution to fill the workpiece through holes.
  • the top plate 11 further desirably includes a plurality of through holes that respectively align with the through holes in the top seal 20 and corresponding holes in the base plate 12 when the fixture is assembled.
  • the top plate 11 may include a raised ridge 31 provided radially inwardly of the through holes and surrounding the cutout 23 .
  • the top plate 11 may include another raised ridge 32 surrounding the through holes, adjacent the periphery of the plate. Inclusion of these ridges 31 and 32 may desirably aid in sealing the top plate 11 against the top seal 20 .
  • the top plate 11 may be fastened to the base plate 12 by suitable elongate fasteners, as shown diagrammatically at 24 in the example embodiment of FIG. 1 , which are inserted through the aligned holes in the top plate 11 , top seal 20 and base plate 12 .
  • the fasteners 24 cooperate with the top plate 11 and the base plate 12 as a compression apparatus that compresses the constituent layers of the fixture stack evenly. This compression may allow the top and bottom seals 20 and 17 to form a fluid tight seal around the foil 18 , thereby preventing the electroplating solution from contacting portions of the foil 18 other than those that cover the workpiece through holes.
  • the elongate fasteners 24 are screws, and the desired fixture stack compression is provided by tightening the screws with a torque screwdriver.
  • the fasteners 24 are made of PVDF or other material suitable for use in electroplating chemistries.
  • the example embodiment shown in FIG. 2 includes a simplified fixture stack for clarity, the example fixture is positioned in the electroplating bath 25 such that electroplating solution fills the through holes 26 of the workpiece, and thus contacts the foil 18 at the ends of the through holes covered by the foil.
  • the example fixture is further positioned such that the peripheral edges of the seals 17 and 20 (see also FIG. 1 ), where the contact portion 21 of the foil 18 emerges from the fixture stack, are desirably outside the electroplating solution 25 . This positioning ensures that the contact portion 21 is not exposed to the electroplating solution.
  • an insulated conductor may be electrically connected to the foil 18 , within the seal formed by the seals 17 and 20 of FIG. 1 .
  • This insulated conductor passes through the electroplating solution, safely transferring the electroplating voltage to the foil 18 .
  • the entire fixture stack of FIG. 1 may be completely immersed in the electroplating solution.
  • the workpiece 15 is a semiconductor die substrate.
  • the structures and processes of the present work are readily scalable and configurable to various substrate sizes and shapes.
  • various example embodiments may accommodate variously sized and shaped semiconductor wafer substrates, and various example embodiments may accommodate variously sized and shaped printed circuit board substrates.
  • FIG. 4 illustrates example operations that may be performed according to the present work.
  • the conductive plating base is positioned to cover one end of the through holes in the substrate.
  • the substrate, with the through holes covered at one end by the plating base is immersed in the electroplating solution, with the contact, portion of the plating base electrically accessible outside the electroplating solution.
  • the electroplating solution fills the through holes in the substrate, while being prevented from contacting the plating base, except for those areas covering the through holes.
  • an electroplating voltage is applied to the contact portion of the plating base to initiate via electrofilling.
  • FIG. 5 diagrammatically illustrates vias 51 formed in substrate through holes according to the electrofilling techniques of the present work. As shown, the conductive foil 18 that remains may be removed by selective etching before planarization.

Abstract

A plurality of through holes in a workpiece are filled with a solid conductive material. The workpiece is immersed in an electroplating solution, with the through holes covered at one end by a portion of a conductive plating base. The electroplating solution is permitted to fill the through holes in the workpiece and contact the portion of the conductive plating base. A voltage applied to the conductive plating base enables an electroplating operation that deposits the solid conductive material on the portion of the conductive plating base to thereby fill the through holes with the solid conductive material.

Description

  • This application claims the priority under 35 U.S.C. §119(e)(1) of co-pending provisional application Ser. No. 61/389,588 filed Oct. 4, 2010 and incorporated herein by reference.
  • This invention was developed under Contract DE-AC04-94AL85000 between Sandia Corporation and the U.S. Department of Energy. The U.S. Government has certain rights in this invention.
  • FIELD
  • The present work relates generally to the formation of conductive vias and, more particularly, the formation of conductive vias in through holes in a substrate used as a connection layer in a multi-layer structure.
  • BACKGROUND
  • Via filling is commonly used in the semiconductor industry to provide electrical connection layers between other adjacent layers in a multi-layered structure. Depending on the type of multi-layered structure involved, the connection layer substrate may be, for example, an integrated circuit die, a semiconductor wafer, a printed circuit board, etc. The substrate is provided with through holes that are filled with electrically conductive vias to permit the desired electrical connection between adjacent layers.
  • Some conventional approaches to via filling employ techniques that fill the through holes in the connection layer substrate with conductive pastes. Other conventional approaches employ techniques for reflowing soft metals into the through holes. The conventional approaches are adequate for filling vias of relatively low aspect ratio (the length-to-diameter ratio of the through holes) in a relatively thin substrate, but they present difficulties, such as bonding and hermeticity problems, as the substrate thickness and/or aspect ratio increases. The conventional approaches also impose limits on via packing density (i.e., the achievable lateral spacing between vias).
  • It is desirable in view of the foregoing to provide for via filling techniques that overcome conventional limitations such as those mentioned above.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention is best understood from the following detailed description when read in connection with the accompanying drawing. It is emphasized that, according to common practice, the various features of the drawing are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Included in the drawing are the following figures:
  • FIG. 1 is an exploded view drawing of an example fixture for use in electrofilling through holes in a substrate to form vias according to example embodiments of the present work.
  • FIG. 2 cut-away side plan drawing illustrating an example fixture similar to the type shown in FIG. 1, immersed in an electroplating solution for an electrofilling operation according to example embodiments of the present work.
  • FIG. 3 is a bottom plan drawing of the top plate of the example fixture of FIG. 1 according to example embodiments of the present work.
  • FIG. 4 illustrates example operations according to example embodiments of the present work.
  • DETAILED DESCRIPTION
  • The present work recognizes that conventional limitations such as described above may be avoided by using an electroplating process to produce the desired conductive vias. Example embodiments provide for filling an array of through holes in a connection layer substrate by electroplating. A conductive plating base is maintained in intimate contact with the area of the substrate that contains the array of through holes, such that the through holes are covered at one end by the conductive plating base. The substrate (also referred to herein as a workpiece) with the covered through holes is immersed in an electroplating solution. The conductive plating base is sealed from exposure to the electroplating solution except where it covers the ends of the through holes. The conductive plating base remains electrically accessible externally of the electroplating solution, thereby permitting application of an electroplating voltage to the conductive plating base. While maintained at the electroplating voltage, the conductive plating base is cooperable with the electroplating solution to carry out an electroplating operation that deposits a solid conductive material on the conductive plating base and thereby fills the array of through holes with the solid conductive material, producing the desired vias. Such via filling by electroplating operation is also referred to herein as electrofilling.
  • Electrofilling capabilities according to the present work provide manufacturable solutions that have several advantages over conventional techniques. Examples of these advantages include: acceptable quality vias packed much more densely (smaller lateral spacing between vias) than possible with conventional techniques; acceptable quality vias with much higher aspect ratios than possible with conventional techniques; and acceptable quality vias through thicker substrates than possible with conventional techniques. Some example embodiments produce 100 micron diameter vias in a 675 micron thick, 6-inch silicon wafer, for an aspect ratio of nearly 7:1. Some example embodiments produce 75 micron diameter vias at a 75 micron center-to-center spacing, for a pitch of 150 microns. However, the via aspect ratios and pitches currently achievable according to the present work are limited only by the capabilities of currently available fabrication technologies to form via through holes in substrates. In general, the techniques of the present work are capable of filling vias with aspect ratios beyond 100:1 and pitches less than 5 microns.
  • Some example embodiments provide a fixture that may be used to electrofill conductive vias into densely packed arrays of high aspect ratio through holes in connection layer substrates of various thicknesses. The electrofilling process provides electrical conductivity at one end of each substrate through hole, to facilitate via filling by metal deposition during an electroplating operation. In some example embodiments, the fixture provides for intimate contact between a compliant, sacrificial metal foil (conductive plating base) and a surface of the substrate, in the area of the substrate that contains the through holes. The metal foil covers the through holes at one end. The intimate contact is maintained by compressing the substrate and the foil together.
  • Some example embodiments include one or more shim/spacer elements to facilitate the compression, and gaskets to seal the conductive foil from all electroplating solution except that which fills the through holes. This sealing provides appropriate chemical isolation of the conductive foil from the electroplating chemistry. If the foil is exposed to the electroplating solution other than at the covered ends of the through holes, all exposed areas of the foil will plate with metal, disadvantageously inhibiting the electrofilling of the through holes. In some example embodiments, the fixture (detailed examples of which are described below) includes components made of materials such as Polyvinylidene Fluoride (PVDF), Teflon and Viton. Such materials are desirably highly resistant to acids, bases and solvents, and are well suited for use in various types of conventional electroplating baths.
  • FIG. 1 diagrammatically illustrates in exploded view an example fixture assembly for use in electrofilling vias according to example embodiments of the present work. The example assembly of FIG. 1 includes a top plate 11 and a base plate 12, which may serve to function as a workpiece holder, with a stack of five distinct fixture layers sandwiched therebetween. In some example embodiments, the top plate 11 and base plate 12 are made of PVDF. The base plate 12 is designed to mount on a support structure 13 within a standard electroplating bath, and provides rigidity for placement of the fixture in the bath during plating, as well as during loading and unloading the fixture. The base plate 12 has a groove 14 (rectangular-shaped in the example of FIG. 1) machined therein from the top. The area of the groove 14 is larger than the area of the workpiece (i.e, the substrate with through holes to be electrofilled) 15. The base plate 12 further may include a plurality of drilled and tapped holes, located adjacent the periphery of the groove 14 as shown in FIG. 1. These holes may desirably be used to attach the top plate 11 to the base plate 12 after the component layers of the fixture stack are placed and aligned. One skilled in the art will understand that other fastening methods, such as for example clamps, may be used as well.
  • The first layer in the fixture stack is a spacer 16 (made from Teflon in some example embodiments) having generally the same shape and size as the groove 14 in the base plate 12. This spacer 16 may be provided to compensate for total thickness variations of the fixture stack. The spacer 16 has various thicknesses in various example embodiments, depending on the thickness of the workpiece 15 relative to the depth of the groove 14 in the base plate 12. As such, the thicker the workpiece, the thinner the spacer 16, and vice-a-versa.
  • The next layer in the fixture stack is bottom seal 17 (a Viton gasket in some example embodiments) having generally the same shape and size as the spacer 16 and the groove 14. This bottom seal 17 seals to the base plate 12, and to the next layer of the stack, a conductive (in some example embodiments, copper) foil electrode 18. The bottom seal 17 desirably has sufficient flexibility to maintain sealing against the conductive foil 18 as the foil conforms to an adjoining surface of the workpiece 15. The conductive foil 18 has generally the same shape as the bottom seal 17 beneath it. Although not shown strictly to scale in FIG. 1, the conductive foil 18 may desirably be slightly dimensionally smaller than the bottom seal 17, to permit the seal 17 to seal around peripheral edges of the foil 18 and prevent undesired exposure of the foil to the electroplating solution.
  • The foil 18 serves as the cathode of the via electrofilling process and, as such, is desirably maintained at a suitable electroplating voltage. To this end, the foil 18 may desirably include a portion (not explicitly shown in FIG. 1) that extends outwardly from one end of the fixture stack. This extension of the foil 18 may serve as a contact portion 21, shown diagrammatically in FIG. 2, which permits electrical access to the foil externally of the electroplating solution 25.
  • Referring again to FIG. 1, a chip locator template 19 (made of Teflon in some example embodiments), with a cutout opening 22 having generally similar dimensions to the workpiece 15, is stacked on the foil 18. The template 19 has generally the same shape and peripheral dimensions as the spacer 16 and bottom seal 17, and generally the same thickness as the workpiece 15. The cutout 22 serves to locate the workpiece 15 on top of the foil 18. The workpiece 15 (a semiconductor die in the example of FIG. 1) is placed into the cutout 22 in the template 19. In the example of FIG. 1, the template 19 is designated as a chip locator because, in this example, it locates the die (or chip) on the foil 18. In some example embodiments, the total height of the spacer 16, the bottom seal 17, the foil 18, and the workpiece 15/template 19 desirably exceeds the depth of the groove 14 by about 2-3 mm.
  • The final layer in the stack is a top seal 20 (a Viton gasket in some example embodiments). This top seal 20 has generally the same shape and dimensions as the top plate 11, and is thus dimensionally larger than the bottom seal 17. The top seal 20 provides sealing against the top plate 11 and the base plate 12, and provides sealing against the bottom seal 17. Recalling that the bottom seal 17 may be desirably dimensionally larger than the foil 18, one skilled in the art will understand that the seals 17 and 20 may cooperate as a seal apparatus to provide a seal structure in a generally surrounding relationship to the foil 18. The top seal 20 also has a small cutout opening to expose to the electroplating solution only the area of the workpiece 15 that contains the through holes (two of which are shown at 26 in FIG. 2). Accordingly, the cutout in the top seal 20 may desirably be dimensionally smaller than the workpiece 15 in a number of example embodiments, as shown in FIG. 1. The top seal 20 has a plurality of through holes that respectively align with corresponding holes in the base plate 12 when the fixture stack is assembled.
  • The top plate 11 has a cutout opening 23 that cooperates with the smaller cutout in the top seal 20 to permit electroplating solution to fill the workpiece through holes. Although the cutout 23 is shown larger than the cutout in the top seal 20 in the example of FIG. 1, it is contemplated that these two cutouts may be the same size in some example embodiments. The top plate 11 further desirably includes a plurality of through holes that respectively align with the through holes in the top seal 20 and corresponding holes in the base plate 12 when the fixture is assembled. As shown in FIG. 3, the top plate 11 may include a raised ridge 31 provided radially inwardly of the through holes and surrounding the cutout 23. The top plate 11 may include another raised ridge 32 surrounding the through holes, adjacent the periphery of the plate. Inclusion of these ridges 31 and 32 may desirably aid in sealing the top plate 11 against the top seal 20.
  • The top plate 11 may be fastened to the base plate 12 by suitable elongate fasteners, as shown diagrammatically at 24 in the example embodiment of FIG. 1, which are inserted through the aligned holes in the top plate 11, top seal 20 and base plate 12. The fasteners 24 cooperate with the top plate 11 and the base plate 12 as a compression apparatus that compresses the constituent layers of the fixture stack evenly. This compression may allow the top and bottom seals 20 and 17 to form a fluid tight seal around the foil 18, thereby preventing the electroplating solution from contacting portions of the foil 18 other than those that cover the workpiece through holes. In some example embodiments, the elongate fasteners 24 are screws, and the desired fixture stack compression is provided by tightening the screws with a torque screwdriver. In various example embodiments, the fasteners 24 are made of PVDF or other material suitable for use in electroplating chemistries.
  • The example embodiment shown in FIG. 2, includes a simplified fixture stack for clarity, the example fixture is positioned in the electroplating bath 25 such that electroplating solution fills the through holes 26 of the workpiece, and thus contacts the foil 18 at the ends of the through holes covered by the foil. The example fixture is further positioned such that the peripheral edges of the seals 17 and 20 (see also FIG. 1), where the contact portion 21 of the foil 18 emerges from the fixture stack, are desirably outside the electroplating solution 25. This positioning ensures that the contact portion 21 is not exposed to the electroplating solution.
  • In some example embodiments, an insulated conductor may be electrically connected to the foil 18, within the seal formed by the seals 17 and 20 of FIG. 1. This insulated conductor passes through the electroplating solution, safely transferring the electroplating voltage to the foil 18. In such embodiments, the entire fixture stack of FIG. 1 may be completely immersed in the electroplating solution.
  • In the examples described above, the workpiece 15 is a semiconductor die substrate. However, it will be appreciated that the structures and processes of the present work are readily scalable and configurable to various substrate sizes and shapes. For example, various example embodiments may accommodate variously sized and shaped semiconductor wafer substrates, and various example embodiments may accommodate variously sized and shaped printed circuit board substrates.
  • FIG. 4 illustrates example operations that may be performed according to the present work. At 41, the conductive plating base is positioned to cover one end of the through holes in the substrate. At 42, the substrate, with the through holes covered at one end by the plating base, is immersed in the electroplating solution, with the contact, portion of the plating base electrically accessible outside the electroplating solution. At 43, the electroplating solution fills the through holes in the substrate, while being prevented from contacting the plating base, except for those areas covering the through holes. At 44, an electroplating voltage is applied to the contact portion of the plating base to initiate via electrofilling.
  • FIG. 5 diagrammatically illustrates vias 51 formed in substrate through holes according to the electrofilling techniques of the present work. As shown, the conductive foil 18 that remains may be removed by selective etching before planarization.
  • Although example embodiments of the present work are described above in detail, this does not limit the scope of the present work, which can be practiced in a variety of embodiments.

Claims (20)

1. An assembly adapted for insertion in a bath of electroplating solution for an electroplating operation on a workpiece, the workpiece having formed therein a plurality of through holes, wherein each said through hole has a first end and a second end, comprising:
a workpiece holder adapted to hold said workpiece such that said first ends of said through holes of said workpiece permit said electroplating solution to fill said through holes when said assembly is inserted in said bath;
a conductive plating base positioned against a surface of said workpiece and having a portion that covers said second ends of said through holes and contacts the electroplating solution that fills said through holes when said assembly is inserted in said bath, wherein said conductive plating base is electrically accessible externally of said electroplating solution when said assembly is inserted in said bath to permit application of a voltage to said conductive plating base to conduct an electroplating operation in said bath; and
a compression apparatus coupled to said workpiece holder pressing said conductive plating base against said surface of said workpiece with said portion covering said second ends of said through holes.
2. The assembly of claim 1, wherein said electroplating operation fills said through holes with a solid conductive material, and wherein said workpiece is a connection layer substrate for a multi-layer semiconductor apparatus.
3. The assembly of claim 2, wherein said workpiece is one of a semiconductor die, a semiconductor wafer, and a printed circuit board, and wherein said solid conductive material forms vias in said through holes.
4. The apparatus of claim 3, wherein said conductive plating base is a sacrificial copper foil.
5. The assembly of claim 1, including a sealing apparatus that seals a further portion of said conductive plating base from contact with said electroplating solution when said assembly is inserted in said bath.
6. The apparatus of claim 5, wherein:
said workpiece holder includes a first plate and a second plate; and
said compression apparatus includes a fastening arrangement coupling said first and second plates of said workpiece holder, and wherein said workpiece, said conductive plating base and said sealing apparatus are disposed between said first and second plates.
7. The apparatus of claim 6, wherein said sealing apparatus includes a first seal adjacent said workpiece and having therein an opening aligned with said workpiece.
8. The apparatus of claim 7, wherein said sealing apparatus includes a second seal adjacent said conductive plating base, and wherein said conductive plating base and said workpiece are disposed between said first and second seals.
9. The apparatus of claim 8, wherein said first seal is adjacent said first plate, and wherein said first plate has formed therein an opening aligned with said opening in said first seal to permit said electroplating solution to fill said through holes when said assembly is inserted in said bath.
10. The apparatus of claim 7, wherein said first seal is adjacent said first plate, and wherein said first plate has formed therein an opening aligned with said opening in said first seal to permit said electroplating solution to fill said through holes when said assembly is inserted in said bath.
11. The apparatus of claim 6, wherein said first plate and said second plate of said workpiece holder, and said fastening arrangement of said compression apparatus are made of Polyvinylidene Fluoride (PVDF), and said sealing arrangement includes a Viton gasket.
12. A method of filling a plurality of through holes in a workpiece with a solid conductive material, comprising:
immersing the workpiece in an electroplating solution, with the through holes covered at one end by a portion of a conductive plating base; and
during said immersing,
permitting the electroplating solution to fill the through holes in the workpiece and contact said portion of the conductive plating base, and
applying a voltage to the conductive plating base to enable an electroplating operation that deposits the solid conductive material on said portion of the conductive plating base to thereby fill the through holes with the solid conductive material.
13. The method of claim 12, including preventing the electroplating solution from contacting a further portion of the conductive plating base.
14. The method of claim 13, including forcibly pressing said portion of the conductive plating base against the workpiece.
15. The method of claim 13, wherein said preventing includes sealing said further portion of the conductive plating base from the electroplating solution.
16. The method of claim 15, wherein said sealing includes forcibly pressing a first seal against the conductive plating base.
17. The method of claim 16, wherein said sealing includes forcibly pressing a second seal against the first seal.
18. The method of claim 15, including forcibly pressing said portion of the conductive plating base against the workpiece.
19. The method of claim 18, wherein said sealing includes forcibly pressing a first seal against the conductive plating base.
20. The method of claim 19, wherein said sealing includes forcibly pressing a second seal against the first seal.
US13/248,225 2010-10-04 2011-09-29 Forming Through-Substrate Vias by Electrofilling Abandoned US20120080318A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/248,225 US20120080318A1 (en) 2010-10-04 2011-09-29 Forming Through-Substrate Vias by Electrofilling

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US38958810P 2010-10-04 2010-10-04
US13/248,225 US20120080318A1 (en) 2010-10-04 2011-09-29 Forming Through-Substrate Vias by Electrofilling

Publications (1)

Publication Number Publication Date
US20120080318A1 true US20120080318A1 (en) 2012-04-05

Family

ID=45888867

Family Applications (1)

Application Number Title Priority Date Filing Date
US13/248,225 Abandoned US20120080318A1 (en) 2010-10-04 2011-09-29 Forming Through-Substrate Vias by Electrofilling

Country Status (1)

Country Link
US (1) US20120080318A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160032476A1 (en) * 2014-07-29 2016-02-04 Min Aik Precision Industrial Co., Ltd. Electroplating equipment capable of gold-plating on a through hole of a workpiece
US10147510B1 (en) 2013-11-15 2018-12-04 National Technology & Engineering Solutions Of Sandia, Llc Electroplated AU for conformal coating of high aspect ratio silicon structures

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5190637A (en) * 1992-04-24 1993-03-02 Wisconsin Alumni Research Foundation Formation of microstructures by multiple level deep X-ray lithography with sacrificial metal layers
US5468681A (en) * 1989-08-28 1995-11-21 Lsi Logic Corporation Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias
US20040173909A1 (en) * 2003-03-05 2004-09-09 Micron Technology, Inc. Conductive through wafer vias
US6902827B2 (en) * 2002-08-15 2005-06-07 Sandia National Laboratories Process for the electrodeposition of low stress nickel-manganese alloys
US20090121344A1 (en) * 2007-10-26 2009-05-14 Shinko Electric Industries Co., Ltd. Silicon interposer and semiconductor device package and semiconductor device incorporating the same
US7608174B1 (en) * 2005-04-22 2009-10-27 Sandia Corporation Apparatus and method for electroforming high aspect ratio micro-parts
WO2010041165A1 (en) * 2008-10-10 2010-04-15 Nxp B.V. Method of plating through wafer vias in a wafer for 3d packaging

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5468681A (en) * 1989-08-28 1995-11-21 Lsi Logic Corporation Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias
US5190637A (en) * 1992-04-24 1993-03-02 Wisconsin Alumni Research Foundation Formation of microstructures by multiple level deep X-ray lithography with sacrificial metal layers
US6902827B2 (en) * 2002-08-15 2005-06-07 Sandia National Laboratories Process for the electrodeposition of low stress nickel-manganese alloys
US20040173909A1 (en) * 2003-03-05 2004-09-09 Micron Technology, Inc. Conductive through wafer vias
US7608174B1 (en) * 2005-04-22 2009-10-27 Sandia Corporation Apparatus and method for electroforming high aspect ratio micro-parts
US20090121344A1 (en) * 2007-10-26 2009-05-14 Shinko Electric Industries Co., Ltd. Silicon interposer and semiconductor device package and semiconductor device incorporating the same
WO2010041165A1 (en) * 2008-10-10 2010-04-15 Nxp B.V. Method of plating through wafer vias in a wafer for 3d packaging

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10147510B1 (en) 2013-11-15 2018-12-04 National Technology & Engineering Solutions Of Sandia, Llc Electroplated AU for conformal coating of high aspect ratio silicon structures
US11053601B2 (en) 2013-11-15 2021-07-06 National Technology & Engineering Solutions Of Sandia, Llc Electroplated Au for conformal coating of high aspect ratio silicon structures
US20160032476A1 (en) * 2014-07-29 2016-02-04 Min Aik Precision Industrial Co., Ltd. Electroplating equipment capable of gold-plating on a through hole of a workpiece
US9512533B2 (en) * 2014-07-29 2016-12-06 Min Aik Precision Industrial Co., Ltd. Electroplating equipment capable of gold-plating on a through hole of a workpiece

Similar Documents

Publication Publication Date Title
KR100537972B1 (en) Chip scale ball grid array for integrated circuit package
US6313402B1 (en) Stress relief bend useful in an integrated circuit redistribution patch
EP0948814B1 (en) Chip scale ball grid array for integrated circuit package
CN101013686B (en) Interconnect substrate, semiconductor device, and method of manufacturing the same
US8617987B2 (en) Through hole via filling using electroless plating
US8900993B2 (en) Semiconductor device sealed in a resin section and method for manufacturing the same
US9583454B2 (en) Semiconductor die package including low stress configuration
US20030139020A1 (en) Semiconductor die package with semiconductor die having side electrical connection
US8618424B2 (en) Multilayer wiring substrate and method of manufacturing the same
US20070096292A1 (en) Electronic-part built-in substrate and manufacturing method therefor
TW201436130A (en) Thermally enhanced wiring board with built-in heat sink and build-up circuitry
JP5232185B2 (en) Manufacturing method of semiconductor device
US7897432B2 (en) Method for producing electronic part package
CN101076883A (en) Structure and method of making interconnect element, and multilayer wiring board including the interconnect element
US20020056922A1 (en) Semiconductor device, production method thereof, and coil spring cutting jig and coil spring guiding jig applied thereto
US10334719B2 (en) Multi-layer circuit board capable of being applied with electrical testing and method for manufacturing the same
CN108022903A (en) Intermediary layer and the semiconductor package body including intermediary layer
KR101124547B1 (en) Method for production of semiconductor package
US20120080318A1 (en) Forming Through-Substrate Vias by Electrofilling
KR100779061B1 (en) Printed circuit board and manufacturing method thereof
JP4509869B2 (en) Circuit board manufacturing method
US8786108B2 (en) Package structure
JP4654065B2 (en) Electrolytic plating jig and electrolytic plating method
KR100782402B1 (en) Printed circuit board and manufacturing method thereof
JP4424486B2 (en) Cathode electrode assembly, cathode electrode device, and plating device

Legal Events

Date Code Title Description
AS Assignment

Owner name: SANDIA CORPORATION, NEW MEXICO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ROWEN, ADAM;GILLEN, JAMES R.;ARRINGTON, CHRISTIAN;SIGNING DATES FROM 20111105 TO 20111108;REEL/FRAME:027314/0308

AS Assignment

Owner name: U.S. DEPARTMENT OF ENERGY, DISTRICT OF COLUMBIA

Free format text: CONFIRMATORY LICENSE;ASSIGNOR:SANDIA CORPORATION;REEL/FRAME:027398/0401

Effective date: 20111123

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION