US20110284965A1 - Reducing external resistance of a multi-gate device using spacer processing techniques - Google Patents
Reducing external resistance of a multi-gate device using spacer processing techniques Download PDFInfo
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- US20110284965A1 US20110284965A1 US13/204,987 US201113204987A US2011284965A1 US 20110284965 A1 US20110284965 A1 US 20110284965A1 US 201113204987 A US201113204987 A US 201113204987A US 2011284965 A1 US2011284965 A1 US 2011284965A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Definitions
- multi-gate devices or non-planar transistors such as tri-gate devices are emerging as a viable option to support future technology scaling.
- FIG. 1 is a process schematic for reducing external resistance of a multi-gate device using spacer processing techniques, according to but one embodiment
- FIG. 2 is a flow diagram of a method for reducing external resistance of a multi-gate device using spacer processing techniques, according to but one embodiment.
- FIG. 3 is a diagram of an example system in which embodiments of the present invention may be used, according to but one embodiment.
- Embodiments of reducing external resistance of a multi-gate device using spacer processing techniques are described herein.
- numerous specific details are set forth to provide a thorough understanding of embodiments disclosed herein.
- One skilled in the relevant art will recognize, however, that the embodiments disclosed herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth.
- well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the specification.
- FIG. 1 is a process schematic for reducing external resistance of a multi-gate device using spacer processing techniques, according to but one embodiment.
- FIGS. 1 a - d and FIGS. 1 i - j include top-down representations while FIGS. 1 e - h include cross-section representations.
- the depictions are represented sequentially (i.e. a through j), other sequences may be readily apparent and/or may fall within the spirit and scope of this description. In other words, the description is not limited to the particular sequence depicted in FIG. 1 .
- Multi-gate transistors or non-planar devices 100 may emerge as an option to support future technology scaling of transistor devices.
- drive current in multi-gate devices may be severely hindered by parasitic resistance.
- the parasitic resistance may result from difficulty in forming low interfacial resistance between epitaxial growth (epi-growth) and fin 104 surfaces (i.e.—sidewalls).
- sidewall spacer dielectric may block epi-growth along the sides of the fin 104 . This may result in forming a low resistance contact only on a portion of the fin 104 that is not impeded by the spacer dielectric, for example.
- Such effect may bottleneck the flow of current into the fin 104 , resulting in a degradation of external resistance (R ext ) of the multi-gate transistor.
- an apparatus 100 includes shallow-trench isolation (STI) material 102 , one or more multi-gate fins 104 , and sacrificial gate electrode 106 , each coupled as shown.
- the one or more multi-gate fins 104 may be referred to as diffusion according to an embodiment and may include doped silicon.
- Fin 104 may include a source region, a drain region, and a gate region, the gate region being disposed between the source and drain regions.
- the visible portion of fin 104 in FIG. 1 a may include a source region and a drain region.
- the portion of fin 104 covered by the sacrificial gate electrode 106 may include a gate region (i.e.—the portion of fin 104 visible in FIG. 1 c ).
- one or more multi-gate fins 104 are coupled with an underlying semiconductor substrate (not shown).
- the STI material 102 may be deposited to the semiconductor substrate.
- FIG. 1 a may depict a tri-gate fin after conventional trench etch and STI isolation processes.
- a sacrificial gate electrode 106 is deposited to the one or more multi-gate fins 104 and patterned such that the sacrificial gate electrode 106 material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins 104 .
- the dimensions of the sacrificial gate electrode 106 may be selected or pre-determined according to several factors.
- the thickness, g, of the sacrificial gate electrode 106 in the direction of the one or more multi-gate fins 104 is equal to or about equal to the following, where f is a pre-determined final gate electrode critical dimension (CD) (see FIG. 1 j ) and where s is a pre-determined spacer gate dielectric thickness (see FIG. 1 i )
- the spacer gate dielectric thickness, s may be accounted for twice to provide for the spacer gate dielectric 110 that is to be coupled to the source side of the final gate electrode 112 and for the spacer gate dielectric 110 that is to be coupled to the drain side of the final gate electrode 112 .
- a spacer gate dielectric thickness may be pre-determined according to size constraints of a multi-gate device, desired dielectric properties, and/or the size of other associated elements such as the final gate electrode 112 , or the one or more multi-gate fins 104 , for example.
- a final gate electrode CD may be pre-determined according to a variety of factors including size constraints of a multi-gate device, or other desired properties of a multi-gate device such as switching speed, among other factors.
- the height of the sacrificial gate electrode 106 is selected such that the height, h 2 , of the remaining spacer gate dielectric 110 (see FIG. 1 f ) after etching the spacer gate dielectric 110 is equal to or about equal to a pre-determined height of the final gate electrode 112 .
- the height of the final gate electrode 112 may be pre-determined according to design size constraints and/or desired properties in a multi-gate device.
- the height of the sacrificial gate electrode 106 may be in the direction coming out of the page.
- the height of the sacrificial gate electrode 106 determines the height of the spacer gate dielectric 110 .
- Etching the spacer gate dielectric 110 may reduce the height of the spacer gate dielectric 110 (see FIGS. 1 e - f ).
- the spacer gate dielectric 110 height, h 1 Prior to the etching, the spacer gate dielectric 110 height, h 1 , may be greater than after the etching (h 1 >h 2 ).
- the final gate electrode 112 height may be determined by the spacer gate dielectric 110 height, h 2 , if the final gate electrode 112 is deposited and/or polished to match the spacer gate dielectric 110 height, h 2 , after etching.
- the height of the sacrificial gate electrode 106 is selected to comprehend these downstream effects.
- a sacrificial gate electrode 106 is geometrically upsized in relation to a final gate electrode 112 .
- a sacrificial gate electrode 106 may include a variety of materials such as polysilicon, metal, or any other suitable gate electrode temporary placeholder for the purposes of defining a region where a final gate electrode 112 and/or spacer gate dielectric 110 are to be formed.
- the final gate electrode 112 is a second sacrificial gate electrode to be replaced by another gate electrode material in subsequent process steps.
- the final gate electrode 112 is incorporated in a finished multi-gate device.
- a final gate stack includes a high-k dielectric (not shown) coupled with the fin 104 and a metal gate electrode 112 coupled with the high-k dielectric.
- a tip implantation may be performed on the gate structure of FIG. 1 a in an embodiment.
- Tip implantation may include implanting the interface between the fin 104 and the sacrificial electrode 106 according to one embodiment.
- Implant may include p-type or n-type dopant.
- an apparatus 100 includes a sacrificial gate electrode 106 coupled with a dielectric film 108 , each coupled as shown.
- FIG. 1 b may be a depiction of FIG. 1 a after a dielectric film 108 has been deposited and polished.
- dielectric film 108 includes oxide materials such as silicon oxide for example.
- dielectric film 108 includes any suitable sacrificial material upon which spacer gate dielectric 110 material may be deposited and/or patterned.
- a dielectric film 108 is deposited or formed such that it is coupled to the source and drain regions of the one or more multi-gate fins 104 . Dielectric film 108 may be polished or planarized back to the level of a sacrificial gate electrode 106 .
- an apparatus 100 includes STI material 102 , one or more multi-gate fins 104 , and dielectric film 108 , each coupled as shown.
- FIG. 1 c may be a depiction of FIG. 1 b after the sacrificial gate electrode 106 has been removed or lifted out.
- sacrificial gate electrode 106 is removed by etching that exposes the underlying gate region of the one or more multi-gate fins 104 .
- an apparatus 100 includes STI material 102 , one or more multi-gate fins 104 , dielectric film 108 , and spacer gate dielectric 110 , each coupled as shown.
- FIG. 1 d may be a depiction of FIG. 1 c after deposition and etching of spacer gate dielectric 110 .
- Spacer gate dielectric 110 may be deposited to the gate region of one or more multi-gate fins 104 .
- the source and drain regions of the one or more multi-gate fins 104 may be protected from spacer 110 deposition by the dielectric film 108 that covers these regions.
- spacer 110 deposition includes conformal growth of a nitride material such as silicon nitride on at least the exposed surfaces within the area exposed after the removal of the sacrificial gate electrode 106 .
- the spacer gate dielectric 110 is conformally grown along the dielectric film 108 in contrast to a conventional process where spacer 110 is conformally grown along the gate electrode 112 .
- a first etch may remove the spacer 110 from the STI surface 102 and from the top (visible from top-down view in FIG. 1 d ) of the multi-gate fin 104 , according to but one embodiment.
- a second etch, or over-etch process may completely remove the spacer gate dielectric 110 from the gate region area 104 to be coupled with a final gate electrode 112 , except a remaining pre-determined thickness, s, of spacer gate dielectric 110 (i.e.—the two spacer films 110 visible in FIG. 1 d ) to be coupled with the final gate electrode 112 .
- the spacer gate dielectric 110 that remains as depicted in FIG. 1 d is coupled to the dielectric film 108 .
- the remaining spacer 110 is coupled to the one or more multi-gate fins 104 at an interface region between the source region and the gate region and at an interface region between the drain region and the gate region of the one or more multi-gate fins 104 .
- a multi-gate fin 104 includes a tri-gate fin having a top surface, a first sidewall surface, and a second sidewall surface where the deposited spacer 110 is etched to the extent that it removes substantially all of the spacer 110 from the top surface, the first sidewall surface, and the second sidewall surface of the gate region area that is to be directly coupled to the final gate electrode 112 .
- spacer 110 material is substantially or completely removed from the area of fin 104 including the top and sidewalls of fin 104 that are to be in direct contact with the final gate electrode 112 material.
- no spacer gate dielectric 110 is deposited to the source and drain regions of the one or more multi-gate fins 104 at any time during a gate formation process.
- a gate formation process may include at least the processes described in this specification.
- the spacer-free source and drain regions 104 may enable lower interfacial resistance between a semiconductor material epitaxially grown (epi-growth) on the top and sidewall surfaces of the source and drain regions 104 .
- spacer 110 material does not block the epi-growth in these regions, reducing the R ext and improving the drive current of a multi-gate device incorporating such techniques.
- an apparatus 100 includes one or more multi-gate fins 104 , dielectric film 108 , and spacer gate dielectric 110 , each coupled as shown.
- FIG. 1 e may be a cross-section depiction of FIG. 1 d along line x, at the intersection of line x and line y.
- a spacer gate dielectric 110 has a height, h 1 , prior to over-etching.
- FIG. 1 f which may be a depiction of FIG. 1 e after over-etching, the spacer gate dielectric 110 height, h 2 , has been reduced in comparison to h 1 as a result of etching.
- FIGS. 1 e - f depict spacer gate dielectric 110 conformally grown along a dielectric film 108 .
- an apparatus 100 includes a multi-gate fin 104 and spacer gate dielectric 110 , each coupled as shown.
- FIG. 1 g may be a cross-section depiction of FIG. 1 d along line y at the intersection of line x and line y.
- a multi-gate fin 104 has spacer gate dielectric 110 coupled to the sidewalls prior to an over-etch process that removes the spacer gate dielectric from the sidewalls, as depicted in FIG. 1 h.
- spacer gate dielectric is removed or substantially removed from the multi-gate fin 104 sidewalls in the gate region.
- FIG. 1 g depicts a tri-gate fin 104 having spacer 110 coupled to a first sidewall and to a second sidewall, wherein the top surface of the tri-gate fin 104 is not coupled directly to spacer 110 .
- the lack of spacer on the top surface may be due to an etch process that is selective to removing spacer from surfaces along the same plane as the top surface of tri-gate fin 104 .
- FIG. 1 h may depict a tri-gate fin after over-etch removes spacer 110 from the sidewalls in the gate region at the intersection of lines x and y of FIG. 1 d.
- an apparatus 100 includes dielectric film 108 , spacer gate dielectric 110 , and final gate electrode 112 , each coupled as shown.
- FIG. 1 i may be a depiction of FIG. 1 d after deposition of a final gate electrode 112 and planarization of the final gate electrode.
- the spacer gate dielectric 110 may have a thickness, s, which may be a pre-determined thickness as already described.
- final gate electrode 112 is grown to a height about equal to the height, h 2 , of the spacer 110 .
- the final gate electrode 112 is planarized back to reach a desired final gate electrode height.
- an apparatus 100 includes STI material 102 , one or more multi-gate fins 104 , spacer gate dielectric 110 , and final gate electrode 112 , each coupled as shown.
- FIG. 1 j may be a depiction of FIG. 1 i after oxide 108 has been removed.
- an etching process removes oxide 108 .
- a conventional replacement metal gate process flow may be used to further process apparatus 100 .
- an apparatus 100 includes a semiconductor substrate, at least one multi-gate fin 104 coupled with the semiconductor substrate, the multi-gate fin including a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions.
- an apparatus 100 further includes epitaxially grown semiconductor material (epi-growth) coupled to the source and drain regions of the multi-gate fin 104 (i.e.—the visible portions of multi-gate fin 104 in FIG. 1 j ).
- epitaxially grown semiconductor material epi-growth
- lack of spacer 110 on the source and drain regions enables lower interfacial resistance between the epi-growth and the multi-gate fin 104 .
- a gate electrode 112 may be further coupled with the gate region of the multi-gate fin 104 , where a spacer gate dielectric 110 is coupled to the gate electrode 112 such that substantially no spacer gate dielectric 110 is disposed between the gate electrode 112 and the one or more multi-gate fins 104 in the gate region.
- the semiconductor substrate includes silicon
- the multi-gate fin 104 includes silicon
- the gate electrode includes polysilicon
- the spacer gate dielectric includes a nitride material.
- an apparatus 100 is a non-planar trigate transistor including one or more multi-gate fins 104 that utilizes a spacer patterning process as described herein. Such apparatus 100 may be processed such that sacrificial gate electrode 106 patterning is geometrically upsized to allow for inclusion of spacer 110 along the final gate electrode 112 . In an embodiment, the sacrificial gate electrode 106 is sufficiently tall to allow for spacer 110 over-etch to remove spacer 110 material from along the sidewalls of the fin 104 in the gate-defined region.
- An apparatus 100 may include spacer 110 that grows conformally along a deposited material 108 such as oxide, for example, rather than a gate electrode material 112 such as polysilicon or metal, for example.
- an apparatus 100 includes sidewalls along the fin 104 that never encounter spacer deposition in the contact area (i.e.—source and drain regions). Such apparatus 100 may demonstrate significantly reduced R ext due to improved epi-growth to fin 104 resistance on the sidewalls of the fin 104 , resulting from no spacer 110 along the fin 104 sidewall in the contact area.
- an apparatus 100 includes a multi-gate fin 104 having a top surface, a first sidewall surface, and a second sidewall surface wherein the source and drain regions have epi-growth on the top surface, the first sidewall surface, and the second sidewall surface. Coupling epi-growth to the fin 104 surfaces in the source and drain region may reduce R ext in a multi-gate transistor device.
- epi-growth is epitaxially deposited to substantially the entire top, first sidewall, and second sidewall surfaces in the source and drain regions.
- the first sidewall surface, and the second sidewall surface of the source and drain regions are substantially free of the spacer gate dielectric 110 material.
- the source and drain regions of the multi-gate fin 104 are not coupled directly to the spacer gate dielectric 110 material at any time during the spacer gate dielectric 110 formation process.
- FIG. 2 is a flow diagram of a method for reducing external resistance of a multi-gate device using spacer processing techniques, according to but one embodiment.
- a method 200 includes preparing one or more multi-gate fins for gate spacer dielectric formation at box 202 , depositing and patterning a first sacrificial gate electrode to the gate region of the one or more multi-gate fins using particular geometries at box 204 , performing tip implantation near the gate region of the one or more multi-gate fins at box 206 , depositing a dielectric film to the source and drain regions of the one or more multi-gate fins at box 208 , removing the first sacrificial gate electrode material at box 210 , depositing gate spacer dielectric to the gate region of one or more multi-gate fins at box 212 , etching to remove gate spacer dielectric completely from the multi-gate fin surfaces in the gate region to be coupled with a second gate electrode at box 214 , depositing a second gate electrode to the gate region of
- a method includes depositing a sacrificial gate electrode to one or more multi-gate fins 204 , the one or more multi-gate fins including a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, and patterning the sacrificial gate electrode such that the gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins 204 .
- a method 200 further includes forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins 208 and removing the sacrificial gate electrode from the gate region of the one or more multi-gate fins 210 .
- a method 200 may further include depositing spacer gate dielectric to the gate region of the one or more multi-gate fins 212 where substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film.
- a method 200 further includes etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode 214 , except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film.
- the remaining spacer gate dielectric may be the spacer gate dielectric 110 of FIG. 1 j.
- the gate region area to be coupled with a final gate electrode may be the region of multi-gate fin 104 coupled to gate electrode 112 in FIG. 1 j.
- the one or more multi-gate fins include at least one tri-gate fin having a top surface, a first sidewall surface, and a second sidewall surface where etching the spacer gate dielectric 214 substantially or completely removes the spacer gate dielectric from the top surface, the first sidewall surface, and the second sidewall surface of the gate region area to be coupled with the final gate electrode.
- patterning the sacrificial gate electrode 204 results in a thickness, g, of the sacrificial gate electrode in the direction of the one or more multi-gate fins that comports with the relationship described in equation (1).
- the height of the sacrificial gate electrode is selected during patterning 204 such that a height of the remaining spacer gate dielectric after etching the spacer gate dielectric 214 is equal to or about equal to a pre-determined height of the final gate electrode, wherein etching the spacer gate dielectric 214 reduces the height of the remaining spacer gate dielectric.
- Forming a dielectric film 208 may include depositing an oxide material to the sacrificial gate electrode and the source and drain regions of the one or more multi-gate fins, and polishing the oxide material back to the level of the sacrificial gate electrode.
- Depositing spacer gate dielectric 212 to the gate region of the one or more multi-gate fins includes conformally growing a nitride material onto the deposited dielectric film while not conformally growing spacer gate dielectric onto a gate electrode material. In another embodiment, substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins at any time during a gate formation process.
- a method 200 includes performing tip implantation 206 prior to forming a dielectric film 208 , depositing the final gate electrode to the gate region of the one or more multi-gate fins 216 such that the final gate electrode is coupled to the pre-determined thickness of spacer gate dielectric that remains after etching the spacer gate dielectric, and removing the dielectric film 218 such that the pre-determined thickness of spacer gate dielectric remains coupled to the deposited final gate electrode.
- a method 200 may include epitaxially depositing a semiconductor material (i.e.—epi or epigrowth) to a top surface, a first sidewall surface and a second sidewall surface of the source and drain regions of one or more multi-gate fins to reduce R ext in a multi-gate transistor device.
- a semiconductor material i.e.—epi or epigrowth
- FIG. 3 is a diagram of an example system in which embodiments of the present invention may be used, according to but one embodiment.
- System 300 is intended to represent a range of electronic systems (either wired or wireless) including, for example, desktop computer systems, laptop computer systems, personal computers (PC), wireless telephones, personal digital assistants (PDA) including cellular-enabled PDAs, set top boxes, pocket PCs, tablet PCs, DVD players, or servers, but is not limited to these examples and may include other electronic systems.
- Alternative electronic systems may include more, fewer and/or different components.
- electronic system 300 includes an apparatus made using spacer processing techniques 100 in accordance with embodiments described with respect to FIGS. 1-2 .
- an apparatus made using spacer processing techniques 100 as described herein is part of an electronic system's processor 310 or memory 320 .
- Electronic system 300 may include bus 305 or other communication device to communicate information, and processor 310 coupled to bus 305 that may process information. While electronic system 300 may be illustrated with a single processor, system 300 may include multiple processors and/or co-processors. In an embodiment, processor 310 includes an apparatus made using spacer processing techniques 100 in accordance with embodiments described herein. System 300 may also include random access memory (RAM) or other storage device 320 (may be referred to as memory), coupled to bus 305 and may store information and instructions that may be executed by processor 310 .
- RAM random access memory
- memory may be referred to as memory
- Memory 320 may also be used to store temporary variables or other intermediate information during execution of instructions by processor 310 .
- Memory 320 is a flash memory device in one embodiment.
- memory 320 includes an apparatus made using spacer processing techniques 100 as described herein.
- System 300 may also include read only memory (ROM) and/or other static storage device 330 coupled to bus 305 that may store static information and instructions for processor 310 .
- Data storage device 340 may be coupled to bus 305 to store information and instructions.
- Data storage device 340 such as a magnetic disk or optical disc and corresponding drive may be coupled with electronic system 300 .
- Electronic system 300 may also be coupled via bus 305 to display device 350 , such as a cathode ray tube (CRT) or liquid crystal display (LCD), to display information to a user.
- display device 350 such as a cathode ray tube (CRT) or liquid crystal display (LCD)
- Alphanumeric input device 360 may be coupled to bus 305 to communicate information and command selections to processor 310 .
- cursor control 370 is Another type of user input device, such as a mouse, a trackball, or cursor direction keys to communicate information and command selections to processor 310 and to control cursor movement on display 350 .
- Electronic system 300 further may include one or more network interfaces 380 to provide access to network, such as a local area network.
- Network interface 380 may include, for example, a wireless network interface having antenna 385 , which may represent one or more antennae.
- Network interface 380 may also include, for example, a wired network interface to communicate with remote devices via network cable 387 , which may be, for example, an Ethernet cable, a coaxial cable, a fiber optic cable, a serial cable, or a parallel cable.
- network interface 380 may provide access to a local area network, for example, by conforming to an Institute of Electrical and Electronics Engineers (IEEE) standard such as IEEE 802.11b and/or IEEE 802.11g standards, and/or the wireless network interface may provide access to a personal area network, for example, by conforming to Bluetooth standards.
- IEEE Institute of Electrical and Electronics Engineers
- Other wireless network interfaces and/or protocols can also be supported.
- IEEE 802.11b corresponds to IEEE Std. 802.11b-1999 entitled “Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: Higher-Speed Physical Layer Extension in the 2.4 GHz Band,” approved Sep. 16, 1999 as well as related documents.
- IEEE 802.11g corresponds to IEEE Std. 802.11g-2003 entitled “Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, Amendment 4: Further Higher Rate Extension in the 2.4 GHz Band,” approved Jun. 27, 2003 as well as related documents.
- Bluetooth protocols are described in “Specification of the Bluetooth System: Core, Version 1.1,” published Feb. 22, 2001 by the Bluetooth Special Interest Group, Inc. Previous or subsequent versions of the Bluetooth standard may also be supported.
- network interface(s) 380 may provide wireless communications using, for example, Time Division, Multiple Access (TDMA) protocols, Global System for Mobile Communications (GSM) protocols, Code Division, Multiple Access (CDMA) protocols, and/or any other type of wireless communications protocol.
- TDMA Time Division, Multiple Access
- GSM Global System for Mobile Communications
- CDMA Code Division, Multiple Access
- a system 300 includes one or more omnidirectional antennae 385 , which may refer to an antenna that is at least partially omnidirectional and/or substantially omnidirectional, and a processor 310 coupled to communicate via the antennae.
Abstract
Reducing external resistance of a multi-gate device using spacer processing techniques is generally described. In one example, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins, forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins, removing the sacrificial gate electrode from the gate region of the one or more to multi-gate fins, depositing spacer gate dielectric to the gate region of the one or more multi-gate fins wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film, and etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film.
Description
- The present patent application is a divisional patent application of U.S. patent application Ser. No. 12/964,593, entitled “REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES,” filed Dec. 26, 2007, and invented by Ravi Pillarisetty et al, the disclosure of which being incorporated by reference herein.
- Generally, multi-gate devices or non-planar transistors such as tri-gate devices are emerging as a viable option to support future technology scaling.
- Embodiments disclosed herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements and in which:
-
FIG. 1 is a process schematic for reducing external resistance of a multi-gate device using spacer processing techniques, according to but one embodiment; -
FIG. 2 is a flow diagram of a method for reducing external resistance of a multi-gate device using spacer processing techniques, according to but one embodiment; and -
FIG. 3 is a diagram of an example system in which embodiments of the present invention may be used, according to but one embodiment. - It will be appreciated that for simplicity and/or clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.
- Embodiments of reducing external resistance of a multi-gate device using spacer processing techniques are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments disclosed herein. One skilled in the relevant art will recognize, however, that the embodiments disclosed herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the specification.
- Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments.
-
FIG. 1 is a process schematic for reducing external resistance of a multi-gate device using spacer processing techniques, according to but one embodiment.FIGS. 1 a-d andFIGS. 1 i-j include top-down representations whileFIGS. 1 e-h include cross-section representations. Although the depictions are represented sequentially (i.e. a through j), other sequences may be readily apparent and/or may fall within the spirit and scope of this description. In other words, the description is not limited to the particular sequence depicted inFIG. 1 . - Multi-gate transistors or
non-planar devices 100, such as tri-gate devices, may emerge as an option to support future technology scaling of transistor devices. However, drive current in multi-gate devices may be severely hindered by parasitic resistance. The parasitic resistance may result from difficulty in forming low interfacial resistance between epitaxial growth (epi-growth) and fin 104 surfaces (i.e.—sidewalls). For example, sidewall spacer dielectric may block epi-growth along the sides of thefin 104. This may result in forming a low resistance contact only on a portion of thefin 104 that is not impeded by the spacer dielectric, for example. Such effect may bottleneck the flow of current into thefin 104, resulting in a degradation of external resistance (Rext) of the multi-gate transistor. - In an embodiment according to
FIG. 1 a, anapparatus 100 includes shallow-trench isolation (STI)material 102, one or moremulti-gate fins 104, andsacrificial gate electrode 106, each coupled as shown. The one or moremulti-gate fins 104 may be referred to as diffusion according to an embodiment and may include doped silicon.Fin 104 may include a source region, a drain region, and a gate region, the gate region being disposed between the source and drain regions. The visible portion offin 104 inFIG. 1 a may include a source region and a drain region. The portion offin 104 covered by thesacrificial gate electrode 106 may include a gate region (i.e.—the portion offin 104 visible inFIG. 1 c). In an embodiment, one or moremulti-gate fins 104 are coupled with an underlying semiconductor substrate (not shown). TheSTI material 102 may be deposited to the semiconductor substrate.FIG. 1 a may depict a tri-gate fin after conventional trench etch and STI isolation processes. - In an embodiment, a
sacrificial gate electrode 106 is deposited to the one or moremulti-gate fins 104 and patterned such that thesacrificial gate electrode 106 material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or moremulti-gate fins 104. The dimensions of thesacrificial gate electrode 106 may be selected or pre-determined according to several factors. In an embodiment, the thickness, g, of thesacrificial gate electrode 106 in the direction of the one or moremulti-gate fins 104 is equal to or about equal to the following, where f is a pre-determined final gate electrode critical dimension (CD) (seeFIG. 1 j) and where s is a pre-determined spacer gate dielectric thickness (seeFIG. 1 i) -
g=f+2s (1) - The spacer gate dielectric thickness, s, may be accounted for twice to provide for the spacer gate dielectric 110 that is to be coupled to the source side of the
final gate electrode 112 and for the spacer gate dielectric 110 that is to be coupled to the drain side of thefinal gate electrode 112. A spacer gate dielectric thickness may be pre-determined according to size constraints of a multi-gate device, desired dielectric properties, and/or the size of other associated elements such as thefinal gate electrode 112, or the one or moremulti-gate fins 104, for example. A final gate electrode CD may be pre-determined according to a variety of factors including size constraints of a multi-gate device, or other desired properties of a multi-gate device such as switching speed, among other factors. - In another embodiment, the height of the
sacrificial gate electrode 106 is selected such that the height, h2, of the remaining spacer gate dielectric 110 (seeFIG. 1 f) after etching the spacer gate dielectric 110 is equal to or about equal to a pre-determined height of thefinal gate electrode 112. For example, the height of thefinal gate electrode 112 may be pre-determined according to design size constraints and/or desired properties in a multi-gate device. In a top down view such as inFIG. 1 a, the height of thesacrificial gate electrode 106 may be in the direction coming out of the page. In an embodiment, the height of thesacrificial gate electrode 106 determines the height of the spacer gate dielectric 110. - Etching the spacer gate dielectric 110 may reduce the height of the spacer gate dielectric 110 (see
FIGS. 1 e-f). Prior to the etching, the spacer gate dielectric 110 height, h1, may be greater than after the etching (h1>h2). Thefinal gate electrode 112 height may be determined by the spacer gate dielectric 110 height, h2, if thefinal gate electrode 112 is deposited and/or polished to match the spacer gate dielectric 110 height, h2, after etching. In an embodiment, the height of thesacrificial gate electrode 106 is selected to comprehend these downstream effects. In an embodiment, asacrificial gate electrode 106 is geometrically upsized in relation to afinal gate electrode 112. - A
sacrificial gate electrode 106 may include a variety of materials such as polysilicon, metal, or any other suitable gate electrode temporary placeholder for the purposes of defining a region where afinal gate electrode 112 and/or spacer gate dielectric 110 are to be formed. In an embodiment, thefinal gate electrode 112 is a second sacrificial gate electrode to be replaced by another gate electrode material in subsequent process steps. In another embodiment, thefinal gate electrode 112 is incorporated in a finished multi-gate device. In other embodiments, a final gate stack includes a high-k dielectric (not shown) coupled with thefin 104 and ametal gate electrode 112 coupled with the high-k dielectric. - Other forms of processing may be performed on the structure of
FIG. 1 a. For example, a tip implantation may be performed on the gate structure ofFIG. 1 a in an embodiment. Tip implantation may include implanting the interface between thefin 104 and thesacrificial electrode 106 according to one embodiment. Implant may include p-type or n-type dopant. - In an embodiment according to
FIG. 1 b, anapparatus 100 includes asacrificial gate electrode 106 coupled with adielectric film 108, each coupled as shown.FIG. 1 b may be a depiction ofFIG. 1 a after adielectric film 108 has been deposited and polished. In an embodiment,dielectric film 108 includes oxide materials such as silicon oxide for example. In other embodiments,dielectric film 108 includes any suitable sacrificial material upon whichspacer gate dielectric 110 material may be deposited and/or patterned. In an embodiment, adielectric film 108 is deposited or formed such that it is coupled to the source and drain regions of the one or moremulti-gate fins 104.Dielectric film 108 may be polished or planarized back to the level of asacrificial gate electrode 106. - In an embodiment according to
FIG. 1 c, anapparatus 100 includesSTI material 102, one or moremulti-gate fins 104, anddielectric film 108, each coupled as shown.FIG. 1 c may be a depiction ofFIG. 1 b after thesacrificial gate electrode 106 has been removed or lifted out. In an embodiment,sacrificial gate electrode 106 is removed by etching that exposes the underlying gate region of the one or moremulti-gate fins 104. - In an embodiment according to
FIG. 1 d, anapparatus 100 includesSTI material 102, one or moremulti-gate fins 104,dielectric film 108, andspacer gate dielectric 110, each coupled as shown.FIG. 1 d may be a depiction ofFIG. 1 c after deposition and etching ofspacer gate dielectric 110. - Spacer gate dielectric 110 may be deposited to the gate region of one or more
multi-gate fins 104. The source and drain regions of the one or moremulti-gate fins 104 may be protected fromspacer 110 deposition by thedielectric film 108 that covers these regions. In an embodiment,spacer 110 deposition includes conformal growth of a nitride material such as silicon nitride on at least the exposed surfaces within the area exposed after the removal of thesacrificial gate electrode 106. In an embodiment, thespacer gate dielectric 110 is conformally grown along thedielectric film 108 in contrast to a conventional process wherespacer 110 is conformally grown along thegate electrode 112. - A first etch may remove the
spacer 110 from theSTI surface 102 and from the top (visible from top-down view inFIG. 1 d) of themulti-gate fin 104, according to but one embodiment. A second etch, or over-etch process may completely remove the spacer gate dielectric 110 from thegate region area 104 to be coupled with afinal gate electrode 112, except a remaining pre-determined thickness, s, of spacer gate dielectric 110 (i.e.—the twospacer films 110 visible inFIG. 1 d) to be coupled with thefinal gate electrode 112. After over-etch, the spacer gate dielectric 110 that remains as depicted inFIG. 1 d is coupled to thedielectric film 108. In another embodiment, the remainingspacer 110 is coupled to the one or moremulti-gate fins 104 at an interface region between the source region and the gate region and at an interface region between the drain region and the gate region of the one or moremulti-gate fins 104. - In an embodiment, a
multi-gate fin 104 includes a tri-gate fin having a top surface, a first sidewall surface, and a second sidewall surface where the depositedspacer 110 is etched to the extent that it removes substantially all of thespacer 110 from the top surface, the first sidewall surface, and the second sidewall surface of the gate region area that is to be directly coupled to thefinal gate electrode 112. In other words,spacer 110 material is substantially or completely removed from the area offin 104 including the top and sidewalls offin 104 that are to be in direct contact with thefinal gate electrode 112 material. - According to an embodiment, no
spacer gate dielectric 110 is deposited to the source and drain regions of the one or moremulti-gate fins 104 at any time during a gate formation process. A gate formation process may include at least the processes described in this specification. The spacer-free source and drainregions 104 may enable lower interfacial resistance between a semiconductor material epitaxially grown (epi-growth) on the top and sidewall surfaces of the source and drainregions 104. For example,spacer 110 material does not block the epi-growth in these regions, reducing the Rext and improving the drive current of a multi-gate device incorporating such techniques. - In an embodiment according to
FIG. 1 e, anapparatus 100 includes one or moremulti-gate fins 104,dielectric film 108, andspacer gate dielectric 110, each coupled as shown.FIG. 1 e may be a cross-section depiction ofFIG. 1 d along line x, at the intersection of line x and line y. In an embodiment, aspacer gate dielectric 110 has a height, h1, prior to over-etching. In an embodiment according toFIG. 1 f, which may be a depiction ofFIG. 1 e after over-etching, the spacer gate dielectric 110 height, h2, has been reduced in comparison to h1 as a result of etching. In an embodiment,FIGS. 1 e-f depict spacer gate dielectric 110 conformally grown along adielectric film 108. - In an embodiment according to
FIG. 1 g, anapparatus 100 includes amulti-gate fin 104 andspacer gate dielectric 110, each coupled as shown.FIG. 1 g may be a cross-section depiction ofFIG. 1 d along line y at the intersection of line x and line y. In an embodiment, amulti-gate fin 104 hasspacer gate dielectric 110 coupled to the sidewalls prior to an over-etch process that removes the spacer gate dielectric from the sidewalls, as depicted inFIG. 1 h. In an embodiment according toFIG. 1 h, spacer gate dielectric is removed or substantially removed from themulti-gate fin 104 sidewalls in the gate region. - In an embodiment,
FIG. 1 g depicts atri-gate fin 104 havingspacer 110 coupled to a first sidewall and to a second sidewall, wherein the top surface of thetri-gate fin 104 is not coupled directly tospacer 110. The lack of spacer on the top surface may be due to an etch process that is selective to removing spacer from surfaces along the same plane as the top surface oftri-gate fin 104.FIG. 1 h may depict a tri-gate fin after over-etch removes spacer 110 from the sidewalls in the gate region at the intersection of lines x and y ofFIG. 1 d. - In an embodiment according to
FIG. 1 i, anapparatus 100 includesdielectric film 108,spacer gate dielectric 110, andfinal gate electrode 112, each coupled as shown.FIG. 1 i may be a depiction ofFIG. 1 d after deposition of afinal gate electrode 112 and planarization of the final gate electrode. Thespacer gate dielectric 110 may have a thickness, s, which may be a pre-determined thickness as already described. In an embodiment,final gate electrode 112 is grown to a height about equal to the height, h2, of thespacer 110. In an embodiment, thefinal gate electrode 112 is planarized back to reach a desired final gate electrode height. - In an embodiment according to
FIG. 1 j, anapparatus 100 includesSTI material 102, one or moremulti-gate fins 104,spacer gate dielectric 110, andfinal gate electrode 112, each coupled as shown.FIG. 1 j may be a depiction ofFIG. 1 i afteroxide 108 has been removed. In an embodiment, an etching process removesoxide 108. A conventional replacement metal gate process flow may be used tofurther process apparatus 100. - In an embodiment, an
apparatus 100 includes a semiconductor substrate, at least onemulti-gate fin 104 coupled with the semiconductor substrate, the multi-gate fin including a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions. In an embodiment, anapparatus 100 further includes epitaxially grown semiconductor material (epi-growth) coupled to the source and drain regions of the multi-gate fin 104 (i.e.—the visible portions ofmulti-gate fin 104 inFIG. 1 j). In an embodiment, lack ofspacer 110 on the source and drain regions enables lower interfacial resistance between the epi-growth and themulti-gate fin 104. Agate electrode 112 may be further coupled with the gate region of themulti-gate fin 104, where aspacer gate dielectric 110 is coupled to thegate electrode 112 such that substantially nospacer gate dielectric 110 is disposed between thegate electrode 112 and the one or moremulti-gate fins 104 in the gate region. In an embodiment, the semiconductor substrate includes silicon, themulti-gate fin 104 includes silicon, the gate electrode includes polysilicon, and the spacer gate dielectric includes a nitride material. - In an embodiment, an
apparatus 100 is a non-planar trigate transistor including one or moremulti-gate fins 104 that utilizes a spacer patterning process as described herein.Such apparatus 100 may be processed such thatsacrificial gate electrode 106 patterning is geometrically upsized to allow for inclusion ofspacer 110 along thefinal gate electrode 112. In an embodiment, thesacrificial gate electrode 106 is sufficiently tall to allow forspacer 110 over-etch to removespacer 110 material from along the sidewalls of thefin 104 in the gate-defined region. Anapparatus 100 may includespacer 110 that grows conformally along a depositedmaterial 108 such as oxide, for example, rather than agate electrode material 112 such as polysilicon or metal, for example. In an embodiment, anapparatus 100 includes sidewalls along thefin 104 that never encounter spacer deposition in the contact area (i.e.—source and drain regions).Such apparatus 100 may demonstrate significantly reduced Rext due to improved epi-growth tofin 104 resistance on the sidewalls of thefin 104, resulting from nospacer 110 along thefin 104 sidewall in the contact area. - In an embodiment, an
apparatus 100 includes amulti-gate fin 104 having a top surface, a first sidewall surface, and a second sidewall surface wherein the source and drain regions have epi-growth on the top surface, the first sidewall surface, and the second sidewall surface. Coupling epi-growth to thefin 104 surfaces in the source and drain region may reduce Rext in a multi-gate transistor device. In an embodiment, epi-growth is epitaxially deposited to substantially the entire top, first sidewall, and second sidewall surfaces in the source and drain regions. In another embodiment, the first sidewall surface, and the second sidewall surface of the source and drain regions are substantially free of thespacer gate dielectric 110 material. In yet another embodiment, the source and drain regions of themulti-gate fin 104 are not coupled directly to thespacer gate dielectric 110 material at any time during the spacer gate dielectric 110 formation process. -
FIG. 2 is a flow diagram of a method for reducing external resistance of a multi-gate device using spacer processing techniques, according to but one embodiment. In an embodiment, amethod 200 includes preparing one or more multi-gate fins for gate spacer dielectric formation atbox 202, depositing and patterning a first sacrificial gate electrode to the gate region of the one or more multi-gate fins using particular geometries atbox 204, performing tip implantation near the gate region of the one or more multi-gate fins atbox 206, depositing a dielectric film to the source and drain regions of the one or more multi-gate fins atbox 208, removing the first sacrificial gate electrode material atbox 210, depositing gate spacer dielectric to the gate region of one or more multi-gate fins atbox 212, etching to remove gate spacer dielectric completely from the multi-gate fin surfaces in the gate region to be coupled with a second gate electrode atbox 214, depositing a second gate electrode to the gate region of the one or more multi-gate fins atbox 216, and removing the dielectric film leaving the gate spacer dielectric coupled with the second gate electrode atbox 218, where arrows provide but one suggested flow. - In an embodiment, a method includes depositing a sacrificial gate electrode to one or more
multi-gate fins 204, the one or more multi-gate fins including a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, and patterning the sacrificial gate electrode such that the gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or moremulti-gate fins 204. In another embodiment, amethod 200 further includes forming a dielectric film coupled to the source and drain regions of the one or moremulti-gate fins 208 and removing the sacrificial gate electrode from the gate region of the one or moremulti-gate fins 210. - A
method 200 may further include depositing spacer gate dielectric to the gate region of the one or moremulti-gate fins 212 where substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film. In an embodiment, amethod 200 further includes etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with afinal gate electrode 214, except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film. The remaining spacer gate dielectric may be thespacer gate dielectric 110 ofFIG. 1 j. The gate region area to be coupled with a final gate electrode may be the region ofmulti-gate fin 104 coupled togate electrode 112 inFIG. 1 j. - In an embodiment, the one or more multi-gate fins include at least one tri-gate fin having a top surface, a first sidewall surface, and a second sidewall surface where etching the spacer gate dielectric 214 substantially or completely removes the spacer gate dielectric from the top surface, the first sidewall surface, and the second sidewall surface of the gate region area to be coupled with the final gate electrode.
- In an embodiment, patterning the
sacrificial gate electrode 204 results in a thickness, g, of the sacrificial gate electrode in the direction of the one or more multi-gate fins that comports with the relationship described in equation (1). In another embodiment, the height of the sacrificial gate electrode is selected during patterning 204 such that a height of the remaining spacer gate dielectric after etching thespacer gate dielectric 214 is equal to or about equal to a pre-determined height of the final gate electrode, wherein etching thespacer gate dielectric 214 reduces the height of the remaining spacer gate dielectric. Forming adielectric film 208 may include depositing an oxide material to the sacrificial gate electrode and the source and drain regions of the one or more multi-gate fins, and polishing the oxide material back to the level of the sacrificial gate electrode. - Depositing spacer gate dielectric 212 to the gate region of the one or more multi-gate fins includes conformally growing a nitride material onto the deposited dielectric film while not conformally growing spacer gate dielectric onto a gate electrode material. In another embodiment, substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins at any time during a gate formation process.
- In other embodiments, a
method 200 includes performingtip implantation 206 prior to forming adielectric film 208, depositing the final gate electrode to the gate region of the one or moremulti-gate fins 216 such that the final gate electrode is coupled to the pre-determined thickness of spacer gate dielectric that remains after etching the spacer gate dielectric, and removing thedielectric film 218 such that the pre-determined thickness of spacer gate dielectric remains coupled to the deposited final gate electrode. Amethod 200 may include epitaxially depositing a semiconductor material (i.e.—epi or epigrowth) to a top surface, a first sidewall surface and a second sidewall surface of the source and drain regions of one or more multi-gate fins to reduce Rext in a multi-gate transistor device. - Various operations may be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the invention. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
-
FIG. 3 is a diagram of an example system in which embodiments of the present invention may be used, according to but one embodiment.System 300 is intended to represent a range of electronic systems (either wired or wireless) including, for example, desktop computer systems, laptop computer systems, personal computers (PC), wireless telephones, personal digital assistants (PDA) including cellular-enabled PDAs, set top boxes, pocket PCs, tablet PCs, DVD players, or servers, but is not limited to these examples and may include other electronic systems. Alternative electronic systems may include more, fewer and/or different components. - In one embodiment,
electronic system 300 includes an apparatus made usingspacer processing techniques 100 in accordance with embodiments described with respect toFIGS. 1-2 . In an embodiment, an apparatus made usingspacer processing techniques 100 as described herein is part of an electronic system'sprocessor 310 ormemory 320. -
Electronic system 300 may includebus 305 or other communication device to communicate information, andprocessor 310 coupled tobus 305 that may process information. Whileelectronic system 300 may be illustrated with a single processor,system 300 may include multiple processors and/or co-processors. In an embodiment,processor 310 includes an apparatus made usingspacer processing techniques 100 in accordance with embodiments described herein.System 300 may also include random access memory (RAM) or other storage device 320 (may be referred to as memory), coupled tobus 305 and may store information and instructions that may be executed byprocessor 310. -
Memory 320 may also be used to store temporary variables or other intermediate information during execution of instructions byprocessor 310.Memory 320 is a flash memory device in one embodiment. In another embodiment,memory 320 includes an apparatus made usingspacer processing techniques 100 as described herein. -
System 300 may also include read only memory (ROM) and/or otherstatic storage device 330 coupled tobus 305 that may store static information and instructions forprocessor 310.Data storage device 340 may be coupled tobus 305 to store information and instructions.Data storage device 340 such as a magnetic disk or optical disc and corresponding drive may be coupled withelectronic system 300. -
Electronic system 300 may also be coupled viabus 305 to displaydevice 350, such as a cathode ray tube (CRT) or liquid crystal display (LCD), to display information to a user.Alphanumeric input device 360, including alphanumeric and other keys, may be coupled tobus 305 to communicate information and command selections toprocessor 310. Another type of user input device iscursor control 370, such as a mouse, a trackball, or cursor direction keys to communicate information and command selections toprocessor 310 and to control cursor movement ondisplay 350. -
Electronic system 300 further may include one ormore network interfaces 380 to provide access to network, such as a local area network.Network interface 380 may include, for example, a wireless networkinterface having antenna 385, which may represent one or more antennae.Network interface 380 may also include, for example, a wired network interface to communicate with remote devices vianetwork cable 387, which may be, for example, an Ethernet cable, a coaxial cable, a fiber optic cable, a serial cable, or a parallel cable. - In one embodiment,
network interface 380 may provide access to a local area network, for example, by conforming to an Institute of Electrical and Electronics Engineers (IEEE) standard such as IEEE 802.11b and/or IEEE 802.11g standards, and/or the wireless network interface may provide access to a personal area network, for example, by conforming to Bluetooth standards. Other wireless network interfaces and/or protocols can also be supported. - IEEE 802.11b corresponds to IEEE Std. 802.11b-1999 entitled “Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: Higher-Speed Physical Layer Extension in the 2.4 GHz Band,” approved Sep. 16, 1999 as well as related documents. IEEE 802.11g corresponds to IEEE Std. 802.11g-2003 entitled “Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, Amendment 4: Further Higher Rate Extension in the 2.4 GHz Band,” approved Jun. 27, 2003 as well as related documents. Bluetooth protocols are described in “Specification of the Bluetooth System: Core, Version 1.1,” published Feb. 22, 2001 by the Bluetooth Special Interest Group, Inc. Previous or subsequent versions of the Bluetooth standard may also be supported.
- In addition to, or instead of, communication via wireless LAN standards, network interface(s) 380 may provide wireless communications using, for example, Time Division, Multiple Access (TDMA) protocols, Global System for Mobile Communications (GSM) protocols, Code Division, Multiple Access (CDMA) protocols, and/or any other type of wireless communications protocol.
- In an embodiment, a
system 300 includes one or moreomnidirectional antennae 385, which may refer to an antenna that is at least partially omnidirectional and/or substantially omnidirectional, and aprocessor 310 coupled to communicate via the antennae. - The above description of illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or to limit to the precise forms disclosed. While specific embodiments and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of this description, as those skilled in the relevant art will recognize.
- These modifications can be made in light of the above detailed description. The terms used in the following claims should not be construed to limit the scope to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the embodiments disclosed herein is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
Claims (7)
1-9. (canceled)
10. An apparatus comprising:
a semiconductor substrate;
at least one multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions;
epi-growth coupled to the source and drain regions of the multi-gate fin;
a gate electrode coupled with the gate region of the multi-gate fin; and
a spacer gate dielectric coupled to the gate electrode wherein substantially no spacer gate dielectric is disposed between the gate electrode and the multi-gate fin in the gate region.
11. An apparatus according to claim 10 wherein the multi-gate fin has a top surface, a first sidewall surface, and a second sidewall surface wherein the source and drain regions have epi-growth on the top surface, the first sidewall surface, and the second sidewall surface, the source and drain regions being substantially free of the spacer gate dielectric material on the top surface, the first sidewall surface, and the second sidewall surface.
12. An apparatus according to claim 11 wherein the source and drain regions of the multi-gate fin are not coupled directly to the spacer gate dielectric material at any time during a spacer gate dielectric formation process.
13. An apparatus according to claim 10 wherein the spacer gate dielectric is conformally grown along a sacrificial dielectric and not conformally grown along the gate electrode.
14. An apparatus according to claim 10 wherein the semiconductor substrate comprises silicon, the multi-gate fin comprises silicon, the gate electrode comprises polysilicon, and the spacer gate dielectric comprises a nitride material.
15. An apparatus according to claim 10 wherein the multi-gate fin comprises a tri-gate fin of a multi-gate transistor device, the tri-gate fin having a top surface, a first sidewall surface, and a second sidewall surface wherein the epi-growth is coupled to the top surface, the first sidewall surface, and the second sidewall surface in the source and drain regions to reduce external resistance (Rext) in the multi-gate transistor device.
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US20090166741A1 (en) | 2009-07-02 |
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