US20110068326A1 - Schottky barrier tunnel transistor and method for fabricating the same - Google Patents
Schottky barrier tunnel transistor and method for fabricating the same Download PDFInfo
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- US20110068326A1 US20110068326A1 US12/957,146 US95714610A US2011068326A1 US 20110068326 A1 US20110068326 A1 US 20110068326A1 US 95714610 A US95714610 A US 95714610A US 2011068326 A1 US2011068326 A1 US 2011068326A1
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- 230000004888 barrier function Effects 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title description 26
- 239000000758 substrate Substances 0.000 claims abstract description 63
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 42
- 229910052710 silicon Inorganic materials 0.000 claims description 42
- 239000010703 silicon Substances 0.000 claims description 42
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 229910021332 silicide Inorganic materials 0.000 claims description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 15
- 229910052761 rare earth metal Inorganic materials 0.000 claims description 15
- 150000002910 rare earth metals Chemical class 0.000 claims description 15
- 125000006850 spacer group Chemical group 0.000 claims description 14
- 229910052723 transition metal Inorganic materials 0.000 claims description 9
- 150000003624 transition metals Chemical class 0.000 claims description 9
- 239000012212 insulator Substances 0.000 claims description 4
- 230000001268 conjugating effect Effects 0.000 claims 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 17
- 238000009413 insulation Methods 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 11
- 150000002500 ions Chemical class 0.000 description 10
- 239000012535 impurity Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 6
- 229910052691 Erbium Inorganic materials 0.000 description 6
- 229910021339 platinum silicide Inorganic materials 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052684 Cerium Inorganic materials 0.000 description 2
- 229910052692 Dysprosium Inorganic materials 0.000 description 2
- 229910052689 Holmium Inorganic materials 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 229910052765 Lutetium Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052772 Samarium Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052771 Terbium Inorganic materials 0.000 description 2
- 229910052775 Thulium Inorganic materials 0.000 description 2
- 229910052769 Ytterbium Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 229910021478 group 5 element Inorganic materials 0.000 description 2
- 229910052746 lanthanum Inorganic materials 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000005293 physical law Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910052727 yttrium Inorganic materials 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- KBQHZAAAGSGFKK-UHFFFAOYSA-N dysprosium atom Chemical compound [Dy] KBQHZAAAGSGFKK-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- KJZYNXUDTRRSPN-UHFFFAOYSA-N holmium atom Chemical compound [Ho] KJZYNXUDTRRSPN-UHFFFAOYSA-N 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- OHSVLFRHMCKCQY-UHFFFAOYSA-N lutetium atom Chemical compound [Lu] OHSVLFRHMCKCQY-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000005233 quantum mechanics related processes and functions Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- KZUNJOHGWZRPMI-UHFFFAOYSA-N samarium atom Chemical compound [Sm] KZUNJOHGWZRPMI-UHFFFAOYSA-N 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- GZCRRIHWUXGPOV-UHFFFAOYSA-N terbium atom Chemical compound [Tb] GZCRRIHWUXGPOV-UHFFFAOYSA-N 0.000 description 1
- FRNOGLGSGLTDKL-UHFFFAOYSA-N thulium atom Chemical compound [Tm] FRNOGLGSGLTDKL-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
- H01L29/8126—Thin film MESFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/095—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being Schottky barrier gate field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
Definitions
- the present invention relates to a semiconductor device and a method for fabricating the same, more particularly, to a Schottky barrier tunnel transistor and a method for fabricating the same.
- a single electron transistor is one representative example for such devices.
- a conventional structure of the SET usually uses a barrier that is generated by forming a pattern in an artificial shape over a silicon-based structure using a difference in an oxidation rate relying on a pattern. This characteristic may worsen an operational characteristic of a device in view of the Moore's law.
- the junction depth of a source and a drain needs to be in a range of 1 ⁇ 3 to 1 ⁇ 4 of the channel length.
- RTP rapid thermal process
- SPD solid phase diffusion
- this impurity ion diffusion method may be limited to obtain a junction depth of 10 nm or less. Furthermore, as the junction depth decreases, parasitic resistance components of the source and drain including a source-drain extension region caused by the diffusion of the impurity ions increase. Based on this relationship, in the assumption that a doping concentration is 1 ⁇ 10 19 atoms/cm 3 and a junction depth is 10 nm, a sheet resistance is 500 ohms ( ⁇ )/sq. or more. This value exceeds a sheet resistance of about 300 ( ⁇ )/sq. proposed by the international technology roadmap for semiconductor (ITRS), and may cause a limitation such as signal delay.
- ITRS international technology roadmap for semiconductor
- a gate insulation layer e.g., oxide
- permittivity of a gate insulation layer needs to increase to suppress the short channel effect.
- Many researches have been done to replace a silicon oxide layer, which is typically used in these days, with an oxide layer containing a rare earth metal of a high dielectric constant.
- the rare earth metal-based oxide layer may not be effectively heat treated due to its thermal instability. Therefore, a heat treatment in semiconductor processes needs to be performed at low temperature to use such a rare earth metal-based oxide layer. In that case, a heat treatment that proceeds after the ion implantation to activate ions and recover crystal damage may be performed with some limitations.
- MOSFETs metal oxide semiconductor field effect transistors
- SBTT Schottky barrier tunnel transistor
- source and drain regions of MOSFETs are replaced with a metal or silicide.
- the sheet resistance measured when the SBTT technology is employed decreases by 1/10-fold to 1/50-fold.
- an operation speed can be improved, and a channel length can decrease to 35 nm or less.
- a subsequent heat treatment is also not necessary.
- a process for fabricating devices using a gate oxide layer based on a high-K dielectric material can be co-used in the SBTT technology.
- the heat treatment is performed at low temperature.
- a process of forming gates based on a metal can be co-used in the SBTT technology.
- FIG. 1 illustrates a cross-sectional view of a conventional SBTT structure.
- the SBTT includes: a substrate 10 ; a buried oxide layer 11 formed on the substrate 10 ; source and drain regions 12 formed inside a silicon-on-insulator (SOI) substrate, which is formed on the buried oxide layer 11 ; a gate insulation layer 13 formed on a channel region 16 of the SOT substrate; a gate electrode 14 formed on the gate insulation layer 13 ; and spacers 15 formed on both sidewalls of the gate electrode 14 .
- SOI silicon-on-insulator
- the conventional SBTT is formed to have a vertical structure in which the gate insulation layer 13 and the gate electrode 14 are formed in sequence on the SOI substrate.
- the conventional SBTT structure is similar to the conventional MOSFET structure.
- the source and drain regions 12 in the SBTT structure are not formed by the ion implantation but usually by a sputtering method. Based on the sputtering method, a thin metal film is first deposited, and heat treated to form a silicide layer.
- the gate insulation layer may be formed of a high-K dielectric material-based thin film, or the thickness of the gate insulate layer needs to be reduced.
- the conventional SBTT technology may have a difficulty in satisfying a required effective oxide thickness of 1.5 nm or less in a device with a line width of 50 nm or less.
- Specific embodiments of the present invention are directed toward providing a Schottky barrier tunnel transistor capable of suppressing a short channel effect with a simple structure.
- Specific embodiments of the present invention are directed toward providing a method for fabricating a Schottky barrier tunnel transistor through a simplified process.
- a Schottky barrier tunnel transistor in accordance with one aspect of the present invention, there is provided a Schottky barrier tunnel transistor.
- the Schottky barrier tunnel transistor includes a gate electrode formed over a channel region of a substrate to form a Schottky junction with the substrate, and source and drain regions formed in the substrate exposed on both sides of the gate electrode.
- a method for fabricating a Schottky barrier tunnel transistor includes forming a gate electrode over a channel region of a substrate, the gate electrode providing a Schottky junction with the substrate, forming spacers over sidewalls of the gate electrode, and forming source and drain regions in the substrate exposed on both sides of the spacers.
- FIG. 1 illustrates a cross-sectional view of a conventional Schottky barrier tunnel transistor (SBTT).
- SBTT Schottky barrier tunnel transistor
- FIG. 2 illustrates a cross-sectional view of a SBTT in accordance with an embodiment of the present invention.
- FIGS. 3A to 3D are cross-sectional views illustrating a method for fabricating a SBTT in accordance with an embodiment of the present invention.
- FIG. 2 illustrates a cross-sectional view of a Schottky barrier tunnel transistor (SBTT) in accordance with an embodiment of the present invention.
- SBTT Schottky barrier tunnel transistor
- the SBTT includes a silicon-based substrate 112 , a gate electrode 113 , and source and drain regions 115 .
- the gate electrode 113 is formed over a channel region of the silicon-based substrate 112 , so as to form a Schottky junction with the silicon-based substrate 112 .
- the source and drain regions 115 are formed inside the silicon-based substrate 112 exposed on both sides of the gate electrode 113 , and include silicide.
- the silicon-based substrate 112 includes the channel region, and may be a silicon-on-insulator (SOI) substrate or a bulk substrate, which has a low unit cost.
- SOI silicon-on-insulator
- the silicon-based substrate 112 is doped with a P-type impurity ion including a group III element such as boron (B).
- the silicon-based substrate 112 is doped with an N-type impurity ion including a group V element such as phosphorus (P) or arsenic (As).
- a concentration of such an impurity ion is low being about 10 17 atoms/cm 3 or less.
- the silicon-based substrate 112 is formed as thin as possible. For instance, a thickness of the silicon-based substrate 112 may be about 100 nm or less. More specifically, the silicon-based substrate 112 is formed to a thickness that allows control of an electric field that a gate controls. Thus, the thickness of the channel region that the gate controls decreases, so that formation of an inversion layer can be easily controlled. As a result, leakage current usually generated between the source and drain regions 115 can be reduced.
- the gate electrode 113 directly contacts the channel region, thereby forming a Schottky junction with the silicon-based substrate 112 .
- the gate electrode 113 may include a metal-based layer or a metal silicide-based layer, which is a conjugate material between a metal and silicon.
- the metal-based layer may include a transition metal or rare earth metal.
- the transition metal may include one selected from a group consisting of iron (Fe), cobalt (Co), tungsten (W), nickel (Ni), palladium (Pd), platinum (Pt), molybdenum (Mo), and titanium (Ti).
- the rare earth metal may include one selected from a group consisting of erbium (Er), ytterbium (Yb), samarium (Sm), yttrium (Y), lanthanum (La), cerium (Ce), terbium (Tb), dysprosium (Dy), holmium (Ho), thulium (Tm), and lutetium (Lu).
- the source and drain regions 115 may include a metal-based layer or a metal silicide-based layer.
- the metal-based layer may include a transition metal or a rare earth metal
- the metal silicide-based layer may include a conjugate material between a metal and silicon.
- the source and drain regions 115 include metal silicide, which is a conjugate material between a rare earth metal and silicon.
- FIGS. 3A to 3D are cross-sectional views illustrating the SBTT fabrication method in accordance with an embodiment of the present invention.
- a SOI substrate includes a support substrate 210 , a buried oxide layer 211 , and a silicon-based substrate 212 .
- a bulk substrate may be used.
- An ion implantation for forming a well and another ion implantation for adjusting a threshold voltage are performed.
- the silicon-based substrate 212 is doped with a P-type impurity ion such as boron.
- the silicon-based substrate 212 is doped with an N-type impurity ion such as phosphorus or arsenic, which is a group V element.
- a concentration of the impurity ion doped into the silicon-based substrate 212 is low being about 10 17 atoms/cm 3 or less.
- the silicon-based substrate 212 Prior to or after performing the ion implantation for forming the well, the silicon-based substrate 212 is dry etched such that a certain portion of the silicon-based substrate 212 remains over the buried oxide layer 211 . One remaining portion of the silicon-based substrate 212 becomes a channel region, and another remaining portion thereof becomes source and drain regions 215 (see FIG. 3D ).
- a gate electrode 213 is formed over a channel region of the silicon-based substrate 212 .
- the gate electrode 213 includes a metal-based layer or a metal silicide-based layer, which is formed of a conjugate material of a metal and silicon.
- the metal-based layer may include a transition metal or a rare earth metal.
- the transition metal may include one selected from a group consisting of Fe, Co, W, Ni, Pd, Pt, Mo, and Ti.
- the rare earth metal may include one selected from a group consisting of Er, Yb, Sm, Y, La, Ce, Tb, Dy, Ho, Tm, and Lu.
- the gate electrode 213 may include Pt, which provides a high Schottky barrier to electrons, or platinum silicide.
- the gate electrode 213 may include erbium silicide, which provides a high Schottky barrier to holes.
- a method of forming the gate electrode 213 based on a metal or silicide will be described in detail. First, among various possible metals, the case of using Pt as the gate electrode 213 will be described. A layer of Pt is formed over the silicon-based substrate 212 , and a buffer layer and a hard mask layer are formed over the Pt layer.
- the buffer layer and the hard mask layer include an oxide-based material and a nitride-based material, respectively.
- the hard mask layer, the buffer layer, and the Pt layer are etched using an etch mask. As a result, the gate electrode 213 having the profile as illustrated in FIG. 3B is formed over the channel region of the silicon-based substrate 212 .
- a method of forming the gate electrode 213 based on platinum silicide will be described.
- a layer of Pt is formed over the silicon-based substrate 212 , and etched using an etch mask to make a portion of the Pt layer remain over the channel region of the silicon-based substrate 212 .
- a resultant structure is then heat treated to allow a reaction between Pt from the Pt layer and silicon from the silicon-based substrate 212 , so as to produce platinum silicide.
- a portion of the Pt layer that does not react with the silicon is removed.
- the gate electrode 213 is formed over the channel region.
- an insulation layer for use in a spacer is formed over a resultant surface profile of the gate electrode 213 and the silicon-based substrate 212 .
- An etch-back treatment such as a dry etching is performed on the insulation layer to form spacers 214 on both sidewalls of the gate electrode 213 .
- the spacers 214 are formed to prevent an electric short circuit event between the gate electrode 213 and the subsequent source and drain regions 215 .
- Any insulation material may be used for the spacers 214 . For instance, an oxide-based material, a nitride-based material, or a stack structure thereof may be used for the spacer material.
- the aforementioned source and drain regions 215 are formed in the silicon-based substrate 212 exposed by the spacers 214 .
- the source and drain regions 215 may include a conjugate material between a transition or rare earth metal and silicon.
- the source and drain regions 215 are formed as follows. A metal-based layer is formed over a resultant surface profile of the spacers 214 and the silicon-based substrate 212 , and heat treated to react with silicon from a region where the source and drain regions 215 are to be formed. As a result, a silicide layer that is self-aligned by the spacers is formed.
- a layer including a transition or rare earth metal is formed over the resultant surface profile of the spacers 214 and the silicon-based substrate 212 , and a rapid thermal annealing (RTA) treatment is performed thereon.
- RTA rapid thermal annealing
- the thickness of the above metal-based layer, reaction temperature, and time are adjusted to allow the silicide reaction to proceed until a bottom portion of the source and drain regions 215 reach an upper portion of the buried oxide layer 211 .
- a portion of the metal-based layer that does not react with the silicon is removed by a cleaning treatment. For instance, a sputtering method is performed inside a chamber using argon (Ar), or the resultant structure including the metal-based layer is cleaned by being dipped into a solution of hydrogen fluoride (HF).
- the source and drain regions 215 may include a rare earth metal-based material having a high Schottky barrier to electrons.
- the rare earth metal-based material may include erbium silicide.
- the source and drain regions 215 may include Pt having a low Schottky barrier to holes or platinum silicide.
- an Er layer is formed over the resultant surface profile, and heat treated at about 500° C. to about 600° C. to make Er from the Er layer react with silicon from the silicon-based substrate 212 .
- an erbium silicide layer is formed.
- a Pt layer is formed over the resultant surface profile, and heat treated at about 400° C. to 600° C. to allow a reaction between silicon and Pt, so as to form a platinum silicide layer.
- silicide-based Schottky junctions formed as the gate electrode and the source and drain regions.
- These embodiments illustrate one approach to overcome a decrease in saturation current, usually caused by parasitic resistance generated when shallow junctions (e.g., source and drain regions) are formed, and a difficulty in thinly forming a gate insulation layer, both usually observed in minimizing MOSFETs based on the conventional technology.
- a SBTT can be fabricated using the conventional MOSFET fabrication equipment, and thus, manufacturing costs can be reduced.
- the embodied SBTT technology allows skipping of several processes (e.g., process of forming gate insulation layer), and thus, a simplified fabrication processes can be achieved. Since the embodied SBTT structure and fabrication method follow an operational principle based on the quantum mechanical physical law, the embodied method can be easily applied in various fields.
Abstract
A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the gate electrode.
Description
- The present invention claims priority of Korean patent application number 10-2006-0118986 filed on Nov. 29, 2006, which is incorporated by reference in its entirety.
- The present invention relates to a semiconductor device and a method for fabricating the same, more particularly, to a Schottky barrier tunnel transistor and a method for fabricating the same.
- Advancement in semiconductor technology and equipment leads to fabrication of transistors with a short channel of 100 nanometers (nm) or less. Devices following the typical simple electrical physical laws accompany quantum mechanical phenomena. A single electron transistor (SET) is one representative example for such devices.
- A conventional structure of the SET usually uses a barrier that is generated by forming a pattern in an artificial shape over a silicon-based structure using a difference in an oxidation rate relying on a pattern. This characteristic may worsen an operational characteristic of a device in view of the Moore's law.
- In a transistor with a channel length less than 100 nm, leakage current is likely to occur due to a short channel effect. Thus, an appropriate control is generally required. In an attempt to suppress the short channel effect, the junction depth of a source and a drain needs to be in a range of ⅓ to ¼ of the channel length. Although many researchers put an effect to form a shallow junction with low accelerating voltage while continuously using an ion implantation, Implemented typically in semiconductor fabrication processes, it is often difficult to control the junction depth of the source and the drain to be shallow and uniform below 30 nm. Thus, one suggested method is to diffuse impurity ions using a rapid thermal process (RTP), a laser annealing process, or a solid phase diffusion (SPD) process. However, this impurity ion diffusion method may be limited to obtain a junction depth of 10 nm or less. Furthermore, as the junction depth decreases, parasitic resistance components of the source and drain including a source-drain extension region caused by the diffusion of the impurity ions increase. Based on this relationship, in the assumption that a doping concentration is 1×1019 atoms/cm3 and a junction depth is 10 nm, a sheet resistance is 500 ohms (Ω)/sq. or more. This value exceeds a sheet resistance of about 300 (Ω)/sq. proposed by the international technology roadmap for semiconductor (ITRS), and may cause a limitation such as signal delay.
- In addition to the implementation of the shallow junction depth of the source and drain, permittivity of a gate insulation layer (e.g., oxide) needs to increase to suppress the short channel effect. Many researches have been done to replace a silicon oxide layer, which is typically used in these days, with an oxide layer containing a rare earth metal of a high dielectric constant. However, as compared with the silicon oxide layer, the rare earth metal-based oxide layer may not be effectively heat treated due to its thermal instability. Therefore, a heat treatment in semiconductor processes needs to be performed at low temperature to use such a rare earth metal-based oxide layer. In that case, a heat treatment that proceeds after the ion implantation to activate ions and recover crystal damage may be performed with some limitations.
- For the minimization of metal oxide semiconductor field effect transistors (MOSFETs), those limitations associated with a gate oxide material and shallow junctions between source-drain regions and channels need to be overcome in respect of the short channel effect. One proposed approach is Schottky barrier tunnel transistor (SBTT) technology. In detail, source and drain regions of MOSFETs are replaced with a metal or silicide. As compared with the conventional MOSFETs, the sheet resistance measured when the SBTT technology is employed decreases by 1/10-fold to 1/50-fold. Thus, an operation speed can be improved, and a channel length can decrease to 35 nm or less. Also, since an ion implantation is not necessary, a subsequent heat treatment is also not necessary. As a result, a process for fabricating devices using a gate oxide layer based on a high-K dielectric material can be co-used in the SBTT technology. As compared with the conventional MOSFET technology, even though the subsequent heat treatment is implemented, the heat treatment is performed at low temperature. Thus, a process of forming gates based on a metal can be co-used in the SBTT technology.
-
FIG. 1 illustrates a cross-sectional view of a conventional SBTT structure. The SBTT includes: asubstrate 10; a buriedoxide layer 11 formed on thesubstrate 10; source anddrain regions 12 formed inside a silicon-on-insulator (SOI) substrate, which is formed on the buriedoxide layer 11; agate insulation layer 13 formed on achannel region 16 of the SOT substrate; agate electrode 14 formed on thegate insulation layer 13; andspacers 15 formed on both sidewalls of thegate electrode 14. - The conventional SBTT is formed to have a vertical structure in which the
gate insulation layer 13 and thegate electrode 14 are formed in sequence on the SOI substrate. The conventional SBTT structure is similar to the conventional MOSFET structure. Different from the conventional MOSFET fabrication process, the source anddrain regions 12 in the SBTT structure are not formed by the ion implantation but usually by a sputtering method. Based on the sputtering method, a thin metal film is first deposited, and heat treated to form a silicide layer. - However, since the conventional SBTT has a structure in which the gate insulation layer is interposed underneath the gate electrode, in consideration of the short channel effect, the gate insulation layer may be formed of a high-K dielectric material-based thin film, or the thickness of the gate insulate layer needs to be reduced. In the case of using polysilicon as a gate electrode material, an effective oxide thickness increases due to a depletion effect observed between the gate electrode and the gate insulation layer. In particular, the conventional SBTT technology may have a difficulty in satisfying a required effective oxide thickness of 1.5 nm or less in a device with a line width of 50 nm or less. Also, among high-K dielectric thin films, it may still be difficult to develop a thin film that can have a stable effective insulation thickness of 2 nm or less.
- Specific embodiments of the present invention are directed toward providing a Schottky barrier tunnel transistor capable of suppressing a short channel effect with a simple structure.
- Specific embodiments of the present invention are directed toward providing a method for fabricating a Schottky barrier tunnel transistor through a simplified process.
- In accordance with one aspect of the present invention, there is provided a Schottky barrier tunnel transistor. The Schottky barrier tunnel transistor includes a gate electrode formed over a channel region of a substrate to form a Schottky junction with the substrate, and source and drain regions formed in the substrate exposed on both sides of the gate electrode.
- In accordance with another embodiment of the present invention, there is provided a method for fabricating a Schottky barrier tunnel transistor. The method includes forming a gate electrode over a channel region of a substrate, the gate electrode providing a Schottky junction with the substrate, forming spacers over sidewalls of the gate electrode, and forming source and drain regions in the substrate exposed on both sides of the spacers.
-
FIG. 1 illustrates a cross-sectional view of a conventional Schottky barrier tunnel transistor (SBTT). -
FIG. 2 illustrates a cross-sectional view of a SBTT in accordance with an embodiment of the present invention. -
FIGS. 3A to 3D are cross-sectional views illustrating a method for fabricating a SBTT in accordance with an embodiment of the present invention. -
FIG. 2 illustrates a cross-sectional view of a Schottky barrier tunnel transistor (SBTT) in accordance with an embodiment of the present invention. In the following drawings, the thickness of layers and regions are exaggerated for clarity of the description, and when it is described that one layer is formed on another layer or a substrate, the term “on” indicates that the layer may be formed directly on the other layer or the substrate, or a third layer may be interposed therebetween. - The SBTT includes a silicon-based
substrate 112, agate electrode 113, and source and drain regions 115. Thegate electrode 113 is formed over a channel region of the silicon-basedsubstrate 112, so as to form a Schottky junction with the silicon-basedsubstrate 112. The source and drain regions 115 are formed inside the silicon-basedsubstrate 112 exposed on both sides of thegate electrode 113, and include silicide. - The silicon-based
substrate 112 includes the channel region, and may be a silicon-on-insulator (SOI) substrate or a bulk substrate, which has a low unit cost. For instance, in the case of fabricating a P-type device in which holes function as carriers, the silicon-basedsubstrate 112 is doped with a P-type impurity ion including a group III element such as boron (B). In the case of fabricating an N-type device in which electrons function as carriers, the silicon-basedsubstrate 112 is doped with an N-type impurity ion including a group V element such as phosphorus (P) or arsenic (As). A concentration of such an impurity ion is low being about 1017 atoms/cm3 or less. The silicon-basedsubstrate 112 is formed as thin as possible. For instance, a thickness of the silicon-basedsubstrate 112 may be about 100 nm or less. More specifically, the silicon-basedsubstrate 112 is formed to a thickness that allows control of an electric field that a gate controls. Thus, the thickness of the channel region that the gate controls decreases, so that formation of an inversion layer can be easily controlled. As a result, leakage current usually generated between the source and drain regions 115 can be reduced. - The
gate electrode 113 directly contacts the channel region, thereby forming a Schottky junction with the silicon-basedsubstrate 112. Thegate electrode 113 may include a metal-based layer or a metal silicide-based layer, which is a conjugate material between a metal and silicon. For example, the metal-based layer may include a transition metal or rare earth metal. The transition metal may include one selected from a group consisting of iron (Fe), cobalt (Co), tungsten (W), nickel (Ni), palladium (Pd), platinum (Pt), molybdenum (Mo), and titanium (Ti). The rare earth metal may include one selected from a group consisting of erbium (Er), ytterbium (Yb), samarium (Sm), yttrium (Y), lanthanum (La), cerium (Ce), terbium (Tb), dysprosium (Dy), holmium (Ho), thulium (Tm), and lutetium (Lu). - As similar to the
gate electrode 113, the source and drain regions 115 may include a metal-based layer or a metal silicide-based layer. The metal-based layer may include a transition metal or a rare earth metal, and the metal silicide-based layer may include a conjugate material between a metal and silicon. More specifically, the source and drain regions 115 include metal silicide, which is a conjugate material between a rare earth metal and silicon. - A method for fabricating the SBTT illustrated in
FIG. 2 will be described in detail.FIGS. 3A to 3D are cross-sectional views illustrating the SBTT fabrication method in accordance with an embodiment of the present invention. - Referring to
FIG. 3A , a SOI substrate includes asupport substrate 210, a buriedoxide layer 211, and a silicon-basedsubstrate 212. Instead of the SOI substrate, a bulk substrate may be used. An ion implantation for forming a well and another ion implantation for adjusting a threshold voltage are performed. For instance, for the ion implantation for forming the well, when a P-type device is to be fabricated, the silicon-basedsubstrate 212 is doped with a P-type impurity ion such as boron. On the other hand, when an N-type device is to be fabricated, the silicon-basedsubstrate 212 is doped with an N-type impurity ion such as phosphorus or arsenic, which is a group V element. A concentration of the impurity ion doped into the silicon-basedsubstrate 212 is low being about 1017 atoms/cm3 or less. - Prior to or after performing the ion implantation for forming the well, the silicon-based
substrate 212 is dry etched such that a certain portion of the silicon-basedsubstrate 212 remains over the buriedoxide layer 211. One remaining portion of the silicon-basedsubstrate 212 becomes a channel region, and another remaining portion thereof becomes source and drain regions 215 (seeFIG. 3D ). - Referring to
FIG. 3B , agate electrode 213 is formed over a channel region of the silicon-basedsubstrate 212. Thegate electrode 213 includes a metal-based layer or a metal silicide-based layer, which is formed of a conjugate material of a metal and silicon. For instance, the metal-based layer may include a transition metal or a rare earth metal. The transition metal may include one selected from a group consisting of Fe, Co, W, Ni, Pd, Pt, Mo, and Ti. The rare earth metal may include one selected from a group consisting of Er, Yb, Sm, Y, La, Ce, Tb, Dy, Ho, Tm, and Lu. - In the case of fabricating an N-type device, the
gate electrode 213 may include Pt, which provides a high Schottky barrier to electrons, or platinum silicide. In the case of fabricating a P-type device, thegate electrode 213 may include erbium silicide, which provides a high Schottky barrier to holes. - A method of forming the
gate electrode 213 based on a metal or silicide will be described in detail. First, among various possible metals, the case of using Pt as thegate electrode 213 will be described. A layer of Pt is formed over the silicon-basedsubstrate 212, and a buffer layer and a hard mask layer are formed over the Pt layer. The buffer layer and the hard mask layer include an oxide-based material and a nitride-based material, respectively. The hard mask layer, the buffer layer, and the Pt layer are etched using an etch mask. As a result, thegate electrode 213 having the profile as illustrated inFIG. 3B is formed over the channel region of the silicon-basedsubstrate 212. - Among various possible metal silicide-based materials, a method of forming the
gate electrode 213 based on platinum silicide will be described. A layer of Pt is formed over the silicon-basedsubstrate 212, and etched using an etch mask to make a portion of the Pt layer remain over the channel region of the silicon-basedsubstrate 212. A resultant structure is then heat treated to allow a reaction between Pt from the Pt layer and silicon from the silicon-basedsubstrate 212, so as to produce platinum silicide. A portion of the Pt layer that does not react with the silicon is removed. As a result, thegate electrode 213 is formed over the channel region. - Referring to
FIG. 3C , although not illustrated, an insulation layer for use in a spacer is formed over a resultant surface profile of thegate electrode 213 and the silicon-basedsubstrate 212. An etch-back treatment such as a dry etching is performed on the insulation layer to form spacers 214 on both sidewalls of thegate electrode 213. Thespacers 214 are formed to prevent an electric short circuit event between thegate electrode 213 and the subsequent source and drainregions 215. Any insulation material may be used for thespacers 214. For instance, an oxide-based material, a nitride-based material, or a stack structure thereof may be used for the spacer material. - Referring to
FIG. 3D , the aforementioned source and drainregions 215 are formed in the silicon-basedsubstrate 212 exposed by thespacers 214. The source and drainregions 215 may include a conjugate material between a transition or rare earth metal and silicon. For instance, the source and drainregions 215 are formed as follows. A metal-based layer is formed over a resultant surface profile of thespacers 214 and the silicon-basedsubstrate 212, and heat treated to react with silicon from a region where the source and drainregions 215 are to be formed. As a result, a silicide layer that is self-aligned by the spacers is formed. - In more detail of the formation of the source and drain
regions 215, a layer including a transition or rare earth metal is formed over the resultant surface profile of thespacers 214 and the silicon-basedsubstrate 212, and a rapid thermal annealing (RTA) treatment is performed thereon. The thickness of the above metal-based layer, reaction temperature, and time are adjusted to allow the silicide reaction to proceed until a bottom portion of the source and drainregions 215 reach an upper portion of the buriedoxide layer 211. A portion of the metal-based layer that does not react with the silicon is removed by a cleaning treatment. For instance, a sputtering method is performed inside a chamber using argon (Ar), or the resultant structure including the metal-based layer is cleaned by being dipped into a solution of hydrogen fluoride (HF). - In the case of fabricating an N-type device, the source and drain
regions 215 may include a rare earth metal-based material having a high Schottky barrier to electrons. The rare earth metal-based material may include erbium silicide. In the case of fabricating a P-type device, the source and drainregions 215 may include Pt having a low Schottky barrier to holes or platinum silicide. - For instance, in the case of using erbium silicide as the source and drain
regions 215, an Er layer is formed over the resultant surface profile, and heat treated at about 500° C. to about 600° C. to make Er from the Er layer react with silicon from the silicon-basedsubstrate 212. As a result of this reaction, an erbium silicide layer is formed. In the case of forming the source and drainregions 215 based on platinum silicide, a Pt layer is formed over the resultant surface profile, and heat treated at about 400° C. to 600° C. to allow a reaction between silicon and Pt, so as to form a platinum silicide layer. - According to various embodiments of the present invention, silicide-based Schottky junctions formed as the gate electrode and the source and drain regions. These embodiments illustrate one approach to overcome a decrease in saturation current, usually caused by parasitic resistance generated when shallow junctions (e.g., source and drain regions) are formed, and a difficulty in thinly forming a gate insulation layer, both usually observed in minimizing MOSFETs based on the conventional technology. Furthermore, a SBTT can be fabricated using the conventional MOSFET fabrication equipment, and thus, manufacturing costs can be reduced. As compared with the conventional technology, the embodied SBTT technology allows skipping of several processes (e.g., process of forming gate insulation layer), and thus, a simplified fabrication processes can be achieved. Since the embodied SBTT structure and fabrication method follow an operational principle based on the quantum mechanical physical law, the embodied method can be easily applied in various fields.
- While the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
Claims (9)
1. A Schottky barrier tunnel transistor comprising:
a gate electrode formed over a channel region of a substrate to form a Schottky junction with the substrate; and
source and drain regions formed in the substrate exposed on both sides of the gate electrode.
2. The Schottky barrier tunnel transistor of claim 1 , wherein the gate electrode comprises one of a metal-based layer and a metal silicide-based layer, wherein the metal-based layer comprises one of a transition metal and a rare earth metal, and the metal silicide-based layer comprises a material obtained by conjugating the metal-based layer and the substrate together.
3. The Schottky barrier tunnel transistor of claim 1 , wherein the source and drain regions comprise a metal silicide-based material.
4. The Schottky barrier tunnel transistor of claim 1 , wherein the source and drain regions comprise one of a metal-based layer and a metal silicide-based layer, wherein the metal-based layer comprises one of a transition metal and a rare earth metal, and the metal silicide-based layer comprises a material obtained by conjugating the metal-based layer and the substrate together.
5. The Schottky barrier tunnel transistor of claim 1 , wherein the substrate comprises one of a silicon-on-insulator (SOI) substrate and a bulk substrate.
6. The Schottky barrier tunnel transistor of claim 5 , wherein the silicon-on-insulator substrate comprises:
a support substrate used to provide a mechanical support;
a buried oxide layer formed over the support substrate; and
a silicon layer formed over the buried oxide layer.
7. The Schottky barrier tunnel transistor of claim 6 , wherein the source and drain regions are formed such that a bottom portion of the source and drain regions contacts an upper portion of the buried oxide layer.
8. The Schottky barrier tunnel transistor of claim 1 , further comprising spacers formed on sidewalls of the gate electrode.
9. The Schottky barrier tunnel transistor of claim 8 , wherein the source and drain regions are self-aligned in the substrate by the spacers.
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KR1020060118986A KR100770012B1 (en) | 2006-11-29 | 2006-11-29 | Schottky barrier tunnel transistor and method for manufacturing the same |
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US11/800,914 US7863121B2 (en) | 2006-11-29 | 2007-05-08 | Method for fabricating Schottky barrier tunnel transistor |
US12/957,146 US20110068326A1 (en) | 2006-11-29 | 2010-11-30 | Schottky barrier tunnel transistor and method for fabricating the same |
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US20120315708A1 (en) * | 2011-06-13 | 2012-12-13 | Mitsubishi Electric Corporation | Method for manufacturing semiconductor device |
WO2019054989A1 (en) * | 2017-09-12 | 2019-03-21 | Intel Corporation | Semiconductor devices with metal contacts including crystalline alloys |
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KR102266960B1 (en) | 2016-03-02 | 2021-06-18 | 한국전자통신연구원 | Schottky diode and manufacturing method of the same |
US10068981B2 (en) * | 2016-03-02 | 2018-09-04 | Lam Research Corporation | Rare earth metal surface-activated plasma doping on semiconductor substrates |
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US7863121B2 (en) | 2011-01-04 |
KR100770012B1 (en) | 2007-10-25 |
US20080121868A1 (en) | 2008-05-29 |
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