US20100044762A1 - Method for forming a semiconductor device and structure thereof - Google Patents
Method for forming a semiconductor device and structure thereof Download PDFInfo
- Publication number
- US20100044762A1 US20100044762A1 US12/605,556 US60555609A US2010044762A1 US 20100044762 A1 US20100044762 A1 US 20100044762A1 US 60555609 A US60555609 A US 60555609A US 2010044762 A1 US2010044762 A1 US 2010044762A1
- Authority
- US
- United States
- Prior art keywords
- current electrode
- fin
- region
- germanium
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 238000000034 method Methods 0.000 title abstract description 41
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 54
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 53
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 31
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 24
- 239000010703 silicon Substances 0.000 claims abstract description 24
- 239000007943 implant Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 14
- 230000008021 deposition Effects 0.000 abstract description 5
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 41
- 238000004519 manufacturing process Methods 0.000 description 29
- 230000003647 oxidation Effects 0.000 description 18
- 238000007254 oxidation reaction Methods 0.000 description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 6
- 230000001590 oxidative effect Effects 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- -1 hafnium oxide) Chemical compound 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
Definitions
- the invention relates in general to semiconductor devices, and in particular to a method for forming a semiconductor device.
- silicon germanium materials in some silicon based semiconductor devices can provide a significant improvement in performance of the devices.
- the silicon germanium materials may be used to increase the hole and electron mobility in the channel region of a transistor.
- An improved method for forming devices using silicon germanium materials is desired.
- FIG. 1 is a cross-sectional view of a portion of a wafer during a stage in its manufacture in accordance with one embodiment
- FIG. 2 is a cross-sectional view of a portion of a wafer during a stage in its manufacture in accordance with one embodiment
- FIG. 3 is a cross-sectional view of a portion of a wafer during a stage in its manufacture in accordance with one embodiment
- FIG. 4 is a cross-sectional view of a portion of a wafer of FIG. 2 during a stage in its manufacture in accordance with an alternate embodiment
- FIG. 5 is a cross-sectional view of a portion of a wafer of FIG. 4 during a stage in its manufacture in accordance with one embodiment
- FIG. 6 is a cross-sectional view of a portion of a wafer of FIG. 2 during a stage in its manufacture in accordance with an alternate embodiment
- FIG. 7 is a cross-sectional view of a portion of a wafer of FIG. 5 during a stage in its manufacture in accordance with one alternate embodiment
- FIG. 8 is a cross-sectional view of a portion of a wafer of FIG. 7 during a stage in its manufacture in accordance with one embodiment
- FIG. 9 is a cross-sectional view of a portion of a wafer of FIG. 3 , 4 , 5 or 6 during a stage in its manufacture in accordance with one embodiment
- FIG. 10 is a top view of a portion of a wafer of FIG. 2 during a stage in its manufacture in accordance with one embodiment
- FIG. 11 is a top view of a portion of a wafer of FIG. 3 , 4 , 5 , or 6 during a stage in its manufacture in accordance with one embodiment
- FIG. 12 is a top view of a portion of a wafer of FIG. 6 during a stage in its manufacture in accordance with one embodiment
- FIG. 13 is a top view of a portion of a wafer of FIG. 8 during a stage in its manufacture in accordance with one embodiment
- FIG. 14 is a top view of a portion of a wafer of FIG. 9 during a stage in its manufacture in accordance with one embodiment.
- FIG. 15 is a cross-sectional view of a portion of a wafer of FIG. 3 , 4 , 5 , or 6 during a stage in its manufacture in accordance with an alternate embodiment.
- FIG. 1 is a cross-sectional view of a portion of a wafer 10 during a stage in its manufacture in accordance with one embodiment.
- wafer 10 comprises a substrate 18 , a insulating layer 16 overlying substrate 18 , a monocrystalline semiconductor layer 14 overlying layer 16 , and an insulating layer 12 overlying layer 14 .
- substrate 18 is monocrystalline semiconductor material such as silicon. Alternate embodiments may use other materials for substrate 18 , such as, for example, sapphire, glass, or any other appropriate substrate material or combination or materials.
- insulating layer 16 is a buried oxide layer (commonly called “BOX”) comprising silicon dioxide.
- Alternate embodiments may use any suitable dielectric materials for layer 16 , such as, for example, silicon nitride, metal oxides (e.g. hafnium oxide), or any plurality of layers of appropriate materials.
- layer 14 is monocrystalline silicon on insulator (SOI) layer.
- layer 14 may be silicon carbon crystal (SiC) or any other semiconductor material with the appropriate properties.
- insulating layer 12 comprises a capping layer of silicon nitride.
- Alternate embodiments may use any suitable dielectric materials for layer 12 , such as, for example, metal oxides (e.g. hafnium oxide), or any plurality of layers of appropriate materials.
- alternate embodiments may include an oxide pad layer interposed between layers 14 and 16 (not shown). Alternate embodiments may not use insulating layer 12 .
- FIG. 2 is a cross-sectional view of a portion of a wafer 10 of FIG. 1 after patterning layers 12 and 14 in accordance with one embodiment.
- the patterned portion of layer 14 is designated with reference number 22
- the patterned portion of layer 12 is designated with reference number 20 .
- structure 42 (formed of material 22 ) is a portion of a fin of a FINFET (fin field effect transistor), MIGFET (multiple independent gate field effect transistor), Tri-gate (three non-independent gates) device, or multi-gate (a plurality of non-independent gates) device. Note that in the case of a Tri-gate transistor, the region 20 may be removed and the geometry of region 22 (fin) may assume other aspect ratios (i.e. height vs.
- structure 22 may be a portion of a fin of a different type of device.
- FINFETs, MIGFETs, Tri-gates, and multi-gates are just three examples of non-planar devices that make use of a fin.
- the illustrated embodiment only shows one fin, alternate embodiments may use any number of fins in the same device.
- FIG. 10 is a top view of a portion of a wafer of FIG. 2 during a stage in its manufacture in accordance with one embodiment.
- FIG. 10 illustrates how fin 42 (comprised of material 22 ) may be coupled to a first current electrode 44 (comprised of material 22 ) and a second current electrode 46 (comprised of material 22 ).
- fin 42 has been shown as having an approximately rectangular shape
- the first current electrode has been shown having an approximately circular shape
- the second current electrode has been shown having an approximately circular shape
- alternate embodiments may use any desired shapes or geometries for structures 42 , 44 , and 46 .
- 42 may comprise 20 and 22 if it is a top view of FIGS. 2-5 , 42 may comprise 20 , 22 , and 32 if it is a top view of FIG. 6 , and 42 may comprise 20 and 36 if it is a top view of FIG. 8 . In alternate embodiments, 42 may comprise fewer, more, or different layers than those illustrated.
- FIG. 3 is a cross-sectional view of a portion of a wafer 10 of FIG. 2 during a stage in its manufacture in accordance with one embodiment.
- FIG. 3 illustrates wafer 10 after selective deposition of a semiconductor material 24 .
- the semiconductor material 24 comprises silicon germanium. Alternate embodiments may deposit any desired semiconductor material that has the necessary properties.
- semiconductor material 24 may be monocrystalline. In alternate embodiments, semiconductor material 24 may be polycrystalline or amorphous.
- FIG. 4 is a cross-sectional view of a portion of a wafer of FIG. 2 during a stage in its manufacture in accordance with an alternate embodiment.
- FIG. 4 illustrates wafer 10 after non-selective deposition of a semiconductor material 26 .
- the semiconductor material 26 comprises silicon germanium. Alternate embodiments may deposit any desired semiconductor material that has the necessary properties.
- the portion of semiconductor material 26 in contact with semiconductor material 22 may be monocrystalline.
- all or various portions of semiconductor material 26 may be polycrystalline or amorphous.
- FIG. 5 is a cross-sectional view of a portion of a wafer of FIG. 4 during a stage in its manufacture in accordance with one embodiment.
- FIG. 5 illustrates wafer 10 of FIG. 4 after anisotropic etch of layer 26 , leaving spacers 28 disposed on the sidewalls of the stack 22 , 20 .
- Any appropriate etch may be used, such as, for example, a plasma etch.
- FIG. 11 is a top view of a portion of a wafer of FIG. 3 , 4 , 5 , or 6 during a stage in its manufacture in accordance with one embodiment.
- FIG. 11 illustrates how fin 42 (comprised of material 22 ) may be coupled to a first current electrode 44 (comprised of material 22 ) and a second current electrode 46 (comprised of material 22 ).
- FIG. 11 differs from FIG. 10 in that semiconductor material 24 (see FIG. 3 ), semiconductor material 26 (see FIG. 4 ), or semiconductor material 28 (see FIG. 5 ) have been formed in contact with material 22 in FIG. 11 .
- FIG. 6 is a cross-sectional view of a portion of a wafer of FIG. 2 during a stage in its manufacture in accordance with an alternate embodiment.
- FIG. 6 illustrates wafer 10 of FIG. 2 after ion implantation 30 of wafer 10 .
- the ion implant species comprises germanium.
- the germanium atom dose may be in the range of 5 ⁇ 10e14 to 5 ⁇ 10e15.
- the germanium atom dose may be in the range of 5 ⁇ 10e13 to 5 ⁇ 10e16.
- Alternate embodiments may use any desired germanium atom dose.
- the ion implant angle may be in the range of 30 degrees to 10 degrees (measured from the perpendicular to the primary wafer surface). In alternate embodiments, the ion implant angle may be in the range of 45 degrees to 5 degrees (again measured from the perpendicular to the primary wafer surface). In one embodiment, the ion implant energy may range from 5 keV to 80 keV. In an alternate embodiment, the implant energy may range from 1 keV to 120 keV. Alternate embodiments may use any desired ion implant energy.
- FIG. 7 is a cross-sectional view of a portion of a wafer of FIG. 5 during a stage in its manufacture in accordance with one alternate embodiment.
- FIG. 7 illustrates wafer 10 of FIG. 5 after oxidation where the spacers 28 have been transformed into the silicon oxide portions 34 during oxidation. Note that in the illustrated embodiment, the oxidation not only transforms spacers 28 , but also may transform portions of material 22 . During this oxidation step, germanium atoms from spacers 28 are injected into the remaining portion of material 22 , transforming the original silicon material 22 into silicon germanium material 36 . Note that oxidizing the fin allows a channel region comprising silicon germanium to be formed in the fin 36 .
- the channel region comprises all of fin 36 once the oxide is removed (see FIG. 8 ). Alternate embodiments may only form the channel region in a portion of fin 36 .
- oxidation such as, for example, wet or steam oxidation, oxidation in hydrochloric acid ambient, or any other appropriate oxidation process. Note that the oxidation step may result in an effectively thinner fin 36 , beyond what the lithographic capabilities of processing equipment may allow. For some embodiments, a thinner fin 36 may produce fully depleted devices which have improved performance characteristics.
- FIGS. 3 and 6 may also be oxidized in the same or similar manner as illustrated in FIG. 7 .
- the top of region 34 will be substantially level with the bottom of layer 20 for the embodiments illustrated in FIG. 3 and 6 .
- wafer 10 illustrated in FIG. 4 may be oxidized in the same or similar manner as illustrated in FIG. 7 .
- the entire layer 26 may be transformed into silicon oxide.
- FIG. 8 is a cross-sectional view of a portion of a wafer of FIG. 7 during a stage in its manufacture in accordance with one embodiment.
- FIG. 8 illustrates the wafer of FIG. 7 after removal of the silicon oxide 34 .
- the etch process used to remove silicon oxide 34 may also cause erosion of the top portion of layer 16 if layer 16 is silicon oxide. In some embodiments, this erosion may be desirable due to better uniformity of gate strength across the entire fin channel.
- FIG. 9 is a cross-sectional view of a portion of a wafer of FIG. 3 , 4 , 5 or 6 during a stage in its manufacture in accordance with one embodiment.
- FIG. 9 illustrates one finished device 10 , namely a FINFET transistor, that may use the structure of FIG. 8 .
- a gate dielectric layer 38 is disposed over stack 36 and 20 .
- the gate dielectric layer 38 may be deposited by PVD (physical vapor deposition), ALD (atomic layer deposition), or CVD (chemical vapor deposition).
- dielectrics For PVD, ALD, and CVD, a variety of dielectrics may be deposited, such as, for example, metal oxides such as hafnium oxide, zirconium oxide, tantalum oxide, or any combination of any appropriate oxides, including oxides containing silicon and/or nitride. Alternately, dielectric layer 38 may be grown on only the sidewalls of 36 by using conventional gate oxidation processes. Still referring to FIG. 9 , the gate electrode may be deposited by CVD or PVD, and may include any appropriate gate materials, such as, for example, polysilicon, metal, metal silicide, or any combination of appropriate conductive materials. Note that the processing required to go from FIG. 8 to FIG. 9 may be performed using any known and appropriate techniques.
- FIG. 12 is a top view of a portion of a wafer of FIG. 6 during a stage in its manufacture in accordance with one embodiment. Note that 32 illustrates the depth of the implantation profile. Alternate embodiments may use a different implantation profile.
- FIG. 13 is a top view of a portion of a wafer of FIG. 8 during a stage in its manufacture in accordance with one embodiment.
- the oxidation process has transformed region 36 into silicon germanium, while the regions 48 and 50 remain silicon material.
- the first current electrode 44 comprises material 48 (e.g. silicon) and the portion of 36 (e.g. silicon germanium) surrounding 48 .
- the second current electrode 46 comprises material 50 (e.g. silicon) and the portion of 36 (e.g. silicon germanium) surrounding 50 .
- the fin (the portion of 36 between the first current electrode 44 and the second current electrode 46 ) is contiguous with the outer layer or region 36 surrounding region 48 , and is also contiguous with the outer layer or region 36 surrounding region 50 .
- the oxidation process produces an outer region 36 of a first current electrode 44 that comprises germanium while the inner region 48 of the first current electrode 44 is substantially free of germanium. Although the diffusion of the germanium which occurs during the oxidation process may result in a small amount of germanium diffusing into the inner region 48 , inner region 48 remains substantially free of germanium compared to the outer region 36 .
- the oxidation process produces an outer region 36 of a second current electrode 46 that comprises germanium while the inner region 50 of the second current electrode 46 is substantially free of germanium. Although the diffusion of the germanium which occurs during the oxidation process may result in a small amount of germanium diffusing into the inner region 50 , inner region 50 remains substantially free of germanium compared to the outer region 36 .
- FIG. 14 is a top view of a portion of a wafer of FIG. 9 during a stage in its manufacture in accordance with one embodiment.
- the oxidation process has transformed region 36 into silicon germanium, while the regions 48 and 50 remain silicon material.
- the first current electrode 44 comprises material 48 (e.g. silicon) and the portion of 36 (e.g. silicon germanium) surrounding 48 .
- the second current electrode 46 comprises material 50 (e.g. silicon) and the portion of 36 (e.g. silicon germanium) surrounding 50 .
- layer 38 is a dielectric layer and 40 is a gate electrode.
- FIG. 15 is a cross-sectional view of a portion of a wafer of FIG. 3 , 4 , 5 , or 6 during a stage in its manufacture in accordance with an alternate embodiment.
- FIG. 15 illustrates one finished device 10 , namely a MIGFET transistor, that may use the structure of FIG. 8 .
- a gate dielectric layer 38 is disposed over stack 36 and 20 .
- the gate dielectric layer 38 may be deposited by PVD (physical vapor deposition), ALD (atomic layer deposition), or CVD (chemical vapor deposition).
- dielectric layer 38 may be grown on only the sidewalls of 36 by using conventional gate oxidation processes.
- the gate electrode may be deposited by CVD or PVD, and may include any appropriate gate materials, such as, for example, polysilicon, metal, metal silicide, or any combination of appropriate conductive materials.
- the independent gate electrode portions 140 and 142 of gate electrode 40 may be formed by using a CMP (chemical mechanical polishing) process on gate electrode 40 . Alternate embodiments may use any other desired and appropriate process to form the independent gate electrode portions 140 and 142 . Note that by using CMP, the portion of gate electrode 40 overlying layer 20 is removed, resulting in two electrically independent gate electrode portion 140 and 142 .
- the processing required to go from FIG. 8 to FIG. 15 may be performed using any known and appropriate techniques.
Abstract
Description
- This is related to U.S. patent application Ser. No. 11/273,092 filed Nov. 14, 2005, and entitled “Electronic Devices Including A Semiconductor Layer And A Process for Forming The Same” and is assigned to the current assignee hereof.
- The invention relates in general to semiconductor devices, and in particular to a method for forming a semiconductor device.
- Using silicon germanium materials in some silicon based semiconductor devices can provide a significant improvement in performance of the devices. For example, the silicon germanium materials may be used to increase the hole and electron mobility in the channel region of a transistor. An improved method for forming devices using silicon germanium materials is desired.
- The present invention is illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements, and in which:
-
FIG. 1 is a cross-sectional view of a portion of a wafer during a stage in its manufacture in accordance with one embodiment; -
FIG. 2 is a cross-sectional view of a portion of a wafer during a stage in its manufacture in accordance with one embodiment; -
FIG. 3 is a cross-sectional view of a portion of a wafer during a stage in its manufacture in accordance with one embodiment; -
FIG. 4 is a cross-sectional view of a portion of a wafer ofFIG. 2 during a stage in its manufacture in accordance with an alternate embodiment; -
FIG. 5 is a cross-sectional view of a portion of a wafer ofFIG. 4 during a stage in its manufacture in accordance with one embodiment; -
FIG. 6 is a cross-sectional view of a portion of a wafer ofFIG. 2 during a stage in its manufacture in accordance with an alternate embodiment; -
FIG. 7 is a cross-sectional view of a portion of a wafer ofFIG. 5 during a stage in its manufacture in accordance with one alternate embodiment; -
FIG. 8 is a cross-sectional view of a portion of a wafer ofFIG. 7 during a stage in its manufacture in accordance with one embodiment; -
FIG. 9 is a cross-sectional view of a portion of a wafer ofFIG. 3 , 4, 5 or 6 during a stage in its manufacture in accordance with one embodiment; -
FIG. 10 is a top view of a portion of a wafer ofFIG. 2 during a stage in its manufacture in accordance with one embodiment; -
FIG. 11 is a top view of a portion of a wafer ofFIG. 3 , 4, 5, or 6 during a stage in its manufacture in accordance with one embodiment; -
FIG. 12 is a top view of a portion of a wafer ofFIG. 6 during a stage in its manufacture in accordance with one embodiment; -
FIG. 13 is a top view of a portion of a wafer ofFIG. 8 during a stage in its manufacture in accordance with one embodiment; -
FIG. 14 is a top view of a portion of a wafer ofFIG. 9 during a stage in its manufacture in accordance with one embodiment; and -
FIG. 15 is a cross-sectional view of a portion of a wafer ofFIG. 3 , 4, 5, or 6 during a stage in its manufacture in accordance with an alternate embodiment. - Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
-
FIG. 1 is a cross-sectional view of a portion of awafer 10 during a stage in its manufacture in accordance with one embodiment. In one embodiment,wafer 10 comprises asubstrate 18, ainsulating layer 16overlying substrate 18, amonocrystalline semiconductor layer 14 overlyinglayer 16, and aninsulating layer 12overlying layer 14. In one embodiment,substrate 18 is monocrystalline semiconductor material such as silicon. Alternate embodiments may use other materials forsubstrate 18, such as, for example, sapphire, glass, or any other appropriate substrate material or combination or materials. In one embodiment,insulating layer 16 is a buried oxide layer (commonly called “BOX”) comprising silicon dioxide. Alternate embodiments may use any suitable dielectric materials forlayer 16, such as, for example, silicon nitride, metal oxides (e.g. hafnium oxide), or any plurality of layers of appropriate materials. In one embodiment,layer 14 is monocrystalline silicon on insulator (SOI) layer. In anotherembodiment layer 14 may be silicon carbon crystal (SiC) or any other semiconductor material with the appropriate properties. In one embodiment,insulating layer 12 comprises a capping layer of silicon nitride. Alternate embodiments may use any suitable dielectric materials forlayer 12, such as, for example, metal oxides (e.g. hafnium oxide), or any plurality of layers of appropriate materials. In addition, alternate embodiments may include an oxide pad layer interposed betweenlayers 14 and 16 (not shown). Alternate embodiments may not useinsulating layer 12. -
FIG. 2 is a cross-sectional view of a portion of awafer 10 ofFIG. 1 after patterninglayers layer 14 is designated withreference number 22, and the patterned portion oflayer 12 is designated withreference number 20. In one embodiment, structure 42 (formed of material 22) is a portion of a fin of a FINFET (fin field effect transistor), MIGFET (multiple independent gate field effect transistor), Tri-gate (three non-independent gates) device, or multi-gate (a plurality of non-independent gates) device. Note that in the case of a Tri-gate transistor, theregion 20 may be removed and the geometry of region 22 (fin) may assume other aspect ratios (i.e. height vs. width) than those shown inFIGS. 2-7 . In alternate embodiments,structure 22 may be a portion of a fin of a different type of device. FINFETs, MIGFETs, Tri-gates, and multi-gates are just three examples of non-planar devices that make use of a fin. In addition, although the illustrated embodiment only shows one fin, alternate embodiments may use any number of fins in the same device. -
FIG. 10 is a top view of a portion of a wafer ofFIG. 2 during a stage in its manufacture in accordance with one embodiment.FIG. 10 illustrates how fin 42 (comprised of material 22) may be coupled to a first current electrode 44 (comprised of material 22) and a second current electrode 46 (comprised of material 22). Althoughfin 42 has been shown as having an approximately rectangular shape, the first current electrode has been shown having an approximately circular shape, and the second current electrode has been shown having an approximately circular shape, alternate embodiments may use any desired shapes or geometries forstructures - Note that the
same reference numbers FIGS. 10-13 to represent thatfin 42, firstcurrent electrode 44, and a secondcurrent electrode 46 still all serve the same functional purpose fordevice 10. - In various embodiments, 42 may comprise 20 and 22 if it is a top view of
FIGS. 2-5 , 42 may comprise 20, 22, and 32 if it is a top view ofFIG. 6 , and 42 may comprise 20 and 36 if it is a top view ofFIG. 8 . In alternate embodiments, 42 may comprise fewer, more, or different layers than those illustrated. -
FIG. 3 is a cross-sectional view of a portion of awafer 10 ofFIG. 2 during a stage in its manufacture in accordance with one embodiment.FIG. 3 illustrateswafer 10 after selective deposition of asemiconductor material 24. In one embodiment, thesemiconductor material 24 comprises silicon germanium. Alternate embodiments may deposit any desired semiconductor material that has the necessary properties. In one embodiment, potentially a preferred embodiment,semiconductor material 24 may be monocrystalline. In alternate embodiments,semiconductor material 24 may be polycrystalline or amorphous. -
FIG. 4 is a cross-sectional view of a portion of a wafer ofFIG. 2 during a stage in its manufacture in accordance with an alternate embodiment.FIG. 4 illustrateswafer 10 after non-selective deposition of asemiconductor material 26. In one embodiment, thesemiconductor material 26 comprises silicon germanium. Alternate embodiments may deposit any desired semiconductor material that has the necessary properties. In one embodiment, potentially a preferred embodiment, the portion ofsemiconductor material 26 in contact withsemiconductor material 22 may be monocrystalline. In alternate embodiments, all or various portions ofsemiconductor material 26 may be polycrystalline or amorphous. -
FIG. 5 is a cross-sectional view of a portion of a wafer ofFIG. 4 during a stage in its manufacture in accordance with one embodiment.FIG. 5 illustrateswafer 10 ofFIG. 4 after anisotropic etch oflayer 26, leavingspacers 28 disposed on the sidewalls of thestack -
FIG. 11 is a top view of a portion of a wafer ofFIG. 3 , 4, 5, or 6 during a stage in its manufacture in accordance with one embodiment.FIG. 11 illustrates how fin 42 (comprised of material 22) may be coupled to a first current electrode 44 (comprised of material 22) and a second current electrode 46 (comprised of material 22). Note that in one embodiment,FIG. 11 differs fromFIG. 10 in that semiconductor material 24 (seeFIG. 3 ), semiconductor material 26 (seeFIG. 4 ), or semiconductor material 28 (seeFIG. 5 ) have been formed in contact withmaterial 22 inFIG. 11 . -
FIG. 6 is a cross-sectional view of a portion of a wafer ofFIG. 2 during a stage in its manufacture in accordance with an alternate embodiment.FIG. 6 illustrateswafer 10 ofFIG. 2 afterion implantation 30 ofwafer 10. In one embodiment, the ion implant species comprises germanium. Alternate embodiments may implant any desired semiconductor species that has the necessary properties. In one embodiment, the germanium atom dose may be in the range of 5×10e14 to 5×10e15. In an alternate embodiment, the germanium atom dose may be in the range of 5×10e13 to 5×10e16. Alternate embodiments may use any desired germanium atom dose. In one embodiment, the ion implant angle may be in the range of 30 degrees to 10 degrees (measured from the perpendicular to the primary wafer surface). In alternate embodiments, the ion implant angle may be in the range of 45 degrees to 5 degrees (again measured from the perpendicular to the primary wafer surface). In one embodiment, the ion implant energy may range from 5 keV to 80 keV. In an alternate embodiment, the implant energy may range from 1 keV to 120 keV. Alternate embodiments may use any desired ion implant energy. -
FIG. 7 is a cross-sectional view of a portion of a wafer ofFIG. 5 during a stage in its manufacture in accordance with one alternate embodiment.FIG. 7 illustrateswafer 10 ofFIG. 5 after oxidation where thespacers 28 have been transformed into thesilicon oxide portions 34 during oxidation. Note that in the illustrated embodiment, the oxidation not only transformsspacers 28, but also may transform portions ofmaterial 22. During this oxidation step, germanium atoms fromspacers 28 are injected into the remaining portion ofmaterial 22, transforming theoriginal silicon material 22 intosilicon germanium material 36. Note that oxidizing the fin allows a channel region comprising silicon germanium to be formed in thefin 36. In the illustrated embodiment, the channel region comprises all offin 36 once the oxide is removed (seeFIG. 8 ). Alternate embodiments may only form the channel region in a portion offin 36. There are a wide variety of methods that may be used to perform oxidation, such as, for example, wet or steam oxidation, oxidation in hydrochloric acid ambient, or any other appropriate oxidation process. Note that the oxidation step may result in an effectivelythinner fin 36, beyond what the lithographic capabilities of processing equipment may allow. For some embodiments, athinner fin 36 may produce fully depleted devices which have improved performance characteristics. - Note that the embodiments of
wafer 10 illustrated inFIGS. 3 and 6 may also be oxidized in the same or similar manner as illustrated inFIG. 7 . However, note that the top ofregion 34 will be substantially level with the bottom oflayer 20 for the embodiments illustrated inFIG. 3 and 6 . - Note that the embodiment of
wafer 10 illustrated inFIG. 4 may be oxidized in the same or similar manner as illustrated inFIG. 7 . However, note that theentire layer 26 may be transformed into silicon oxide. -
FIG. 8 is a cross-sectional view of a portion of a wafer ofFIG. 7 during a stage in its manufacture in accordance with one embodiment.FIG. 8 illustrates the wafer ofFIG. 7 after removal of thesilicon oxide 34. Note that for some embodiments, the etch process used to removesilicon oxide 34 may also cause erosion of the top portion oflayer 16 iflayer 16 is silicon oxide. In some embodiments, this erosion may be desirable due to better uniformity of gate strength across the entire fin channel. -
FIG. 9 is a cross-sectional view of a portion of a wafer ofFIG. 3 , 4, 5 or 6 during a stage in its manufacture in accordance with one embodiment.FIG. 9 illustrates onefinished device 10, namely a FINFET transistor, that may use the structure ofFIG. 8 . In the illustrated embodiment ofdevice 10, agate dielectric layer 38 is disposed overstack gate dielectric layer 38 may be deposited by PVD (physical vapor deposition), ALD (atomic layer deposition), or CVD (chemical vapor deposition). For PVD, ALD, and CVD, a variety of dielectrics may be deposited, such as, for example, metal oxides such as hafnium oxide, zirconium oxide, tantalum oxide, or any combination of any appropriate oxides, including oxides containing silicon and/or nitride. Alternately,dielectric layer 38 may be grown on only the sidewalls of 36 by using conventional gate oxidation processes. Still referring toFIG. 9 , the gate electrode may be deposited by CVD or PVD, and may include any appropriate gate materials, such as, for example, polysilicon, metal, metal silicide, or any combination of appropriate conductive materials. Note that the processing required to go fromFIG. 8 toFIG. 9 may be performed using any known and appropriate techniques. -
FIG. 12 is a top view of a portion of a wafer ofFIG. 6 during a stage in its manufacture in accordance with one embodiment. Note that 32 illustrates the depth of the implantation profile. Alternate embodiments may use a different implantation profile. -
FIG. 13 is a top view of a portion of a wafer ofFIG. 8 during a stage in its manufacture in accordance with one embodiment. Note that the oxidation process has transformedregion 36 into silicon germanium, while theregions current electrode 44 comprises material 48 (e.g. silicon) and the portion of 36 (e.g. silicon germanium) surrounding 48. The secondcurrent electrode 46 comprises material 50 (e.g. silicon) and the portion of 36 (e.g. silicon germanium) surrounding 50. In one embodiment of the present invention, the fin (the portion of 36 between the firstcurrent electrode 44 and the second current electrode 46) is contiguous with the outer layer orregion 36surrounding region 48, and is also contiguous with the outer layer orregion 36surrounding region 50. - Note that in one embodiment, the oxidation process produces an
outer region 36 of a firstcurrent electrode 44 that comprises germanium while theinner region 48 of the firstcurrent electrode 44 is substantially free of germanium. Although the diffusion of the germanium which occurs during the oxidation process may result in a small amount of germanium diffusing into theinner region 48,inner region 48 remains substantially free of germanium compared to theouter region 36. Note that in one embodiment, the oxidation process produces anouter region 36 of a secondcurrent electrode 46 that comprises germanium while theinner region 50 of the secondcurrent electrode 46 is substantially free of germanium. Although the diffusion of the germanium which occurs during the oxidation process may result in a small amount of germanium diffusing into theinner region 50,inner region 50 remains substantially free of germanium compared to theouter region 36. -
FIG. 14 is a top view of a portion of a wafer ofFIG. 9 during a stage in its manufacture in accordance with one embodiment. Note that the oxidation process has transformedregion 36 into silicon germanium, while theregions current electrode 44 comprises material 48 (e.g. silicon) and the portion of 36 (e.g. silicon germanium) surrounding 48. The secondcurrent electrode 46 comprises material 50 (e.g. silicon) and the portion of 36 (e.g. silicon germanium) surrounding 50. Note thatlayer 38 is a dielectric layer and 40 is a gate electrode. -
FIG. 15 is a cross-sectional view of a portion of a wafer ofFIG. 3 , 4, 5, or 6 during a stage in its manufacture in accordance with an alternate embodiment.FIG. 15 illustrates onefinished device 10, namely a MIGFET transistor, that may use the structure ofFIG. 8 . In the illustrated embodiment ofdevice 10, agate dielectric layer 38 is disposed overstack gate dielectric layer 38 may be deposited by PVD (physical vapor deposition), ALD (atomic layer deposition), or CVD (chemical vapor deposition). For PVD, ALD, and CVD, a variety of dielectrics may be deposited, such as, for example, metal oxides such as hafnium oxide, zirconium oxide, tantalum oxide, or any combination of any appropriate oxides, including oxides containing silicon and/or nitride. Alternately,dielectric layer 38 may be grown on only the sidewalls of 36 by using conventional gate oxidation processes. - Still referring to
FIG. 15 , the gate electrode may be deposited by CVD or PVD, and may include any appropriate gate materials, such as, for example, polysilicon, metal, metal silicide, or any combination of appropriate conductive materials. In one embodiment, the independentgate electrode portions gate electrode 40 may be formed by using a CMP (chemical mechanical polishing) process ongate electrode 40. Alternate embodiments may use any other desired and appropriate process to form the independentgate electrode portions gate electrode 40 overlyinglayer 20 is removed, resulting in two electrically independentgate electrode portion FIG. 8 toFIG. 15 may be performed using any known and appropriate techniques. - In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.
- Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
- Additional Text in the Specification to Support the Claims:
- 1. A method for forming a non-planar semiconductor device, comprising:
- forming a fin of the non-planar semiconductor device, wherein the fin comprises silicon;
- providing a source of germanium to the fin;
- oxidizing the fin to form a channel region comprising silicon germanium in the fin; and
- completing formation of the non-planar semiconductor device.
- 2. A method as in statement 1, wherein said step of providing the source of germanium to the fin comprises:
- implanting the fin with germanium.
- 3. A method as in statement 2, wherein said step of implanting the fin with germanium comprises:
- using a germanium atom dose in the range of 5×10e13 to 5×10e16.
- 4. A method as in statement 2, wherein said step of implanting the fin with germanium comprises:
- using an ion implant energy in the range of 1 keV to 120 keV.
- 5. A method as in statement 1, wherein said step of providing the source of germanium to the fin comprises:
- forming a silicon germanium layer on the sidewalls of the fin.
- 6. A method as in statement 5, wherein said step of forming a silicon germanium layer on the sidewalls of the fin comprises:
- selective deposition of silicon germanium.
- 7. A method as in statement 5, wherein said step of forming a silicon germanium layer on the sidewalls of the fin comprises:
- non-selective deposition of silicon germanium.
- 8. A method as in statement 1, further comprising:
- after said step of forming the fin and before said step of providing the source of germanium, forming a silicon nitride layer overlying the fin.
- 9. A method as in statement 1, further comprising:
- after said step of oxidizing the fin, etching at least a portion of silicon dioxide formed during the oxidation step.
- 10. A method as in statement 1, wherein the channel region comprises all of the fin.
- 11. A method as in statement 1, wherein the non-planar semiconductor device comprises a FINFET.
- 12. A method as in statement 1, wherein the non-planar semiconductor device comprises a MIGFET.
- 13. A method as in statement 1, wherein the non-planar semiconductor device comprises a Tri-gate transistor.
- 14. A method for forming a non-planar semiconductor device, comprising:
- forming a fin, a first current electrode, and a second current electrode of the non-planar semiconductor device, wherein the fin, the first current electrode, and the second current electrode each comprises silicon;
- providing a source of germanium to the fin, to the first current electrode, and to the second current electrode;
- oxidizing to distribute the germanium throughout the fin, to form an inner region and an outer region of the first current electrode, and to form an inner region and an outer region of the second current electrode, wherein the outer region of the first current electrode comprises germanium but the inner region of the first current electrode is substantially free of germanium, and wherein the outer region of the second current electrode comprises germanium but the inner region of the second current electrode is substantially free of germanium; and
- completing formation of the non-planar semiconductor device.
- 15. A method as in
statement 14, further comprising:- removing at least a portion of an oxide formed during said step of oxidizing.
- 16. A method as in
statement 14, wherein the non-planar semiconductor device comprises a FINFET. - 17. A method as in
statement 14, wherein the non-planar semiconductor device comprises a MIGFET. - 18. A non-planar semiconductor device, comprising:
- a fin in which a channel region is formed, said fin comprising silicon germanium;
- a first current electrode, coupled to said fin, said first current electrode comprising a first region and a second region, wherein the first region comprises silicon germanium and the second region comprises silicon and not germanium; and
- a second current electrode, coupled to said fin, said second current electrode comprising a first region and a second region, wherein the first region comprises silicon germanium and the second region comprises silicon and not germanium.
- 19. A non-planar semiconductor device as in
statement 18, wherein the fin, the first region of the first current electrode, and the first region of the second current electrode are contiguous. - 20. A non-planar semiconductor device as in
statement 18, wherein the first region of the first current electrode is formed on the outside walls of the second region of the first current electrode, and wherein the first region of the second current electrode is formed on the outside walls of the second region of the second current electrode.
Claims (19)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/605,556 US20100044762A1 (en) | 2006-06-30 | 2009-10-26 | Method for forming a semiconductor device and structure thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/428,038 US7629220B2 (en) | 2006-06-30 | 2006-06-30 | Method for forming a semiconductor device and structure thereof |
US12/605,556 US20100044762A1 (en) | 2006-06-30 | 2009-10-26 | Method for forming a semiconductor device and structure thereof |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/428,038 Division US7629220B2 (en) | 2006-06-30 | 2006-06-30 | Method for forming a semiconductor device and structure thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
US20100044762A1 true US20100044762A1 (en) | 2010-02-25 |
Family
ID=38877184
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/428,038 Expired - Fee Related US7629220B2 (en) | 2006-06-30 | 2006-06-30 | Method for forming a semiconductor device and structure thereof |
US12/605,556 Abandoned US20100044762A1 (en) | 2006-06-30 | 2009-10-26 | Method for forming a semiconductor device and structure thereof |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/428,038 Expired - Fee Related US7629220B2 (en) | 2006-06-30 | 2006-06-30 | Method for forming a semiconductor device and structure thereof |
Country Status (5)
Country | Link |
---|---|
US (2) | US7629220B2 (en) |
KR (1) | KR101310434B1 (en) |
CN (1) | CN101490857B (en) |
TW (1) | TW200802616A (en) |
WO (1) | WO2008005612A1 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110129978A1 (en) * | 2009-12-01 | 2011-06-02 | Kangguo Cheng | Method and structure for forming finfets with multiple doping regions on a same chip |
US20130075621A1 (en) * | 2011-09-22 | 2013-03-28 | Canon Kabushiki Kaisha | Radiation detection apparatus and detection system including same |
US8957476B2 (en) * | 2012-12-20 | 2015-02-17 | Intel Corporation | Conversion of thin transistor elements from silicon to silicon germanium |
US9018054B2 (en) | 2013-03-15 | 2015-04-28 | Applied Materials, Inc. | Metal gate structures for field effect transistors and method of fabrication |
US9390925B1 (en) * | 2014-12-17 | 2016-07-12 | GlobalFoundries, Inc. | Silicon—germanium (SiGe) fin formation |
US20160225881A1 (en) * | 2013-11-22 | 2016-08-04 | Qualcomm Incorporated | Silicon germanium finfet formation |
US9536900B2 (en) | 2014-05-22 | 2017-01-03 | Globalfoundries Inc. | Forming fins of different semiconductor materials on the same substrate |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2500766A1 (en) | 2005-03-14 | 2006-09-14 | National Research Council Of Canada | Method and apparatus for the continuous production and functionalization of single-walled carbon nanotubes using a high frequency induction plasma torch |
KR100868100B1 (en) * | 2007-03-05 | 2008-11-11 | 삼성전자주식회사 | Method for fabricating semiconductor device and semiconductor device fabricated thereby |
US9245805B2 (en) * | 2009-09-24 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium FinFETs with metal gates and stressors |
US7993999B2 (en) | 2009-11-09 | 2011-08-09 | International Business Machines Corporation | High-K/metal gate CMOS finFET with improved pFET threshold voltage |
KR101119136B1 (en) * | 2010-01-07 | 2012-03-20 | 주식회사 하이닉스반도체 | Semiconductor device and method for fabricating the same |
CN102446747A (en) * | 2010-10-14 | 2012-05-09 | 中芯国际集成电路制造(上海)有限公司 | Method for forming side wall and p-channel metal oxide semiconductor (PMOS) transistor |
CN103165455B (en) * | 2011-12-13 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Make the method for fin-shaped field effect transistor |
US9607987B2 (en) * | 2011-12-21 | 2017-03-28 | Intel Corporation | Methods for forming fins for metal oxide semiconductor device structures |
US8865560B2 (en) | 2012-03-02 | 2014-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET design with LDD extensions |
CN103730367B (en) * | 2012-10-16 | 2017-05-03 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
CN103117227B (en) | 2013-02-05 | 2015-11-25 | 华为技术有限公司 | The preparation method of multiple-grid fin field effect pipe |
US9299840B2 (en) | 2013-03-08 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs and methods for forming the same |
US9142650B2 (en) * | 2013-09-18 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company Limited | Tilt implantation for forming FinFETs |
US20150097217A1 (en) * | 2013-10-03 | 2015-04-09 | International Business Machines Corporation | Semiconductor attenuated fins |
CN104681445B (en) * | 2013-11-27 | 2017-11-10 | 中芯国际集成电路制造(上海)有限公司 | The method for making FinFET |
US9257556B2 (en) * | 2014-01-03 | 2016-02-09 | Qualcomm Incorporated | Silicon germanium FinFET formation by Ge condensation |
US9553174B2 (en) | 2014-03-28 | 2017-01-24 | Applied Materials, Inc. | Conversion process utilized for manufacturing advanced 3D features for semiconductor device applications |
CN105097513B (en) * | 2014-04-24 | 2019-09-03 | 中芯国际集成电路制造(北京)有限公司 | A kind of manufacturing method of semiconductor devices, semiconductor devices and electronic device |
US9472573B2 (en) | 2014-12-30 | 2016-10-18 | International Business Machines Corporation | Silicon-germanium fin formation |
US9859423B2 (en) * | 2014-12-31 | 2018-01-02 | Stmicroelectronics, Inc. | Hetero-channel FinFET |
US9954107B2 (en) | 2015-05-05 | 2018-04-24 | International Business Machines Corporation | Strained FinFET source drain isolation |
US9583572B2 (en) | 2015-06-25 | 2017-02-28 | International Business Machines Corporation | FinFET devices having silicon germanium channel fin structures with uniform thickness |
KR102434914B1 (en) | 2016-01-15 | 2022-08-23 | 삼성전자주식회사 | Method for forming patterns of semiconductor device and method for fabricating semiconductor device using the same |
CN107437544A (en) * | 2016-05-27 | 2017-12-05 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device, semiconductor devices and electronic installation |
US9773875B1 (en) * | 2016-07-20 | 2017-09-26 | International Business Machines Corporation | Fabrication of silicon-germanium fin structure having silicon-rich outer surface |
US10141189B2 (en) * | 2016-12-29 | 2018-11-27 | Asm Ip Holding B.V. | Methods for forming semiconductors by diffusion |
US10361130B2 (en) * | 2017-04-26 | 2019-07-23 | International Business Machines Corporation | Dual channel silicon/silicon germanium complementary metal oxide semiconductor performance with interface engineering |
KR102099896B1 (en) * | 2018-03-30 | 2020-04-13 | 아주대학교산학협력단 | Tunneling field-effect transistor and method for manufacturing thereof |
US10505019B1 (en) * | 2018-05-15 | 2019-12-10 | International Business Machines Corporation | Vertical field effect transistors with self aligned source/drain junctions |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6326667B1 (en) * | 1999-09-09 | 2001-12-04 | Kabushiki Kaisha Toshiba | Semiconductor devices and methods for producing semiconductor devices |
US6369438B1 (en) * | 1998-12-24 | 2002-04-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
US6458662B1 (en) * | 2001-04-04 | 2002-10-01 | Advanced Micro Devices, Inc. | Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed |
US20040140479A1 (en) * | 2003-01-10 | 2004-07-22 | Takeshi Akatsu | Compliant substrate for a heteroepitaxial structure and method for making same |
US6774391B1 (en) * | 1999-10-25 | 2004-08-10 | Cambridge University Technical Svcs. | Magnetic logic element |
US6774390B2 (en) * | 2002-02-22 | 2004-08-10 | Kabushiki Kaisha Toshiba | Semiconductor device |
US20050093154A1 (en) * | 2003-07-25 | 2005-05-05 | Interuniversitair Microelektronica Centrum (Imec Vzw) | Multiple gate semiconductor device and method for forming same |
US6936516B1 (en) * | 2004-01-12 | 2005-08-30 | Advanced Micro Devices, Inc. | Replacement gate strained silicon finFET process |
US20050245092A1 (en) * | 2004-04-30 | 2005-11-03 | Orlowski Marius K | Method for making a semiconductor structure using silicon germanium |
US20050272186A1 (en) * | 2004-06-08 | 2005-12-08 | Te-Ming Chu | Method for forming a lightly doped drain in a thin film transistor |
US20050272188A1 (en) * | 2003-03-07 | 2005-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement |
US20060042542A1 (en) * | 2004-09-02 | 2006-03-02 | International Business Machines Corporation | Method of producing silicon-germanium-on-insulator material using unstrained Ge-containing source layers |
US7029980B2 (en) * | 2003-09-25 | 2006-04-18 | Freescale Semiconductor Inc. | Method of manufacturing SOI template layer |
US7056773B2 (en) * | 2004-04-28 | 2006-06-06 | International Business Machines Corporation | Backgated FinFET having different oxide thicknesses |
US20060242542A1 (en) * | 2001-12-28 | 2006-10-26 | English Robert M | Correcting multiple block data loss in a storage array using a combination of a single diagonal parity group and multiple row parity groups |
US7217603B2 (en) * | 2002-06-25 | 2007-05-15 | Amberwave Systems Corporation | Methods of forming reacted conductive gate electrodes |
US7265004B2 (en) * | 2005-11-14 | 2007-09-04 | Freescale Semiconductor, Inc. | Electronic devices including a semiconductor layer and a process for forming the same |
-
2006
- 2006-06-30 US US11/428,038 patent/US7629220B2/en not_active Expired - Fee Related
-
2007
- 2007-04-24 CN CN2007800247074A patent/CN101490857B/en not_active Expired - Fee Related
- 2007-04-24 KR KR1020087031752A patent/KR101310434B1/en active IP Right Grant
- 2007-04-24 WO PCT/US2007/067291 patent/WO2008005612A1/en active Application Filing
- 2007-04-30 TW TW096115322A patent/TW200802616A/en unknown
-
2009
- 2009-10-26 US US12/605,556 patent/US20100044762A1/en not_active Abandoned
Patent Citations (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6369438B1 (en) * | 1998-12-24 | 2002-04-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
US6326667B1 (en) * | 1999-09-09 | 2001-12-04 | Kabushiki Kaisha Toshiba | Semiconductor devices and methods for producing semiconductor devices |
US6774391B1 (en) * | 1999-10-25 | 2004-08-10 | Cambridge University Technical Svcs. | Magnetic logic element |
US6458662B1 (en) * | 2001-04-04 | 2002-10-01 | Advanced Micro Devices, Inc. | Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed |
US20060242542A1 (en) * | 2001-12-28 | 2006-10-26 | English Robert M | Correcting multiple block data loss in a storage array using a combination of a single diagonal parity group and multiple row parity groups |
US6774390B2 (en) * | 2002-02-22 | 2004-08-10 | Kabushiki Kaisha Toshiba | Semiconductor device |
US7217603B2 (en) * | 2002-06-25 | 2007-05-15 | Amberwave Systems Corporation | Methods of forming reacted conductive gate electrodes |
US20040140479A1 (en) * | 2003-01-10 | 2004-07-22 | Takeshi Akatsu | Compliant substrate for a heteroepitaxial structure and method for making same |
US20050272188A1 (en) * | 2003-03-07 | 2005-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement |
US20050093154A1 (en) * | 2003-07-25 | 2005-05-05 | Interuniversitair Microelektronica Centrum (Imec Vzw) | Multiple gate semiconductor device and method for forming same |
US7029980B2 (en) * | 2003-09-25 | 2006-04-18 | Freescale Semiconductor Inc. | Method of manufacturing SOI template layer |
US7056778B2 (en) * | 2003-09-25 | 2006-06-06 | Freescale Semiconductor, Inc. | Semiconductor layer formation |
US7208357B2 (en) * | 2003-09-25 | 2007-04-24 | Freescale Semiconductor, Inc. | Template layer formation |
US6936516B1 (en) * | 2004-01-12 | 2005-08-30 | Advanced Micro Devices, Inc. | Replacement gate strained silicon finFET process |
US7056773B2 (en) * | 2004-04-28 | 2006-06-06 | International Business Machines Corporation | Backgated FinFET having different oxide thicknesses |
US20050245092A1 (en) * | 2004-04-30 | 2005-11-03 | Orlowski Marius K | Method for making a semiconductor structure using silicon germanium |
US20050272186A1 (en) * | 2004-06-08 | 2005-12-08 | Te-Ming Chu | Method for forming a lightly doped drain in a thin film transistor |
US20060042542A1 (en) * | 2004-09-02 | 2006-03-02 | International Business Machines Corporation | Method of producing silicon-germanium-on-insulator material using unstrained Ge-containing source layers |
US7265004B2 (en) * | 2005-11-14 | 2007-09-04 | Freescale Semiconductor, Inc. | Electronic devices including a semiconductor layer and a process for forming the same |
US20070272952A1 (en) * | 2005-11-14 | 2007-11-29 | Freescale Semiconductor, Inc. | Electronic devices including a semiconductor layer |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110129978A1 (en) * | 2009-12-01 | 2011-06-02 | Kangguo Cheng | Method and structure for forming finfets with multiple doping regions on a same chip |
US8021949B2 (en) * | 2009-12-01 | 2011-09-20 | International Business Machines Corporation | Method and structure for forming finFETs with multiple doping regions on a same chip |
US20130075621A1 (en) * | 2011-09-22 | 2013-03-28 | Canon Kabushiki Kaisha | Radiation detection apparatus and detection system including same |
US8957476B2 (en) * | 2012-12-20 | 2015-02-17 | Intel Corporation | Conversion of thin transistor elements from silicon to silicon germanium |
US9018054B2 (en) | 2013-03-15 | 2015-04-28 | Applied Materials, Inc. | Metal gate structures for field effect transistors and method of fabrication |
US20160225881A1 (en) * | 2013-11-22 | 2016-08-04 | Qualcomm Incorporated | Silicon germanium finfet formation |
US9536900B2 (en) | 2014-05-22 | 2017-01-03 | Globalfoundries Inc. | Forming fins of different semiconductor materials on the same substrate |
US9390925B1 (en) * | 2014-12-17 | 2016-07-12 | GlobalFoundries, Inc. | Silicon—germanium (SiGe) fin formation |
Also Published As
Publication number | Publication date |
---|---|
KR20090031525A (en) | 2009-03-26 |
WO2008005612A1 (en) | 2008-01-10 |
CN101490857B (en) | 2010-12-01 |
US20080003725A1 (en) | 2008-01-03 |
CN101490857A (en) | 2009-07-22 |
KR101310434B1 (en) | 2013-09-24 |
US7629220B2 (en) | 2009-12-08 |
TW200802616A (en) | 2008-01-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7629220B2 (en) | Method for forming a semiconductor device and structure thereof | |
US9853124B2 (en) | Method for fabricating a nanowire semiconductor transistor having an auto-aligned gate and spacers | |
US10032915B2 (en) | Non-planar transistors and methods of fabrication thereof | |
US9741716B1 (en) | Forming vertical and horizontal field effect transistors on the same substrate | |
US7476578B1 (en) | Process for finFET spacer formation | |
US10170609B2 (en) | Internal spacer formation from selective oxidation for Fin-first wire-last replacement gate-all-around nanowire FET | |
KR101802715B1 (en) | Semiconductor device and manufacturing method thereof | |
CN103325831B (en) | For the source/drain profile of FinFET | |
US7154118B2 (en) | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication | |
US8159018B2 (en) | Non-volatile memory device | |
US20160308014A1 (en) | Fabrication of channel wraparound gate structure for field-effect transistor | |
US20070029586A1 (en) | Multi-channel transistor structure and method of making thereof | |
US10037916B2 (en) | Semiconductor fins for finFET devices and sidewall image transfer (SIT) processes for manufacturing the same | |
US8742508B2 (en) | Three dimensional FET devices having different device widths | |
US20140231913A1 (en) | Trilayer SIT Process with Transfer Layer for FINFET Patterning | |
US9666679B2 (en) | Transistor with a low-k sidewall spacer and method of making same | |
CN112530942A (en) | Semiconductor device and method of forming the same | |
CN108074974B (en) | Method for forming semiconductor device | |
US20100151649A1 (en) | Method of forming a minute pattern and method of manufacturing a transistor using the same | |
KR100989738B1 (en) | Flash Memory of having Spiral Channel and Method of Manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: CITIBANK, N.A.,NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024079/0082 Effective date: 20100212 Owner name: CITIBANK, N.A., NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024079/0082 Effective date: 20100212 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037355/0723 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:038017/0058 Effective date: 20160218 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:039361/0212 Effective date: 20160218 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:042762/0145 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:042985/0001 Effective date: 20160218 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:050745/0001 Effective date: 20190903 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0001 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051145/0184 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0387 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051030/0001 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0387 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051029/0001 Effective date: 20160218 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:051145/0184 Effective date: 20160218 |