US20090261429A1 - Transistor and method for manufacturing thereof - Google Patents
Transistor and method for manufacturing thereof Download PDFInfo
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- US20090261429A1 US20090261429A1 US12/491,590 US49159009A US2009261429A1 US 20090261429 A1 US20090261429 A1 US 20090261429A1 US 49159009 A US49159009 A US 49159009A US 2009261429 A1 US2009261429 A1 US 2009261429A1
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- insulating layer
- spacers
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- conductive plug
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- 238000000034 method Methods 0.000 title abstract description 31
- 238000004519 manufacturing process Methods 0.000 title abstract description 14
- 125000006850 spacer group Chemical group 0.000 claims abstract description 47
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 7
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 125000001475 halogen functional group Chemical group 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000000151 deposition Methods 0.000 abstract description 14
- 238000005530 etching Methods 0.000 abstract description 12
- 239000012535 impurity Substances 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000007943 implant Substances 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Definitions
- the present invention relates to a transistor, and more particularly, to a transistor capable of improving short channel effect, and a method for manufacturing thereof.
- the size of the semiconductor devices needs to be reduced.
- a linewidth of a gate electrode in a metal oxide semiconductor field effect transistor (MOSFET) needs to be reduced, which also reduces the width of the channel of the MOSFET due to lateral diffusion of source/drain regions.
- MOSFET metal oxide semiconductor field effect transistor
- FIG. 1 is a cross-sectional view illustrating a related art method for manufacturing a transistor.
- a layer of gate insulating material, a polysilicon layer, and a hard mask layer 40 are sequentially formed on a semiconductor substrate 10 in which a field oxide layer (not shown) with a predetermined height is formed in advance.
- the polysilicon layer and the layer of gate insulating material are patterned into the shape of hard mask layer 40 by an etch process, to thereby form a gate 50 including gate dielectric 20 and gate electrode 30 .
- hard mask 40 may be removed and gate spacers 60 are formed on sidewalls of gate 50 by a conventional method. Then, impurities are implanted into the semiconductor substrate 10 using gate 50 and gate spacers 60 as a mask to form source/drain regions 70 .
- the present invention is directed to a transistor and a method for manufacturing thereof that substantially obviates one or more problems due to limitations and disadvantages of the related art.
- An object of the present invention is to provide a transistor capable of improving short channel effect, and a method for manufacturing thereof.
- Another object of the present invention is to provide a transistor capable of reducing a gate resistance with respect to a gate area on which a silicide is formed using a damascene process, and a method for manufacturing thereof.
- a transistor including a gate insulating layer over a semiconductor substrate; a first insulating layer over the semiconductor substrate on both sides of the gate insulating layer; first spacers over the first insulating layer, the first spacers being spaced apart from each other by a predetermined distance; and a gate conductive plug between the first spacers, wherein the first spacers are formed before the gate insulating layer is deposited.
- a method for manufacturing a transistor that includes sequentially depositing a first insulating layer and a second insulating layer over a semiconductor substrate; etching a predetermined portion of the second insulating layer; implanting impurity ions; depositing a layer of spacer material, and forming first spacers by etching the layer of spacer material; removing a first portion of the first insulating layer exposed between the first spacers by wet etching process; depositing a gate insulating layer in a region where the first portion of the first insulating layer is removed; forming a gate conductive plug on the gate insulating layer; forming second spacers on sidewalls of the gate conductive plug; and forming a silicide on an upper surface of the gate conductive plug.
- a method for manufacturing a transistor that includes depositing a first insulating layer and a second insulating layer on a semiconductor substrate in sequence, and forming a photoresist pattern on the second insulating layer; etching the second insulating layer by dry etching process using the photoresist pattern as a mask; removing the photoresist pattern after etching the second insulating layer; implanting first impurity ions; forming first spacers by depositing and etching a first layer of spacer material; removing a portion of the first insulating layer using wet etching process; depositing a gate insulating layer on a region where the portion of the first insulating layer is removed; forming a gate conductive plug on the gate insulating layer; removing the second insulating layer using wet etching process; implanting second impurity ions after removing the second insulating layer; forming second spacers by depositing and etching
- FIG. 1 is a cross-sectional view illustrating a conventional method for manufacturing a transistor
- FIGS. 2 to 11 are cross-sectional views illustrating a method for manufacturing a transistor consistent with embodiments of the present invention.
- FIG. 12 is an enlarged view of the transistor consistent with embodiments of the present invention.
- FIGS. 2 to 11 are cross-sectional views illustrating a method for manufacturing a transistor according to embodiments of the present invention.
- a photoresist pattern 120 is formed on the resultant structure.
- First insulating layer 110 acts as an etch stop layer for preventing a surface of semiconductor substrate 100 from being damaged during a subsequent etching process.
- First insulating layer 110 may be formed using a deposition method such as a chemical vapor deposition (CVD), a low pressure CVD (LPCVD), a plasma enhanced CVD (PECVD), a semi-atmospheric CVD (SACVD), a sputtering, an atomic layer deposition (ALD), or the like.
- First insulating layer 110 may have a thickness of 20 ⁇ 5 ⁇ so that first insulating layer 110 may act as an effective etch stop layer in later formation of a gate insulating layer and a silicide.
- Second insulating layer 115 may be formed of a material which has a different etching rate from that of first insulating layer 110 under the same etchant.
- second insulating layer 115 may be formed of tetra ethyl ortho silicate (TEOS), medium temperature deposition of oxide (MTO), undoped silicate glass (USG), or silane (SiH 4 )-rich oxide.
- TEOS tetra ethyl ortho silicate
- MTO medium temperature deposition of oxide
- USG undoped silicate glass
- SiH 4 silane
- second insulating layer 115 may be formed using a CVD method, a sputtering method, and so forth.
- second insulating layer 115 is etched using photoresist pattern 120 as a mask layer. Particularly, portions of second insulating layer 115 not masked by photoresist pattern 120 are removed to expose the underlying first insulating layer 110 .
- Second insulating layer 115 may be etched using a conventional dry etching process. After the etch of second insulating layer 115 , photoresist pattern 120 may be removed through an ashing or a strip process.
- a first ion implantation process is performed to implant impurity 130 into semiconductor substrate 100 , which will contribute to form halo/pocket implants (not shown in FIG. 3 ) together with subsequent ion implantations.
- First insulating layer 110 serves as a buffer for preventing the lattice of semiconductor substrate 100 from being damaged during the formation of the halo/pocket implants.
- first spacers 140 serve to reduce a width of the gate and thereby reduce a resistance of the gate.
- first insulating layer 110 between first spacers 140 is removed using wet etching process.
- a predetermined portion of first insulating layer 110 under first spacers 140 is also etched so that a gate insulating layer to be formed later may be formed partially under first spacers 140 .
- a gate insulating layer 150 is deposited in the region of the portion of first insulating layers 110 previously removed. As noted above, because a predetermined portion of first insulating layer 110 under first spacers 140 is also removed, gate insulating layer 150 also extends under first spacers 140 . Subsequently, gate insulating layer 150 is planarized using CMP process. Gate insulating layer 150 may have the same thickness as first insulating layer 110 .
- gate conductive plug 160 is formed on gate insulating layer 110 and an upper surface of gate conductive plug 160 may be planarized by performing CMP process.
- Gate insulating layer 150 may be formed using CVD, physical vapor deposition (PVD), or ALD method.
- Gate conductive plug 160 may be formed of polysilicon.
- second insulating layer 115 is removed by wet etching process using a solution of dilute hydrofluoric acid (HF(49%):H 2 O) or buffered oxide etchant (BOE, NH 4 F:HF). Afterwards, a second ion implantation process for lightly doped drain/source (LDD) is performed using first spacers 140 and gate conductive plug 160 as a mask layer, to form shallow source/drain extension regions 171 .
- HF(49%):H 2 O dilute hydrofluoric acid
- BOE buffered oxide etchant
- second spacers 180 are formed on sidewalls of gate conductive plug 160 and first spacers 140 .
- Second spacers 180 may be formed by depositing a layer of nitride or oxide and etching the same.
- first insulating layer 110 portions of first insulating layer 110 exposed on both sides of second spacers 180 and gate conductive plug 160 are removed to expose an upper surface of semiconductor substrate 100 .
- a portion of first insulating layer 110 remains underneath first spacers 140 , second spacers 180 , and gate conductive plug 160 .
- the remaining portion of first insulating layer 110 is referred to as third insulating layer 110 a .
- the layer of nitride or oxide for forming spacers 180 and first insulating layer 110 may be etched using the same etchant. In other words, spacers 180 and third insulating layer 110 a may be formed through the same etching process.
- a third ion implantation process is performed second spacers 180 as a mask to form deep source/drain regions 172 . Therefore, there are formed source/drain regions 170 each with a shallow source/drain extension region 171 and a deep source/drain region 172 .
- a silicide 200 is formed on gate conductive plug 160 and on shallow source/drain extension region 171 .
- Silicide 200 may comprise Ti-silicide, Co-silicide, or Ni-silicide.
- a thickness of silicide 200 depends on the thickness of the gate insulating layer 150 or the third insulating layer 110 a . For example, when third insulating layer 110 a has a thickness of 20 ⁇ 5 ⁇ thick, silicide layer 200 may be 100 ⁇ 20 ⁇ thick.
- FIG. 11 also shows halo/pocket implants 220 formed as a result of the first, second, and third ion implantations.
- FIG. 12 is an enlarged view of the transistor according to embodiments of the present invention.
- gate insulating layer 150 and third insulating layer 110 a are formed on semiconductor substrate 100 .
- Silicide layer 200 is formed on both sides of second spacers 180 and third insulating layer 110 .
- a ratio between the thickness a of third insulating layer 110 a and the thickness b of silicide layer 200 is in a range of 1:4 to 1:6.
- silicide layer 200 is formed in coincidence with the fabrication of the transistor in virtue of a damascene process so that it is possible to fabricate the transistor using an existing device without employing additional device. Moreover, since the gate area can be reduced, the present invention is effective for decreasing the gate resistance.
Abstract
A transistor includes a gate insulating layer over a semiconductor substrate; a first insulating layer on both sides of the gate insulating layer; first spacers over the first insulating layer and being spaced apart from each other; and a gate conductive plug between the first spacers. A method for manufacturing a transistor includes sequentially depositing a first insulating layer and a second insulating layer over a semiconductor substrate; etching the second insulating layer; implanting impurity ions; depositing and etching a layer of spacer material to form first spacers; removing a first portion of the first insulating layer between the first spacers; depositing a gate insulating layer the place of the first portion of the first insulating layer; forming a gate conductive plug on the gate insulating layer; forming second spacers on sidewalls of the gate conductive plug; and forming a silicide on an upper surface of the gate conductive plug.
Description
- This application is based upon and claims the benefit of priority from the prior Korean Patent Application No. 10-2004-0106054, filed Dec. 15, 2004, the entire contents of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a transistor, and more particularly, to a transistor capable of improving short channel effect, and a method for manufacturing thereof.
- 2. Description of the Related Art
- To achieve a higher integration of a semiconductor devices, the size of the semiconductor devices needs to be reduced. For example, a linewidth of a gate electrode in a metal oxide semiconductor field effect transistor (MOSFET) needs to be reduced, which also reduces the width of the channel of the MOSFET due to lateral diffusion of source/drain regions. However, as a result of reduced channel length, short channel effects increase.
-
FIG. 1 is a cross-sectional view illustrating a related art method for manufacturing a transistor. - Referring to
FIG. 1 , a layer of gate insulating material, a polysilicon layer, and ahard mask layer 40 are sequentially formed on asemiconductor substrate 10 in which a field oxide layer (not shown) with a predetermined height is formed in advance. - After
hard mask 40 is patterned into a shape of a gate electrode, the polysilicon layer and the layer of gate insulating material are patterned into the shape ofhard mask layer 40 by an etch process, to thereby form agate 50 including gate dielectric 20 andgate electrode 30. - Thereafter,
hard mask 40 may be removed andgate spacers 60 are formed on sidewalls ofgate 50 by a conventional method. Then, impurities are implanted into thesemiconductor substrate 10 usinggate 50 andgate spacers 60 as a mask to form source/drain regions 70. - However, according to the related art method for manufacturing the transistor, there is a problem that an additional purchase of a device should be needed in order to fabricate the transistor.
- In addition, as the gate length is reduced, a narrow line effect gives rise to problems such as formation of silicide contacts being difficult and gate resistance being higher.
- Accordingly, the present invention is directed to a transistor and a method for manufacturing thereof that substantially obviates one or more problems due to limitations and disadvantages of the related art.
- An object of the present invention is to provide a transistor capable of improving short channel effect, and a method for manufacturing thereof.
- Another object of the present invention is to provide a transistor capable of reducing a gate resistance with respect to a gate area on which a silicide is formed using a damascene process, and a method for manufacturing thereof.
- Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
- Consistent with embodiments of the present invention, there is provided a transistor including a gate insulating layer over a semiconductor substrate; a first insulating layer over the semiconductor substrate on both sides of the gate insulating layer; first spacers over the first insulating layer, the first spacers being spaced apart from each other by a predetermined distance; and a gate conductive plug between the first spacers, wherein the first spacers are formed before the gate insulating layer is deposited.
- Consistent with embodiments of the present invention, there is also provided a method for manufacturing a transistor that includes sequentially depositing a first insulating layer and a second insulating layer over a semiconductor substrate; etching a predetermined portion of the second insulating layer; implanting impurity ions; depositing a layer of spacer material, and forming first spacers by etching the layer of spacer material; removing a first portion of the first insulating layer exposed between the first spacers by wet etching process; depositing a gate insulating layer in a region where the first portion of the first insulating layer is removed; forming a gate conductive plug on the gate insulating layer; forming second spacers on sidewalls of the gate conductive plug; and forming a silicide on an upper surface of the gate conductive plug.
- Consistent with embodiments of the present invention, there is further provided a method for manufacturing a transistor that includes depositing a first insulating layer and a second insulating layer on a semiconductor substrate in sequence, and forming a photoresist pattern on the second insulating layer; etching the second insulating layer by dry etching process using the photoresist pattern as a mask; removing the photoresist pattern after etching the second insulating layer; implanting first impurity ions; forming first spacers by depositing and etching a first layer of spacer material; removing a portion of the first insulating layer using wet etching process; depositing a gate insulating layer on a region where the portion of the first insulating layer is removed; forming a gate conductive plug on the gate insulating layer; removing the second insulating layer using wet etching process; implanting second impurity ions after removing the second insulating layer; forming second spacers by depositing and etching a second layer of spacer material; implanting third impurity ions; and forming a silicide on an upper surface of the gate conductive plug.
- It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle of the invention. In the drawings:
-
FIG. 1 is a cross-sectional view illustrating a conventional method for manufacturing a transistor; -
FIGS. 2 to 11 are cross-sectional views illustrating a method for manufacturing a transistor consistent with embodiments of the present invention; and -
FIG. 12 is an enlarged view of the transistor consistent with embodiments of the present invention. - Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments described herein. Other embodiments through modifications and variations which may be apparent to those skilled in the art also fall within the scope of the present invention.
- In the drawings, the thickness of layers and regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements. It is also to be understood that when one layer is said to be “on” another layer or substrate, the one layer can be directly on the other layer or substrate, or intervening layers may also be present.
-
FIGS. 2 to 11 are cross-sectional views illustrating a method for manufacturing a transistor according to embodiments of the present invention. - Referring to
FIG. 2 , after depositing a firstinsulating layer 110 and a secondinsulating layer 115 on asemiconductor substrate 100 in sequence, aphotoresist pattern 120 is formed on the resultant structure. - First
insulating layer 110 acts as an etch stop layer for preventing a surface ofsemiconductor substrate 100 from being damaged during a subsequent etching process. Firstinsulating layer 110 may be formed using a deposition method such as a chemical vapor deposition (CVD), a low pressure CVD (LPCVD), a plasma enhanced CVD (PECVD), a semi-atmospheric CVD (SACVD), a sputtering, an atomic layer deposition (ALD), or the like. Firstinsulating layer 110 may have a thickness of 20±5 Å so that firstinsulating layer 110 may act as an effective etch stop layer in later formation of a gate insulating layer and a silicide. - Second
insulating layer 115 may be formed of a material which has a different etching rate from that of firstinsulating layer 110 under the same etchant. For instance, secondinsulating layer 115 may be formed of tetra ethyl ortho silicate (TEOS), medium temperature deposition of oxide (MTO), undoped silicate glass (USG), or silane (SiH4)-rich oxide. Furthermore, secondinsulating layer 115 may be formed using a CVD method, a sputtering method, and so forth. - Referring to
FIG. 3 , secondinsulating layer 115 is etched usingphotoresist pattern 120 as a mask layer. Particularly, portions of secondinsulating layer 115 not masked byphotoresist pattern 120 are removed to expose the underlying firstinsulating layer 110. -
Second insulating layer 115 may be etched using a conventional dry etching process. After the etch of secondinsulating layer 115,photoresist pattern 120 may be removed through an ashing or a strip process. - After
photoresist pattern 120 is removed, a first ion implantation process is performed to implantimpurity 130 intosemiconductor substrate 100, which will contribute to form halo/pocket implants (not shown inFIG. 3 ) together with subsequent ion implantations. - First insulating
layer 110 serves as a buffer for preventing the lattice ofsemiconductor substrate 100 from being damaged during the formation of the halo/pocket implants. - Referring to
FIG. 4 , a nitride layer (not shown) is deposited on first and secondinsulating layers first spacers 140 on sidewalls of secondinsulating layer 115. Because a gate will be formed in the opening in secondinsulating layer 115,first spacers 140 serve to reduce a width of the gate and thereby reduce a resistance of the gate. - Referring to
FIG. 5 , the portion of firstinsulating layer 110 betweenfirst spacers 140 is removed using wet etching process. A predetermined portion offirst insulating layer 110 underfirst spacers 140 is also etched so that a gate insulating layer to be formed later may be formed partially underfirst spacers 140. - Referring to
FIG. 6 , agate insulating layer 150 is deposited in the region of the portion of firstinsulating layers 110 previously removed. As noted above, because a predetermined portion of firstinsulating layer 110 underfirst spacers 140 is also removed,gate insulating layer 150 also extends underfirst spacers 140. Subsequently,gate insulating layer 150 is planarized using CMP process.Gate insulating layer 150 may have the same thickness as firstinsulating layer 110. - Thereafter, a gate
conductive plug 160 is formed ongate insulating layer 110 and an upper surface of gateconductive plug 160 may be planarized by performing CMP process.Gate insulating layer 150 may be formed using CVD, physical vapor deposition (PVD), or ALD method. Gateconductive plug 160 may be formed of polysilicon. - Referring to
FIG. 7 , second insulatinglayer 115 is removed by wet etching process using a solution of dilute hydrofluoric acid (HF(49%):H2O) or buffered oxide etchant (BOE, NH4F:HF). Afterwards, a second ion implantation process for lightly doped drain/source (LDD) is performed usingfirst spacers 140 and gateconductive plug 160 as a mask layer, to form shallow source/drain extension regions 171. - Referring to
FIG. 8 , after forming shallow source/drain extension regions 171,second spacers 180 are formed on sidewalls of gateconductive plug 160 andfirst spacers 140.Second spacers 180 may be formed by depositing a layer of nitride or oxide and etching the same. - Referring to
FIG. 9 , portions of first insulatinglayer 110 exposed on both sides ofsecond spacers 180 and gateconductive plug 160 are removed to expose an upper surface ofsemiconductor substrate 100. As a result, a portion of first insulatinglayer 110 remains underneathfirst spacers 140,second spacers 180, and gateconductive plug 160. The remaining portion of first insulatinglayer 110 is referred to as third insulatinglayer 110 a. The layer of nitride or oxide for formingspacers 180 and first insulatinglayer 110 may be etched using the same etchant. In other words,spacers 180 and thirdinsulating layer 110 a may be formed through the same etching process. - Referring to
FIG. 10 , a third ion implantation process is performedsecond spacers 180 as a mask to form deep source/drain regions 172. Therefore, there are formed source/drain regions 170 each with a shallow source/drain extension region 171 and a deep source/drain region 172. - Referring to
FIG. 11 , asilicide 200 is formed on gateconductive plug 160 and on shallow source/drain extension region 171.Silicide 200 may comprise Ti-silicide, Co-silicide, or Ni-silicide. A thickness ofsilicide 200 depends on the thickness of thegate insulating layer 150 or the third insulatinglayer 110 a. For example, when third insulatinglayer 110 a has a thickness of 20±5 Å thick,silicide layer 200 may be 100±20 Å thick.FIG. 11 also shows halo/pocket implants 220 formed as a result of the first, second, and third ion implantations. -
FIG. 12 is an enlarged view of the transistor according to embodiments of the present invention. Referring toFIG. 12 ,gate insulating layer 150 and thirdinsulating layer 110 a are formed onsemiconductor substrate 100.Silicide layer 200 is formed on both sides ofsecond spacers 180 and thirdinsulating layer 110. In one aspect, a ratio between the thickness a of thirdinsulating layer 110 a and the thickness b ofsilicide layer 200 is in a range of 1:4 to 1:6. - Consistent with embodiments of the present invention,
silicide layer 200 is formed in coincidence with the fabrication of the transistor in virtue of a damascene process so that it is possible to fabricate the transistor using an existing device without employing additional device. Moreover, since the gate area can be reduced, the present invention is effective for decreasing the gate resistance. - It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Claims (13)
1. A transistor comprising:
a gate insulating layer over a semiconductor substrate;
a first insulating layer over the semiconductor substrate on both sides of the gate insulating layer;
first spacers over the first insulating layer, the first spacers being spaced apart from each other by a predetermined distance;
a gate conductive plug between the first spacers; and
a silicide layer over an upper surface of the gate conductive plug,
wherein a thickness ratio between the first insulating layer and the silicide layer is in a range of about 1:4 to 1:6.
2. The transistor according to claim 1 , wherein at least one of the gate insulating layer and the first insulating layer has a thickness of 20±5 Å.
3. (canceled)
4. The transistor according to claim 1 , wherein the silicide layer has a thickness of 100±20 Å.
5-20. (canceled)
21. The transistor according to claim 1 , wherein the first spacers are formed before the gate insulating layer is deposited.
22. The transistor according to claim 1 , wherein the gate insulating layer and first insulating layer have an equal thickness.
23. The transistor according to claim 1 , further comprising a halo/pocket region under the gate insulating layer.
24. The transistor according to claim 1 , further comprising second spacers formed on side walls of the gate conductive plug and having the first spacers formed thereon.
25. The transistor according to claim 1 , wherein the first spacers comprise nitride.
26. The transistor according to claim 1 , wherein the gate conductive plug comprises polysilicon.
27. The transistor according to claim 24 , wherein the second spacers comprise one of nitride and oxide.
28. The transistor according to claim 1 , wherein the silicide layer comprises a silicide material selected form the group consisting of Ti, Co, and Ni.
Priority Applications (1)
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US12/491,590 US20090261429A1 (en) | 2004-12-15 | 2009-06-25 | Transistor and method for manufacturing thereof |
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KR10-2004-0106054 | 2004-12-15 | ||
KR1020040106054A KR20060068102A (en) | 2004-12-15 | 2004-12-15 | Method for manufacturing short-channel transistor |
US11/302,137 US7569444B2 (en) | 2004-12-15 | 2005-12-14 | Transistor and method for manufacturing thereof |
US12/491,590 US20090261429A1 (en) | 2004-12-15 | 2009-06-25 | Transistor and method for manufacturing thereof |
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US11/302,137 Division US7569444B2 (en) | 2004-12-15 | 2005-12-14 | Transistor and method for manufacturing thereof |
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US11/302,137 Expired - Fee Related US7569444B2 (en) | 2004-12-15 | 2005-12-14 | Transistor and method for manufacturing thereof |
US12/491,590 Abandoned US20090261429A1 (en) | 2004-12-15 | 2009-06-25 | Transistor and method for manufacturing thereof |
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KR100702324B1 (en) * | 2005-12-14 | 2007-03-30 | 동부일렉트로닉스 주식회사 | Semiconductor device and method for fabricating the same |
KR100832717B1 (en) * | 2006-12-26 | 2008-05-28 | 동부일렉트로닉스 주식회사 | Method for forming the gate of a transistor |
US9530647B2 (en) * | 2013-09-25 | 2016-12-27 | Cree, Inc. | Devices including ultra-short gates and methods of forming same |
KR102167625B1 (en) * | 2013-10-24 | 2020-10-19 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing the same |
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US5668021A (en) * | 1996-06-04 | 1997-09-16 | Motorola, Inc. | Process for fabricating a semiconductor device having a segmented channel region |
US5747381A (en) * | 1996-02-12 | 1998-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Technique for the removal of residual spin-on-glass (SOG) after full SOG etchback |
US5856226A (en) * | 1997-12-19 | 1999-01-05 | Texas Instruments-Acer Incorporated | Method of making ultra-short channel MOSFET with self-aligned silicided contact and extended S/D junction |
US6054355A (en) * | 1997-06-30 | 2000-04-25 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device which includes forming a dummy gate |
US6287924B1 (en) * | 1998-09-21 | 2001-09-11 | Texas Instruments Incorporated | Integrated circuit and method |
US6461904B1 (en) * | 2001-01-09 | 2002-10-08 | Cypress Semiconductor Corp. | Structure and method for making a notched transistor with spacers |
US20040157383A1 (en) * | 2002-07-26 | 2004-08-12 | Park Jeong Ho | Method for forming short-channel transistors |
-
2004
- 2004-12-15 KR KR1020040106054A patent/KR20060068102A/en not_active Application Discontinuation
-
2005
- 2005-12-14 US US11/302,137 patent/US7569444B2/en not_active Expired - Fee Related
-
2009
- 2009-06-25 US US12/491,590 patent/US20090261429A1/en not_active Abandoned
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US5747381A (en) * | 1996-02-12 | 1998-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Technique for the removal of residual spin-on-glass (SOG) after full SOG etchback |
US5668021A (en) * | 1996-06-04 | 1997-09-16 | Motorola, Inc. | Process for fabricating a semiconductor device having a segmented channel region |
US6054355A (en) * | 1997-06-30 | 2000-04-25 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device which includes forming a dummy gate |
US5856226A (en) * | 1997-12-19 | 1999-01-05 | Texas Instruments-Acer Incorporated | Method of making ultra-short channel MOSFET with self-aligned silicided contact and extended S/D junction |
US6287924B1 (en) * | 1998-09-21 | 2001-09-11 | Texas Instruments Incorporated | Integrated circuit and method |
US6461904B1 (en) * | 2001-01-09 | 2002-10-08 | Cypress Semiconductor Corp. | Structure and method for making a notched transistor with spacers |
US20040157383A1 (en) * | 2002-07-26 | 2004-08-12 | Park Jeong Ho | Method for forming short-channel transistors |
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US20060128106A1 (en) | 2006-06-15 |
KR20060068102A (en) | 2006-06-21 |
US7569444B2 (en) | 2009-08-04 |
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