US20090194819A1 - Cmos structures and methods using self-aligned dual stressed layers - Google Patents

Cmos structures and methods using self-aligned dual stressed layers Download PDF

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US20090194819A1
US20090194819A1 US12/424,981 US42498109A US2009194819A1 US 20090194819 A1 US20090194819 A1 US 20090194819A1 US 42498109 A US42498109 A US 42498109A US 2009194819 A1 US2009194819 A1 US 2009194819A1
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transistor
stressed layer
layer
stress
stressed
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Huilong Zhu
Daewon Yang
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Elpis Technologies Inc
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer

Definitions

  • the invention relates generally to mechanical stress within complementary metal oxide semiconductor (CMOS) structures. More particularly, the invention relates to structures and methods that provide mechanical stress within CMOS structures to enhance device performance and improve chip yield.
  • CMOS complementary metal oxide semiconductor
  • CMOS structures comprise complementary mated pairs of field effect transistors of differing conductivity type. Due to the use of complementary mated pairs of differing conductivity type, CMOS structures also provide for reduced energy or power consumption.
  • CMOS transistors A trend within CMOS fabrication is the use of stressed layers as a means to produce a mechanical stress or strain field within a channel region of a CMOS transistor. Certain types of mechanical stresses are desirable insofar as they introduce a stress into a semiconductor channel. Such a stress generally provides for enhanced charge carrier mobilities within a CMOS transistor. Complementary types of channel stress (i.e., tensile or compressive stress or strain in the direction of electrical current) enhance complementary types of charge carrier mobility (i.e., electron or hole) within complementary types of CMOS transistors (i.e., nFET or pFET).
  • channel stress i.e., tensile or compressive stress or strain in the direction of electrical current
  • charge carrier mobility i.e., electron or hole
  • CMOS structures and methods that provide for enhanced levels of mechanical stress within CMOS transistor channels are desirable.
  • CMOS transistors Since use of mechanical stress as a means to enhance charge carrier mobility is likely to continue within future generations of CMOS transistors, desirable are additional CMOS structures and methods for fabrication thereof that provide for charge carrier mobility enhancement incident to use of mechanical stress effects.
  • the invention provides CMOS structures and methods for fabrication thereof wherein complementary transistors are covered with appropriate complementary stressed layers for purposes of providing a mechanical stress effect and enhancing a charge carrier mobility.
  • the complementary stressed layers abut, but do not overlap at a location interposed between a pair of complementary transistors within the CMOS structure.
  • the complementary stressed layers abut, and neither overlap, nor underlap, at a location over a source/drain region where a contact via is intended to be formed.
  • absence of underlap or overlap of the complementary stressed layers provides for an enhanced manufacturing process window or improved chip yield, while avoiding overetching into the silicide layer or underetching into the complementary stressed layers.
  • the invention also provides an etching method for fabricating the CMOS structure.
  • etching method for fabricating the CMOS structure.
  • at least one of a first stressed layer and a second stressed layer different from the first stressed layer that overlap and abut interposed between a first transistor and a second transistor is etched so that the first stressed layer and the second stressed layer abut, but do not overlap.
  • a CMOS structure in accordance with the invention includes a first transistor of a first polarity located laterally separated from a second transistor of a second polarity different from the first polarity over a semiconductor substrate.
  • the CMOS structure also includes a first stressed layer having a first stress located over the first transistor and a second stressed layer having a second stress different from the first stress located over the second transistor.
  • the first stressed layer and the second stressed layer abut and do not overlap.
  • a particular method for fabricating a CMOS structure in accordance with the invention includes forming a first transistor of a first polarity laterally separated from a second transistor of a second polarity different from the first polarity over a semiconductor substrate.
  • the particular method also includes forming a first stressed layer having a first stress located over the first transistor and a second stressed layer having a second stress different from the first stress located over the second transistor.
  • the first stressed layer and the second stressed layer abut and overlap.
  • This particular method also includes etching at least one of the first stressed layer and the second stressed layer so that the first stressed layer and the second stressed layer abut and do not overlap.
  • Another method for fabricating a CMOS structure includes forming a first transistor of a first polarity laterally separated from a second transistor of a second polarity different than the first polarity over a semiconductor substrate.
  • This other method also includes forming a first stressed layer having a first stress located over the first transistor and a second stressed layer having a second stress different from the first stress located over the second transistor.
  • the first stressed layer and the second stressed layer abut and overlap.
  • This other method also includes further masking at least one of the first transistor and the second transistor to leave exposed at least the portion of the first stressed layer and the second stressed layer that abut and overlap.
  • This other method also includes etching at least one of the first stressed layer and the second stressed layer so that the first stressed layer and the second stressed layer abut and do not overlap.
  • the phrase “abut and do not overlap” is intended to describe a disposition and location of a first stressed layer and a second stressed layer that contact completely at end portions thereof. In addition, no portion of either the first stressed layer or the second stressed layer lies above the other of the first stressed layer or the second stressed layer.
  • FIG. 1 to FIG. 9 show a series of schematic cross-sectional diagrams illustrating the results of progressive stages in fabricating a CMOS structure in accordance with an embodiment of the invention.
  • FIG. 10 to FIG. 12 show a series of schematic cross-sectional diagrams illustrating the results of progressive stages in fabricating a CMOS structure in accordance with another embodiment of the invention.
  • FIG. 13 to FIG. 15 show a series of schematic cross-sectional diagrams illustrating the results of progressive stages in fabricating a CMOS structure in accordance with yet another embodiment of the invention.
  • FIG. 16 to FIG. 18 show a series of schematic cross-sectional diagrams illustrating the results of progressive stages in fabricating a CMOS structure in accordance with still yet another embodiment of the invention.
  • FIG. 1 to FIG. 9 show a series of schematic cross-sectional diagrams illustrating the results of progressive stages in fabricating a CMOS structure in accordance with an embodiment of the invention.
  • FIG. 1 shows a semiconductor substrate 10 that comprises active regions separated by an isolation region 12 .
  • a first transistor T 1 is located upon one active region and a second transistor T 2 is located upon an adjacent active region.
  • Transistors T 1 and T 2 are of different polarity (i.e., conductivity type) and thus the doping type in each of active regions is different.
  • the transistors T 1 and T 2 comprise gate dielectrics 14 located upon the active regions of the semiconductor substrate 10 .
  • Gate electrodes 16 are aligned upon gate dielectrics 14 , although such alignment is not a requirement of the invention.
  • Two part spacer layers 18 i.e.
  • Source/drain regions 20 are located within the active regions of the semiconductor substrate and separated by channel regions located beneath the gate electrodes 16 .
  • Silicide layers 22 are located upon source/drain regions 20 and gate electrodes 16 .
  • Each of the foregoing semiconductor substrate 10 , layers and structures may comprise materials and have dimensions that are conventional in the semiconductor fabrication art.
  • Each of the foregoing semiconductor substrate 10 , layers and structures may be formed using methods that are conventional in the semiconductor fabrication art.
  • the semiconductor substrate 10 comprises a semiconductor material.
  • semiconductor materials from which may be comprised the semiconductor substrate 10 include silicon, germanium, silicon-germanium alloy, silicon carbide, silicon-germanium carbide alloy and compound semiconductor materials.
  • Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide and indium phosphide semiconductor materials.
  • the semiconductor substrate 10 may comprise a bulk semiconductor substrate.
  • the embodiment and the invention also contemplates that the semiconductor substrate 10 may comprise a semiconductor-on-insulator substrate.
  • the embodiments and the invention also contemplate that the semiconductor substrate may comprise a hybrid orientation substrate.
  • a semiconductor-on-insulator substrate comprises a base semiconductor substrate, a buried dielectric layer located thereupon and a surface semiconductor layer located further thereupon.
  • a hybrid orientation substrate comprises a semiconductor substrate having multiple crystallographic orientations that may provide different crystallographic orientation channel regions for each transistor within a CMOS structure.
  • Semiconductor-on-insulator substrates and hybrid orientation substrates may be formed using any of several layer lamination methods and layer transfer methods.
  • the foregoing substrates may also be formed using separation by implantation of oxygen (SIMOX) methods.
  • SIMOX separation by implantation of oxygen
  • the isolation region 12 comprises a dielectric isolation material.
  • the embodiments and the invention contemplate that isolation regions may comprise shallow trench isolation regions, deep trench isolation regions and, to a lesser extent, local oxidation of silicon isolation regions.
  • the dielectric isolation material from which is comprised the isolation region 12 may comprise an oxide, a nitride and/or an oxynitride of silicon. Oxides, nitrides and oxynitrides of other elements are not excluded as dielectric isolation materials.
  • Dielectric isolation materials may be formed using methods including, but not limited to: thermal or plasma oxidation or nitridation methods, chemical vapor deposition methods and physical vapor deposition methods.
  • the isolation region 12 is formed at least in part from a silicon oxide dielectric isolation material that has a thickness from about 100 to about 50000 angstroms, where the thickness is highly dependent upon the use of a SOI or a bulk semiconductor substrate.
  • the gate dielectrics 14 may comprise generally conventional gate dielectric materials having a dielectric constant from about 4 to about 20, measured in vacuum. Such generally conventional gate dielectric materials may include, but are not limited to: oxides, nitrides and oxynitrides of silicon. They may be formed using methods analogous or identical to those disclosed above with respect to forming the isolation region 12 . Alternatively, the gate dielectrics 14 may also comprise generally higher dielectric constant dielectric materials having a dielectric constant from about 20 to at least about 100, also measured in a vacuum.
  • dielectric constant dielectric materials may include, but are not limited to: hafnium oxides, hafnium silicates, titanium oxides, lanthanum oxides, barium-strontium titantates (BSTs) and lead-zirconate titantates (PZTs).
  • the gate dielectrics 14 comprise a thermal silicon oxide gate dielectric material having a thickness from about 5 to about 70 angstroms.
  • the gate electrodes 18 comprise gate electrode conductor materials.
  • Typical gate electrode conductor materials include certain metals, metal alloys, metal nitrides and metal suicides, as well as polysilicon materials.
  • the gate electrode conductor materials may be formed using methods including, but not limited to: plating methods, chemical vapor deposition methods (including atomic layer chemical vapor deposition methods) and physical vapor deposition methods (including sputtering methods).
  • the gate electrodes 18 comprise a metal, metal silicide or polysilicon gate electrode conductor material having a thickness from about 500 to about 1500 angstroms.
  • spacer layers 18 are intended as two component structures comprising: (1) the illustrated “L” or invented “L:” shaped portions adjoining the gate electrodes 16 ; in conjunction with, (2) the more traditional spacer shaped portions nested within the “L” shaped portions or the inverted “L” shaped portions.
  • Each of the foregoing two component structures may comprise materials analogous, equivalent or identical to the materials from which are comprised the isolation region 12 .
  • the “L” or inverted “L” shaped structures are typically deposited using a conformal layer deposition method.
  • the spacer shaped portions are formed using a blanket layer deposition and anisotropic etchback method.
  • the source/drain regions 20 are formed using a two step ion implantation method.
  • a first step within the two step ion implantation method uses the gates 16 , absent the spacers 18 , as a mask to form extension regions into the semiconductor substrate 10 .
  • a second step within the two step ion implantation method uses the gates 16 and the spacers 18 as a mask to form conductor region portions of the source/drain regions 20 into the semiconductor substrate.
  • the source/drain regions 20 comprise extension region components and conductor region components. Dopant concentrations within the source/drain regions 20 range from about 1 ⁇ 10 20 to about 3 ⁇ 10 21 dopant atoms per cubic centimeter.
  • the silicide layers 22 may comprise any of several metal silicide forming metals.
  • Non-limiting examples of silicide forming metals include titanium, tungsten, nickel, cobalt, vanadium and molybdenum silicide forming metals.
  • the silicide layers 22 are typically formed using a self-aligned silicide (i.e., salicide) method that provides for: (1) a blanket metal silicide forming metal layer deposition; (2) a subsequent thermal annealing to provide for silicide formation in contact with silicon; and (3) a subsequent excess silicide forming metal layer stripping.
  • each of the silicide layers 22 has a thickness from about 50 to about 200 angstroms.
  • FIG. 2 shows a first stressed layer 24 located upon the CMOS structure of FIG. 1 .
  • FIG. 2 also shows an etch stop layer 26 located upon the first stressed layer 24 .
  • the first stressed layer 24 comprises a material that has a first stress intended to compliment and enhance performance of the first transistor T 1 .
  • the first stress is preferably a tensile stress that provides a tensile stress within the channel of the first transistor T 1 .
  • an electron charge carrier mobility within the first transistor T 1 is enhanced.
  • a compressive stress of an overlying layer is desirable for purposes of generating compressive channel stress that yields an enhanced hole mobility.
  • the first transistor T 1 is preferably an nFET and the first stressed layer 24 preferably comprises a tensile stressed layer.
  • the first stressed layer 24 may comprise any of several stressed materials.
  • Non-limiting examples includes nitrides and oxynitrides.
  • Nitrides are particularly common stressed layer materials insofar as different magnitudes and types of stress may be introduced into a nitride layer material by using different deposition conditions for forming the nitride layer.
  • Particular deposition conditions that affect nitride layer stress include a changing of the ratio of a low frequency plasma to a high frequency plasma at temperature range from 200° C. to 600° C.
  • the first stressed layer 24 comprises a nitride material that has a thickness from about 500 to about 1000 angstroms, although the invention is not limited to stressed layers comprising only nitride materials.
  • the etch stop layer 26 may comprise any of several etch stop materials. Etch stop materials will typically have a different composition from the first stressed layer 24 . Typically, the etch stop layer 26 comprises an oxide etch stop material when the first stressed layer 24 comprises a nitride material. Within the instant embodiment, the etch stop layer 26 typically comprises a silicon oxide etch stop material that has a thickness from about 50 to about 300 angstroms. The etch stop layer 26 may be formed using methods analogous to the methods used for forming the isolation region 12 .
  • FIG. 3 shows a block mask 28 located upon the etch stop layer 26 and covering the first transistor T 1 .
  • the block mask 28 may comprise any of several mask materials. Non-limiting examples include hard mask materials and photoresist mask materials. Photoresist mask materials are considerably more common. Non-limiting examples of photoresist mask materials include positive photoresist materials, negative photoresist materials and hybrid photoresist materials.
  • the block mask 28 comprises a photoresist material having a thickness from about 1000 to about 5000 angstroms.
  • FIG. 4 shows the results of etching the etch stop layer 26 and the first stressed layer 24 to form corresponding etch stop layer 26 ′ and first stressed layer 24 ′, while using the block mask 28 as an etch mask.
  • the foregoing etching is typically undertaken while using a plasma etchant, although neither the embodiment nor the invention is so limited. Wet chemical etchants, while generally less common, may also be used.
  • the plasma etchant uses a fluorine containing etchant gas composition for etching each of the etch stop layer 26 and the first stressed layer 24 when forming therefrom the etch stop layer 26 ′ and the first stressed layer 24 ′.
  • the etching also forms the spacers 18 ′ from the spacers 18 .
  • FIG. 5 first shows the results of stripping the block mask 28 from the CMOS structure of FIG. 4 .
  • the block mask 28 may be stripped using methods and materials that are otherwise conventional in the semiconductor fabrication art. Included are wet chemical stripping methods and materials, dry plasma stripping methods and materials and aggregate stripping methods and materials thereof. Dry plasma stripping methods and materials are particularly common, but do not limit the invention.
  • FIG. 5 also shows a second stressed layer 30 located upon the semiconductor structure of FIG. 4 , subsequent to removing the block mask 28 therefrom.
  • the second stressed layer 30 has an appropriate stress engineered to promote enhanced performance (generally within the context of charge carrier mobility) of the second transistor T 2 .
  • the second stressed layer 30 may comprise materials and have dimensions that are analogous, equivalent or identical to the materials and dimensions used for forming the first stressed layer 24 that is illustrated in FIG. 3 .
  • the first stressed layer 24 typically comprises a silicon nitride material whose stress (i.e., tensile or compressive) may be engineered incident to control of particular deposition conditions.
  • the second stressed layer 30 thus also comprises a nitride material, but for which deposition conditions are selected to have a type of stress (i.e., tensile or compressive) typically opposite the first stressed layer 24 .
  • the first stressed layer 24 preferably comprises a tensile stress from about 500 MPa to about 4 GPa (when the first transistor T 1 is an nFET) and the second stressed layer 30 preferably a compressive stress from about ⁇ 500 MPa to about ⁇ 5 GPa (when the second transistor T 2 is a pFET).
  • FIG. 6 shows a block mask 28 ′ located upon the second stressed layer 30 and covering the second transistor T 2 .
  • the block mask 28 ′ otherwise comprises materials and has dimensions analogous or equivalent to the block mask 28 that is illustrated in FIG. 3 .
  • FIG. 7 shows the results of patterning the second stressed layer 30 to form a second stressed layer 30 ′, and subsequently stripping the block mask 28 ′ from the CMOS structure of FIG. 6 .
  • the second stressed layer 30 may be etched to form the second stressed layer 30 , while using methods and materials analogous equivalent or identical to the methods and materials used for etching the first stressed layer 24 to from the first stressed layer 24 ′.
  • the second block mask 28 ′ may be stripped using methods and materials analogous equivalent or identical to the methods and materials used for stripping the first block mask 28 .
  • the first stressed layer 24 ′ and the second stressed layer 30 ′ abut and overlap.
  • FIG. 8 shows the results of etching the etch stop layer 26 ′, the first stressed layer 24 ′ and the second stressed layer 30 ′ so that a resulting first stressed layer 24 ′′ and a resulting second stressed layer 30 ′′ abut and do not overlap, rather than abut and overlap. Also resulting from this etching is etch stop layers 26 ′′.
  • etching may be undertaken using methods that are conventional in the semiconductor fabrication art.
  • Non-limiting examples are plasma etch methods and sputter etch methods.
  • Desirable are sputter etch methods that use argon or nitrogen sputter etchants.
  • Such sputter etchants desirably have a tendency to etch more from top surfaces than lower surfaces of the first stressed layer 24 ′ and the second stressed layer 30 ′ when forming the first stressed layer 24 ′′ and the second stressed layer 30 ′′.
  • the abutment of the first stressed layer 24 ′′ with the second stressed layer 30 ′′ absent overlap thereof provides for enhanced manufacturability.
  • the enhanced manufacturability is desirable under circumstances where overlapped portions of the first stressed layer 24 ′ and the second stressed layer 30 ′ are located over a contact region portion of a source/drain region, particularly when the source/drain region has a silicide layer thereupon.
  • FIG. 9 shows the results of etching remaining portions of the etch stop layer 26 ′′ from the CMOS structure of FIG. 8 .
  • FIG. 9 also shows a capping layer 32 located upon the CMOS structure of FIG. 8 after etching remaining portions of the etch stop layer 26 ′′.
  • the remaining portions of the etch stop layer 26 ′′ may be etched using a wet chemical etchant or a dry plasma etchant.
  • the capping layer 30 may comprise any of several capping materials. Included are oxides, nitrides and oxynitrides of silicon, as well as oxides, nitrides and oxynitrides of other elements.
  • the capping layer 32 preferably comprises a silicon nitride material having a thickness from about 50 to about 100 angstroms.
  • FIG. 9 shows a CMOS structure in accordance with a first embodiment of the invention.
  • the CMOS structure comprises complementary first stressed layer 24 ′′ located upon first transistor T 1 and second stressed layer 30 ′′ located upon second transistor T 2 .
  • the complementary first stressed layer 24 ′′ and second stressed layer 30 ′′ abut, but do not overlap at a location interposed between the first transistor T 1 and the second transistor T 2 .
  • the CMOS structure that is illustrated in FIG. 9 provides for enhanced manufacturability.
  • the enhanced manufacturability results from a nominally level surface provided by the first stressed layer 24 ′′ and the second stressed layer 30 ′′ so that a contact via may be efficiently etched reaching a source/drain region 20 having a silicide layer 22 thereupon while not damaging the silicide layer 22 .
  • FIG. 10 to FIG. 12 show a series of schematic cross-sectional diagrams illustrating the results of progressive stages in fabricating a CMOS structure in accordance with another embodiment of the invention.
  • This other embodiment of the invention comprises a second embodiment of the invention.
  • FIG. 10 shows a CMOS structure that derives from the CMOS structure of FIG. 7 within the first embodiment.
  • the CMOS structure of FIG. 10 however shows a blocking layer 34 located upon the CMOS structure of FIG. 7 .
  • a block mask 36 is located upon the blocking layer 34 and covering the first transistor T 1 .
  • a block mask 36 ′ is located upon the blocking layer 34 and covering the second transistor T 2 .
  • the blocking layer 34 preferably comprises an oxide material under circumstances where the first stressed layer 24 and the second stressed layer 30 comprise nitride materials.
  • the blocking layer 34 may be formed using methods and materials analogous, equivalent or identical to the methods and materials used for forming the etch stop layer 26 .
  • the blocking layer 34 has a thickness from about 300 to about 500 angstroms.
  • the block masks 36 and 36 ′ may comprise any of several block mask materials that are disclosed above for the block masks 28 and 28 ′.
  • FIG. 11 shows the results of further processing of the CMOS structure of FIG. 10 .
  • FIG. 11 shows the results of etching the blocking layer 34 to form blocking layers 34 ′ that straddle the first transistor T 1 and the second transistor T 2 . In so doing, an abutted and overlapped portion of the first stressed layer 24 ′ and the second stressed layer 30 ′ is exposed.
  • FIG. 11 also shows the results of stripping the block masks 36 and 36 ′.
  • FIG. 12 shows the results of further processing of the CMOS structure of FIG. 11 .
  • FIG. 12 shows the results of etching the first stressed layer 24 ′ and the second stressed layer 30 ′ to yield first stressed layer 24 ′′ and second stressed layer 30 ′′ that are abutted and do not overlap.
  • the etching preferably uses a nitrogen or argon sputter etching as is disclosed above within the context of the first embodiment.
  • abutment absent overlap of the first stressed layer 24 ′′ and the second stressed layer 30 ′′ provides for enhanced manufacturability of the CMOS structure of FIG. 12 .
  • the use of the blocking layers 34 ′ also assist in preserving a full initial thicknesses of the first stressed layer 24 ′′ and the second stressed layer 30 ′′ at locations over the first transistor T 1 and the second transistor T 2 .
  • a full effect of stress from the first stressed layer 24 ′′ and the second stressed layer 30 ′′ is transmitted into respective semiconductor channels over which they are formed.
  • FIG. 13 to FIG. 15 show a series of schematic cross-sectional diagrams corresponding with FIG. 10 to FIG. 12 , but where the block mask 36 is located over the first transistor T 1 only, and not the second transistor T 2 .
  • FIG. 13 to FIG. 15 comprise a third embodiment of the invention.
  • FIG. 16 to FIG. 18 show a series of schematic cross-sectional diagrams corresponding with FIG. 10 to FIG. 12 or FIG. 13 to FIG. 15 , but where the block mask 36 ′ is located over the second transistor T 2 only and not the first transistor T 1 .
  • FIG. 16 to FIG. 18 comprise a fourth embodiment of the invention.
  • FIG. 13 to FIG. 15 or FIG. 16 to FIG. 18 follows analogously from the processing of FIG. 10 to FIG. 12 .
  • the first stressed layer 24 ′′ i.e., FIG. 15
  • the second stressed layer 30 ′′ i.e., FIG. 18
  • the first stressed layer 24 ′ that abuts and overlaps the second stressed layer 30 ′ are etched to form the first stressed layer 24 ′′ and the second stressed layer 30 ′′ that abut, but do not overlap.
  • the second embodiment, the third embodiment and the fourth embodiment provide for enhanced manufacturability of a CMOS structure due to the foregoing abutment absent overlap.

Abstract

A CMOS structure and methods for fabricating the CMOS structure provide that a first stressed layer located over a first transistor and a second stressed layer located over a second transistor abut but do not overlap. Such an abutment absent overlap provides for enhanced manufacturing flexibility when forming a contact to a silicide layer upon a source/drain region within one of the first transistor and the second transistor.

Description

    RELATED APPLICATION
  • This application is a divisional of U.S. patent application Ser. No. 11/380,695, filed Apr. 28, 2006.
    • BACKGROUND
  • 1. Field of the Invention
  • The invention relates generally to mechanical stress within complementary metal oxide semiconductor (CMOS) structures. More particularly, the invention relates to structures and methods that provide mechanical stress within CMOS structures to enhance device performance and improve chip yield.
  • 2. Description of the Related Art
  • CMOS structures comprise complementary mated pairs of field effect transistors of differing conductivity type. Due to the use of complementary mated pairs of differing conductivity type, CMOS structures also provide for reduced energy or power consumption.
  • A trend within CMOS fabrication is the use of stressed layers as a means to produce a mechanical stress or strain field within a channel region of a CMOS transistor. Certain types of mechanical stresses are desirable insofar as they introduce a stress into a semiconductor channel. Such a stress generally provides for enhanced charge carrier mobilities within a CMOS transistor. Complementary types of channel stress (i.e., tensile or compressive stress or strain in the direction of electrical current) enhance complementary types of charge carrier mobility (i.e., electron or hole) within complementary types of CMOS transistors (i.e., nFET or pFET).
  • Since mechanical stress is a significant factor that may considerably improve field effect transistor performance, CMOS structures and methods that provide for enhanced levels of mechanical stress within CMOS transistor channels are desirable.
  • Methods for improving charge carrier mobility within CMOS structures that include pFET and nFET devices are known in the semiconductor fabrication art. For example, En et al, in U.S. Pat. No. 6,573,172 teaches the use of a tensile stressed layer over a pFET device to provide a compressive stress of a pFET channel therein and a compressive stressed layer over an nFET device to cause a tensile stress of an nFET channel therein.
  • Since use of mechanical stress as a means to enhance charge carrier mobility is likely to continue within future generations of CMOS transistors, desirable are additional CMOS structures and methods for fabrication thereof that provide for charge carrier mobility enhancement incident to use of mechanical stress effects.
    • SUMMARY OF THE INVENTION
  • The invention provides CMOS structures and methods for fabrication thereof wherein complementary transistors are covered with appropriate complementary stressed layers for purposes of providing a mechanical stress effect and enhancing a charge carrier mobility. The complementary stressed layers abut, but do not overlap at a location interposed between a pair of complementary transistors within the CMOS structure. In particular, the complementary stressed layers abut, and neither overlap, nor underlap, at a location over a source/drain region where a contact via is intended to be formed. When a silicide layer is located upon the source/drain region, absence of underlap or overlap of the complementary stressed layers provides for an enhanced manufacturing process window or improved chip yield, while avoiding overetching into the silicide layer or underetching into the complementary stressed layers.
  • The invention also provides an etching method for fabricating the CMOS structure. Within the etching method, at least one of a first stressed layer and a second stressed layer different from the first stressed layer that overlap and abut interposed between a first transistor and a second transistor is etched so that the first stressed layer and the second stressed layer abut, but do not overlap.
  • A CMOS structure in accordance with the invention includes a first transistor of a first polarity located laterally separated from a second transistor of a second polarity different from the first polarity over a semiconductor substrate. The CMOS structure also includes a first stressed layer having a first stress located over the first transistor and a second stressed layer having a second stress different from the first stress located over the second transistor. Within the CMOS structure, the first stressed layer and the second stressed layer abut and do not overlap.
  • A particular method for fabricating a CMOS structure in accordance with the invention includes forming a first transistor of a first polarity laterally separated from a second transistor of a second polarity different from the first polarity over a semiconductor substrate. The particular method also includes forming a first stressed layer having a first stress located over the first transistor and a second stressed layer having a second stress different from the first stress located over the second transistor. Within this particular method, the first stressed layer and the second stressed layer abut and overlap. This particular method also includes etching at least one of the first stressed layer and the second stressed layer so that the first stressed layer and the second stressed layer abut and do not overlap.
  • Another method for fabricating a CMOS structure includes forming a first transistor of a first polarity laterally separated from a second transistor of a second polarity different than the first polarity over a semiconductor substrate. This other method also includes forming a first stressed layer having a first stress located over the first transistor and a second stressed layer having a second stress different from the first stress located over the second transistor. Within this other method, the first stressed layer and the second stressed layer abut and overlap. This other method also includes further masking at least one of the first transistor and the second transistor to leave exposed at least the portion of the first stressed layer and the second stressed layer that abut and overlap. This other method also includes etching at least one of the first stressed layer and the second stressed layer so that the first stressed layer and the second stressed layer abut and do not overlap.
  • Within the disclosed invention the phrase “abut and do not overlap” is intended to describe a disposition and location of a first stressed layer and a second stressed layer that contact completely at end portions thereof. In addition, no portion of either the first stressed layer or the second stressed layer lies above the other of the first stressed layer or the second stressed layer.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The objects, features and advantages of the invention are understood within the context of the Description of the Preferred Embodiments, as set forth below. The Description of the Preferred Embodiments is understood within the context of the accompanying drawings, which form a material part of this disclosure, wherein:
  • FIG. 1 to FIG. 9 show a series of schematic cross-sectional diagrams illustrating the results of progressive stages in fabricating a CMOS structure in accordance with an embodiment of the invention.
  • FIG. 10 to FIG. 12 show a series of schematic cross-sectional diagrams illustrating the results of progressive stages in fabricating a CMOS structure in accordance with another embodiment of the invention.
  • FIG. 13 to FIG. 15 show a series of schematic cross-sectional diagrams illustrating the results of progressive stages in fabricating a CMOS structure in accordance with yet another embodiment of the invention.
  • FIG. 16 to FIG. 18 show a series of schematic cross-sectional diagrams illustrating the results of progressive stages in fabricating a CMOS structure in accordance with still yet another embodiment of the invention.
    •  DESCRIPTION OF THE PREFERRED EMBODIMENT
  • The invention, which provides CMOS structures and methods for fabrication thereof that include complementary stressed layers that abut and do not overlap, is described in further detail within the context of the description below. The description below is understood within the context of the drawings described above. Since the drawings are intended for illustrative purposes, they are not necessarily drawn to scale.
  • FIG. 1 to FIG. 9 show a series of schematic cross-sectional diagrams illustrating the results of progressive stages in fabricating a CMOS structure in accordance with an embodiment of the invention.
  • FIG. 1 shows a semiconductor substrate 10 that comprises active regions separated by an isolation region 12. A first transistor T1 is located upon one active region and a second transistor T2 is located upon an adjacent active region. Transistors T1 and T2 are of different polarity (i.e., conductivity type) and thus the doping type in each of active regions is different. The transistors T1 and T2 comprise gate dielectrics 14 located upon the active regions of the semiconductor substrate 10. Gate electrodes 16 are aligned upon gate dielectrics 14, although such alignment is not a requirement of the invention. Two part spacer layers 18 (i.e. “L” or inverted “L” portions adjoining gate electrodes 16 and spacer shaped portions nested therein) adjoin gate electrodes 16 and are illustrated as mirrored spacer 18 components although they are single components that surround each individual gate 16. Source/drain regions 20 are located within the active regions of the semiconductor substrate and separated by channel regions located beneath the gate electrodes 16. Silicide layers 22 are located upon source/drain regions 20 and gate electrodes 16.
  • Each of the foregoing semiconductor substrate 10, layers and structures may comprise materials and have dimensions that are conventional in the semiconductor fabrication art. Each of the foregoing semiconductor substrate 10, layers and structures may be formed using methods that are conventional in the semiconductor fabrication art.
  • The semiconductor substrate 10 comprises a semiconductor material. Non-limiting examples of semiconductor materials from which may be comprised the semiconductor substrate 10 include silicon, germanium, silicon-germanium alloy, silicon carbide, silicon-germanium carbide alloy and compound semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide and indium phosphide semiconductor materials.
  • The embodiments and the invention contemplate that the semiconductor substrate 10 may comprise a bulk semiconductor substrate. Alternatively, the embodiment and the invention also contemplates that the semiconductor substrate 10 may comprise a semiconductor-on-insulator substrate. As a further alternative, the embodiments and the invention also contemplate that the semiconductor substrate may comprise a hybrid orientation substrate.
  • A semiconductor-on-insulator substrate comprises a base semiconductor substrate, a buried dielectric layer located thereupon and a surface semiconductor layer located further thereupon. A hybrid orientation substrate comprises a semiconductor substrate having multiple crystallographic orientations that may provide different crystallographic orientation channel regions for each transistor within a CMOS structure.
  • Semiconductor-on-insulator substrates and hybrid orientation substrates may be formed using any of several layer lamination methods and layer transfer methods. The foregoing substrates may also be formed using separation by implantation of oxygen (SIMOX) methods.
  • The isolation region 12 comprises a dielectric isolation material. The embodiments and the invention contemplate that isolation regions may comprise shallow trench isolation regions, deep trench isolation regions and, to a lesser extent, local oxidation of silicon isolation regions. The dielectric isolation material from which is comprised the isolation region 12 may comprise an oxide, a nitride and/or an oxynitride of silicon. Oxides, nitrides and oxynitrides of other elements are not excluded as dielectric isolation materials. Dielectric isolation materials may be formed using methods including, but not limited to: thermal or plasma oxidation or nitridation methods, chemical vapor deposition methods and physical vapor deposition methods. Typically, the isolation region 12 is formed at least in part from a silicon oxide dielectric isolation material that has a thickness from about 100 to about 50000 angstroms, where the thickness is highly dependent upon the use of a SOI or a bulk semiconductor substrate.
  • The gate dielectrics 14 may comprise generally conventional gate dielectric materials having a dielectric constant from about 4 to about 20, measured in vacuum. Such generally conventional gate dielectric materials may include, but are not limited to: oxides, nitrides and oxynitrides of silicon. They may be formed using methods analogous or identical to those disclosed above with respect to forming the isolation region 12. Alternatively, the gate dielectrics 14 may also comprise generally higher dielectric constant dielectric materials having a dielectric constant from about 20 to at least about 100, also measured in a vacuum. These generally higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxides, hafnium silicates, titanium oxides, lanthanum oxides, barium-strontium titantates (BSTs) and lead-zirconate titantates (PZTs). Typically, the gate dielectrics 14 comprise a thermal silicon oxide gate dielectric material having a thickness from about 5 to about 70 angstroms.
  • The gate electrodes 18 comprise gate electrode conductor materials. Typical gate electrode conductor materials include certain metals, metal alloys, metal nitrides and metal suicides, as well as polysilicon materials. The gate electrode conductor materials may be formed using methods including, but not limited to: plating methods, chemical vapor deposition methods (including atomic layer chemical vapor deposition methods) and physical vapor deposition methods (including sputtering methods). Typically, the gate electrodes 18 comprise a metal, metal silicide or polysilicon gate electrode conductor material having a thickness from about 500 to about 1500 angstroms.
  • As noted above, spacer layers 18 are intended as two component structures comprising: (1) the illustrated “L” or invented “L:” shaped portions adjoining the gate electrodes 16; in conjunction with, (2) the more traditional spacer shaped portions nested within the “L” shaped portions or the inverted “L” shaped portions. Each of the foregoing two component structures may comprise materials analogous, equivalent or identical to the materials from which are comprised the isolation region 12. The “L” or inverted “L” shaped structures are typically deposited using a conformal layer deposition method. The spacer shaped portions are formed using a blanket layer deposition and anisotropic etchback method.
  • The source/drain regions 20 are formed using a two step ion implantation method. A first step within the two step ion implantation method uses the gates 16, absent the spacers 18, as a mask to form extension regions into the semiconductor substrate 10. A second step within the two step ion implantation method uses the gates 16 and the spacers 18 as a mask to form conductor region portions of the source/drain regions 20 into the semiconductor substrate. Thus, the source/drain regions 20 comprise extension region components and conductor region components. Dopant concentrations within the source/drain regions 20 range from about 1×1020 to about 3×1021 dopant atoms per cubic centimeter.
  • The silicide layers 22 may comprise any of several metal silicide forming metals. Non-limiting examples of silicide forming metals include titanium, tungsten, nickel, cobalt, vanadium and molybdenum silicide forming metals. The silicide layers 22 are typically formed using a self-aligned silicide (i.e., salicide) method that provides for: (1) a blanket metal silicide forming metal layer deposition; (2) a subsequent thermal annealing to provide for silicide formation in contact with silicon; and (3) a subsequent excess silicide forming metal layer stripping. Typically, each of the silicide layers 22 has a thickness from about 50 to about 200 angstroms.
  • FIG. 2 shows a first stressed layer 24 located upon the CMOS structure of FIG. 1. FIG. 2 also shows an etch stop layer 26 located upon the first stressed layer 24.
  • The first stressed layer 24 comprises a material that has a first stress intended to compliment and enhance performance of the first transistor T1. When the first transistor T1 is an nFET, the first stress is preferably a tensile stress that provides a tensile stress within the channel of the first transistor T1. Under those circumstances, an electron charge carrier mobility within the first transistor T1 is enhanced. Conversely, when the first transistor is a pFET, a compressive stress of an overlying layer is desirable for purposes of generating compressive channel stress that yields an enhanced hole mobility.
  • Within the instant embodiment, the first transistor T1 is preferably an nFET and the first stressed layer 24 preferably comprises a tensile stressed layer.
  • The first stressed layer 24 may comprise any of several stressed materials. Non-limiting examples includes nitrides and oxynitrides. Nitrides are particularly common stressed layer materials insofar as different magnitudes and types of stress may be introduced into a nitride layer material by using different deposition conditions for forming the nitride layer. Particular deposition conditions that affect nitride layer stress include a changing of the ratio of a low frequency plasma to a high frequency plasma at temperature range from 200° C. to 600° C.
  • Typically, the first stressed layer 24 comprises a nitride material that has a thickness from about 500 to about 1000 angstroms, although the invention is not limited to stressed layers comprising only nitride materials.
  • The etch stop layer 26 may comprise any of several etch stop materials. Etch stop materials will typically have a different composition from the first stressed layer 24. Typically, the etch stop layer 26 comprises an oxide etch stop material when the first stressed layer 24 comprises a nitride material. Within the instant embodiment, the etch stop layer 26 typically comprises a silicon oxide etch stop material that has a thickness from about 50 to about 300 angstroms. The etch stop layer 26 may be formed using methods analogous to the methods used for forming the isolation region 12.
  • FIG. 3 shows a block mask 28 located upon the etch stop layer 26 and covering the first transistor T1. The block mask 28 may comprise any of several mask materials. Non-limiting examples include hard mask materials and photoresist mask materials. Photoresist mask materials are considerably more common. Non-limiting examples of photoresist mask materials include positive photoresist materials, negative photoresist materials and hybrid photoresist materials. Typically, the block mask 28 comprises a photoresist material having a thickness from about 1000 to about 5000 angstroms.
  • FIG. 4 shows the results of etching the etch stop layer 26 and the first stressed layer 24 to form corresponding etch stop layer 26′ and first stressed layer 24′, while using the block mask 28 as an etch mask. The foregoing etching is typically undertaken while using a plasma etchant, although neither the embodiment nor the invention is so limited. Wet chemical etchants, while generally less common, may also be used. Typically, the plasma etchant uses a fluorine containing etchant gas composition for etching each of the etch stop layer 26 and the first stressed layer 24 when forming therefrom the etch stop layer 26′ and the first stressed layer 24′. As is illustrated in FIG. 4, the etching also forms the spacers 18′ from the spacers 18.
  • FIG. 5 first shows the results of stripping the block mask 28 from the CMOS structure of FIG. 4. The block mask 28 may be stripped using methods and materials that are otherwise conventional in the semiconductor fabrication art. Included are wet chemical stripping methods and materials, dry plasma stripping methods and materials and aggregate stripping methods and materials thereof. Dry plasma stripping methods and materials are particularly common, but do not limit the invention.
  • FIG. 5 also shows a second stressed layer 30 located upon the semiconductor structure of FIG. 4, subsequent to removing the block mask 28 therefrom.
  • The second stressed layer 30 has an appropriate stress engineered to promote enhanced performance (generally within the context of charge carrier mobility) of the second transistor T2. The second stressed layer 30 may comprise materials and have dimensions that are analogous, equivalent or identical to the materials and dimensions used for forming the first stressed layer 24 that is illustrated in FIG. 3. As is disclosed above, the first stressed layer 24 typically comprises a silicon nitride material whose stress (i.e., tensile or compressive) may be engineered incident to control of particular deposition conditions. The second stressed layer 30 thus also comprises a nitride material, but for which deposition conditions are selected to have a type of stress (i.e., tensile or compressive) typically opposite the first stressed layer 24.
  • Within the context of the instant embodiment, the first stressed layer 24 preferably comprises a tensile stress from about 500 MPa to about 4 GPa (when the first transistor T1 is an nFET) and the second stressed layer 30 preferably a compressive stress from about −500 MPa to about −5 GPa (when the second transistor T2 is a pFET).
  • FIG. 6 shows a block mask 28′ located upon the second stressed layer 30 and covering the second transistor T2. The block mask 28′ otherwise comprises materials and has dimensions analogous or equivalent to the block mask 28 that is illustrated in FIG. 3.
  • FIG. 7 shows the results of patterning the second stressed layer 30 to form a second stressed layer 30′, and subsequently stripping the block mask 28′ from the CMOS structure of FIG. 6.
  • The second stressed layer 30 may be etched to form the second stressed layer 30, while using methods and materials analogous equivalent or identical to the methods and materials used for etching the first stressed layer 24 to from the first stressed layer 24′. The second block mask 28′ may be stripped using methods and materials analogous equivalent or identical to the methods and materials used for stripping the first block mask 28.
  • As is illustrated within the schematic diagram of FIG. 7, the first stressed layer 24′ and the second stressed layer 30′ abut and overlap.
  • FIG. 8 shows the results of etching the etch stop layer 26′, the first stressed layer 24′ and the second stressed layer 30′ so that a resulting first stressed layer 24″ and a resulting second stressed layer 30″ abut and do not overlap, rather than abut and overlap. Also resulting from this etching is etch stop layers 26″.
  • The foregoing etching may be undertaken using methods that are conventional in the semiconductor fabrication art. Non-limiting examples are plasma etch methods and sputter etch methods. Desirable are sputter etch methods that use argon or nitrogen sputter etchants. Such sputter etchants desirably have a tendency to etch more from top surfaces than lower surfaces of the first stressed layer 24′ and the second stressed layer 30′ when forming the first stressed layer 24″ and the second stressed layer 30″.
  • Within the context of the instant embodiment and the invention, the abutment of the first stressed layer 24″ with the second stressed layer 30″ absent overlap thereof provides for enhanced manufacturability. The enhanced manufacturability is desirable under circumstances where overlapped portions of the first stressed layer 24′ and the second stressed layer 30′ are located over a contact region portion of a source/drain region, particularly when the source/drain region has a silicide layer thereupon.
  • FIG. 9 shows the results of etching remaining portions of the etch stop layer 26″ from the CMOS structure of FIG. 8. FIG. 9 also shows a capping layer 32 located upon the CMOS structure of FIG. 8 after etching remaining portions of the etch stop layer 26″. The remaining portions of the etch stop layer 26″ may be etched using a wet chemical etchant or a dry plasma etchant.
  • The capping layer 30 may comprise any of several capping materials. Included are oxides, nitrides and oxynitrides of silicon, as well as oxides, nitrides and oxynitrides of other elements. The capping layer 32 preferably comprises a silicon nitride material having a thickness from about 50 to about 100 angstroms.
  • FIG. 9 shows a CMOS structure in accordance with a first embodiment of the invention. The CMOS structure comprises complementary first stressed layer 24″ located upon first transistor T1 and second stressed layer 30″ located upon second transistor T2. The complementary first stressed layer 24″ and second stressed layer 30″ abut, but do not overlap at a location interposed between the first transistor T1 and the second transistor T2.
  • Since the complementary first stressed layer 24″ and second stressed layer 30″ abut, but do not overlap, the CMOS structure that is illustrated in FIG. 9 provides for enhanced manufacturability. The enhanced manufacturability results from a nominally level surface provided by the first stressed layer 24″ and the second stressed layer 30″ so that a contact via may be efficiently etched reaching a source/drain region 20 having a silicide layer 22 thereupon while not damaging the silicide layer 22.
  • FIG. 10 to FIG. 12 show a series of schematic cross-sectional diagrams illustrating the results of progressive stages in fabricating a CMOS structure in accordance with another embodiment of the invention. This other embodiment of the invention comprises a second embodiment of the invention.
  • FIG. 10 shows a CMOS structure that derives from the CMOS structure of FIG. 7 within the first embodiment. The CMOS structure of FIG. 10 however shows a blocking layer 34 located upon the CMOS structure of FIG. 7. A block mask 36 is located upon the blocking layer 34 and covering the first transistor T1. A block mask 36′ is located upon the blocking layer 34 and covering the second transistor T2.
  • The blocking layer 34 preferably comprises an oxide material under circumstances where the first stressed layer 24 and the second stressed layer 30 comprise nitride materials. The blocking layer 34 may be formed using methods and materials analogous, equivalent or identical to the methods and materials used for forming the etch stop layer 26. Typically, the blocking layer 34 has a thickness from about 300 to about 500 angstroms.
  • The block masks 36 and 36′ may comprise any of several block mask materials that are disclosed above for the block masks 28 and 28′.
  • FIG. 11 shows the results of further processing of the CMOS structure of FIG. 10. FIG. 11 shows the results of etching the blocking layer 34 to form blocking layers 34′ that straddle the first transistor T1 and the second transistor T2. In so doing, an abutted and overlapped portion of the first stressed layer 24′ and the second stressed layer 30′ is exposed. FIG. 11 also shows the results of stripping the block masks 36 and 36′.
  • FIG. 12 shows the results of further processing of the CMOS structure of FIG. 11. FIG. 12 shows the results of etching the first stressed layer 24′ and the second stressed layer 30′ to yield first stressed layer 24″ and second stressed layer 30″ that are abutted and do not overlap. The etching preferably uses a nitrogen or argon sputter etching as is disclosed above within the context of the first embodiment.
  • For reasons disclosed above within the context of the first embodiment, abutment absent overlap of the first stressed layer 24″ and the second stressed layer 30″ provides for enhanced manufacturability of the CMOS structure of FIG. 12.
  • Within the second embodiment, the use of the blocking layers 34′ also assist in preserving a full initial thicknesses of the first stressed layer 24″ and the second stressed layer 30″ at locations over the first transistor T1 and the second transistor T2. Thus, a full effect of stress from the first stressed layer 24″ and the second stressed layer 30″ is transmitted into respective semiconductor channels over which they are formed.
  • FIG. 13 to FIG. 15 show a series of schematic cross-sectional diagrams corresponding with FIG. 10 to FIG. 12, but where the block mask 36 is located over the first transistor T1 only, and not the second transistor T2. FIG. 13 to FIG. 15 comprise a third embodiment of the invention.
  • FIG. 16 to FIG. 18 show a series of schematic cross-sectional diagrams corresponding with FIG. 10 to FIG. 12 or FIG. 13 to FIG. 15, but where the block mask 36′ is located over the second transistor T2 only and not the first transistor T1. FIG. 16 to FIG. 18 comprise a fourth embodiment of the invention.
  • The processing for either FIG. 13 to FIG. 15 or FIG. 16 to FIG. 18 follows analogously from the processing of FIG. 10 to FIG. 12. However, due to the presence of only a single block mask 36 or 36′, only one of the first stressed layer 24″ (i.e., FIG. 15) and the second stressed layer 30″ (i.e., FIG. 18) has an initial thickness after sputter etching.
  • In each of the second embodiment of the invention that is illustrated in FIG. 10 to FIG. 12, the third embodiment of the invention that is illustrated in FIG. 13 to FIG. 15 and the fourth embodiment of the invention that is illustrated in FIG. 16 to FIG. 18, the first stressed layer 24′ that abuts and overlaps the second stressed layer 30′ are etched to form the first stressed layer 24″ and the second stressed layer 30″ that abut, but do not overlap.
  • In accordance with the first embodiment of the invention, the second embodiment, the third embodiment and the fourth embodiment provide for enhanced manufacturability of a CMOS structure due to the foregoing abutment absent overlap.
  • The preferred embodiments of the invention are illustrative of the invention rater than limiting of the invention. Revisions and modifications may be made to methods, materials, structures and dimensions of a CMOS structure or method for fabrication thereof in accordance with the preferred embodiments of the invention while still providing a CMOS structure in accordance with the invention, further in accordance with the accompanying claims.

Claims (12)

1. A CMOS structure comprising:
a first transistor of a first polarity located laterally separated from a second transistor of a second polarity different from the first polarity over a semiconductor substrate; and
a first stressed layer having a first stress located over the first transistor and a second stressed layer having a second stress different from the first stress located over the second transistor, where the first stressed layer and the second stressed layer abut and do not overlap.
2. The CMOS structure of claim 1 wherein:
the semiconductor substrate comprises a hybrid orientation substrate; and
the first transistor and the second transistor use different crystallographic orientation channel regions.
3. The CMOS structure of claim 1 wherein the first stressed layer and the second stressed layer abut, but do not overlap at a location over a source/drain region within one of the first transistor and the second transistor.
4. The CMOS structure of claim 3 further comprising a silicide layer located upon the source/drain region.
5. The CMOS structure of claim 1 wherein each of the first stressed layer and the second stressed layer comprises a nitride material.
6. The CMOS structure of claim 1 wherein:
the first stress is a tensile stress and the first transistor is an nFET; and
the second stress is a compressive stress and the second transistor in a pFET.
7. A method for fabricating a CMOS structure comprising:
forming a first transistor of a first polarity laterally separated from a second transistor of a second polarity different from the first polarity over a semiconductor substrate;
forming a first stressed layer having a first stress located over the first transistor and a second stressed layer having a second stress different from the first stress located over the second transistor, where the first stressed layer and the second stressed layer abut and overlap; and
etching at least one of the first stressed layer and the second stressed layer so that the first stressed layer and the second stressed layer abut and do not overlap.
8. The method of claim 7 wherein the forming the first transistor and the second transistor uses a hybrid orientation substrate that provides a different crystallographic orientation channel for each of the first transistor and the second transistor.
9. The method of claim 7 wherein each of the first stressed layer and the second stressed layer comprises a nitride material.
10. The method of claim 7 wherein:
the first stress is a tensile stress and the first transistor is an nFET; and
the second stress is a compressive stress and the second transistor in a pFET.
11. The method of claim 7 wherein the etching provides that the first stressed layer and the second stressed layer abut but do not overlap over a source/drain region within one of the first transistor and the second transistor.
12. The method of claim 7 wherein the etching of the first stressed layer and the second stressed layer is undertaken absent masking of the first stressed layer and the second stressed layer.
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