US20090121324A1 - Etch with striation control - Google Patents

Etch with striation control Download PDF

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Publication number
US20090121324A1
US20090121324A1 US12/349,142 US34914209A US2009121324A1 US 20090121324 A1 US20090121324 A1 US 20090121324A1 US 34914209 A US34914209 A US 34914209A US 2009121324 A1 US2009121324 A1 US 2009121324A1
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United States
Prior art keywords
computer readable
photoresist
readable code
photoresist features
sidewalls
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US12/349,142
Inventor
S. M. Reza Sadjadi
Peter Cirigliano
Ji Soo Kim
Zhisong Huang
Eric A. Hudson
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Lam Research Corp
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Lam Research Corp
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Publication date
Priority claimed from US11/076,087 external-priority patent/US7241683B2/en
Application filed by Lam Research Corp filed Critical Lam Research Corp
Priority to US12/349,142 priority Critical patent/US20090121324A1/en
Publication of US20090121324A1 publication Critical patent/US20090121324A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/949—Energy beam treating radiation resist on semiconductor

Definitions

  • the present invention relates to the formation of semiconductor devices.
  • features of the semiconductor device are defined in the wafer using well-known patterning and etching processes.
  • a photoresist (PR) material is deposited on the wafer and then is exposed to light filtered by a reticle.
  • the reticle is generally a glass plate that is patterned with exemplary feature geometries that block light from propagating through the reticle.
  • the light After passing through the reticle, the light contacts the surface of the photoresist material.
  • the light changes the chemical composition of the photoresist material such that a developer can remove a portion of the photoresist material.
  • the exposed regions are removed, and in the case of negative photoresist materials, the unexposed regions are removed.
  • the wafer is etched to remove the underlying material from the areas that are no longer protected by the photoresist material, and thereby define the desired features in the wafer.
  • a method for etching a feature in an etch layer is provided.
  • a patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys.
  • the striations of the sidewalls of the photoresist features are reduced.
  • the reducing the striations comprises at least one cycle, wherein each cycle comprises etching back peaks formed by the striations of the sidewalls of the photoresist features and depositing on the sidewalls of the photoresist features.
  • Features are etched into the etch layer through the photoresist features.
  • the photoresist mask is removed.
  • a method of etching features in an etch layer disposed below a patterned photoresist mask with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys is provided.
  • the striations of the sidewalls of the photoresist features are reduced comprising at least one cycle, wherein each cycle comprises providing a striation peak etch back gas, generating a plasma from the striation peak etch back gas, stopping the striation peak etch back gas, providing a photoresist feature sidewall deposition gas, generating a plasma from the photoresist feature sidewall deposition gas, and stopping the photoresist feature sidewall deposition gas.
  • the etch layer is etched.
  • the photoresist mask is removed.
  • an apparatus for etching a feature in an etch layer, below a photoresist mask with photoresist features with sidewalls with striations forming peaks and valleys comprising a chamber wall forming a plasma processing chamber enclosure, a substrate support for supporting a substrate within the plasma processing chamber enclosure, a pressure regulator for regulating the pressure in the plasma processing chamber enclosure, at least one electrode for providing power to the plasma processing chamber enclosure for sustaining a plasma, a gas inlet for providing gas into the plasma processing chamber enclosure, and a gas outlet for exhausting gas from the plasma processing chamber enclosure is provided.
  • a gas source is in fluid connection with the gas inlet, where the gas source comprises a striation peak etch back gas source, a photoresist feature sidewall deposition gas source, and an etch layer etch gas source.
  • a controller is controllably connected to the gas source and the at least one electrode. The controller comprises at least one processor and computer readable media.
  • the computer readable media comprises computer readable code for reducing the striations of the photoresist features, comprising a plurality of cycles, wherein each cycle comprises computer readable code for providing a striation peak etch back gas from the striation peak etch back gas source, computer readable code for generating a plasma from the striation peak etch back gas, computer readable code for stopping the striation peak etch back gas from the striation peak etch back gas source, computer readable code for providing a photoresist feature sidewall deposition gas from the photoresist feature sidewall deposition gas source, computer readable code for generating a plasma from the photoresist feature sidewall deposition gas, and computer readable code for stopping the photoresist feature sidewall deposition gas from the photoresist feature sidewall deposition gas.
  • the computer readable media further comprises computer readable code for etching the etch layer and computer readable code for removing the photoresist mask.
  • FIG. 1 is a high level flow chart of a process that may be used in an embodiment of the invention.
  • FIGS. 2A-I are schematic cross-sectional and top views of a stack processed according to an embodiment of the invention.
  • FIG. 3 is a more detailed flow chart of a step of reducing striation.
  • FIG. 4 is a schematic view of a plasma processing chamber that may be used in practicing the invention.
  • FIGS. 5A-B illustrate a computer system, which is suitable for implementing a controller used in embodiments of the present invention.
  • FIG. 1 is a high level flow chart of a process that may be used in an embodiment of the invention.
  • a patterned photoresist mask is provided (step 104 ).
  • FIG. 2A is a schematic cross-sectional view of a layer to be etched 208 over a substrate 204 , with a patterned photoresist mask 212 with photoresist features 214 , over an ARL 210 , over the layer 208 to be etched forming a stack 200 .
  • the photoresist mask has a photoresist feature critical dimension (CD), which may be the widest part of the width of the smallest possible feature.
  • CD photoresist feature critical dimension
  • a photoresist layer may be first formed over the layer to be etched.
  • FIG. 2B is a top view of the photoresist mask 212 .
  • manufacturing processes such as lithography, may cause the features 214 to be irregularly shaped.
  • the dotted line circles 216 illustrate the reticle pattern provided for the photoresist mask 212 .
  • the actual photoresist openings may have sidewalls with peaks 220 and valleys 224 , as shown. These peaks 220 and valleys 224 , which cause the irregular shape that deviates from the original reticle pattern, in this case a circle, and often extends for some length along the sidewall, are called striations.
  • the photoresist features have a diameter S p , as shown.
  • the photoresist features are enlarged (step 108 ).
  • the photoresist features are enlarged using a laterally etched so that spaces 224 in the photoresist features 214 have widths “‘S e ’ that are greater than the widths “S p ” of the photoresist features before the etch, as shown in FIG. 2C , which is a cross-sectional view of the stack after the photoresist features are enlarged.
  • FIG. 2D is a top view of the photoresist mask 212 of FIG. 2C .
  • a lateral etch is defined as an etch of sides of a mask which form features, wherein the lateral etch increases the size of the widths of the photoresist features.
  • such a lateral etch may be a trimming of the trench mask. Such lateral etches may also reduce the thickness of the mask.
  • the lateral etch does not etch the layer under the photoresist layer 212 .
  • An outer dotted line circle 217 indicates a target feature shape after the lateral etching.
  • Other embodiments of the invention do not enlarge the photoresist features or provide enlargement after the striation reduction.
  • the striations are reduced (step 112 ).
  • FIG. 3 is a more detailed flow chart of this step.
  • the reduction of the striations comprises at least one cycle of a cyclic process comprising the steps of etching back striation peaks and depositing on the sidewalls of the photoresist features.
  • FIG. 2E shows a top view of the photoresist layer 212 after an etching back of striation peaks 220 (step 304 ). Without being bound by theory, it is believed that certain etching recipes selectively etch the striation peaks. As shown in FIG. 2E , some of the striation peaks are reduced.
  • FIG. 2F shows a top view of the photoresist layer 212 after depositing on the sidewall (step 308 ).
  • FIG. 2G is a top view of the photoresist layer 212 after a plurality of cycles of etching back the striation peaks (step 304 ) and depositing on the sidewall (step 308 ). As shown, the striation peaks 220 are greatly reduced, and the striation valleys 224 are significantly filled, thus overall striations are significantly reduced.
  • Features 228 are then etched into the etch layer 208 through the photoresist mask 212 (step 116 ), as shown in FIG. 2H .
  • the photoresist mask 212 is then removed (step 120 ), as shown in FIG. 21 .
  • patterned photoresist layer is formed (step 104 ).
  • a substrate 204 , with the etch layer 208 , an ARC layer 210 , and a patterned photoresist mask 212 is placed in an etch chamber.
  • FIG. 4 is a schematic view of an processing chamber 400 that may be used for enlarging the photoresist features, reducing striations, etching, and stripping.
  • the plasma processing chamber 400 comprises confinement rings 402 , an upper electrode 404 , a lower electrode 408 , a gas source 410 , and an exhaust pump 420 .
  • the gas source 410 comprises a deposition gas source 412 and an etch back gas source 416 .
  • the gas source 410 may comprise additional gas sources, such as an etching gas source 418 .
  • the substrate 204 is positioned upon the lower electrode 408 .
  • the lower electrode 408 incorporates a suitable substrate chucking mechanism (e.g., electrostatic, mechanical clamping, or the like) for holding the substrate 204 .
  • the reactor top 428 incorporates the upper electrode 404 disposed immediately opposite the lower electrode 408 .
  • the upper electrode 404 , lower electrode 408 , and confinement rings 402 define the confined plasma volume. Gas is supplied to the confined plasma volume by the gas source 410 and is exhausted from the confined plasma volume through the confinement rings 402 and an exhaust port by the exhaust pump 420 .
  • a first RF source 444 is electrically connected to the upper electrode 404 .
  • a second RF source 448 is electrically connected to the lower electrode 408 .
  • Chamber walls 452 surround the confinement rings 402 , the upper electrode 404 , and the lower electrode 408 .
  • Both the first RF source 444 and the second RF source 448 may comprise a 27 MHz power source and a 2 MHz power source. Different combinations of connecting RF power to the electrode are possible. In the case of Lam Research Corporation's Dual Frequency Capacitive (DFC) System, made by LAM Research CorporationTM of Fremont, Calif., which may be used in a preferred embodiment of the invention, both the 27 MHz and 2 MHz power sources make up the second RF power source 448 connected to the lower electrode, and the upper electrode is grounded.
  • DFC Dual Frequency Capacitive
  • a controller 435 is controllably connected to the RF sources 444 , 448 , exhaust pump 420 , and the gas source 410 .
  • the DFC System would be used when the layer to be etched 208 is a dielectric layer, such as silicon oxide, organo silicate glass, or organic dielectric film.
  • FIGS. 5A and 5B illustrate a computer system 1300 , which is suitable for implementing a controller 435 used in embodiments of the present invention.
  • FIG. 5A shows one possible physical form of the computer system.
  • the computer system may have many physical forms ranging from an integrated circuit, a printed circuit board, and a small handheld device up to a huge super computer.
  • Computer system 1300 includes a monitor 1302 , a display 1304 , a housing 1306 , a disk drive 1308 , a keyboard 1310 , and a mouse 1312 .
  • Disk 1314 is a computer-readable medium used to transfer data to and from computer system 1300 .
  • FIG. 5B is an example of a block diagram for computer system 1300 . Attached to system bus 1320 is a wide variety of subsystems.
  • Processor(s) 1322 also referred to as central processing units, or CPUs
  • Memory 1324 includes random access memory (RAM) and read-only memory (ROM).
  • RAM random access memory
  • ROM read-only memory
  • RAM random access memory
  • ROM read-only memory
  • RAM random access memory
  • ROM read-only memory
  • a fixed disk 1326 is also coupled bi-directionally to CPU 1322 ; it provides additional data storage capacity and may also include any of the computer-readable media described below.
  • Fixed disk 1326 may be used to store programs, data, and the like and is typically a secondary storage medium (such as a hard disk) that is slower than primary storage. It will be appreciated that the information retained within fixed disk 1326 may, in appropriate cases, be incorporated in standard fashion as virtual memory in memory 1324 .
  • Removable disk 1314 may take the form of any of the computer-readable media described below.
  • CPU 1322 is also coupled to a variety of input/output devices, such as display 1304 , keyboard 1310 , mouse 1312 , and speakers 1330 .
  • an input/output device may be any of: video displays, track balls, mice, keyboards, microphones, touch-sensitive displays, transducer card readers, magnetic or paper tape readers, tablets, styluses, voice or handwriting recognizers, biometrics readers, or other computers.
  • CPU 1322 optionally may be coupled to another computer or telecommunications network using network interface 1340 . With such a network interface, it is contemplated that the CPU might receive information from the network, or might output information to the network in the course of performing the above-described method steps.
  • method embodiments of the present invention may execute solely upon CPU 1322 or may execute over a network such as the Internet in conjunction with a remote CPU that shares a portion of the processing.
  • embodiments of the present invention further relate to computer storage products with a computer-readable medium that have computer code thereon for performing various computer-implemented operations.
  • the media and computer code may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well known and available to those having skill in the computer software arts.
  • Examples of computer-readable media include, but are not limited to: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROMs and holographic devices; magneto-optical media such as floptical disks; and hardware devices that are specially configured to store and execute program code, such as application-specific integrated circuits (ASICs), programmable logic devices (PLDs) and ROM and RAM devices.
  • ASICs application-specific integrated circuits
  • PLDs programmable logic devices
  • Computer code examples include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter.
  • Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.
  • the photoresist mask features are enlarged (step 108 ).
  • Such an enlargement process would use, for example, an enlargement gas of at least one of CF 4 , H 2 , NF 3 , C x H y F z , and O 2 .
  • a recipe for mask feature enlargement provides an etch chamber or plasma processing chamber pressure of 1 to 300 mT. 50 to 800 Watts of power are supplied to the plasma processing chamber at 27 MHz. 0 to 200 sccm of CF 4 and 5 to 30 sccm of O2 are provided to the plasma processing chamber. More preferably, the pressure for laterally etching the mask is between 20-150 mT.
  • the striation is reduced (step 112 ).
  • An example recipe for the step of etching back striation peaks (step 304 ) provides a halogen (i.e. fluorine, bromine, chlorine) containing gas, such as 100 sccm CF 4 .
  • CF 4 is the only gas provided during the etch back.
  • a pressure of 20 mTorr is provided to the chamber.
  • the second RF source 448 provides 600 Watts at a frequency of 27 MHz and 0 Watts a frequency of 2 MHz.
  • step 308 An example of the step of depositing on the sidewalls (step 308 ) provides a flow of 150 sccm CH 3 F, 75 sccm N 2 , and 100 sccm Ar.
  • the pressure is set to 80 mTorr.
  • the substrate is maintained at a temperature of 20° C.
  • the second RF source 448 provides 400 Watts at a frequency of 27 MHz and 0 Watts a frequency of 2 MHz.
  • a layer to be etched is may be a conventional etch layer, such as SiN, SiC, an oxide, or low-k dielectric.
  • a conventional etch recipe may be used to etch the layer to be etched.
  • an oxygen ashing may be used.
  • the enlargement of the photoresist features, reduction of striations, and etching the features into the etch layer are done in situ in the same etch chamber, as shown.
  • the reducing the striation is performed over at least three cycles. More preferably, the reducing the striation is performed over at least five cycles.
  • the depositing provides a gas containing at least one of a hydrocarbon and fluorohydrocarbon causing the deposition of at least one of a hydrocarbon and fluorohydrocarbon on the sidewalls of the photoresist features.

Abstract

A method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striations of the sidewalls of the photoresist features are reduced. The reducing the striations comprises at least one cycle, wherein each cycle comprises etching back peaks formed by the striations of the sidewalls of the photoresist features and depositing on the sidewalls of the photoresist features. Features are etched into the etch layer through the photoresist features. The photoresist mask is removed.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional of U.S. patent application Ser. No. 11/223,363 entitled “Etch With Striation Control” filed on Sep. 9, 2005 by Sadjadi et al., which is a continuation-in-part of U.S. patent application Ser. No. 11/067,087 entitled “Stabilized Photoresist Structure For Etching Process,” by Hudson et al. filed Mar. 8, 2005, which are hereby incorporated by reference and from which priority under 35 U.S.C. § 120 is claimed.
    • BACKGROUND OF THE INVENTION
  • The present invention relates to the formation of semiconductor devices. During semiconductor wafer processing, features of the semiconductor device are defined in the wafer using well-known patterning and etching processes. In these processes, a photoresist (PR) material is deposited on the wafer and then is exposed to light filtered by a reticle. The reticle is generally a glass plate that is patterned with exemplary feature geometries that block light from propagating through the reticle.
  • After passing through the reticle, the light contacts the surface of the photoresist material. The light changes the chemical composition of the photoresist material such that a developer can remove a portion of the photoresist material. In the case of positive photoresist materials, the exposed regions are removed, and in the case of negative photoresist materials, the unexposed regions are removed. Thereafter, the wafer is etched to remove the underlying material from the areas that are no longer protected by the photoresist material, and thereby define the desired features in the wafer.
  • Problems that may be encountered during this process are striation and limitations on critical dimensions (CD).
    • SUMMARY OF THE INVENTION
  • To achieve the foregoing and in accordance with the purpose of the present invention a method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striations of the sidewalls of the photoresist features are reduced. The reducing the striations comprises at least one cycle, wherein each cycle comprises etching back peaks formed by the striations of the sidewalls of the photoresist features and depositing on the sidewalls of the photoresist features. Features are etched into the etch layer through the photoresist features. The photoresist mask is removed.
  • In another manifestation of the invention a method of etching features in an etch layer disposed below a patterned photoresist mask with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys is provided. The striations of the sidewalls of the photoresist features are reduced comprising at least one cycle, wherein each cycle comprises providing a striation peak etch back gas, generating a plasma from the striation peak etch back gas, stopping the striation peak etch back gas, providing a photoresist feature sidewall deposition gas, generating a plasma from the photoresist feature sidewall deposition gas, and stopping the photoresist feature sidewall deposition gas. The etch layer is etched. The photoresist mask is removed.
  • In another manifestation of the invention an apparatus for etching a feature in an etch layer, below a photoresist mask with photoresist features with sidewalls with striations forming peaks and valleys is provided. A plasma processing chamber, comprising a chamber wall forming a plasma processing chamber enclosure, a substrate support for supporting a substrate within the plasma processing chamber enclosure, a pressure regulator for regulating the pressure in the plasma processing chamber enclosure, at least one electrode for providing power to the plasma processing chamber enclosure for sustaining a plasma, a gas inlet for providing gas into the plasma processing chamber enclosure, and a gas outlet for exhausting gas from the plasma processing chamber enclosure is provided. A gas source is in fluid connection with the gas inlet, where the gas source comprises a striation peak etch back gas source, a photoresist feature sidewall deposition gas source, and an etch layer etch gas source. A controller is controllably connected to the gas source and the at least one electrode. The controller comprises at least one processor and computer readable media. The computer readable media comprises computer readable code for reducing the striations of the photoresist features, comprising a plurality of cycles, wherein each cycle comprises computer readable code for providing a striation peak etch back gas from the striation peak etch back gas source, computer readable code for generating a plasma from the striation peak etch back gas, computer readable code for stopping the striation peak etch back gas from the striation peak etch back gas source, computer readable code for providing a photoresist feature sidewall deposition gas from the photoresist feature sidewall deposition gas source, computer readable code for generating a plasma from the photoresist feature sidewall deposition gas, and computer readable code for stopping the photoresist feature sidewall deposition gas from the photoresist feature sidewall deposition gas. The computer readable media further comprises computer readable code for etching the etch layer and computer readable code for removing the photoresist mask.
  • These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
  • FIG. 1 is a high level flow chart of a process that may be used in an embodiment of the invention.
  • FIGS. 2A-I are schematic cross-sectional and top views of a stack processed according to an embodiment of the invention.
  • FIG. 3 is a more detailed flow chart of a step of reducing striation.
  • FIG. 4 is a schematic view of a plasma processing chamber that may be used in practicing the invention.
  • FIGS. 5A-B illustrate a computer system, which is suitable for implementing a controller used in embodiments of the present invention.
    •  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The present invention will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps and/or structures have not been described in detail in order to not unnecessarily obscure the present invention.
  • To facilitate understanding, FIG. 1 is a high level flow chart of a process that may be used in an embodiment of the invention. A patterned photoresist mask is provided (step 104). FIG. 2A is a schematic cross-sectional view of a layer to be etched 208 over a substrate 204, with a patterned photoresist mask 212 with photoresist features 214, over an ARL 210, over the layer 208 to be etched forming a stack 200. The photoresist mask has a photoresist feature critical dimension (CD), which may be the widest part of the width of the smallest possible feature. To provide the patterned photoresist mask, a photoresist layer may be first formed over the layer to be etched. Then the photoresist layer is patterned to form photoresist features with photoresist sidewalls. FIG. 2B is a top view of the photoresist mask 212. Generally, manufacturing processes, such as lithography, may cause the features 214 to be irregularly shaped. The dotted line circles 216 illustrate the reticle pattern provided for the photoresist mask 212. The actual photoresist openings may have sidewalls with peaks 220 and valleys 224, as shown. These peaks 220 and valleys 224, which cause the irregular shape that deviates from the original reticle pattern, in this case a circle, and often extends for some length along the sidewall, are called striations. The photoresist features have a diameter Sp, as shown.
  • The photoresist features are enlarged (step 108). In one example the photoresist features are enlarged using a laterally etched so that spaces 224 in the photoresist features 214 have widths “‘Se’ that are greater than the widths “Sp” of the photoresist features before the etch, as shown in FIG. 2C, which is a cross-sectional view of the stack after the photoresist features are enlarged. FIG. 2D is a top view of the photoresist mask 212 of FIG. 2C. In the specification and claims, a lateral etch is defined as an etch of sides of a mask which form features, wherein the lateral etch increases the size of the widths of the photoresist features. For a trench mask, such a lateral etch may be a trimming of the trench mask. Such lateral etches may also reduce the thickness of the mask. Preferably, the lateral etch does not etch the layer under the photoresist layer 212. An outer dotted line circle 217 indicates a target feature shape after the lateral etching. Other embodiments of the invention do not enlarge the photoresist features or provide enlargement after the striation reduction.
  • The striations are reduced (step 112). FIG. 3 is a more detailed flow chart of this step. As shown in FIG. 3, the reduction of the striations comprises at least one cycle of a cyclic process comprising the steps of etching back striation peaks and depositing on the sidewalls of the photoresist features. FIG. 2E shows a top view of the photoresist layer 212 after an etching back of striation peaks 220 (step 304). Without being bound by theory, it is believed that certain etching recipes selectively etch the striation peaks. As shown in FIG. 2E, some of the striation peaks are reduced.
  • FIG. 2F shows a top view of the photoresist layer 212 after depositing on the sidewall (step 308). FIG. 2G is a top view of the photoresist layer 212 after a plurality of cycles of etching back the striation peaks (step 304) and depositing on the sidewall (step 308). As shown, the striation peaks 220 are greatly reduced, and the striation valleys 224 are significantly filled, thus overall striations are significantly reduced.
  • Features 228 are then etched into the etch layer 208 through the photoresist mask 212 (step 116), as shown in FIG. 2H. The photoresist mask 212 is then removed (step 120), as shown in FIG. 21.
    • EXAMPLE
  • In an example of this process patterned photoresist layer is formed (step 104). A substrate 204, with the etch layer 208, an ARC layer 210, and a patterned photoresist mask 212 is placed in an etch chamber.
  • FIG. 4 is a schematic view of an processing chamber 400 that may be used for enlarging the photoresist features, reducing striations, etching, and stripping. The plasma processing chamber 400 comprises confinement rings 402, an upper electrode 404, a lower electrode 408, a gas source 410, and an exhaust pump 420. The gas source 410 comprises a deposition gas source 412 and an etch back gas source 416. The gas source 410 may comprise additional gas sources, such as an etching gas source 418. Within plasma processing chamber 400, the substrate 204 is positioned upon the lower electrode 408. The lower electrode 408 incorporates a suitable substrate chucking mechanism (e.g., electrostatic, mechanical clamping, or the like) for holding the substrate 204. The reactor top 428 incorporates the upper electrode 404 disposed immediately opposite the lower electrode 408. The upper electrode 404, lower electrode 408, and confinement rings 402 define the confined plasma volume. Gas is supplied to the confined plasma volume by the gas source 410 and is exhausted from the confined plasma volume through the confinement rings 402 and an exhaust port by the exhaust pump 420. A first RF source 444 is electrically connected to the upper electrode 404. A second RF source 448 is electrically connected to the lower electrode 408. Chamber walls 452 surround the confinement rings 402, the upper electrode 404, and the lower electrode 408. Both the first RF source 444 and the second RF source 448 may comprise a 27 MHz power source and a 2 MHz power source. Different combinations of connecting RF power to the electrode are possible. In the case of Lam Research Corporation's Dual Frequency Capacitive (DFC) System, made by LAM Research Corporation™ of Fremont, Calif., which may be used in a preferred embodiment of the invention, both the 27 MHz and 2 MHz power sources make up the second RF power source 448 connected to the lower electrode, and the upper electrode is grounded. A controller 435 is controllably connected to the RF sources 444, 448, exhaust pump 420, and the gas source 410. The DFC System would be used when the layer to be etched 208 is a dielectric layer, such as silicon oxide, organo silicate glass, or organic dielectric film.
  • FIGS. 5A and 5B illustrate a computer system 1300, which is suitable for implementing a controller 435 used in embodiments of the present invention. FIG. 5A shows one possible physical form of the computer system. Of course, the computer system may have many physical forms ranging from an integrated circuit, a printed circuit board, and a small handheld device up to a huge super computer. Computer system 1300 includes a monitor 1302, a display 1304, a housing 1306, a disk drive 1308, a keyboard 1310, and a mouse 1312. Disk 1314 is a computer-readable medium used to transfer data to and from computer system 1300.
  • FIG. 5B is an example of a block diagram for computer system 1300. Attached to system bus 1320 is a wide variety of subsystems. Processor(s) 1322 (also referred to as central processing units, or CPUs) are coupled to storage devices, including memory 1324. Memory 1324 includes random access memory (RAM) and read-only memory (ROM). As is well known in the art, ROM acts to transfer data and instructions uni-directionally to the CPU and RAM is used typically to transfer data and instructions in a bi-directional manner. Both of these types of memories may include any suitable of the computer-readable media described below. A fixed disk 1326 is also coupled bi-directionally to CPU 1322; it provides additional data storage capacity and may also include any of the computer-readable media described below. Fixed disk 1326 may be used to store programs, data, and the like and is typically a secondary storage medium (such as a hard disk) that is slower than primary storage. It will be appreciated that the information retained within fixed disk 1326 may, in appropriate cases, be incorporated in standard fashion as virtual memory in memory 1324. Removable disk 1314 may take the form of any of the computer-readable media described below.
  • CPU 1322 is also coupled to a variety of input/output devices, such as display 1304, keyboard 1310, mouse 1312, and speakers 1330. In general, an input/output device may be any of: video displays, track balls, mice, keyboards, microphones, touch-sensitive displays, transducer card readers, magnetic or paper tape readers, tablets, styluses, voice or handwriting recognizers, biometrics readers, or other computers. CPU 1322 optionally may be coupled to another computer or telecommunications network using network interface 1340. With such a network interface, it is contemplated that the CPU might receive information from the network, or might output information to the network in the course of performing the above-described method steps. Furthermore, method embodiments of the present invention may execute solely upon CPU 1322 or may execute over a network such as the Internet in conjunction with a remote CPU that shares a portion of the processing.
  • In addition, embodiments of the present invention further relate to computer storage products with a computer-readable medium that have computer code thereon for performing various computer-implemented operations. The media and computer code may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well known and available to those having skill in the computer software arts. Examples of computer-readable media include, but are not limited to: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROMs and holographic devices; magneto-optical media such as floptical disks; and hardware devices that are specially configured to store and execute program code, such as application-specific integrated circuits (ASICs), programmable logic devices (PLDs) and ROM and RAM devices. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.
  • The photoresist mask features are enlarged (step 108). Such an enlargement process would use, for example, an enlargement gas of at least one of CF4, H2, NF3, CxHyFz, and O2. In one example of a recipe for mask feature enlargement provides an etch chamber or plasma processing chamber pressure of 1 to 300 mT. 50 to 800 Watts of power are supplied to the plasma processing chamber at 27 MHz. 0 to 200 sccm of CF4 and 5 to 30 sccm of O2 are provided to the plasma processing chamber. More preferably, the pressure for laterally etching the mask is between 20-150 mT.
  • The striation is reduced (step 112). Using multiple cycles of the cycle shown in FIG. 3 An example recipe for the step of etching back striation peaks (step 304) provides a halogen (i.e. fluorine, bromine, chlorine) containing gas, such as 100 sccm CF4. In this example, CF4 is the only gas provided during the etch back. A pressure of 20 mTorr is provided to the chamber. The second RF source 448 provides 600 Watts at a frequency of 27 MHz and 0 Watts a frequency of 2 MHz.
  • An example of the step of depositing on the sidewalls (step 308) provides a flow of 150 sccm CH3F, 75 sccm N2, and 100 sccm Ar. The pressure is set to 80 mTorr. The substrate is maintained at a temperature of 20° C. The second RF source 448 provides 400 Watts at a frequency of 27 MHz and 0 Watts a frequency of 2 MHz.
  • Features are then etched into the etch layer (step 116). An example of a layer to be etched is may be a conventional etch layer, such as SiN, SiC, an oxide, or low-k dielectric. A conventional etch recipe may be used to etch the layer to be etched.
  • To remove the mask (step 120) an oxygen ashing may be used.
  • In a preferred embodiment of the invention, the enlargement of the photoresist features, reduction of striations, and etching the features into the etch layer are done in situ in the same etch chamber, as shown. Preferably, the reducing the striation is performed over at least three cycles. More preferably, the reducing the striation is performed over at least five cycles.
  • Preferably, the depositing provides a gas containing at least one of a hydrocarbon and fluorohydrocarbon causing the deposition of at least one of a hydrocarbon and fluorohydrocarbon on the sidewalls of the photoresist features.
  • While this invention has been described in terms of several preferred embodiments, there are alterations, permutations, and various substitute equivalents, which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations, and various substitute equivalents as fall within the true spirit and scope of the present invention.

Claims (21)

1-19. (canceled)
20. An apparatus for etching a feature in an etch layer, below a photoresist mask with photoresist features with sidewalls with striations forming peaks and valleys, comprising:
a plasma processing chamber, comprising:
a chamber wall forming a plasma processing chamber enclosure;
a substrate support for supporting a substrate within the plasma processing chamber enclosure;
a pressure regulator for regulating the pressure in the plasma processing chamber enclosure;
at least one electrode for providing power to the plasma processing chamber enclosure for sustaining a plasma;
a gas inlet for providing gas into the plasma processing chamber enclosure; and
a gas outlet for exhausting gas from the plasma processing chamber enclosure;
a gas source in fluid connection with the gas inlet, comprising;
a striation peak etch back gas source;
a photoresist feature sidewall deposition gas source; and
an etch layer etch gas source;
a controller controllably connected to the gas source and the at least one electrode, comprising:
at least one processor; and
computer readable media comprising:
computer readable code for reducing the striations of the photoresist features, comprising a plurality of cycles, wherein each cycle comprises:
computer readable code for etching back peaks formed by the striations, comprising:
computer readable code for providing a striation peak etch back gas from the striation peak etch back gas source;
computer readable code for generating a plasma from the striation peak etch back gas, wherein the plasma from the striation peak etch back gas etches peaks of the photoresist features to reduce striation; and
 computer readable code for stopping the striation peak etch back gas from the striation peak etch back gas source;
computer readable code for depositing on the sidewalls of the photoresist features, comprising:
computer readable code for providing a photoresist feature sidewall deposition gas from the photoresist feature sidewall deposition gas source;
computer readable code for generating a plasma from the photoresist feature sidewall deposition gas; and
computer readable code for stopping the photoresist feature sidewall deposition gas from the photoresist feature sidewall deposition gas;
computer readable code for etching the etch layer through the photoresist features; and
computer readable code for removing the photoresist mask.
21. The apparatus, as recited in claim 20, wherein the computer readable code for reducing the striations of the sidewalls comprises computer readable code for providing at least three cycles.
22. The apparatus, as recited in claim 21, wherein the computer readable code for etching back peaks selectively etches peaks formed by the striations of the side walls of the photoresist features.
23. The apparatus, as recited in claim 22, wherein the computer readable code for depositing on the sidewalls of the photoresist features fills valleys formed by the striations of the sidewalls of the photoresist features.
24. The apparatus, as recited in claim 23, wherein the striation peak etch back gas source comprises a halogen containing gas source.
25. The apparatus, as recited in claim 24, wherein the sidewall deposition gas source, comprises at least one of a hydrocarbon source or a hydrofluorocarbon source.
26. The apparatus, as recited in claim 25, further comprising computer readable code for laterally etching the photoresist features to enlarge the photoresist features before etching the etch layer.
27. The apparatus, as recited in claim 25, further comprising computer readable code for laterally etching the photoresist features to enlarge the photoresist features before reducing the striation.
28. The apparatus, as recited in claim 20, wherein the computer readable code for etching back peaks selectively etches peaks formed by the striations of the side walls of the photoresist features.
29. The apparatus, as recited in claim 20, wherein the computer readable code for depositing on the sidewalls of the photoresist features fills valleys formed by the striations of the sidewalls of the photoresist features.
30. The apparatus, as recited in claim 20, wherein the striation peak etch back gas source comprises a halogen containing gas source.
31. The apparatus, as recited in claim 20, wherein the sidewall deposition gas source, comprises at least one of a hydrocarbon source or a hydrofluorocarbon source.
32. The apparatus, as recited in claim 20, further comprising computer readable code for laterally etching the photoresist features to enlarge the photoresist features before etching the etch layer.
33. The apparatus, as recited in claim 20, further comprising computer readable code for laterally etching the photoresist features to enlarge the photoresist features before reducing the striation.
34. An apparatus for etching a feature in an etch layer, below a photoresist mask with photoresist features with sidewalls with striations forming peaks and valleys, comprising:
a plasma processing chamber, comprising:
a chamber wall forming a plasma processing chamber enclosure;
a substrate support for supporting a substrate within the plasma processing chamber enclosure;
a pressure regulator for regulating the pressure in the plasma processing chamber enclosure;
at least one electrode for providing power to the plasma processing chamber enclosure for sustaining a plasma;
a gas inlet for providing gas into the plasma processing chamber enclosure; and
a gas outlet for exhausting gas from the plasma processing chamber enclosure;
a gas source in fluid connection with the gas inlet, comprising;
a striation peak etch back gas source;
a photoresist feature sidewall deposition gas source; and
an etch layer etch gas source;
a controller controllably connected to the gas source and the at least one electrode, comprising:
at least one processor; and
computer readable media comprising:
computer readable code for reducing the striations of the photoresist features, comprising a plurality of cycles, wherein each cycle comprises:
computer readable code for etching back peaks formed by the striations; and
computer readable code for depositing on the sidewalls of the photoresist features;
computer readable code for etching the etch layer through the photoresist features; and
computer readable code for removing the photoresist mask.
35. The apparatus, as recited in claim 34, wherein the computer readable code for reducing the striations of the sidewalls comprises computer readable code for providing at least three cycles.
36. The apparatus, as recited in claim 34, wherein the computer readable code for reducing the striation selectively etches peaks formed by the striations of the side walls of the photoresist features.
37. The apparatus, as recited in claim 36, wherein the computer readable code for depositing on the sidewalls of the photoresist features fills valleys formed by the striations of the sidewalls of the photoresist features.
38. The apparatus, as recited in claim 34, wherein the striation peak etch back gas source comprises a halogen containing gas source.
39. A semiconductor device formed by the method, comprising:
forming a patterned photoresist mask over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys;
reducing the striations of the sidewalls of the photoresist features comprising at least one cycle, wherein each cycle comprises:
etching back peaks formed by the striations of the sidewalls of the photoresist features; and
depositing on the sidewalls of the photoresist features;
etching features into the etch layer through the photoresist features; and
removing the photoresist mask.
US12/349,142 2005-03-08 2009-01-06 Etch with striation control Abandoned US20090121324A1 (en)

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