US20090039476A1 - Apparatus and method for selectively recessing spacers on multi-gate devices - Google Patents
Apparatus and method for selectively recessing spacers on multi-gate devices Download PDFInfo
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- US20090039476A1 US20090039476A1 US12/287,319 US28731908A US2009039476A1 US 20090039476 A1 US20090039476 A1 US 20090039476A1 US 28731908 A US28731908 A US 28731908A US 2009039476 A1 US2009039476 A1 US 2009039476A1
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- 125000006850 spacer group Chemical group 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title abstract description 40
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 10
- 229910021332 silicide Inorganic materials 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 5
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical group [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052454 barium strontium titanate Inorganic materials 0.000 claims description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 claims description 2
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 claims description 2
- 229910052451 lead zirconate titanate Inorganic materials 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims 1
- 230000003628 erosive effect Effects 0.000 description 11
- 238000000151 deposition Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 6
- 229910018503 SF6 Inorganic materials 0.000 description 6
- 229910002091 carbon monoxide Inorganic materials 0.000 description 6
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 6
- 229960000909 sulfur hexafluoride Drugs 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 239000004215 Carbon black (E152) Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229930195733 hydrocarbon Natural products 0.000 description 3
- 150000002430 hydrocarbons Chemical class 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/90—MOSFET type gate sidewall insulating spacer
Definitions
- the field of invention relates generally to the field of semiconductor integrated circuit manufacturing and, more specifically but not exclusively, relates to CMOS (complementary metal oxide semiconductor) devices with a spacer on a first part of a multi-gate transistor and no spacer on a second part of the multi-gate transistor thereby increasing a transistor current.
- CMOS complementary metal oxide semiconductor
- MOSFET metal oxide semiconductor field effect transistor
- the source, channel, and drain structures are constructed adjacent to each other within the same plane.
- a gate dielectric is formed on the channel area and a gate electrode is deposited on the gate dielectric.
- the transistor is controlled by applying a voltage to the gate electrode, thereby allowing a current to flow through the channel between source and drain.
- the alternative method involves a construction of three dimensional MOSFETs, in the form of a multi-gate transistor such as a dual-gate field effect transistor (FinFET) or a tri-gate transistor, as a replacement for the conventional planar MOSFET.
- a multi-gate transistor such as a dual-gate field effect transistor (FinFET) or a tri-gate transistor
- Three-dimensional transistor designs such as the dual-gate FinFET and the tri-gate transistor allow tighter packing of the same number of transistors on a semiconductor chip by using vertical or angled surfaces for the gates.
- a tri-gate transistor comprises three equal length gates situated on three exposed surfaces of a body whereas a dual-gate transistor comprises two equal length gates situated along the sides of a narrow body.
- An overall contact resistance of the tri-gate transistor is a function of a contact resistance contributed by the top gate and a contact resistance contributed by each of the two side gates.
- the contact resistance at each gate is determined in part by the contact area of the source and drain, materials used at the interface of the source and drain regions, such as a silicide layer, and the manner in which those materials interface.
- the silicide layer may be formed on the source and drain regions for the top and side gates of a multi-gate transistor to reduce the contact resistance, thereby increasing a transistor current.
- the contact resistance can increase when a portion of the silicide material is blocked or is otherwise prevented from contacting a source or drain region.
- FIG. 1 is an illustration of a cross-sectional view of a multi-gate transistor after forming a first dielectric layer for a spacer.
- FIG. 2 illustrates the transistor in FIG. 1 after planarizing the first dielectric layer and exposing a top surface of a gate.
- FIG. 3 illustrates the transistor in FIG. 2 after eroding a portion of the first dielectric layer to expose a side surface of the gate.
- FIG. 4 illustrates the transistor in FIG. 3 after depositing a second dielectric layer for a spacer cap on the first dielectric layer.
- FIG. 5 illustrates the transistor of FIG. 4 after eroding a portion of the second dielectric layer to expose the top surface of the gate and to form the spacer cap on the first dielectric layer.
- FIG. 6 illustrates the transistor of FIG. 5 after eroding the first dielectric layer to expose a top surface and a side surface of a body.
- FIG. 7 illustrates the transistor of FIG. 6 after forming an epitaxial layer on the top surface and the side surface of the body.
- FIG. 7A is a cross-sectional view of the transistor of FIG. 7 taken through section line A-A of FIG. 7 . This view illustrates the formation of the epitaxial layer on a front surface and a back surface of the body.
- FIG. 8 illustrates the transistor of FIG. 7 after forming a silicide layer on the epitaxial layer on the top surface and the side surface of the body.
- FIG. 8A is a cross-sectional view of the transistor of FIG. 8 taken through section line A-A of FIG. 8 . This view illustrates the formation of a silicide layer on the epitaxial layer on the front surface and the back surface of the body.
- FIG. 9 is a flowchart describing one embodiment of a fabrication process used to form a spacer adjacent to a gate without forming a spacer adjacent to a body of a multi-gate transistor.
- FIG. 10 is a flowchart describing another embodiment of a fabrication process used to form a spacer adjacent to a gate without forming a spacer adjacent to a body of a multi-gate transistor.
- One embodiment of a method for fabricating a multi-gate transistor may comprise depositing a first dielectric or blanket layer for a spacer on a top surface and a side surface of a gate and a body.
- the first dielectric layer is planarized to expose the top surface of the gate.
- the first dielectric layer is eroded to reduce the thickness of the first dielectric layer and to expose the side surface of the gate.
- a second dielectric layer is deposited to create a spacer cap on the first dielectric, or blanket layer.
- the second dielectric layer is eroded to expose the top surface of the gate and to form the spacer cap on a portion of the first dielectric layer.
- the first dielectric layer is eroded to expose the top surface and the side surface of the body.
- the illustration in FIG. 1 is a cross-sectional view of a multi-gate transistor after depositing a first dielectric layer 110 on a gate 120 and a body 150 .
- the gate 120 may comprise a thin gate dielectric layer, a conductor such as doped or un-doped polysilicon, and a hard mask such as silicon nitride.
- the gate 120 may comprise at least one of a thin gate dielectric layer and a conductor such as tungsten, tantalum, titanium and/or nitrides and alloys thereof.
- the gate 120 may comprise at least one of a thin gate dielectric layer and a conductor comprising both doped or un-doped polysilicon and a metal such as tungsten, tantalum, titanium and/or nitrides and alloys thereof.
- the thin gate dielectric layer may comprise at least one of an oxide or a high-K layer.
- the high-K layer may comprise at least one of lanthanum oxide, tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, lead-zirconate-titanate, barium-strontium-titanate, or aluminum oxide.
- the body 150 may comprise silicon, gallium arsenide (GaAs), or indium antimonide (InSb).
- the body 150 may be formed from a monocrystalline substrate or from a silicon-on-insulator (SOI) layer.
- the first dielectric layer, or blanket layer 110 may comprise at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, or titanium oxide, but the embodiment is not so limited.
- the first dielectric layer 110 is deposited as a blanket layer on a top of the gate 130 , a side of the gate 140 , a top of the body 160 , and a side of the body 170 using methods known to persons having ordinary skill in the art, such as plasma enhanced chemical vapor deposition (PECVD), high density chemical vapor deposition (HDCVD), or sputtering.
- PECVD plasma enhanced chemical vapor deposition
- HDCVD high density chemical vapor deposition
- sputtering sputtering.
- the illustration in FIG. 2 depicts the transistor in FIG. 1 after planarizing the first dielectric layer 110 and exposing the top of the gate 130 .
- the first dielectric layer 110 is planarized, or polished using a process such as chemical mechanical planarization (CMP), though the embodiment is not so limited.
- CMP chemical mechanical planarization
- the planarization process erodes a top portion of the dielectric material to create a uniform surface while improving the optical resolution of subsequent lithography steps.
- the planarization process may be terminated by detecting the presence of the top of the gate 130 .
- FIG. 3 illustrates the transistor in FIG. 2 after eroding a portion of the first dielectric layer 110 to expose a side surface of the gate 140 .
- the portion of the first dielectric layer 110 is removed anisotropically, meaning that an etch rate in the direction normal to a surface is much higher than in a direction parallel to the surface.
- the portion of the first dielectric layer 110 may be eroded using sulfur hexafluoride (SF6), oxygen (O2), carbon monoxide (CO), and argon (Ar), or a fluorinated hydrocarbon (CHxFy) gas in a magnetically enhanced reactive ion etch (MERIE) or an electron cyclotron resonance (ECR) chamber or tool.
- SF6 sulfur hexafluoride
- O2 oxygen
- CO carbon monoxide
- Ar argon
- CHxFy fluorinated hydrocarbon
- MIE magnetically enhanced reactive ion etch
- ECR electron cyclotron resonance
- the portion of the first dielectric layer 110 is eroded isotropically, meaning that a rate of etching is substantially the same in any direction and largely non-directional, which is typical of a wet-etch process.
- the appropriate wet-etch process is selectively designed to erode the first dielectric layer 110 without significantly eroding the top of the gate 130 or the side of the gate 140 and may comprise a hydrous hydrofluoric (HF) solution, a buffered HF solution or a hot phosphoric acid (H3PO4) solution.
- HF hydrous hydrofluoric
- H3PO4 hot phosphoric acid
- FIG. 4 illustrates the transistor in FIG. 3 after depositing a second dielectric layer 410 for a spacer cap on the first dielectric layer 110 .
- the second dielectric layer 410 may comprise at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, or titanium oxide, but the embodiment is not so limited.
- the second dielectric layer 410 is deposited as a blanket layer on the gate 120 and the first dielectric layer 110 using methods known to persons having ordinary skill in the art, such as plasma enhanced chemical vapor deposition (PECVD), high density chemical vapor deposition (HDCVD), or sputtering.
- PECVD plasma enhanced chemical vapor deposition
- HDCVD high density chemical vapor deposition
- FIG. 5 illustrates the transistor of FIG. 4 after eroding a portion of the second dielectric layer 410 to expose the top surface of the gate 130 and to form a spacer cap on the first dielectric layer 110 .
- the second dielectric layer 410 is eroded anisotropically using a dry-etch process such as sulfur hexafluoride (SF6), oxygen (O2), carbon monoxide (CO), and argon (Ar), or a fluorinated hydrocarbon (CHxFy) gas in a MERIE or an ECR chamber or tool.
- SF6 sulfur hexafluoride
- O2 oxygen
- CO carbon monoxide
- Ar argon
- CHxFy fluorinated hydrocarbon
- a remaining portion of the second dielectric layer 410 will form a spacer cap on the side of the gate 140 and a top portion of the first dielectric layer 110 as a result of the erosion process, thereby shielding a top portion of the first dielectric layer 110 from subsequent anisotropic dry-etch processes.
- FIG. 6 illustrates the transistor of FIG. 5 after eroding the first dielectric layer 110 to expose the top of the body 160 and the side of the body 170 .
- the first dielectric layer 110 is eroded anisotropically using a dry-etch process such as sulfur hexafluoride (SF6), oxygen (O2), carbon monoxide (CO), and argon (Ar), or a fluorinated hydrocarbon (CHxFy) gas in a MERIE or an ECR chamber or tool.
- SF6 sulfur hexafluoride
- O2 oxygen
- CO carbon monoxide
- Ar argon
- CHxFy fluorinated hydrocarbon
- the process for eroding the first dielectric layer 110 is selectively designed to erode the first dielectric layer 110 without significantly eroding the second dielectric layer 410 or the top of the gate 130 , thereby exposing the top of the body 160 and the side of the body 170 while leaving a protective dielectric spacer on the side of the gate 140 .
- the dielectric spacer may be used to help shield the channel from subsequent ion implantation steps while also protecting the side of the gate 140 .
- FIG. 7 illustrates the transistor of FIG. 6 after forming an epitaxial layer 710 on the top of the body 160 and the side of the body 170 .
- the epitaxial layer 710 may be formed using a CVD chamber using a source gas such as silane, or by molecular beam epitaxy (MBE), though the embodiment is not limited in this respect.
- MBE molecular beam epitaxy
- FIG. 7A a cross-section through section line A-A of FIG. 7 , shows an embodiment with an epitaxial layer 710 formed on a front and a back of the body 150 .
- FIG. 8 illustrates the transistor of FIG. 7 after forming a silicide 810 on the epitaxial layer 710 .
- the silicide 810 may be formed on the exposed epitaxial layer 710 by depositing a metal such as titanium (Ti), cobalt (Co), nickel (Ni), or platinum (Pt) using a physical vapor deposition (PVD) technique or a chemical vapor deposition (CVD) technique, then etching, and heating with a subsequent high temperature process, although the scope of the embodiment is not limited in this respect.
- FIG. 8A is a cross-sectional illustration of section line A-A of FIG. 8 , which shows one embodiment of a silicide layer 810 formed on a front and a back of the body 150 and the epitaxial layer 710 .
- FIG. 9 is a flowchart describing one embodiment of a fabrication process used to form a spacer adjacent to a gate 120 without forming a spacer adjacent to a body 150 of a multi-gate transistor illustrated in FIG. 1 through FIG. 6 .
- the process may be initiated (element 900 ) by depositing a blanket layer 110 on a top of a body 160 , a side of a body 170 , a top of a gate 130 , and a side of the gate 140 .
- the blanket layer 110 is polished (element 910 ) to create a nearly planar surface and to expose the top of the gate 130 using methods known to one skilled in the art.
- the blanket layer 110 is then etched (element 920 ) to expose a top portion of the side of the gate 140 .
- the dielectric layer may be eroded by a dry-etch process.
- the dielectric material may be eroded using a wet-etch process or an ion milling process.
- a spacer cap is formed on the blanket layer 110 by first depositing a second dielectric layer 410 on the blanket layer 110 .
- the second dielectric layer 410 is then eroded to expose the top of the gate 130 and to form the spacer cap on the blanket layer 110 .
- the second dielectric layer 410 may be eroded by an anisotropic dry-etch process.
- the blanket layer 410 is further etched (element 940 ) to expose the top of the body 160 , the side of the body 170 , and the top of the gate 130 , while leaving a protective spacer adjacent to the side of the gate 140 .
- FIG. 1 through FIG. 6 were used as possible embodiments to help describe the method.
- FIG. 10 is a flowchart describing another embodiment of a fabrication process used to form a spacer adjacent to a gate 120 without forming a spacer adjacent to a body 150 of a multi-gate transistor illustrated in FIG. 1 through FIG. 6 .
- the process may be initiated (element 1000 ) by depositing a first dielectric layer 110 on a top of a body 160 and at least one side of a body 170 .
- the first dielectric layer 110 is then polished (element 1010 ) to create a nearly planar surface and to expose a top of the gate 130 .
- the first dielectric layer 110 is then eroded (element 1020 ) to expose a side of the gate 140 .
- the dielectric layer may be eroded by a dry-etch process.
- the dielectric material may be eroded using a wet-etch process or an ion milling process.
- a second dielectric layer 410 is deposited (element 1030 ) on the first dielectric layer 110 .
- the second dielectric layer 410 is then eroded (element 1040 ) to expose the top of the gate 130 and to form a spacer cap on the first dielectric layer 110 .
- the second dielectric layer 410 may be eroded by an anisotropic dry-etch process.
- the first dielectric layer 410 is further eroded (element 1050 ) to expose the top of the body 160 , the side of the body 170 , and the top of the gate 130 , while leaving a protective spacer adjacent to the side of the gate 140 .
- FIG. 1 through FIG. 6 were used as illustrations to help describe the method.
- terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the “top” surface of that substrate; the substrate may actually be in any orientation so that a “top” side of a substrate may be lower than the “bottom” side in a standard terrestrial frame of reference and still fall within the meaning of the term “top.”
- the term “on” as used herein does not indicate that a first layer “on” a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer.
- the embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations.
Abstract
Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed.
Description
- The field of invention relates generally to the field of semiconductor integrated circuit manufacturing and, more specifically but not exclusively, relates to CMOS (complementary metal oxide semiconductor) devices with a spacer on a first part of a multi-gate transistor and no spacer on a second part of the multi-gate transistor thereby increasing a transistor current.
- In a conventional metal oxide semiconductor field effect transistor (MOSFET), the source, channel, and drain structures are constructed adjacent to each other within the same plane. Typically, a gate dielectric is formed on the channel area and a gate electrode is deposited on the gate dielectric. The transistor is controlled by applying a voltage to the gate electrode, thereby allowing a current to flow through the channel between source and drain.
- An alternative to methods of building planar MOSFETs has been proposed to help alleviate some of the physical barriers to scaling down existing designs. The alternative method involves a construction of three dimensional MOSFETs, in the form of a multi-gate transistor such as a dual-gate field effect transistor (FinFET) or a tri-gate transistor, as a replacement for the conventional planar MOSFET.
- Three-dimensional transistor designs such as the dual-gate FinFET and the tri-gate transistor allow tighter packing of the same number of transistors on a semiconductor chip by using vertical or angled surfaces for the gates. A tri-gate transistor comprises three equal length gates situated on three exposed surfaces of a body whereas a dual-gate transistor comprises two equal length gates situated along the sides of a narrow body.
- An overall contact resistance of the tri-gate transistor is a function of a contact resistance contributed by the top gate and a contact resistance contributed by each of the two side gates. The contact resistance at each gate is determined in part by the contact area of the source and drain, materials used at the interface of the source and drain regions, such as a silicide layer, and the manner in which those materials interface. The silicide layer may be formed on the source and drain regions for the top and side gates of a multi-gate transistor to reduce the contact resistance, thereby increasing a transistor current. The contact resistance can increase when a portion of the silicide material is blocked or is otherwise prevented from contacting a source or drain region.
- The present invention is illustrated by way of example and not as a limitation in the figures of the accompanying drawings, in which
-
FIG. 1 is an illustration of a cross-sectional view of a multi-gate transistor after forming a first dielectric layer for a spacer. -
FIG. 2 illustrates the transistor inFIG. 1 after planarizing the first dielectric layer and exposing a top surface of a gate. -
FIG. 3 illustrates the transistor inFIG. 2 after eroding a portion of the first dielectric layer to expose a side surface of the gate. -
FIG. 4 illustrates the transistor inFIG. 3 after depositing a second dielectric layer for a spacer cap on the first dielectric layer. -
FIG. 5 illustrates the transistor ofFIG. 4 after eroding a portion of the second dielectric layer to expose the top surface of the gate and to form the spacer cap on the first dielectric layer. -
FIG. 6 illustrates the transistor ofFIG. 5 after eroding the first dielectric layer to expose a top surface and a side surface of a body. -
FIG. 7 illustrates the transistor ofFIG. 6 after forming an epitaxial layer on the top surface and the side surface of the body. -
FIG. 7A is a cross-sectional view of the transistor ofFIG. 7 taken through section line A-A ofFIG. 7 . This view illustrates the formation of the epitaxial layer on a front surface and a back surface of the body. -
FIG. 8 illustrates the transistor ofFIG. 7 after forming a silicide layer on the epitaxial layer on the top surface and the side surface of the body. -
FIG. 8A is a cross-sectional view of the transistor ofFIG. 8 taken through section line A-A ofFIG. 8 . This view illustrates the formation of a silicide layer on the epitaxial layer on the front surface and the back surface of the body. -
FIG. 9 is a flowchart describing one embodiment of a fabrication process used to form a spacer adjacent to a gate without forming a spacer adjacent to a body of a multi-gate transistor. -
FIG. 10 is a flowchart describing another embodiment of a fabrication process used to form a spacer adjacent to a gate without forming a spacer adjacent to a body of a multi-gate transistor. - An apparatus and method for increasing transistor current in a multi-gate device is disclosed in various embodiments. However, one skilled in the relevant art will recognize that the various embodiments may be practiced without one or more of the specific details, or with other replacement and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the invention. Nevertheless, the invention may be practiced without specific details. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
- Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention, but do not denote that they are present in every embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. Various additional layers and/or structures may be included and/or described features may be omitted in other embodiments.
- Various operations will be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the invention. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
- There is a general need for maximizing the available contact area for the source drain regions in a multi-gate transistor. By increasing the area of contact in the source and drain regions and reducing the overall contact resistance, the transistor current for the multi-gate transistor can be increased. One embodiment of a method for fabricating a multi-gate transistor may comprise depositing a first dielectric or blanket layer for a spacer on a top surface and a side surface of a gate and a body. The first dielectric layer is planarized to expose the top surface of the gate. The first dielectric layer is eroded to reduce the thickness of the first dielectric layer and to expose the side surface of the gate. A second dielectric layer is deposited to create a spacer cap on the first dielectric, or blanket layer. The second dielectric layer is eroded to expose the top surface of the gate and to form the spacer cap on a portion of the first dielectric layer. The first dielectric layer is eroded to expose the top surface and the side surface of the body.
- The illustration in
FIG. 1 is a cross-sectional view of a multi-gate transistor after depositing a firstdielectric layer 110 on agate 120 and abody 150. Thegate 120 may comprise a thin gate dielectric layer, a conductor such as doped or un-doped polysilicon, and a hard mask such as silicon nitride. In another embodiment, thegate 120 may comprise at least one of a thin gate dielectric layer and a conductor such as tungsten, tantalum, titanium and/or nitrides and alloys thereof. Alternatively, thegate 120 may comprise at least one of a thin gate dielectric layer and a conductor comprising both doped or un-doped polysilicon and a metal such as tungsten, tantalum, titanium and/or nitrides and alloys thereof. The thin gate dielectric layer may comprise at least one of an oxide or a high-K layer. The high-K layer may comprise at least one of lanthanum oxide, tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, lead-zirconate-titanate, barium-strontium-titanate, or aluminum oxide. Thebody 150 may comprise silicon, gallium arsenide (GaAs), or indium antimonide (InSb). Thebody 150 may be formed from a monocrystalline substrate or from a silicon-on-insulator (SOI) layer. - The first dielectric layer, or
blanket layer 110 may comprise at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, or titanium oxide, but the embodiment is not so limited. Thefirst dielectric layer 110 is deposited as a blanket layer on a top of thegate 130, a side of thegate 140, a top of thebody 160, and a side of thebody 170 using methods known to persons having ordinary skill in the art, such as plasma enhanced chemical vapor deposition (PECVD), high density chemical vapor deposition (HDCVD), or sputtering. - The illustration in
FIG. 2 depicts the transistor inFIG. 1 after planarizing thefirst dielectric layer 110 and exposing the top of thegate 130. Thefirst dielectric layer 110 is planarized, or polished using a process such as chemical mechanical planarization (CMP), though the embodiment is not so limited. The planarization process erodes a top portion of the dielectric material to create a uniform surface while improving the optical resolution of subsequent lithography steps. The planarization process may be terminated by detecting the presence of the top of thegate 130. -
FIG. 3 illustrates the transistor inFIG. 2 after eroding a portion of thefirst dielectric layer 110 to expose a side surface of thegate 140. In one embodiment, the portion of thefirst dielectric layer 110 is removed anisotropically, meaning that an etch rate in the direction normal to a surface is much higher than in a direction parallel to the surface. The portion of thefirst dielectric layer 110 may be eroded using sulfur hexafluoride (SF6), oxygen (O2), carbon monoxide (CO), and argon (Ar), or a fluorinated hydrocarbon (CHxFy) gas in a magnetically enhanced reactive ion etch (MERIE) or an electron cyclotron resonance (ECR) chamber or tool. In another embodiment, the portion of thefirst dielectric layer 110 is eroded isotropically, meaning that a rate of etching is substantially the same in any direction and largely non-directional, which is typical of a wet-etch process. The appropriate wet-etch process is selectively designed to erode thefirst dielectric layer 110 without significantly eroding the top of thegate 130 or the side of thegate 140 and may comprise a hydrous hydrofluoric (HF) solution, a buffered HF solution or a hot phosphoric acid (H3PO4) solution. -
FIG. 4 illustrates the transistor inFIG. 3 after depositing asecond dielectric layer 410 for a spacer cap on thefirst dielectric layer 110. Thesecond dielectric layer 410 may comprise at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, or titanium oxide, but the embodiment is not so limited. Thesecond dielectric layer 410 is deposited as a blanket layer on thegate 120 and thefirst dielectric layer 110 using methods known to persons having ordinary skill in the art, such as plasma enhanced chemical vapor deposition (PECVD), high density chemical vapor deposition (HDCVD), or sputtering. -
FIG. 5 illustrates the transistor ofFIG. 4 after eroding a portion of thesecond dielectric layer 410 to expose the top surface of thegate 130 and to form a spacer cap on thefirst dielectric layer 110. Thesecond dielectric layer 410 is eroded anisotropically using a dry-etch process such as sulfur hexafluoride (SF6), oxygen (O2), carbon monoxide (CO), and argon (Ar), or a fluorinated hydrocarbon (CHxFy) gas in a MERIE or an ECR chamber or tool. The dry-etch process may be terminated by using at least one of a timing mechanism or by sensing the presence of thefirst dielectric layer 110. A remaining portion of thesecond dielectric layer 410 will form a spacer cap on the side of thegate 140 and a top portion of thefirst dielectric layer 110 as a result of the erosion process, thereby shielding a top portion of thefirst dielectric layer 110 from subsequent anisotropic dry-etch processes. -
FIG. 6 illustrates the transistor ofFIG. 5 after eroding thefirst dielectric layer 110 to expose the top of thebody 160 and the side of thebody 170. Thefirst dielectric layer 110 is eroded anisotropically using a dry-etch process such as sulfur hexafluoride (SF6), oxygen (O2), carbon monoxide (CO), and argon (Ar), or a fluorinated hydrocarbon (CHxFy) gas in a MERIE or an ECR chamber or tool. The process for eroding thefirst dielectric layer 110 is selectively designed to erode thefirst dielectric layer 110 without significantly eroding thesecond dielectric layer 410 or the top of thegate 130, thereby exposing the top of thebody 160 and the side of thebody 170 while leaving a protective dielectric spacer on the side of thegate 140. The dielectric spacer may be used to help shield the channel from subsequent ion implantation steps while also protecting the side of thegate 140. -
FIG. 7 illustrates the transistor ofFIG. 6 after forming anepitaxial layer 710 on the top of thebody 160 and the side of thebody 170. Theepitaxial layer 710 may be formed using a CVD chamber using a source gas such as silane, or by molecular beam epitaxy (MBE), though the embodiment is not limited in this respect. The illustration ofFIG. 7A , a cross-section through section line A-A ofFIG. 7 , shows an embodiment with anepitaxial layer 710 formed on a front and a back of thebody 150. -
FIG. 8 illustrates the transistor ofFIG. 7 after forming asilicide 810 on theepitaxial layer 710. Thesilicide 810 may be formed on the exposedepitaxial layer 710 by depositing a metal such as titanium (Ti), cobalt (Co), nickel (Ni), or platinum (Pt) using a physical vapor deposition (PVD) technique or a chemical vapor deposition (CVD) technique, then etching, and heating with a subsequent high temperature process, although the scope of the embodiment is not limited in this respect.FIG. 8A is a cross-sectional illustration of section line A-A ofFIG. 8 , which shows one embodiment of asilicide layer 810 formed on a front and a back of thebody 150 and theepitaxial layer 710. -
FIG. 9 is a flowchart describing one embodiment of a fabrication process used to form a spacer adjacent to agate 120 without forming a spacer adjacent to abody 150 of a multi-gate transistor illustrated inFIG. 1 throughFIG. 6 . The process may be initiated (element 900) by depositing ablanket layer 110 on a top of abody 160, a side of abody 170, a top of agate 130, and a side of thegate 140. Theblanket layer 110 is polished (element 910) to create a nearly planar surface and to expose the top of thegate 130 using methods known to one skilled in the art. Theblanket layer 110 is then etched (element 920) to expose a top portion of the side of thegate 140. In one embodiment, the dielectric layer may be eroded by a dry-etch process. In another embodiment, the dielectric material may be eroded using a wet-etch process or an ion milling process. - After etching a portion of the
blanket layer 110, a spacer cap is formed on theblanket layer 110 by first depositing asecond dielectric layer 410 on theblanket layer 110. Thesecond dielectric layer 410 is then eroded to expose the top of thegate 130 and to form the spacer cap on theblanket layer 110. In one embodiment, thesecond dielectric layer 410 may be eroded by an anisotropic dry-etch process. - The
blanket layer 410 is further etched (element 940) to expose the top of thebody 160, the side of thebody 170, and the top of thegate 130, while leaving a protective spacer adjacent to the side of thegate 140.FIG. 1 throughFIG. 6 were used as possible embodiments to help describe the method. -
FIG. 10 is a flowchart describing another embodiment of a fabrication process used to form a spacer adjacent to agate 120 without forming a spacer adjacent to abody 150 of a multi-gate transistor illustrated inFIG. 1 throughFIG. 6 . The process may be initiated (element 1000) by depositing a firstdielectric layer 110 on a top of abody 160 and at least one side of abody 170. Thefirst dielectric layer 110 is then polished (element 1010) to create a nearly planar surface and to expose a top of thegate 130. Thefirst dielectric layer 110 is then eroded (element 1020) to expose a side of thegate 140. In one embodiment, the dielectric layer may be eroded by a dry-etch process. In another embodiment, the dielectric material may be eroded using a wet-etch process or an ion milling process. - After eroding the
first dielectric layer 110, asecond dielectric layer 410 is deposited (element 1030) on thefirst dielectric layer 110. Thesecond dielectric layer 410 is then eroded (element 1040) to expose the top of thegate 130 and to form a spacer cap on thefirst dielectric layer 110. In one embodiment, thesecond dielectric layer 410 may be eroded by an anisotropic dry-etch process. - The
first dielectric layer 410 is further eroded (element 1050) to expose the top of thebody 160, the side of thebody 170, and the top of thegate 130, while leaving a protective spacer adjacent to the side of thegate 140.FIG. 1 throughFIG. 6 were used as illustrations to help describe the method. - A plurality of embodiments of a multi-gate transistor with an increased area of contact in the source and drain regions, which allows for increased transistor current, have been described. The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the “top” surface of that substrate; the substrate may actually be in any orientation so that a “top” side of a substrate may be lower than the “bottom” side in a standard terrestrial frame of reference and still fall within the meaning of the term “top.” The term “on” as used herein (including in the claims) does not indicate that a first layer “on” a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations.
- Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
Claims (7)
1-13. (canceled)
14. A multi-gate semiconductor apparatus comprising:
a body having a top surface and side surfaces;
a gate formed on the top surface of the body;
a dielectric spacer formed on side surfaces of the gate;
a dielectric cap formed on a top surface of the dielectric spacer and adjacent to the side surfaces of the gate; and
an epitaxial layer formed on the top surface of the body and the side surfaces of the body.
15. The multi-gate semiconductor apparatus of claim 14 , further including a silicide layer formed on the epitaxial layer.
16. The multi-gate semiconductor apparatus of claim 14 , wherein the dielectric spacer is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, and titanium oxide.
17. The multi-gate semiconductor apparatus of claim 14 , wherein the gate comprises an oxide or a high-K gate dielectric layer.
18. The multi-gate semiconductor apparatus of claim 17 , wherein the high-K gate dielectric layer is selected from the group consisting of lanthanum oxide, tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, lead-zirconate-titanate, barium-strontium-titanate, and aluminum oxide.
19. The multi-gate semiconductor apparatus of claim 14 , wherein the body is selected from the group consisting of silicon, gallium-arsenide, and indium antimonide.
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