US20080277778A1 - Layer Transfer Process and Functionally Enhanced Integrated Circuits Products Thereby - Google Patents
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- US20080277778A1 US20080277778A1 US11/746,680 US74668007A US2008277778A1 US 20080277778 A1 US20080277778 A1 US 20080277778A1 US 74668007 A US74668007 A US 74668007A US 2008277778 A1 US2008277778 A1 US 2008277778A1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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Definitions
- the present invention relates to the three dimensional integration of circuit components into functionally enhanced structures using wafer-level layer transfer process based on the incorporation of added functional elements such as new wiring and placement schemes for interconnection of semiconductor components.
- BEOL back-end-of-the-line
- 3D integration and packaging techniques are being evaluated in the art.
- 3D wafer-scale integration is a relatively new technology and further investigations including methodologies for reliable etching, cleaning, filling, aligning, bonding integrity, wafer-scale planarity, and integration with active circuits still have to be demonstrated.
- 3D integration based on stacking of wafer-level device layers has been a main focus of 3D IC technology. This process includes fabrication of each component on a separate wafer with its optimized processing technology, followed by aligning, bonding, and vertical interconnection of the wafers to build a new high functionality system.
- the present invention pertains to the design, fabrication, and the resulting structures that enable enhanced functionality of semiconductor elements, such as devices and interconnects, using a judicious combination of sequential build up of layers and a layer transfer process. More specifically it overcomes the difficulties associated with the interconnect challenges arising form the continued push to increase the number of metalization layers with higher aspect ratio for many of the wiring levels, and related design issues, as it provides an enhanced 2D IC scheme (referred to hereafter as 2D+) based on wafer-level layer transfer process and a sequential layer wise build compatible with current CMOS technology.
- 2D+ enhanced 2D IC scheme
- this invention provides a supporting structure for integrated planar ICs for high frequency and high speed computing applications. It is further an object of this invention to leverage the know-how of the layer transfer technology to form a complete high density interconnect structure with integrated functional components such as ground connections/networks and power planes providing thermal and electrical “drops” or conducting elements. Finally, this invention provides a low cost of ownership scheme to create integrated structures with enhanced functionality by extending the art in existing semiconductor technology as it is based on wafer level technology.
- This invention is of wide applicability since it provides a technique and structure in which functional elements such as wiring levels are added in the form of networks or planes underneath a device layer, more particularly a semiconductor device layer. These added elements enable a new level of electrical as well as thermal components to be easily used to enhance CMOS and other technologies. Additional functional elements to enable MEMS, optoelectronics and biotechnology can also be added above or below the device layer to achieve hybrid multifunctional systems currently not feasible by conventional art of fabrication in CMOS technology.
- FIG. 1 Schematic diagram of a CMOS IC structure representing integrated front end of the line (FEOL) semiconductor device layers and back end of the line (BEOL) interconnect functional elements.
- FEOL front end of the line
- BEOL back end of the line
- FIG. 2 Schematic diagram of the novel 2D+ CMOS IC structure representing a design related to the present invention in which the functionality and performance of the structure shown in FIG. 1 is enhanced by placing functional elements on both sides of the semiconductor device layer.
- Functional elements illustrated are BEOL wiring elements, hence allowing for optimization of the signal routing, power distribution and clock signal distribution and the like to and from the device layer in the structure.
- FIG. 3 Schematic illustration of the current inventive process for the creation of the 2D+ CMOS IC with enhanced functionality shown after the following steps:
- FIG. 3 a Attachment of the carrier substrate to the original substrate with a CMOS structure including a semiconductor device layer and interconnect elements.
- FIG. 3 b Removal of the original Si substrate to expose the bottom surface of the device structures for further processing.
- FIG. 3 c Formation of the additional functional elements on the bottom side of the device layer to create sandwich-like interconnect element/device/functional element system.
- FIG. 3 d Attachment of a new foundation substrate to the bottom of the new structure.
- the foundation substrate is chosen according to the application to provide improved performance of the entire system.
- FIG. 3 e Optional parallel processing of elements in the foundation substrate and original substrate through the carrier substrate attachment step.
- FIG. 3 f Removal of the top carrier substrate to provide access to the interconnect elements to form input output means to connect with packaging elements.
- FIG. 3 g Optional thinning of a Si-based carrier substrate to create an interposer serving as a packaging component with added functionality.
- FIG. 4 Schematic representation of an inventive structure providing cooling and heat dissipation capabilities incorporated by transfer onto heat sink-based foundation substrate or substrate with heat-spreading components. Also shown is a Si-based carrier substrate on top of the upper functional element.
- the present invention is based on the creation of enhanced 2D CMOS IC structure with functional elements on both sides BEOL IC solution enables improved performance of this novel structure, adds functionality and simplifies processing issues related to multilevel builds by utilizing layer transfer and sequential layer wise build approaches as and where appropriate.
- CMOS technology structure (see FIG. 1 ) with its problems related to the via blockage, multi-layer wiring, etc., is transformed into an enhanced planar IC CMOS structure based on creation of a wiring scheme that is disposed on both sides of the device layer (see FIG. 2 ).
- FIG. 1 the structure illustrated in FIG. 1 which can be described as follows:
- the FEOL structure [ 110 ] is fabricated on the substrate [ 100 ] and interconnected on the top using BEOL levels [ 120 ].
- FEOL structure [ 110 ] would include the various transistors and the associated contact regions required for such devices.
- a transition region of local interconnects [ 111 ] to connect the device contacts [ 114 ] to the BEOL layers above [ 120 ] and surrounded by a passivation dielectric [ 112 ] is also usually present in these structures.
- the BEOL interconnection layer [ 120 ] further comprises metallic wiring [ 121 ] surrounded by dielectric insulation layers [ 122 , 123 , 124 ] which are preferably low in dielectric constant (low k).
- the FEOL region [ 110 ] especially for high performance applications may be built on a silicon-on-insulator (SOI) or other similar substrate in which an embedded layer [ 113 ] (such as oxide) may be implemented under the device region [ 110 ]. This structure is then interfaced with an appropriate package element [ 130 ]. Most often this connection between package carrier [ 131 ] and the chip is done via solder ball connections [ 132 ].
- interconnect element [ 240 ] in addition to the already described components in the above FIG. 1 structure, at least one additional functional element, in this case an interconnect element [ 240 ], is provided underneath the FEOL level [ 110 ].
- Interconnect element [ 240 ] can itself comprise many layers or components.
- element [ 240 ] can consist of metalized lines, and functional elements [ 241 ] embedded in an appropriate dielectric layer [ 242 ] disposed below the device region [ 110 ] and on top of the substrate [ 300 ], and separated from the substrate by a capping layer [ 243 ].
- FIG. 2 shows three metal levels of interconnection in the functional interconnect element [ 240 ] for the purpose of illustrating this idea but number and type of layers will depend on the application for which this 2D+ IC structure is intended.
- FIGS. 3 a through 3 d are schematic representations of the process utilized to create the structure shown in FIG. 2 .
- This process enables creation of the 2D+ IC CMOS structure using only prior art Si CMOS technology compatible processing steps while leveraging the benefits of selected layer transfer process steps.
- a CMOS structure is fabricated on a first substrate [ 100 ] and then attached to the carrier substrate [ 350 ].
- This original CMOS structure consists of Si substrate, a semiconductor device layer stack [ 110 ] and a first set of functional elements [ 120 ] which in the depicted example are BEOL interconnect elements which in turn are preferably terminated by a capping layer [ 133 ].
- the BEOL interconnect elements at least partially connect the circuits present in the semiconductor device layer [ 110 ].
- This entire structure is attached to a standard carrier wafer [ 352 ] such as Si or a glass wafer by means of bonding.
- a standard carrier wafer [ 352 ] such as Si or a glass wafer by means of bonding.
- Such bonding can be accomplished using fusion bonding (for example silicon oxide to silicon oxide) or by means of intermediate-layer bonding (for example using adhesives).
- the appropriate bonding material for such process [ 351 ] is included between the capping layer and the carrier.
- the first Si substrate [ 100 ] is removed to create a decal structure.
- a combination of polishing, grinding and wet etching techniques known in the art can be used to remove the first substrate [ 100 ].
- This process is followed by a formation of the second set of functional elements [ 240 ] on the newly exposed under side of the device layer to create a sandwich-like system, as presented in FIG. 3 c.
- a silicon-based carrier is the carrier substrate [ 350 ] of choice to enable convenient fabrication of the second set of functional elements using state of the art semiconductor fabrication tools.
- polyimide coated glass substrates can also be used, especially since their release process, such as laser ablation, is CMOS-compatible and has been successfully described in the prior art in many packaging applications.
- the second set of functional elements are shown as a wiring stack that completes the interconnection of the circuits in the semiconductor device layer [ 110 ].
- a foundation substrate [ 300 ] chosen according to the final application of the finished 2 d + component is attached to the bottom of the structure by bonding methods described previously (see FIG. 3 d ). More specifically such bonding could be done using direct bonding or by use of the capping layer [ 243 ] which can include needed adhesives.
- a parallel processing similar to the 3D assembly approach, can be utilized to shorten the overall fabrication time.
- the structure is created on substrate [ 100 ] (processes described in FIGS. 3 a to 3 b ) the elements on the foundation substrate [ 300 ] are also fabricated.
- the foundation substrate [ 300 ] is processed with the second functional elements [ 240 ] (built in the reverse order when compared to the FIG. 3 c build).
- This approach allows faster turn around for the fabrication of the parts but it may require different metalization schemes to provide the bonded electrical interconnection between the bottom side of the semiconductor device layer [ 110 ] and the second functional elements [ 240 ].
- metal contacts [ 244 ] are processed, and mated to contacts in a semiconductor device layer [ 110 ] and bonded. After bonding, the final structure will look the same as in the previously proposed schemes presented in FIG. 3 d. Due to the need to mate the interconnect layer stack [ 240 ], and in particular the contacts [ 244 ], to corresponding regions in the device element [ 110 ] a more stringent alignment methodology would be required for this embodiment as compared to the first embodiment. Thus there is a trade off between faster turn around time processing versus the requirement of tighter alignment tolerance and joining yields. The remaining steps of removing the carrier substrate and creation of input output connection on top are carried out as in the method described earlier.
- a separation process of the carrier has to be performed.
- the structure after such separation, and after the creation of input output means [ 132 ] and attachment to a packaging interface [ 131 ] is depicted in FIG. 3 f.
- the separation can be accomplished by a variety of processes, such as aforementioned laser releases of a glass substrate, mechanical grinding, etching or splitting etc of a silicon substrate.
- splitting can be accomplished using a tailored interface release layer (having a region with built-in internal stress) and application of ultrasonic waves, thermal stress, oxidation from the edge, insertion of solid wedge, or insertion of fluid wedge methods.
- a tailored interface release layer having a region with built-in internal stress
- FIGS. 3 f and 3 g show two possible end results of the functionally enhanced planar IC structures (2D+ ICs).
- FIG. 3 f shows the use of a current input output technology such as solder balls [ 132 ] to connect to the package interface [ 131 ].
- FIG. 3 g shows a structure made using layer transfer process to create a Si interposer [ 350 ], a specialized packaging interface with optimized I/O density, decoupling capacitors, and mechanical robustness for specific applications.
- FIG. 3 f depicts the structure obtained after removing the carrier wafer and providing a connection from the set of functional elements [ 120 ] to packaging component [ 131 ] by C 4 's or other interconnect elements [ 132 ].
- FIG. 3 g Schematic diagram of the functionally enhanced structure in FIG. 3 g is based on optional thinning of Si-based carrier substrate [ 350 ] of FIG. 3 d to create an interposer serving as a packaging component.
- substrate [ 350 ] is predisposed with integrated passive circuit elements [ 353 ] and through contact elements [ 354 ] for example before it is attached the original wafer [ 100 ] in the step shown in FIG. 3 a.
- Such elements can be fabricated, for example, using the prior art method described in U.S. Pat. No. 6,962,872 (the teaching of which is incorporated herein by reference) by some of the present authors.
- Another important aspect of the present inventive structure is that an increased functionality can be accomplished and new circuit design can be implemented providing optimized layout for local and global interconnects and hence assuring shorter clock wiring, faster routing paths for signal propagation, and allowing functional partitioning of the overall system.
- the new wiring layer underneath the device layer not only provides a new real estate for interconnects hence enabling higher wiring density but it also allows to redesign the wiring hierarchy as to optimize the functionality of the structure. Namely, repeaters, decoupling circuit elements, power and signal lines, can be better utilized as they can now be placed where they are most needed, i.e., closer to the devices or I/O elements.
- Another benefit from the implementation of such structure is the ability to create added level of ground connections or power planes.
- the function of the metal planes is to supply current and to provide the return paths for current in wires to the power distribution grids. Therefore the main advantage of being able to create a power network underneath the device layer is that it provides a predictable thermal and electrical propagation path through the regular patterns of “drops” or short vertical connections.
- Such metal planes can be made with application-specific dimensions creating power networks and can be incorporated with complementing decoupling components such as capacitors.
- Another embodiment of this invention relates to the heat dissipation or so called “power issues” of the multilayer system. Since the device layer will no longer be in very close proximity to the bulk of the Si substrate, local heating may be expected, and hence the second functional elements may be chosen to include cooling elements or heat spreading elements. In addition since the 2D+ IC structure is based on the layer transfer process such process can be repeated to bring in additional and different functional layers. Namely, additional layers of the heat-sink components can be readily incorporated into the process in the form of heat-dissipating layers, films with patterned thermal-vias, or even cooling-channels for incorporation of fluid or air-cooling systems.
- thermoelectric coolers may be added to the structure by the transfer process to provide local cooling of high power density regions. As depicted in FIG. 4 these elements may be incorporated in the bottom foundation substrate [ 300 ] or the upper silicon interposer [ 350 ]. Most importantly, the added functional components can be optimized to provide high electrical and heat conduction capabilities, namely metal embedded in the relatively good heat dissipating dielectric material can be utilized.
- This invention enables double-sided access to a semiconductor device layer by wafer-level layer transfer process.
- This type of structure was proposed since it uses processes compatible with current CMOS technology and it brings potential performance enhancements to a planar Ics by using selected aspects of 3D layer transfer process to create reliable and mechanically stable multi-layer IC structure. Integration of multifunctional structures with active, passive and interconnecting components is made possible by this invention.
- the concepts taught in the present invention can be used to add functionality to other 2D ICs without deviating from the spirit of the invention.
- the methods can be applied to future optoelectronic, MEMs or biotechnology device structures.
- the type of the material to create the layers can be replaced by other materials such as II-VI and III-V materials for optical components (example: gallium arsenide or indium phosphide) and organic materials, and should be selected according to the specific application.
- the functional carrier can be an integral part of complex multifunctional and mixed-technology systems or elements created at the wafer level.
Abstract
Description
- The present invention relates to the three dimensional integration of circuit components into functionally enhanced structures using wafer-level layer transfer process based on the incorporation of added functional elements such as new wiring and placement schemes for interconnection of semiconductor components.
- Interconnect challenges for future microprocessors and other high performance chips arise from the continued push to lower k-effective of interlevel dielectric materials, higher aspect ratio for all wiring levels, and increasing number of metalization layers. At this point the back-end-of-the-line (BEOL) consists of as many as ten metalization levels that contain wires to provide interconnections for signal, clock, power, repeaters, devices, decoupling elements, etc.
- Optimization of the microelectronic interconnects is critical for high performance, minimizing the energy dissipation, and maintaining a high level of signal integrity. However, as future interconnects shrink in dimension to allow gigascale integration, the signal delay and the signal fidelity problems associated with the interconnects become significant limiters of the overall system performance (e.g., maximum supportable chip clock frequencies or via blockage due to the need of a large number of vias to connect the multiplicity of wiring levels).
- Since changes in system architectures of the planar CMOS IC technology do not achieve a significant performance yield increase per year, and further increase of the number of the interconnect levels raises significant reliability questions, new solutions become a necessity if significant improvements of planar CMOS technology are to be achieved in future IC generations.
- Improved performance at a system level can also be achieved by changing the systems architecture. This solution comes at a high cost and is very time consuming as every new generation of products has to be redesigned and verified. Changes in architecture are difficult as they encompass a span of many critical building blocks including: memory and logic, routing, hierarchy, etc.
- Therefore, it has been realized that there will be a slow down in the rate of performance improvements for new generations relative to the famous Moore's law of microprocessors if one were to depend on planar architecture alone.
- To overcome the limitations of the fully planar integration schemes a variety of three-dimensional (3D) integration and packaging techniques are being evaluated in the art. The main considerations behind the use of 3D Integration are: minimization of the wire length, incorporation of new processes that are currently limited by conventional planar technology, and implementation of related design flexibility including new system architectures. All of which would allow significantly reduced interconnect delay as well as enable mixed system integration to increase both performance and functionality.
- At this point 3D wafer-scale integration is a relatively new technology and further investigations including methodologies for reliable etching, cleaning, filling, aligning, bonding integrity, wafer-scale planarity, and integration with active circuits still have to be demonstrated. 3D integration based on stacking of wafer-level device layers has been a main focus of 3D IC technology. This process includes fabrication of each component on a separate wafer with its optimized processing technology, followed by aligning, bonding, and vertical interconnection of the wafers to build a new high functionality system.
- The proposed 3D IC solutions show a great potential for future microprocessor generations. However the cost/benefit balance is likely to be favorable only for mature technology elements as in order to implement them in a 3D stacked IC solution reliability and high yields of individual elements along with very high bonding yields need to be realized. In addition, to fully utilize the capability of the 3D technology architectural changes at the micro and macro level of the system need to be implemented. Hence the time of clear insertion of 3D IC in the semiconductor technology road map is not well defined. Therefore, solutions in which some of the elements of the 3D integration schemes can be implemented with only small changes to the current ICs technology offerings to achieve performance and cost benefits are very desirable.
- The present invention pertains to the design, fabrication, and the resulting structures that enable enhanced functionality of semiconductor elements, such as devices and interconnects, using a judicious combination of sequential build up of layers and a layer transfer process. More specifically it overcomes the difficulties associated with the interconnect challenges arising form the continued push to increase the number of metalization layers with higher aspect ratio for many of the wiring levels, and related design issues, as it provides an enhanced 2D IC scheme (referred to hereafter as 2D+) based on wafer-level layer transfer process and a sequential layer wise build compatible with current CMOS technology.
- In particular, it is an object of this invention to provide a supporting structure for integrated planar ICs for high frequency and high speed computing applications. It is further an object of this invention to leverage the know-how of the layer transfer technology to form a complete high density interconnect structure with integrated functional components such as ground connections/networks and power planes providing thermal and electrical “drops” or conducting elements. Finally, this invention provides a low cost of ownership scheme to create integrated structures with enhanced functionality by extending the art in existing semiconductor technology as it is based on wafer level technology.
- This invention is of wide applicability since it provides a technique and structure in which functional elements such as wiring levels are added in the form of networks or planes underneath a device layer, more particularly a semiconductor device layer. These added elements enable a new level of electrical as well as thermal components to be easily used to enhance CMOS and other technologies. Additional functional elements to enable MEMS, optoelectronics and biotechnology can also be added above or below the device layer to achieve hybrid multifunctional systems currently not feasible by conventional art of fabrication in CMOS technology.
- These objects and the associated preferred embodiments are described in detail below along with illustrative figures listed herein.
- The inventions described herein are explained in more detail below with reference to the accompanying drawings, in which:
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FIG. 1 . Schematic diagram of a CMOS IC structure representing integrated front end of the line (FEOL) semiconductor device layers and back end of the line (BEOL) interconnect functional elements. -
FIG. 2 . Schematic diagram of the novel 2D+ CMOS IC structure representing a design related to the present invention in which the functionality and performance of the structure shown inFIG. 1 is enhanced by placing functional elements on both sides of the semiconductor device layer. Functional elements illustrated are BEOL wiring elements, hence allowing for optimization of the signal routing, power distribution and clock signal distribution and the like to and from the device layer in the structure. -
FIG. 3 . Schematic illustration of the current inventive process for the creation of the 2D+ CMOS IC with enhanced functionality shown after the following steps: -
FIG. 3 a. Attachment of the carrier substrate to the original substrate with a CMOS structure including a semiconductor device layer and interconnect elements. -
FIG. 3 b. Removal of the original Si substrate to expose the bottom surface of the device structures for further processing. -
FIG. 3 c. Formation of the additional functional elements on the bottom side of the device layer to create sandwich-like interconnect element/device/functional element system. -
FIG. 3 d. Attachment of a new foundation substrate to the bottom of the new structure. The foundation substrate is chosen according to the application to provide improved performance of the entire system. -
FIG. 3 e. Optional parallel processing of elements in the foundation substrate and original substrate through the carrier substrate attachment step. -
FIG. 3 f. Removal of the top carrier substrate to provide access to the interconnect elements to form input output means to connect with packaging elements. -
FIG. 3 g. Optional thinning of a Si-based carrier substrate to create an interposer serving as a packaging component with added functionality. -
FIG. 4 . Schematic representation of an inventive structure providing cooling and heat dissipation capabilities incorporated by transfer onto heat sink-based foundation substrate or substrate with heat-spreading components. Also shown is a Si-based carrier substrate on top of the upper functional element. - The present invention is based on the creation of enhanced 2D CMOS IC structure with functional elements on both sides BEOL IC solution enables improved performance of this novel structure, adds functionality and simplifies processing issues related to multilevel builds by utilizing layer transfer and sequential layer wise build approaches as and where appropriate.
- In the first embodiment of the present invention, a CMOS technology structure (see
FIG. 1 ) with its problems related to the via blockage, multi-layer wiring, etc., is transformed into an enhanced planar IC CMOS structure based on creation of a wiring scheme that is disposed on both sides of the device layer (seeFIG. 2 ). This is distinct from the structure illustrated inFIG. 1 which can be described as follows: InFIG. 1 the FEOL structure [110] is fabricated on the substrate [100] and interconnected on the top using BEOL levels [120]. FEOL structure [110] would include the various transistors and the associated contact regions required for such devices. A transition region of local interconnects [111] to connect the device contacts [114] to the BEOL layers above [120] and surrounded by a passivation dielectric [112] is also usually present in these structures. The BEOL interconnection layer [120] further comprises metallic wiring [121] surrounded by dielectric insulation layers [122, 123, 124] which are preferably low in dielectric constant (low k). The FEOL region [110] especially for high performance applications may be built on a silicon-on-insulator (SOI) or other similar substrate in which an embedded layer [113] (such as oxide) may be implemented under the device region [110]. This structure is then interfaced with an appropriate package element [130]. Most often this connection between package carrier [131] and the chip is done via solder ball connections [132]. - The Changes to this Structure Taught Under the Present Invention are as Follows:
- Upon completion of the proposed combination of the layer transfer process and additional sequential build process (detailed subsequently) the final structure of enhanced planar IC (2D+) is achieved. In this structure shown schematically in
FIG. 2 , in addition to the already described components in the aboveFIG. 1 structure, at least one additional functional element, in this case an interconnect element [240], is provided underneath the FEOL level [110]. Interconnect element [240] can itself comprise many layers or components. In other words, element [240] can consist of metalized lines, and functional elements [241] embedded in an appropriate dielectric layer [242] disposed below the device region [110] and on top of the substrate [300], and separated from the substrate by a capping layer [243]. The direct contact to the top device layer stack [110] is made though metal contacts [244].FIG. 2 shows three metal levels of interconnection in the functional interconnect element [240] for the purpose of illustrating this idea but number and type of layers will depend on the application for which this 2D+ IC structure is intended. -
FIGS. 3 a through 3 d are schematic representations of the process utilized to create the structure shown inFIG. 2 . This process enables creation of the 2D+ IC CMOS structure using only prior art Si CMOS technology compatible processing steps while leveraging the benefits of selected layer transfer process steps. Firstly, as shown in exemplary process beginning withFIG. 3 a, a CMOS structure is fabricated on a first substrate [100] and then attached to the carrier substrate [350]. This original CMOS structure consists of Si substrate, a semiconductor device layer stack [110] and a first set of functional elements [120] which in the depicted example are BEOL interconnect elements which in turn are preferably terminated by a capping layer [133]. In this case, the BEOL interconnect elements at least partially connect the circuits present in the semiconductor device layer [110]. This entire structure is attached to a standard carrier wafer [352] such as Si or a glass wafer by means of bonding. Such bonding can be accomplished using fusion bonding (for example silicon oxide to silicon oxide) or by means of intermediate-layer bonding (for example using adhesives). The appropriate bonding material for such process [351] is included between the capping layer and the carrier. - Secondly, as shown in
FIG. 3 b the first Si substrate [100] is removed to create a decal structure. A combination of polishing, grinding and wet etching techniques known in the art can be used to remove the first substrate [100]. This process is followed by a formation of the second set of functional elements [240] on the newly exposed under side of the device layer to create a sandwich-like system, as presented inFIG. 3 c. Taking into consideration the compatibility of silicon substrates with current IC technology and advances in silicon processing (for example lithography, autohandling in high throughput clusters tooling used in reactive etching or deposition, deep via patterning, thinning, and polishing), a silicon-based carrier is the carrier substrate [350] of choice to enable convenient fabrication of the second set of functional elements using state of the art semiconductor fabrication tools. However, polyimide coated glass substrates can also be used, especially since their release process, such as laser ablation, is CMOS-compatible and has been successfully described in the prior art in many packaging applications. In the exemplary illustration inFIG. 3 c, the second set of functional elements are shown as a wiring stack that completes the interconnection of the circuits in the semiconductor device layer [110]. Additional functions such as a power distribution, ground shielding, clock signal distribution and the like are also possible by appropriately designing and utilizing this second functional element. Once the processing of the second functional element [240] is accomplished, a foundation substrate [300] chosen according to the final application of the finished 2 d+ component is attached to the bottom of the structure by bonding methods described previously (seeFIG. 3 d). More specifically such bonding could be done using direct bonding or by use of the capping layer [243] which can include needed adhesives. - In one variant of the above process a parallel processing, similar to the 3D assembly approach, can be utilized to shorten the overall fabrication time. In this process, during the time the structure is created on substrate [100] (processes described in
FIGS. 3 a to 3 b) the elements on the foundation substrate [300] are also fabricated. As depicted inFIG. 3 e, in this case the foundation substrate [300] is processed with the second functional elements [240] (built in the reverse order when compared to theFIG. 3 c build). This approach allows faster turn around for the fabrication of the parts but it may require different metalization schemes to provide the bonded electrical interconnection between the bottom side of the semiconductor device layer [110] and the second functional elements [240]. For example, after the second functional elements are created on the foundation structure, metal contacts [244] are processed, and mated to contacts in a semiconductor device layer [110] and bonded. After bonding, the final structure will look the same as in the previously proposed schemes presented inFIG. 3 d. Due to the need to mate the interconnect layer stack [240], and in particular the contacts [244], to corresponding regions in the device element [110] a more stringent alignment methodology would be required for this embodiment as compared to the first embodiment. Thus there is a trade off between faster turn around time processing versus the requirement of tighter alignment tolerance and joining yields. The remaining steps of removing the carrier substrate and creation of input output connection on top are carried out as in the method described earlier. - To release the transferred layers from the carrier substrate [350], a separation process of the carrier has to be performed. The structure after such separation, and after the creation of input output means [132] and attachment to a packaging interface [131] is depicted in
FIG. 3 f. The separation can be accomplished by a variety of processes, such as aforementioned laser releases of a glass substrate, mechanical grinding, etching or splitting etc of a silicon substrate. In particular, splitting can be accomplished using a tailored interface release layer (having a region with built-in internal stress) and application of ultrasonic waves, thermal stress, oxidation from the edge, insertion of solid wedge, or insertion of fluid wedge methods. Ability to create a reliable release layer using splitting has been well studied in the art and some possible examples cited without attempting to be complete or exhaustive are: - 1) Smart-cut® method, based on use of heavy dose hydrogen implantation and a thermal cycle to release the region of the wafer below the implant zone (see for example, Smart-cut® METHOD: Auberton-Herue, Bruel, Aspar, Maleville, and Morieceau, “Smart-Cut®. The Basic Fabrication Process for UNIBOND® SOI Wafer”. IEEE TRANS ELECTRON Devices, March 1997.; U.S. Pat. No. 6,320,228 the teaching of which is incorporated herein by reference)
- 2) separation by implantation of other elements, such as boron, carbon, phosphorus, nitrogen, arsenic, or fluorine to create a mechanically weaker interface, see for example U.S. Pat. No. 6,150,239 the teaching of which is incorporated herein by reference.
- 3) Epitaxial Layer TRANsfer method (ELTRAN® or SOI-Epi wafer™ Technology) based on use of the porous Si layers to define the separation plane, as described in U.S. Pat. Nos. 6,140,209, 6,350,702, 6,121,112, 5,679,475, 5,856,229, 6,258,698, 6,309,945 the teaching of which is incorporated herein by reference) and in relation to the fabrication of semiconductor device such as thin-film crystalline solar cell (U.S. Pat. Nos. 6,211,038, 6,331,208, 6,190,937 the teaching of which is incorporated herein by reference), and the fabrication of semiconductor article utilizing few layers of porous Si (U.S. Pat. Nos. 6,306,729, 6,100,165 the teaching of which is incorporated herein by reference).
-
FIGS. 3 f and 3 g show two possible end results of the functionally enhanced planar IC structures (2D+ ICs).FIG. 3 f shows the use of a current input output technology such as solder balls [132] to connect to the package interface [131].FIG. 3 g shows a structure made using layer transfer process to create a Si interposer [350], a specialized packaging interface with optimized I/O density, decoupling capacitors, and mechanical robustness for specific applications. - More specifically, the schematic diagram in
FIG. 3 f depicts the structure obtained after removing the carrier wafer and providing a connection from the set of functional elements [120] to packaging component [131] by C4's or other interconnect elements [132]. - Schematic diagram of the functionally enhanced structure in
FIG. 3 g is based on optional thinning of Si-based carrier substrate [350] ofFIG. 3 d to create an interposer serving as a packaging component. In this case, substrate [350] is predisposed with integrated passive circuit elements [353] and through contact elements [354] for example before it is attached the original wafer [100] in the step shown inFIG. 3 a. Such elements can be fabricated, for example, using the prior art method described in U.S. Pat. No. 6,962,872 (the teaching of which is incorporated herein by reference) by some of the present authors. Incorporation of such a structure would enable integration of passive circuit elements [353], such as capacitors and resistors, within a close proximity to the relevant circuit elements on the chip. More specifically, such design overcomes difficulties associated with the slower access times of discrete passives mounted on the microelectronic chip packages. Such a solution provides a low inductance and low resistance integration of active circuit elements with passive components as described in U.S. Pat. No. 6,962,872 (the teaching of which is incorporated herein by reference). In addition, a silicon-based carrier allows a very high chip-to-chip wiring density (<5 micrometer pitch) interconnects to connect chips of different technologies using for example micro joint input/output contacts as described in the prior art patents U.S. Pat. Nos. 6,819,000, 6,661,098 and 6,732,908 (the teaching of which is incorporated herein by reference) held by the present assignee. The added functionality does not have to be limited to passive components only. By extension of this concept, other optical, mechanical, biochemical and electromechanical circuit elements can be formed on the surface (both top and bottom of the carrier) or in the body of the carrier improving its functionality. For example stacks of memory and logic components can be achieved, or digital, analog, and RF circuits can be placed on different layers. Optical interconnects or microfluidic channels can also be incorporated in this carrier. - Another important aspect of the present inventive structure is that an increased functionality can be accomplished and new circuit design can be implemented providing optimized layout for local and global interconnects and hence assuring shorter clock wiring, faster routing paths for signal propagation, and allowing functional partitioning of the overall system. For example, the new wiring layer underneath the device layer not only provides a new real estate for interconnects hence enabling higher wiring density but it also allows to redesign the wiring hierarchy as to optimize the functionality of the structure. Namely, repeaters, decoupling circuit elements, power and signal lines, can be better utilized as they can now be placed where they are most needed, i.e., closer to the devices or I/O elements.
- Another benefit from the implementation of such structure is the ability to create added level of ground connections or power planes. In the integrated circuit layouts the function of the metal planes is to supply current and to provide the return paths for current in wires to the power distribution grids. Therefore the main advantage of being able to create a power network underneath the device layer is that it provides a predictable thermal and electrical propagation path through the regular patterns of “drops” or short vertical connections. Such metal planes can be made with application-specific dimensions creating power networks and can be incorporated with complementing decoupling components such as capacitors.
- Another embodiment of this invention relates to the heat dissipation or so called “power issues” of the multilayer system. Since the device layer will no longer be in very close proximity to the bulk of the Si substrate, local heating may be expected, and hence the second functional elements may be chosen to include cooling elements or heat spreading elements. In addition since the 2D+ IC structure is based on the layer transfer process such process can be repeated to bring in additional and different functional layers. Namely, additional layers of the heat-sink components can be readily incorporated into the process in the form of heat-dissipating layers, films with patterned thermal-vias, or even cooling-channels for incorporation of fluid or air-cooling systems. Active cooling facilities such as thermoelectric coolers may be added to the structure by the transfer process to provide local cooling of high power density regions. As depicted in
FIG. 4 these elements may be incorporated in the bottom foundation substrate [300] or the upper silicon interposer [350]. Most importantly, the added functional components can be optimized to provide high electrical and heat conduction capabilities, namely metal embedded in the relatively good heat dissipating dielectric material can be utilized. - This invention enables double-sided access to a semiconductor device layer by wafer-level layer transfer process. This type of structure was proposed since it uses processes compatible with current CMOS technology and it brings potential performance enhancements to a planar Ics by using selected aspects of 3D layer transfer process to create reliable and mechanically stable multi-layer IC structure. Integration of multifunctional structures with active, passive and interconnecting components is made possible by this invention.
- Furthermore, the concepts taught in the present invention can be used to add functionality to other 2D ICs without deviating from the spirit of the invention. For example, the methods can be applied to future optoelectronic, MEMs or biotechnology device structures. In such cases, firstly the type of the material to create the layers can be replaced by other materials such as II-VI and III-V materials for optical components (example: gallium arsenide or indium phosphide) and organic materials, and should be selected according to the specific application. Secondly the functional carrier can be an integral part of complex multifunctional and mixed-technology systems or elements created at the wafer level.
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Cited By (215)
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---|---|---|---|---|
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US20120129301A1 (en) * | 2010-11-18 | 2012-05-24 | Monolithic 3D Inc. | System comprising a semiconductor device and structure |
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US8536023B2 (en) | 2010-11-22 | 2013-09-17 | Monolithic 3D Inc. | Method of manufacturing a semiconductor device and structure |
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US8574929B1 (en) | 2012-11-16 | 2013-11-05 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US8581349B1 (en) | 2011-05-02 | 2013-11-12 | Monolithic 3D Inc. | 3D memory semiconductor device and structure |
US8642416B2 (en) | 2010-07-30 | 2014-02-04 | Monolithic 3D Inc. | Method of forming three dimensional integrated circuit devices using layer transfer technique |
US8669778B1 (en) | 2009-04-14 | 2014-03-11 | Monolithic 3D Inc. | Method for design and manufacturing of a 3D semiconductor device |
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US8709880B2 (en) | 2010-07-30 | 2014-04-29 | Monolithic 3D Inc | Method for fabrication of a semiconductor device and structure |
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US8803206B1 (en) | 2012-12-29 | 2014-08-12 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US20140240944A1 (en) * | 2013-02-25 | 2014-08-28 | Analog Devices Technology | Insulating low signal loss substrate, integrated circuits including a non-silicon substrate and methods of manufacture of integrated circuits |
US8901613B2 (en) | 2011-03-06 | 2014-12-02 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
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US9029173B2 (en) | 2011-10-18 | 2015-05-12 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US9099526B2 (en) | 2010-02-16 | 2015-08-04 | Monolithic 3D Inc. | Integrated circuit device and structure |
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US9117749B1 (en) | 2013-03-15 | 2015-08-25 | Monolithic 3D Inc. | Semiconductor device and structure |
US9197804B1 (en) | 2011-10-14 | 2015-11-24 | Monolithic 3D Inc. | Semiconductor and optoelectronic devices |
US9219005B2 (en) | 2011-06-28 | 2015-12-22 | Monolithic 3D Inc. | Semiconductor system and device |
CN105190875A (en) * | 2013-03-13 | 2015-12-23 | 英特尔公司 | Methods of forming under device interconnect structures |
US20160214855A1 (en) * | 2015-01-28 | 2016-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device and method for protecting feol element and beol element |
US9509313B2 (en) | 2009-04-14 | 2016-11-29 | Monolithic 3D Inc. | 3D semiconductor device |
US20160379943A1 (en) * | 2015-06-25 | 2016-12-29 | Skyworks Solutions, Inc. | Method and apparatus for high performance passive-active circuit integration |
KR20170016325A (en) * | 2014-06-16 | 2017-02-13 | 인텔 코포레이션 | Metal on both sides with clock gated power and signal routing underneath |
US9577642B2 (en) | 2009-04-14 | 2017-02-21 | Monolithic 3D Inc. | Method to form a 3D semiconductor device |
US20170084647A1 (en) * | 2009-11-30 | 2017-03-23 | Sony Corporation | Method of manufacturing bonded substrate, bonded substrate, method of manufacturing solid-state imaging apparatus, solid-state imaging apparatus, and camera |
WO2017111775A1 (en) * | 2015-12-23 | 2017-06-29 | Intel Corporation | Back-end repeater element integration techniques |
US9711407B2 (en) | 2009-04-14 | 2017-07-18 | Monolithic 3D Inc. | Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer |
US20170338150A1 (en) * | 2013-03-15 | 2017-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for Hybrid Wafer Bonding Integrated with CMOS Processing |
US20170372983A1 (en) * | 2016-06-27 | 2017-12-28 | Newport Fab, Llc Dba Jazz Semiconductor | Thermally Conductive and Electrically Isolating Layers in Semiconductor Structures |
US9871034B1 (en) | 2012-12-29 | 2018-01-16 | Monolithic 3D Inc. | Semiconductor device and structure |
US9953925B2 (en) | 2011-06-28 | 2018-04-24 | Monolithic 3D Inc. | Semiconductor system and device |
US9966301B2 (en) * | 2016-06-27 | 2018-05-08 | New Fab, LLC | Reduced substrate effects in monolithically integrated RF circuits |
US10043781B2 (en) | 2009-10-12 | 2018-08-07 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US20180269105A1 (en) * | 2017-03-15 | 2018-09-20 | Globalfoundries Singapore Pte. Ltd. | Bonding of iii-v-and-si substrates with interconnect metal layers |
US10115663B2 (en) | 2012-12-29 | 2018-10-30 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10127344B2 (en) | 2013-04-15 | 2018-11-13 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US10157909B2 (en) | 2009-10-12 | 2018-12-18 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10217667B2 (en) | 2011-06-28 | 2019-02-26 | Monolithic 3D Inc. | 3D semiconductor device, fabrication method and system |
US10224279B2 (en) | 2013-03-15 | 2019-03-05 | Monolithic 3D Inc. | Semiconductor device and structure |
US10290682B2 (en) | 2010-10-11 | 2019-05-14 | Monolithic 3D Inc. | 3D IC semiconductor device and structure with stacked memory |
US10297586B2 (en) | 2015-03-09 | 2019-05-21 | Monolithic 3D Inc. | Methods for processing a 3D semiconductor device |
US10325651B2 (en) | 2013-03-11 | 2019-06-18 | Monolithic 3D Inc. | 3D semiconductor device with stacked memory |
US10354995B2 (en) | 2009-10-12 | 2019-07-16 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US10366970B2 (en) | 2009-10-12 | 2019-07-30 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10381328B2 (en) | 2015-04-19 | 2019-08-13 | Monolithic 3D Inc. | Semiconductor device and structure |
US10388568B2 (en) | 2011-06-28 | 2019-08-20 | Monolithic 3D Inc. | 3D semiconductor device and system |
US10388863B2 (en) | 2009-10-12 | 2019-08-20 | Monolithic 3D Inc. | 3D memory device and structure |
US10418369B2 (en) | 2015-10-24 | 2019-09-17 | Monolithic 3D Inc. | Multi-level semiconductor memory device and structure |
US10497713B2 (en) | 2010-11-18 | 2019-12-03 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US10515981B2 (en) | 2015-09-21 | 2019-12-24 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with memory |
US10522225B1 (en) | 2015-10-02 | 2019-12-31 | Monolithic 3D Inc. | Semiconductor device with non-volatile memory |
WO2020018847A1 (en) * | 2018-07-19 | 2020-01-23 | Psemi Corporation | High-q integrated circuit inductor structure and methods |
US10573674B2 (en) | 2018-07-19 | 2020-02-25 | Psemi Corporation | SLT integrated circuit capacitor structure and methods |
US10580903B2 (en) | 2018-03-13 | 2020-03-03 | Psemi Corporation | Semiconductor-on-insulator transistor with improved breakdown characteristics |
US10600657B2 (en) | 2012-12-29 | 2020-03-24 | Monolithic 3D Inc | 3D semiconductor device and structure |
US10600888B2 (en) | 2012-04-09 | 2020-03-24 | Monolithic 3D Inc. | 3D semiconductor device |
US10651054B2 (en) | 2012-12-29 | 2020-05-12 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10658386B2 (en) | 2018-07-19 | 2020-05-19 | Psemi Corporation | Thermal extraction of single layer transfer integrated circuits |
US10679977B2 (en) | 2010-10-13 | 2020-06-09 | Monolithic 3D Inc. | 3D microdisplay device and structure |
US10777636B1 (en) | 2019-06-12 | 2020-09-15 | Psemi Corporation | High density IC capacitor structure |
US10825779B2 (en) | 2015-04-19 | 2020-11-03 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10833108B2 (en) | 2010-10-13 | 2020-11-10 | Monolithic 3D Inc. | 3D microdisplay device and structure |
US10840239B2 (en) | 2014-08-26 | 2020-11-17 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10847540B2 (en) | 2015-10-24 | 2020-11-24 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US10892016B1 (en) | 2019-04-08 | 2021-01-12 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US10892169B2 (en) | 2012-12-29 | 2021-01-12 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10896931B1 (en) | 2010-10-11 | 2021-01-19 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10903089B1 (en) | 2012-12-29 | 2021-01-26 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10910364B2 (en) | 2009-10-12 | 2021-02-02 | Monolitaic 3D Inc. | 3D semiconductor device |
US10943934B2 (en) | 2010-10-13 | 2021-03-09 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US10978501B1 (en) | 2010-10-13 | 2021-04-13 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with waveguides |
US10998374B1 (en) | 2010-10-13 | 2021-05-04 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US11004694B1 (en) | 2012-12-29 | 2021-05-11 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11004719B1 (en) | 2010-11-18 | 2021-05-11 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11011507B1 (en) | 2015-04-19 | 2021-05-18 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11018156B2 (en) | 2019-04-08 | 2021-05-25 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11018042B1 (en) | 2010-11-18 | 2021-05-25 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11018191B1 (en) | 2010-10-11 | 2021-05-25 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11018133B2 (en) | 2009-10-12 | 2021-05-25 | Monolithic 3D Inc. | 3D integrated circuit |
US11018116B2 (en) | 2012-12-22 | 2021-05-25 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11024673B1 (en) | 2010-10-11 | 2021-06-01 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11031275B2 (en) | 2010-11-18 | 2021-06-08 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11030371B2 (en) | 2013-04-15 | 2021-06-08 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11031394B1 (en) | 2014-01-28 | 2021-06-08 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11043523B1 (en) | 2010-10-13 | 2021-06-22 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US11056468B1 (en) | 2015-04-19 | 2021-07-06 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11063024B1 (en) | 2012-12-22 | 2021-07-13 | Monlithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11063071B1 (en) | 2010-10-13 | 2021-07-13 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with waveguides |
US11087995B1 (en) | 2012-12-29 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11088130B2 (en) | 2014-01-28 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11088050B2 (en) | 2012-04-09 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device with isolation layers |
US11094576B1 (en) | 2010-11-18 | 2021-08-17 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11107808B1 (en) | 2014-01-28 | 2021-08-31 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11107721B2 (en) | 2010-11-18 | 2021-08-31 | Monolithic 3D Inc. | 3D semiconductor device and structure with NAND logic |
US11114427B2 (en) | 2015-11-07 | 2021-09-07 | Monolithic 3D Inc. | 3D semiconductor processor and memory device and structure |
US11114464B2 (en) | 2015-10-24 | 2021-09-07 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11121021B2 (en) | 2010-11-18 | 2021-09-14 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11133344B2 (en) | 2010-10-13 | 2021-09-28 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US11158652B1 (en) | 2019-04-08 | 2021-10-26 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11158674B2 (en) | 2010-10-11 | 2021-10-26 | Monolithic 3D Inc. | Method to produce a 3D semiconductor device and structure |
US11164898B2 (en) | 2010-10-13 | 2021-11-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US11164811B2 (en) | 2012-04-09 | 2021-11-02 | Monolithic 3D Inc. | 3D semiconductor device with isolation layers and oxide-to-oxide bonding |
US11163112B2 (en) | 2010-10-13 | 2021-11-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with electromagnetic modulators |
US11164770B1 (en) | 2010-11-18 | 2021-11-02 | Monolithic 3D Inc. | Method for producing a 3D semiconductor memory device and structure |
US11177140B2 (en) | 2012-12-29 | 2021-11-16 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11211279B2 (en) | 2010-11-18 | 2021-12-28 | Monolithic 3D Inc. | Method for processing a 3D integrated circuit and structure |
US11217565B2 (en) | 2012-12-22 | 2022-01-04 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11227897B2 (en) | 2010-10-11 | 2022-01-18 | Monolithic 3D Inc. | Method for producing a 3D semiconductor memory device and structure |
US11251149B2 (en) | 2016-10-10 | 2022-02-15 | Monolithic 3D Inc. | 3D memory device and structure |
US11257741B2 (en) * | 2019-05-28 | 2022-02-22 | Samsung Electronics Co., Ltd. | Semiconductor package |
US11257867B1 (en) | 2010-10-11 | 2022-02-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with oxide bonds |
US11270055B1 (en) | 2013-04-15 | 2022-03-08 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US20220093571A1 (en) * | 2019-09-12 | 2022-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside contact for thermal displacement in a multi-wafer stacked integrated circuit |
US11296106B2 (en) | 2019-04-08 | 2022-04-05 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11296115B1 (en) | 2015-10-24 | 2022-04-05 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11309292B2 (en) | 2012-12-22 | 2022-04-19 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11315980B1 (en) | 2010-10-11 | 2022-04-26 | Monolithic 3D Inc. | 3D semiconductor device and structure with transistors |
US11327227B2 (en) | 2010-10-13 | 2022-05-10 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with electromagnetic modulators |
US11329059B1 (en) | 2016-10-10 | 2022-05-10 | Monolithic 3D Inc. | 3D memory devices and structures with thinned single crystal substrates |
US11341309B1 (en) | 2013-04-15 | 2022-05-24 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
EP3844810A4 (en) * | 2018-11-30 | 2022-06-01 | Yangtze Memory Technologies Co., Ltd. | Bonded memory device and fabrication methods thereof |
US11355381B2 (en) | 2010-11-18 | 2022-06-07 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11355380B2 (en) | 2010-11-18 | 2022-06-07 | Monolithic 3D Inc. | Methods for producing 3D semiconductor memory device and structure utilizing alignment marks |
US11374118B2 (en) | 2009-10-12 | 2022-06-28 | Monolithic 3D Inc. | Method to form a 3D integrated circuit |
US11398569B2 (en) | 2013-03-12 | 2022-07-26 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11404466B2 (en) | 2010-10-13 | 2022-08-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US11410912B2 (en) | 2012-04-09 | 2022-08-09 | Monolithic 3D Inc. | 3D semiconductor device with vias and isolation layers |
US11430667B2 (en) | 2012-12-29 | 2022-08-30 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11430668B2 (en) | 2012-12-29 | 2022-08-30 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11437368B2 (en) | 2010-10-13 | 2022-09-06 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11443971B2 (en) | 2010-11-18 | 2022-09-13 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11469271B2 (en) | 2010-10-11 | 2022-10-11 | Monolithic 3D Inc. | Method to produce 3D semiconductor devices and structures with memory |
US11476181B1 (en) | 2012-04-09 | 2022-10-18 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11482440B2 (en) | 2010-12-16 | 2022-10-25 | Monolithic 3D Inc. | 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits |
US11482438B2 (en) | 2010-11-18 | 2022-10-25 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11482439B2 (en) | 2010-11-18 | 2022-10-25 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors |
US11487928B2 (en) | 2013-04-15 | 2022-11-01 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11495484B2 (en) | 2010-11-18 | 2022-11-08 | Monolithic 3D Inc. | 3D semiconductor devices and structures with at least two single-crystal layers |
US11508605B2 (en) | 2010-11-18 | 2022-11-22 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11521888B2 (en) | 2010-11-18 | 2022-12-06 | Monolithic 3D Inc. | 3D semiconductor device and structure with high-k metal gate transistors |
US11569117B2 (en) | 2010-11-18 | 2023-01-31 | Monolithic 3D Inc. | 3D semiconductor device and structure with single-crystal layers |
US11574109B1 (en) | 2013-04-15 | 2023-02-07 | Monolithic 3D Inc | Automation methods for 3D integrated circuits and devices |
US11594473B2 (en) | 2012-04-09 | 2023-02-28 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11600667B1 (en) | 2010-10-11 | 2023-03-07 | Monolithic 3D Inc. | Method to produce 3D semiconductor devices and structures with memory |
US11605663B2 (en) | 2010-10-13 | 2023-03-14 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US11610802B2 (en) | 2010-11-18 | 2023-03-21 | Monolithic 3D Inc. | Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes |
US11615977B2 (en) | 2010-11-18 | 2023-03-28 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11616004B1 (en) | 2012-04-09 | 2023-03-28 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11694944B1 (en) | 2012-04-09 | 2023-07-04 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11694922B2 (en) | 2010-10-13 | 2023-07-04 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11711928B2 (en) | 2016-10-10 | 2023-07-25 | Monolithic 3D Inc. | 3D memory devices and structures with control circuits |
US11720736B2 (en) | 2013-04-15 | 2023-08-08 | Monolithic 3D Inc. | Automation methods for 3D integrated circuits and devices |
US11735462B2 (en) | 2010-11-18 | 2023-08-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with single-crystal layers |
US11735501B1 (en) | 2012-04-09 | 2023-08-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11763864B2 (en) | 2019-04-08 | 2023-09-19 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures with bit-line pillars |
US11784169B2 (en) | 2012-12-22 | 2023-10-10 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11784082B2 (en) | 2010-11-18 | 2023-10-10 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11804396B2 (en) | 2010-11-18 | 2023-10-31 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11812620B2 (en) | 2016-10-10 | 2023-11-07 | Monolithic 3D Inc. | 3D DRAM memory devices and structures with control circuits |
US11855100B2 (en) | 2010-10-13 | 2023-12-26 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11854857B1 (en) | 2010-11-18 | 2023-12-26 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11855114B2 (en) | 2010-10-13 | 2023-12-26 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US11862503B2 (en) | 2010-11-18 | 2024-01-02 | Monolithic 3D Inc. | Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11869915B2 (en) | 2010-10-13 | 2024-01-09 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US11869965B2 (en) | 2013-03-11 | 2024-01-09 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and memory cells |
US11869591B2 (en) | 2016-10-10 | 2024-01-09 | Monolithic 3D Inc. | 3D memory devices and structures with control circuits |
US11881443B2 (en) | 2012-04-09 | 2024-01-23 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11901210B2 (en) | 2010-11-18 | 2024-02-13 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11916045B2 (en) | 2012-12-22 | 2024-02-27 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11923230B1 (en) | 2010-11-18 | 2024-03-05 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11923374B2 (en) | 2013-03-12 | 2024-03-05 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11930648B1 (en) | 2016-10-10 | 2024-03-12 | Monolithic 3D Inc. | 3D memory devices and structures with metal layers |
US11929372B2 (en) | 2010-10-13 | 2024-03-12 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US11937422B2 (en) | 2015-11-07 | 2024-03-19 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US11935949B1 (en) | 2013-03-11 | 2024-03-19 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and memory cells |
US11956952B2 (en) | 2015-08-23 | 2024-04-09 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US11961827B1 (en) | 2023-12-23 | 2024-04-16 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
Families Citing this family (60)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8309627B2 (en) | 2007-09-07 | 2012-11-13 | Nexolve Corporation | Polymeric coating for the protection of objects |
US8258810B2 (en) | 2010-09-30 | 2012-09-04 | Monolithic 3D Inc. | 3D semiconductor device |
US8298875B1 (en) | 2011-03-06 | 2012-10-30 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US8525342B2 (en) | 2010-04-12 | 2013-09-03 | Qualcomm Incorporated | Dual-side interconnected CMOS for stacked integrated circuits |
US8283215B2 (en) | 2010-10-13 | 2012-10-09 | Monolithic 3D Inc. | Semiconductor and optoelectronic devices |
FR2966268B1 (en) | 2010-10-18 | 2013-08-16 | St Microelectronics Rousset | METHOD COMPRISING DETECTION OF INTEGRATED CIRCUIT BOX RETRIEVAL AFTER INITIAL SET-UP, AND CORRESPONDING INTEGRATED CIRCUIT. |
US8624323B2 (en) | 2011-05-31 | 2014-01-07 | International Business Machines Corporation | BEOL structures incorporating active devices and mechanical strength |
US9070686B2 (en) | 2011-05-31 | 2015-06-30 | International Business Machines Corporation | Wiring switch designs based on a field effect device for reconfigurable interconnect paths |
US8822309B2 (en) | 2011-12-23 | 2014-09-02 | Athenaeum, Llc | Heterogeneous integration process incorporating layer transfer in epitaxy level packaging |
US9812350B2 (en) | 2013-03-06 | 2017-11-07 | Qorvo Us, Inc. | Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer |
US9214337B2 (en) | 2013-03-06 | 2015-12-15 | Rf Micro Devices, Inc. | Patterned silicon-on-plastic (SOP) technology and methods of manufacturing the same |
US9583414B2 (en) | 2013-10-31 | 2017-02-28 | Qorvo Us, Inc. | Silicon-on-plastic semiconductor device and method of making the same |
US9543229B2 (en) | 2013-12-27 | 2017-01-10 | International Business Machines Corporation | Combination of TSV and back side wiring in 3D integration |
US9412736B2 (en) | 2014-06-05 | 2016-08-09 | Globalfoundries Inc. | Embedding semiconductor devices in silicon-on-insulator wafers connected using through silicon vias |
EP3155653A4 (en) * | 2014-06-16 | 2018-02-21 | Intel Corporation | Embedded memory in interconnect stack on silicon die |
CN106463467B (en) | 2014-06-16 | 2019-12-10 | 英特尔公司 | method for directly integrating memory die to logic die without using Through Silicon Vias (TSVs) |
KR102274274B1 (en) * | 2014-06-16 | 2021-07-07 | 인텔 코포레이션 | Silicon die with integrated high voltage devices |
US9991158B2 (en) * | 2014-09-12 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device |
EP2996143B1 (en) | 2014-09-12 | 2018-12-26 | Qorvo US, Inc. | Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same |
US10085352B2 (en) | 2014-10-01 | 2018-09-25 | Qorvo Us, Inc. | Method for manufacturing an integrated circuit package |
US10121718B2 (en) | 2014-11-03 | 2018-11-06 | Qorvo Us, Inc. | Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer |
BR112017015039A2 (en) | 2015-01-14 | 2018-03-20 | Bio Rad Innovations | blood analysis systems and methods |
WO2016118757A1 (en) | 2015-01-23 | 2016-07-28 | Bio-Rad Laboratories, Inc. | Immunoblotting systems and methods |
US9613831B2 (en) | 2015-03-25 | 2017-04-04 | Qorvo Us, Inc. | Encapsulated dies with enhanced thermal performance |
US9960145B2 (en) | 2015-03-25 | 2018-05-01 | Qorvo Us, Inc. | Flip chip module with enhanced properties |
US20160343604A1 (en) | 2015-05-22 | 2016-11-24 | Rf Micro Devices, Inc. | Substrate structure with embedded layer for post-processing silicon handle elimination |
US10692847B2 (en) | 2015-08-31 | 2020-06-23 | Intel Corporation | Inorganic interposer for multi-chip packaging |
US10276495B2 (en) | 2015-09-11 | 2019-04-30 | Qorvo Us, Inc. | Backside semiconductor die trimming |
US10020405B2 (en) | 2016-01-19 | 2018-07-10 | Qorvo Us, Inc. | Microelectronics package with integrated sensors |
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US10784149B2 (en) | 2016-05-20 | 2020-09-22 | Qorvo Us, Inc. | Air-cavity module with enhanced device isolation |
US10103080B2 (en) | 2016-06-10 | 2018-10-16 | Qorvo Us, Inc. | Thermally enhanced semiconductor package with thermal additive and process for making the same |
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US10109502B2 (en) | 2016-09-12 | 2018-10-23 | Qorvo Us, Inc. | Semiconductor package with reduced parasitic coupling effects and process for making the same |
US10090339B2 (en) | 2016-10-21 | 2018-10-02 | Qorvo Us, Inc. | Radio frequency (RF) switch |
US10749518B2 (en) | 2016-11-18 | 2020-08-18 | Qorvo Us, Inc. | Stacked field-effect transistor switch |
US10068831B2 (en) | 2016-12-09 | 2018-09-04 | Qorvo Us, Inc. | Thermally enhanced semiconductor package and process for making the same |
US10147676B1 (en) | 2017-05-15 | 2018-12-04 | International Business Machines Corporation | Wafer-scale power delivery |
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US10388631B1 (en) | 2018-01-29 | 2019-08-20 | Globalfoundries Inc. | 3D IC package with RDL interposer and related method |
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US20200235040A1 (en) | 2019-01-23 | 2020-07-23 | Qorvo Us, Inc. | Rf devices with enhanced performance and methods of forming the same |
US11387157B2 (en) | 2019-01-23 | 2022-07-12 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
KR20210129656A (en) | 2019-01-23 | 2021-10-28 | 코르보 유에스, 인크. | RF semiconductor device and method of forming same |
US11705428B2 (en) | 2019-01-23 | 2023-07-18 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
US11646289B2 (en) | 2019-12-02 | 2023-05-09 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
US11923238B2 (en) | 2019-12-12 | 2024-03-05 | Qorvo Us, Inc. | Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive |
US11353597B2 (en) | 2020-04-29 | 2022-06-07 | Tower Semiconductor Ltd. | High resolution radiation sensor based on single polysilicon floating gate array |
CN115548117A (en) | 2021-06-29 | 2022-12-30 | 联华电子股份有限公司 | Semiconductor structure and manufacturing method thereof |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4939568A (en) * | 1986-03-20 | 1990-07-03 | Fujitsu Limited | Three-dimensional integrated circuit and manufacturing method thereof |
US6765301B2 (en) * | 2001-11-22 | 2004-07-20 | Silicon Integrated Systems Corp. | Integrated circuit bonding device and manufacturing method thereof |
US20050285260A1 (en) * | 2004-06-25 | 2005-12-29 | Dale Hackitt | Bottom heat spreader |
US7042753B2 (en) * | 2001-02-14 | 2006-05-09 | Kabushiki Kaisha Toshiba | Multi-value magnetic random access memory with stacked tunnel magnetoresistance (TMR) elements |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3112106B2 (en) * | 1991-10-11 | 2000-11-27 | キヤノン株式会社 | Manufacturing method of semiconductor substrate |
JP3261685B2 (en) * | 1992-01-31 | 2002-03-04 | キヤノン株式会社 | Semiconductor element substrate and method of manufacturing the same |
JP3214631B2 (en) | 1992-01-31 | 2001-10-02 | キヤノン株式会社 | Semiconductor substrate and method of manufacturing the same |
JP3416163B2 (en) * | 1992-01-31 | 2003-06-16 | キヤノン株式会社 | Semiconductor substrate and manufacturing method thereof |
JP3293736B2 (en) | 1996-02-28 | 2002-06-17 | キヤノン株式会社 | Semiconductor substrate manufacturing method and bonded substrate |
JP3257580B2 (en) | 1994-03-10 | 2002-02-18 | キヤノン株式会社 | Manufacturing method of semiconductor substrate |
CA2182442C (en) * | 1995-08-02 | 2000-10-24 | Kiyofumi Sakaguchi | Semiconductor substrate and fabrication method for the same |
SG55413A1 (en) | 1996-11-15 | 1998-12-21 | Method Of Manufacturing Semico | Method of manufacturing semiconductor article |
EP0851513B1 (en) | 1996-12-27 | 2007-11-21 | Canon Kabushiki Kaisha | Method of producing semiconductor member and method of producing solar cell |
CA2232796C (en) | 1997-03-26 | 2002-01-22 | Canon Kabushiki Kaisha | Thin film forming process |
JP3647191B2 (en) * | 1997-03-27 | 2005-05-11 | キヤノン株式会社 | Manufacturing method of semiconductor device |
JP3492142B2 (en) | 1997-03-27 | 2004-02-03 | キヤノン株式会社 | Manufacturing method of semiconductor substrate |
US6150239A (en) | 1997-05-31 | 2000-11-21 | Max Planck Society | Method for the transfer of thin layers monocrystalline material onto a desirable substrate |
EP0926709A3 (en) | 1997-12-26 | 2000-08-30 | Canon Kabushiki Kaisha | Method of manufacturing an SOI structure |
EP1041624A1 (en) * | 1999-04-02 | 2000-10-04 | Interuniversitair Microelektronica Centrum Vzw | Method of transferring ultra-thin substrates and application of the method to the manufacture of a multilayer thin film device |
US6320228B1 (en) | 2000-01-14 | 2001-11-20 | Advanced Micro Devices, Inc. | Multiple active layer integrated circuit and a method of making such a circuit |
US6732908B2 (en) | 2002-01-18 | 2004-05-11 | International Business Machines Corporation | High density raised stud microjoining system and methods of fabricating the same |
US6661098B2 (en) | 2002-01-18 | 2003-12-09 | International Business Machines Corporation | High density area array solder microjoining interconnect structure and fabrication method |
US7622363B2 (en) * | 2003-05-06 | 2009-11-24 | Canon Kabushiki Kaisha | Semiconductor substrate, semiconductor device, light emitting diode and producing method therefor |
US8183151B2 (en) * | 2007-05-04 | 2012-05-22 | Micron Technology, Inc. | Methods of forming conductive vias through substrates, and structures and assemblies resulting therefrom |
-
2007
- 2007-05-10 US US11/746,680 patent/US20080277778A1/en not_active Abandoned
-
2009
- 2009-08-20 US US12/544,226 patent/US7855101B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4939568A (en) * | 1986-03-20 | 1990-07-03 | Fujitsu Limited | Three-dimensional integrated circuit and manufacturing method thereof |
US7042753B2 (en) * | 2001-02-14 | 2006-05-09 | Kabushiki Kaisha Toshiba | Multi-value magnetic random access memory with stacked tunnel magnetoresistance (TMR) elements |
US6765301B2 (en) * | 2001-11-22 | 2004-07-20 | Silicon Integrated Systems Corp. | Integrated circuit bonding device and manufacturing method thereof |
US20050285260A1 (en) * | 2004-06-25 | 2005-12-29 | Dale Hackitt | Bottom heat spreader |
Cited By (279)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080308937A1 (en) * | 2007-06-14 | 2008-12-18 | Svtc Technologies, Llc | Copper-free semiconductor device interface and methods of fabrication and use thereof |
US20080315431A1 (en) * | 2007-06-19 | 2008-12-25 | Samsung Electro-Mechanics Co., Ltd. | Mounting substrate and manufacturing method thereof |
US8022553B2 (en) * | 2007-06-19 | 2011-09-20 | Samsung Electro-Mechanics Co., Ltd. | Mounting substrate and manufacturing method thereof |
US8937339B2 (en) | 2008-04-24 | 2015-01-20 | Sumitomo Electric Industries, Ltd. | Si(1-V-W-X)CWAlXNV substrate, and epitaxial wafer |
US8357597B2 (en) * | 2008-04-24 | 2013-01-22 | Sumitomo Electric Industries, Ltd. | Process for producing Si(1-v-w-x)CwAlxNv base material, process for producing epitaxial wafer, Si(1-v-w-x)CwAlxNv base material, and epitaxial wafer |
US20110031534A1 (en) * | 2008-04-24 | 2011-02-10 | Sumitomo Electric Industries, Ltd | PROCESS FOR PRODUCING Si(1-v-w-x)CwAlxNv BASE MATERIAL, PROCESS FOR PRODUCING EPITAXIAL WAFER, Si(1-v-w-x)CwAlxNv BASE MATERIAL, AND EPITAXIAL WAFER |
US20110039071A1 (en) * | 2008-04-24 | 2011-02-17 | Sumitomo Electric Industries, Ltd | METHOD OF MANUFACTURING A Si(1-v-w-x)CwAlxNv SUBSTRATE, METHOD OF MANUFACTURING AN EPITAXIAL WAFER, Si(1-v-w-x)CwAlxNv SUBSTRATE, AND EPITAXIAL WAFER |
US20110042788A1 (en) * | 2008-04-24 | 2011-02-24 | Sumitomo Electric Industries, Ltd. | PROCESS FOR PRODUCING Si(1-v-w-x)CwAlxNv BASE MATERIAL, PROCESS FOR PRODUCING EPITAXIAL WAFER, SI(1-v-w-x)CwAlxNv BASE MATERIAL, AND EPITAXIAL WAFER |
US8715414B2 (en) | 2008-04-24 | 2014-05-06 | Sumitomo Electric Industries, Ltd. | Process for producing Si(1-v-w-x)CwAlxNv base material, process for producing epitaxial wafer, Si(1-v-w-x)CwAlxNv base material, and epitaxial wafer |
US8540817B2 (en) | 2008-04-24 | 2013-09-24 | Sumitomo Electric Industries, Ltd. | Method of manufacturing a Si(1-v-w-x)CwAlxNv substrate, method of manufacturing an epitaxial wafer, Si(1-v-w-x)CwAlxNv substrate, and epitaxial wafer |
US20100164783A1 (en) * | 2008-12-31 | 2010-07-01 | Debabani Choudhury | Platform Integrated Phased Array Transmit/Receive Module |
US8706049B2 (en) * | 2008-12-31 | 2014-04-22 | Intel Corporation | Platform integrated phased array transmit/receive module |
US20100167666A1 (en) * | 2008-12-31 | 2010-07-01 | Debabani Choudhury | Integrated Array Transmit/Receive Module |
US8467737B2 (en) | 2008-12-31 | 2013-06-18 | Intel Corporation | Integrated array transmit/receive module |
US9412645B1 (en) | 2009-04-14 | 2016-08-09 | Monolithic 3D Inc. | Semiconductor devices and structures |
US8427200B2 (en) | 2009-04-14 | 2013-04-23 | Monolithic 3D Inc. | 3D semiconductor device |
US8362482B2 (en) | 2009-04-14 | 2013-01-29 | Monolithic 3D Inc. | Semiconductor device and structure |
US8987079B2 (en) | 2009-04-14 | 2015-03-24 | Monolithic 3D Inc. | Method for developing a custom device |
US8669778B1 (en) | 2009-04-14 | 2014-03-11 | Monolithic 3D Inc. | Method for design and manufacturing of a 3D semiconductor device |
US8373439B2 (en) | 2009-04-14 | 2013-02-12 | Monolithic 3D Inc. | 3D semiconductor device |
US8378494B2 (en) | 2009-04-14 | 2013-02-19 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US8754533B2 (en) | 2009-04-14 | 2014-06-17 | Monolithic 3D Inc. | Monolithic three-dimensional semiconductor device and structure |
US9509313B2 (en) | 2009-04-14 | 2016-11-29 | Monolithic 3D Inc. | 3D semiconductor device |
US8384426B2 (en) | 2009-04-14 | 2013-02-26 | Monolithic 3D Inc. | Semiconductor device and structure |
US9577642B2 (en) | 2009-04-14 | 2017-02-21 | Monolithic 3D Inc. | Method to form a 3D semiconductor device |
US8405420B2 (en) | 2009-04-14 | 2013-03-26 | Monolithic 3D Inc. | System comprising a semiconductor device and structure |
US8378715B2 (en) | 2009-04-14 | 2013-02-19 | Monolithic 3D Inc. | Method to construct systems |
US9711407B2 (en) | 2009-04-14 | 2017-07-18 | Monolithic 3D Inc. | Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer |
US8395191B2 (en) | 2009-10-12 | 2013-03-12 | Monolithic 3D Inc. | Semiconductor device and structure |
US11018133B2 (en) | 2009-10-12 | 2021-05-25 | Monolithic 3D Inc. | 3D integrated circuit |
US8664042B2 (en) | 2009-10-12 | 2014-03-04 | Monolithic 3D Inc. | Method for fabrication of configurable systems |
US8907442B2 (en) | 2009-10-12 | 2014-12-09 | Monolthic 3D Inc. | System comprising a semiconductor device and structure |
US10157909B2 (en) | 2009-10-12 | 2018-12-18 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US8294159B2 (en) | 2009-10-12 | 2012-10-23 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US11374118B2 (en) | 2009-10-12 | 2022-06-28 | Monolithic 3D Inc. | Method to form a 3D integrated circuit |
US10366970B2 (en) | 2009-10-12 | 2019-07-30 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10388863B2 (en) | 2009-10-12 | 2019-08-20 | Monolithic 3D Inc. | 3D memory device and structure |
US10910364B2 (en) | 2009-10-12 | 2021-02-02 | Monolitaic 3D Inc. | 3D semiconductor device |
US8237228B2 (en) | 2009-10-12 | 2012-08-07 | Monolithic 3D Inc. | System comprising a semiconductor device and structure |
US10354995B2 (en) | 2009-10-12 | 2019-07-16 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US9406670B1 (en) | 2009-10-12 | 2016-08-02 | Monolithic 3D Inc. | System comprising a semiconductor device and structure |
US10043781B2 (en) | 2009-10-12 | 2018-08-07 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10217791B2 (en) * | 2009-11-30 | 2019-02-26 | Sony Corporation | Method of manufacturing bonded substrate, bonded substrate, method of manufacturing solid-state imaging apparatus, solid-state imaging apparatus, and camera |
US20170084647A1 (en) * | 2009-11-30 | 2017-03-23 | Sony Corporation | Method of manufacturing bonded substrate, bonded substrate, method of manufacturing solid-state imaging apparatus, solid-state imaging apparatus, and camera |
US9099526B2 (en) | 2010-02-16 | 2015-08-04 | Monolithic 3D Inc. | Integrated circuit device and structure |
US8492886B2 (en) | 2010-02-16 | 2013-07-23 | Monolithic 3D Inc | 3D integrated circuit with logic |
US9564432B2 (en) | 2010-02-16 | 2017-02-07 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US8846463B1 (en) | 2010-02-16 | 2014-09-30 | Monolithic 3D Inc. | Method to construct a 3D semiconductor device |
US8642416B2 (en) | 2010-07-30 | 2014-02-04 | Monolithic 3D Inc. | Method of forming three dimensional integrated circuit devices using layer transfer technique |
US8912052B2 (en) | 2010-07-30 | 2014-12-16 | Monolithic 3D Inc. | Semiconductor device and structure |
US8709880B2 (en) | 2010-07-30 | 2014-04-29 | Monolithic 3D Inc | Method for fabrication of a semiconductor device and structure |
US8703597B1 (en) | 2010-09-30 | 2014-04-22 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US8461035B1 (en) | 2010-09-30 | 2013-06-11 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
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US8956959B2 (en) | 2010-10-11 | 2015-02-17 | Monolithic 3D Inc. | Method of manufacturing a semiconductor device with two monocrystalline layers |
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US11227897B2 (en) | 2010-10-11 | 2022-01-18 | Monolithic 3D Inc. | Method for producing a 3D semiconductor memory device and structure |
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US10290682B2 (en) | 2010-10-11 | 2019-05-14 | Monolithic 3D Inc. | 3D IC semiconductor device and structure with stacked memory |
US11469271B2 (en) | 2010-10-11 | 2022-10-11 | Monolithic 3D Inc. | Method to produce 3D semiconductor devices and structures with memory |
US9818800B2 (en) | 2010-10-11 | 2017-11-14 | Monolithic 3D Inc. | Self aligned semiconductor device and structure |
US11018191B1 (en) | 2010-10-11 | 2021-05-25 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US8440542B2 (en) | 2010-10-11 | 2013-05-14 | Monolithic 3D Inc. | Semiconductor device and structure |
US10896931B1 (en) | 2010-10-11 | 2021-01-19 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11600667B1 (en) | 2010-10-11 | 2023-03-07 | Monolithic 3D Inc. | Method to produce 3D semiconductor devices and structures with memory |
US11374042B1 (en) | 2010-10-13 | 2022-06-28 | Monolithic 3D Inc. | 3D micro display semiconductor device and structure |
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US10679977B2 (en) | 2010-10-13 | 2020-06-09 | Monolithic 3D Inc. | 3D microdisplay device and structure |
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US11043523B1 (en) | 2010-10-13 | 2021-06-22 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
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US8373230B1 (en) | 2010-10-13 | 2013-02-12 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
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US11694922B2 (en) | 2010-10-13 | 2023-07-04 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11437368B2 (en) | 2010-10-13 | 2022-09-06 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11869915B2 (en) | 2010-10-13 | 2024-01-09 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US10943934B2 (en) | 2010-10-13 | 2021-03-09 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US11063071B1 (en) | 2010-10-13 | 2021-07-13 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with waveguides |
US11164898B2 (en) | 2010-10-13 | 2021-11-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
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US8476145B2 (en) | 2010-10-13 | 2013-07-02 | Monolithic 3D Inc. | Method of fabricating a semiconductor device and structure |
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US11107721B2 (en) | 2010-11-18 | 2021-08-31 | Monolithic 3D Inc. | 3D semiconductor device and structure with NAND logic |
US11784082B2 (en) | 2010-11-18 | 2023-10-10 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11164770B1 (en) | 2010-11-18 | 2021-11-02 | Monolithic 3D Inc. | Method for producing a 3D semiconductor memory device and structure |
US11521888B2 (en) | 2010-11-18 | 2022-12-06 | Monolithic 3D Inc. | 3D semiconductor device and structure with high-k metal gate transistors |
US11508605B2 (en) | 2010-11-18 | 2022-11-22 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11495484B2 (en) | 2010-11-18 | 2022-11-08 | Monolithic 3D Inc. | 3D semiconductor devices and structures with at least two single-crystal layers |
US11482439B2 (en) | 2010-11-18 | 2022-10-25 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors |
US11482438B2 (en) | 2010-11-18 | 2022-10-25 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11211279B2 (en) | 2010-11-18 | 2021-12-28 | Monolithic 3D Inc. | Method for processing a 3D integrated circuit and structure |
US11804396B2 (en) | 2010-11-18 | 2023-10-31 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11569117B2 (en) | 2010-11-18 | 2023-01-31 | Monolithic 3D Inc. | 3D semiconductor device and structure with single-crystal layers |
US11121021B2 (en) | 2010-11-18 | 2021-09-14 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US20120129301A1 (en) * | 2010-11-18 | 2012-05-24 | Monolithic 3D Inc. | System comprising a semiconductor device and structure |
US11443971B2 (en) | 2010-11-18 | 2022-09-13 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11862503B2 (en) | 2010-11-18 | 2024-01-02 | Monolithic 3D Inc. | Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
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US11901210B2 (en) | 2010-11-18 | 2024-02-13 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11610802B2 (en) | 2010-11-18 | 2023-03-21 | Monolithic 3D Inc. | Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes |
US9136153B2 (en) | 2010-11-18 | 2015-09-15 | Monolithic 3D Inc. | 3D semiconductor device and structure with back-bias |
US11615977B2 (en) | 2010-11-18 | 2023-03-28 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US10497713B2 (en) | 2010-11-18 | 2019-12-03 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US8273610B2 (en) * | 2010-11-18 | 2012-09-25 | Monolithic 3D Inc. | Method of constructing a semiconductor device and structure |
US11355380B2 (en) | 2010-11-18 | 2022-06-07 | Monolithic 3D Inc. | Methods for producing 3D semiconductor memory device and structure utilizing alignment marks |
US11018042B1 (en) | 2010-11-18 | 2021-05-25 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11355381B2 (en) | 2010-11-18 | 2022-06-07 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11031275B2 (en) | 2010-11-18 | 2021-06-08 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11854857B1 (en) | 2010-11-18 | 2023-12-26 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11094576B1 (en) | 2010-11-18 | 2021-08-17 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11735462B2 (en) | 2010-11-18 | 2023-08-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with single-crystal layers |
US11923230B1 (en) | 2010-11-18 | 2024-03-05 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US8536023B2 (en) | 2010-11-22 | 2013-09-17 | Monolithic 3D Inc. | Method of manufacturing a semiconductor device and structure |
US8541819B1 (en) | 2010-12-09 | 2013-09-24 | Monolithic 3D Inc. | Semiconductor device and structure |
US11482440B2 (en) | 2010-12-16 | 2022-10-25 | Monolithic 3D Inc. | 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits |
US8975670B2 (en) | 2011-03-06 | 2015-03-10 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
US8901613B2 (en) | 2011-03-06 | 2014-12-02 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
US8450804B2 (en) | 2011-03-06 | 2013-05-28 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
US8581349B1 (en) | 2011-05-02 | 2013-11-12 | Monolithic 3D Inc. | 3D memory semiconductor device and structure |
US10217667B2 (en) | 2011-06-28 | 2019-02-26 | Monolithic 3D Inc. | 3D semiconductor device, fabrication method and system |
US9219005B2 (en) | 2011-06-28 | 2015-12-22 | Monolithic 3D Inc. | Semiconductor system and device |
US9953925B2 (en) | 2011-06-28 | 2018-04-24 | Monolithic 3D Inc. | Semiconductor system and device |
US10388568B2 (en) | 2011-06-28 | 2019-08-20 | Monolithic 3D Inc. | 3D semiconductor device and system |
US9030858B2 (en) | 2011-10-02 | 2015-05-12 | Monolithic 3D Inc. | Semiconductor device and structure |
US8687399B2 (en) | 2011-10-02 | 2014-04-01 | Monolithic 3D Inc. | Semiconductor device and structure |
US9197804B1 (en) | 2011-10-14 | 2015-11-24 | Monolithic 3D Inc. | Semiconductor and optoelectronic devices |
US9029173B2 (en) | 2011-10-18 | 2015-05-12 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US9000557B2 (en) | 2012-03-17 | 2015-04-07 | Zvi Or-Bach | Semiconductor device and structure |
US11694944B1 (en) | 2012-04-09 | 2023-07-04 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US9305867B1 (en) | 2012-04-09 | 2016-04-05 | Monolithic 3D Inc. | Semiconductor devices and structures |
US10600888B2 (en) | 2012-04-09 | 2020-03-24 | Monolithic 3D Inc. | 3D semiconductor device |
US8836073B1 (en) | 2012-04-09 | 2014-09-16 | Monolithic 3D Inc. | Semiconductor device and structure |
US11881443B2 (en) | 2012-04-09 | 2024-01-23 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11088050B2 (en) | 2012-04-09 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device with isolation layers |
US11735501B1 (en) | 2012-04-09 | 2023-08-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11410912B2 (en) | 2012-04-09 | 2022-08-09 | Monolithic 3D Inc. | 3D semiconductor device with vias and isolation layers |
US11476181B1 (en) | 2012-04-09 | 2022-10-18 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11594473B2 (en) | 2012-04-09 | 2023-02-28 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11616004B1 (en) | 2012-04-09 | 2023-03-28 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US8557632B1 (en) | 2012-04-09 | 2013-10-15 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US11164811B2 (en) | 2012-04-09 | 2021-11-02 | Monolithic 3D Inc. | 3D semiconductor device with isolation layers and oxide-to-oxide bonding |
US9099424B1 (en) | 2012-08-10 | 2015-08-04 | Monolithic 3D Inc. | Semiconductor system, device and structure with heat removal |
US8686428B1 (en) | 2012-11-16 | 2014-04-01 | Monolithic 3D Inc. | Semiconductor device and structure |
US8574929B1 (en) | 2012-11-16 | 2013-11-05 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US8742476B1 (en) | 2012-11-27 | 2014-06-03 | Monolithic 3D Inc. | Semiconductor device and structure |
US11063024B1 (en) | 2012-12-22 | 2021-07-13 | Monlithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US8674470B1 (en) | 2012-12-22 | 2014-03-18 | Monolithic 3D Inc. | Semiconductor device and structure |
US11916045B2 (en) | 2012-12-22 | 2024-02-27 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11784169B2 (en) | 2012-12-22 | 2023-10-10 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11309292B2 (en) | 2012-12-22 | 2022-04-19 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US8921970B1 (en) | 2012-12-22 | 2014-12-30 | Monolithic 3D Inc | Semiconductor device and structure |
US9252134B2 (en) | 2012-12-22 | 2016-02-02 | Monolithic 3D Inc. | Semiconductor device and structure |
US11018116B2 (en) | 2012-12-22 | 2021-05-25 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11217565B2 (en) | 2012-12-22 | 2022-01-04 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US9911627B1 (en) | 2012-12-29 | 2018-03-06 | Monolithic 3D Inc. | Method of processing a semiconductor device |
US11004694B1 (en) | 2012-12-29 | 2021-05-11 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10115663B2 (en) | 2012-12-29 | 2018-10-30 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11430668B2 (en) | 2012-12-29 | 2022-08-30 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US10651054B2 (en) | 2012-12-29 | 2020-05-12 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11430667B2 (en) | 2012-12-29 | 2022-08-30 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US8803206B1 (en) | 2012-12-29 | 2014-08-12 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11087995B1 (en) | 2012-12-29 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10892169B2 (en) | 2012-12-29 | 2021-01-12 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US9385058B1 (en) | 2012-12-29 | 2016-07-05 | Monolithic 3D Inc. | Semiconductor device and structure |
US9871034B1 (en) | 2012-12-29 | 2018-01-16 | Monolithic 3D Inc. | Semiconductor device and structure |
US9460978B1 (en) | 2012-12-29 | 2016-10-04 | Monolithic 3D Inc. | Semiconductor device and structure |
US10903089B1 (en) | 2012-12-29 | 2021-01-26 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US9460991B1 (en) * | 2012-12-29 | 2016-10-04 | Monolithic 3D Inc. | Semiconductor device and structure |
US11177140B2 (en) | 2012-12-29 | 2021-11-16 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10600657B2 (en) | 2012-12-29 | 2020-03-24 | Monolithic 3D Inc | 3D semiconductor device and structure |
US10283582B2 (en) * | 2013-02-25 | 2019-05-07 | Analog Devices Global | Microelectronic circuits and integrated circuits including a non-silicon substrate |
US20140240944A1 (en) * | 2013-02-25 | 2014-08-28 | Analog Devices Technology | Insulating low signal loss substrate, integrated circuits including a non-silicon substrate and methods of manufacture of integrated circuits |
US11515413B2 (en) | 2013-03-11 | 2022-11-29 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US9496271B2 (en) | 2013-03-11 | 2016-11-15 | Monolithic 3D Inc. | 3DIC system with a two stable state memory and back-bias region |
US8902663B1 (en) | 2013-03-11 | 2014-12-02 | Monolithic 3D Inc. | Method of maintaining a memory state |
US11004967B1 (en) | 2013-03-11 | 2021-05-11 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US10325651B2 (en) | 2013-03-11 | 2019-06-18 | Monolithic 3D Inc. | 3D semiconductor device with stacked memory |
US10964807B2 (en) | 2013-03-11 | 2021-03-30 | Monolithic 3D Inc. | 3D semiconductor device with memory |
US10355121B2 (en) | 2013-03-11 | 2019-07-16 | Monolithic 3D Inc. | 3D semiconductor device with stacked memory |
US11935949B1 (en) | 2013-03-11 | 2024-03-19 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and memory cells |
US11121246B2 (en) | 2013-03-11 | 2021-09-14 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11869965B2 (en) | 2013-03-11 | 2024-01-09 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and memory cells |
US8994404B1 (en) | 2013-03-12 | 2015-03-31 | Monolithic 3D Inc. | Semiconductor device and structure |
US11923374B2 (en) | 2013-03-12 | 2024-03-05 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11398569B2 (en) | 2013-03-12 | 2022-07-26 | Monolithic 3D Inc. | 3D semiconductor device and structure |
CN105190875A (en) * | 2013-03-13 | 2015-12-23 | 英特尔公司 | Methods of forming under device interconnect structures |
JP2016512656A (en) * | 2013-03-13 | 2016-04-28 | インテル・コーポレーション | Method for forming an in-device interconnect structure |
US9117749B1 (en) | 2013-03-15 | 2015-08-25 | Monolithic 3D Inc. | Semiconductor device and structure |
US20170338150A1 (en) * | 2013-03-15 | 2017-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for Hybrid Wafer Bonding Integrated with CMOS Processing |
US10224279B2 (en) | 2013-03-15 | 2019-03-05 | Monolithic 3D Inc. | Semiconductor device and structure |
US10510597B2 (en) * | 2013-03-15 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for hybrid wafer bonding integrated with CMOS processing |
US11341309B1 (en) | 2013-04-15 | 2022-05-24 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11574109B1 (en) | 2013-04-15 | 2023-02-07 | Monolithic 3D Inc | Automation methods for 3D integrated circuits and devices |
US10127344B2 (en) | 2013-04-15 | 2018-11-13 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11720736B2 (en) | 2013-04-15 | 2023-08-08 | Monolithic 3D Inc. | Automation methods for 3D integrated circuits and devices |
US11270055B1 (en) | 2013-04-15 | 2022-03-08 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11030371B2 (en) | 2013-04-15 | 2021-06-08 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11487928B2 (en) | 2013-04-15 | 2022-11-01 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11088130B2 (en) | 2014-01-28 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11107808B1 (en) | 2014-01-28 | 2021-08-31 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11031394B1 (en) | 2014-01-28 | 2021-06-08 | Monolithic 3D Inc. | 3D semiconductor device and structure |
KR102502496B1 (en) | 2014-06-16 | 2023-02-23 | 인텔 코포레이션 | Metal on both sides with clock gated power and signal routing underneath |
US10658291B2 (en) | 2014-06-16 | 2020-05-19 | Intel Corporation | Metal on both sides with clock gated-power and signal routing underneath |
CN106463530A (en) * | 2014-06-16 | 2017-02-22 | 英特尔公司 | Metal on both sides with clock gated power and signal routing underneath |
EP3155666A4 (en) * | 2014-06-16 | 2018-03-14 | Intel Corporation | Metal on both sides with clock gated power and signal routing underneath |
US10186484B2 (en) | 2014-06-16 | 2019-01-22 | Intel Corporation | Metal on both sides with clock gated-power and signal routing underneath |
KR20210125609A (en) * | 2014-06-16 | 2021-10-18 | 인텔 코포레이션 | Metal on both sides with clock gated power and signal routing underneath |
KR20170016325A (en) * | 2014-06-16 | 2017-02-13 | 인텔 코포레이션 | Metal on both sides with clock gated power and signal routing underneath |
KR102312250B1 (en) | 2014-06-16 | 2021-10-14 | 인텔 코포레이션 | Metal on both sides with clock gated power and signal routing underneath |
US10840239B2 (en) | 2014-08-26 | 2020-11-17 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11345591B2 (en) | 2015-01-28 | 2022-05-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device for protecting FEOL element and BEOL element |
US10508028B2 (en) | 2015-01-28 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device for protecting FEOL element and BEOL element |
US20160214855A1 (en) * | 2015-01-28 | 2016-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device and method for protecting feol element and beol element |
US10155660B2 (en) * | 2015-01-28 | 2018-12-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device and method for protecting FEOL element and BEOL element |
TWI581405B (en) * | 2015-01-28 | 2017-05-01 | 台灣積體電路製造股份有限公司 | Semiconductor device and method for fabricating the same |
US10297586B2 (en) | 2015-03-09 | 2019-05-21 | Monolithic 3D Inc. | Methods for processing a 3D semiconductor device |
US11056468B1 (en) | 2015-04-19 | 2021-07-06 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10825779B2 (en) | 2015-04-19 | 2020-11-03 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11011507B1 (en) | 2015-04-19 | 2021-05-18 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10381328B2 (en) | 2015-04-19 | 2019-08-13 | Monolithic 3D Inc. | Semiconductor device and structure |
US20160379943A1 (en) * | 2015-06-25 | 2016-12-29 | Skyworks Solutions, Inc. | Method and apparatus for high performance passive-active circuit integration |
US11956952B2 (en) | 2015-08-23 | 2024-04-09 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US10515981B2 (en) | 2015-09-21 | 2019-12-24 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with memory |
US10522225B1 (en) | 2015-10-02 | 2019-12-31 | Monolithic 3D Inc. | Semiconductor device with non-volatile memory |
US11296115B1 (en) | 2015-10-24 | 2022-04-05 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10418369B2 (en) | 2015-10-24 | 2019-09-17 | Monolithic 3D Inc. | Multi-level semiconductor memory device and structure |
US10847540B2 (en) | 2015-10-24 | 2020-11-24 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11114464B2 (en) | 2015-10-24 | 2021-09-07 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11114427B2 (en) | 2015-11-07 | 2021-09-07 | Monolithic 3D Inc. | 3D semiconductor processor and memory device and structure |
US11937422B2 (en) | 2015-11-07 | 2024-03-19 | Monolithic 3D Inc. | Semiconductor memory device and structure |
WO2017111775A1 (en) * | 2015-12-23 | 2017-06-29 | Intel Corporation | Back-end repeater element integration techniques |
US20170372983A1 (en) * | 2016-06-27 | 2017-12-28 | Newport Fab, Llc Dba Jazz Semiconductor | Thermally Conductive and Electrically Isolating Layers in Semiconductor Structures |
US10192805B2 (en) * | 2016-06-27 | 2019-01-29 | Newport Fab, Llc | Thermally conductive and electrically isolating layers in semiconductor structures |
US9966301B2 (en) * | 2016-06-27 | 2018-05-08 | New Fab, LLC | Reduced substrate effects in monolithically integrated RF circuits |
US10062636B2 (en) | 2016-06-27 | 2018-08-28 | Newport Fab, Llc | Integration of thermally conductive but electrically isolating layers with semiconductor devices |
US11251149B2 (en) | 2016-10-10 | 2022-02-15 | Monolithic 3D Inc. | 3D memory device and structure |
US11711928B2 (en) | 2016-10-10 | 2023-07-25 | Monolithic 3D Inc. | 3D memory devices and structures with control circuits |
US11930648B1 (en) | 2016-10-10 | 2024-03-12 | Monolithic 3D Inc. | 3D memory devices and structures with metal layers |
US11869591B2 (en) | 2016-10-10 | 2024-01-09 | Monolithic 3D Inc. | 3D memory devices and structures with control circuits |
US11812620B2 (en) | 2016-10-10 | 2023-11-07 | Monolithic 3D Inc. | 3D DRAM memory devices and structures with control circuits |
US11329059B1 (en) | 2016-10-10 | 2022-05-10 | Monolithic 3D Inc. | 3D memory devices and structures with thinned single crystal substrates |
US20180269105A1 (en) * | 2017-03-15 | 2018-09-20 | Globalfoundries Singapore Pte. Ltd. | Bonding of iii-v-and-si substrates with interconnect metal layers |
US10580903B2 (en) | 2018-03-13 | 2020-03-03 | Psemi Corporation | Semiconductor-on-insulator transistor with improved breakdown characteristics |
WO2020018847A1 (en) * | 2018-07-19 | 2020-01-23 | Psemi Corporation | High-q integrated circuit inductor structure and methods |
US11133338B2 (en) | 2018-07-19 | 2021-09-28 | Psemi Corporation | SLT integrated circuit capacitor structure and methods |
US10573674B2 (en) | 2018-07-19 | 2020-02-25 | Psemi Corporation | SLT integrated circuit capacitor structure and methods |
US11652112B2 (en) | 2018-07-19 | 2023-05-16 | Psemi Corporation | SLT integrated circuit capacitor structure and methods |
US11437404B2 (en) | 2018-07-19 | 2022-09-06 | Psemi Corporation | Thermal extraction of single layer transfer integrated circuits |
US10658386B2 (en) | 2018-07-19 | 2020-05-19 | Psemi Corporation | Thermal extraction of single layer transfer integrated circuits |
US10672806B2 (en) | 2018-07-19 | 2020-06-02 | Psemi Corporation | High-Q integrated circuit inductor structure and methods |
EP3844810A4 (en) * | 2018-11-30 | 2022-06-01 | Yangtze Memory Technologies Co., Ltd. | Bonded memory device and fabrication methods thereof |
US10892016B1 (en) | 2019-04-08 | 2021-01-12 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11158652B1 (en) | 2019-04-08 | 2021-10-26 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11018156B2 (en) | 2019-04-08 | 2021-05-25 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11763864B2 (en) | 2019-04-08 | 2023-09-19 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures with bit-line pillars |
US11296106B2 (en) | 2019-04-08 | 2022-04-05 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11257741B2 (en) * | 2019-05-28 | 2022-02-22 | Samsung Electronics Co., Ltd. | Semiconductor package |
US11276749B2 (en) | 2019-06-12 | 2022-03-15 | Psemi Corporation | High density IC capacitor structure |
US10777636B1 (en) | 2019-06-12 | 2020-09-15 | Psemi Corporation | High density IC capacitor structure |
US20220093571A1 (en) * | 2019-09-12 | 2022-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside contact for thermal displacement in a multi-wafer stacked integrated circuit |
US11694997B2 (en) * | 2019-09-12 | 2023-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside contact for thermal displacement in a multi-wafer stacked integrated circuit |
US11961827B1 (en) | 2023-12-23 | 2024-04-16 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
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