US20080200019A9 - Selective Deposition of Noble Metal Thin Films - Google Patents

Selective Deposition of Noble Metal Thin Films Download PDF

Info

Publication number
US20080200019A9
US20080200019A9 US11/376,704 US37670406A US2008200019A9 US 20080200019 A9 US20080200019 A9 US 20080200019A9 US 37670406 A US37670406 A US 37670406A US 2008200019 A9 US2008200019 A9 US 2008200019A9
Authority
US
United States
Prior art keywords
metal
substrate
noble metal
silicon
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US11/376,704
Other versions
US20070026654A1 (en
US7666773B2 (en
Inventor
Hannu Huotari
Marko Tuominen
Miika Leinikka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ASM International NV
Original Assignee
ASM International NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ASM International NV filed Critical ASM International NV
Priority to US11/376,704 priority Critical patent/US7666773B2/en
Assigned to ASM INTERNATIONAL N.V. reassignment ASM INTERNATIONAL N.V. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUOTARI, HANNU, TUOMINEN, MARKO, LEINIKKA, MIIKA
Publication of US20070026654A1 publication Critical patent/US20070026654A1/en
Publication of US20080200019A9 publication Critical patent/US20080200019A9/en
Priority to US12/649,817 priority patent/US7985669B2/en
Application granted granted Critical
Publication of US7666773B2 publication Critical patent/US7666773B2/en
Priority to US13/188,087 priority patent/US8927403B2/en
Priority to US14/557,874 priority patent/US9469899B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • C23C16/45525Atomic layer deposition [ALD]
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/32Carbides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34Nitrides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/38Borides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40Oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/517Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Definitions

  • Conductive thin films can be selectively deposited by vapor deposition processes, such as by atomic layer deposition type processes. Such films find use, for example, in integrated circuits (IC) and magnetic recording media.
  • vapor deposition processes such as by atomic layer deposition type processes.
  • Such films find use, for example, in integrated circuits (IC) and magnetic recording media.
  • ruthenium and other noble metals can be used in a wide variety of applications including integrated circuits and magnetic recording media.
  • ruthenium may be used as an electrode material in transistors, particularly those where silicon oxide is replaced by high-k dielectrics. They can also be used as copper seed layers in metallization processes.
  • Noble metals are advantageous because they tend not to oxidize or otherwise corrode.
  • Noble metal films can also be used for capacitor electrodes of dynamic random access memories (DRAMs).
  • Noble metals are also a potential electrode material for nonvolatile ferroelectric memories.
  • thin noble metal films find potential use in magnetic recording technology.
  • a thin Ru film may be used for separating two ferromagnetic layers.
  • a preferred ALD process comprises alternately contacting a first surface and a second surface of a substrate with a noble metal precursor and a second reactant, such that a thin noble metal film is selectively formed on the first surface relative to the second surface.
  • the first surface may be, for example, a high-k material, a metal or a conductive metal compound, such as a metal nitride or metal oxide.
  • the second surface preferably comprises a lower k insulator, such as a form of silicon oxide or silicon nitride.
  • the second surface may comprise SiO 2 or silicon oxynitride.
  • the atomic layer deposition reactions are preferably carried out at a temperature less than about 400° C., more preferably less than about 350° C.
  • a gate electrode is formed by a method comprising depositing and patterning a gate dielectric layer and selectively depositing a noble metal such as ruthenium over the gate dielectric layer by a vapor phase deposition process, preferably an atomic layer deposition process.
  • an interface layer is formed on the substrate.
  • the interface layer may comprise, for example, silicon oxide or silicon nitride.
  • a layer of high-k material is deposited over the interface layer and patterned. Ruthenium or another noble metal is selectively deposited over the high-k material by a vapor deposition process, more preferably an atomic layer deposition process.
  • ALD processes for depositing noble metal preferably comprise contacting the substrate with alternating and sequential pulses of a noble metal precursor, such as a ruthenium precursor, and a second reactant, such as an oxygen precursor.
  • the noble metal precursor is preferably a cyclopentadienyl compound, more preferably an ethyl cyclopentadienyl compound, such as Ru(EtCp) 2.
  • FIGS. 1-6 are schematic cross-sections of partially fabricated integrated circuits, illustrating a process flow for the formation of a gate electrode utilizing a selective noble metal deposition process.
  • FIGS. 7-9 are schematic cross-sections of partially fabricated integrated circuits, illustrating another process flow for the formation of a gate electrode utilizing a selective noble metal deposition process.
  • FIGS. 10-16 are schematic cross-sections of partially fabricated integrated circuits, illustrating a gate-last process flow for the formation of a gate electrode utilizing selective noble metal deposition.
  • FIGS. 17-23 are schematic cross-sections of partially fabricated integrated circuits, illustrating another gate-last process flow for the formation of a gate electrode utilizing selective noble metal deposition.
  • Ruthenium thin films and thin films comprising other noble metals can be selectively deposited on a substrate by vapor phase deposition processes, such as atomic layer deposition (ALD) type processes.
  • the substrate includes at least a first surface and a second surface, which differ in material composition and properties.
  • the first surface is preferably susceptible to the vapor phase deposition process, such as an ALD process, used to form the desired noble metal layer while the second surface is substantially insensitive to the same deposition process.
  • the noble metal is selectively deposited on the first surface relative to the second surface.
  • deposition occurs on the first surface but not on the second surface.
  • the film is deposited selectively on the first surface, some deposition on the second surface is possible. Thus, in other embodiments deposition occurs to a greater extent on the first surface than the second surface in a given time.
  • noble metals are readily deposited on many high-k materials, metals, metal nitrides, and other conductive metal compounds from vapor phase reactants. For example, they can be deposited by ALD. However, they are not readily deposited on lower k materials, such as silicon oxides and silicon nitrides.
  • a thin film containing noble metal is selectively deposited on a first surface comprising a high-k material while avoiding deposition on a second surface comprising a lower k insulator such as a silicon oxide, silicon nitride, silicon oxynitride, fluorinated silica glass (FSG), carbon doped silicon oxide (SiOC) or material containing more than 50% of silicon oxide.
  • a lower k insulator such as a silicon oxide, silicon nitride, silicon oxynitride, fluorinated silica glass (FSG), carbon doped silicon oxide (SiOC) or material containing more than 50% of silicon oxide.
  • the thin film comprising one or more noble metals is selectively deposited on a first surface comprising a metal, metal nitride, metal carbide, metal boride, other conductive metal compound or mixtures thereof, while avoiding deposition on a second surface comprising an insulating material., such as a low k insulator
  • an ALD type process is employed to selectively deposit the noble metal containing film.
  • High-k generally refers to a dielectric material having a dielectric constant (k) value greater than that of silicon oxide.
  • the high-k material has a dielectric constant greater than 5, more preferably greater than about 10.
  • Exemplary high-k materials include, without limitation, HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , Ta 2 O 5 , lanthanide oxides and mixtures thereof, silicates and materials such as YSZ (yttria-stabilized zirconia), BST, BT, ST, and SBT.
  • Metals, metal nitrides, metal carbides, metal borides, conductive oxides and other conductive metal compounds that can serve as substrate materials over which noble metals can be selectively deposited may include, for example and without limitation, selected from the group consisting of Ta, TaN, TaC x , TaB x , Ti, TiN, TiC x , TiB x , Nb, NbN, NbC X , NbB x Mo, MoN, MoC x , MoB x , W, WN, WC x , WB x , V, Cr, Fe, Cu, Co, Ni, Cd, Zn, Al, Ag, Au, Ru, RuO x , Rh, Pt, Pd, Ir, IrO x and Os.
  • ALD type processes are based on controlled, self-limiting surface reactions of the precursor chemicals. Gas phase reactions are avoided by feeding the precursors alternately and sequentially into the reaction chamber. Vapor phase reactants are separated from each other in the reaction chamber, for example, by removing excess reactants and/or reactant by-products from the reaction chamber between reactant pulses. This may be accomplished with an evacuation step and/or with an inactive gas pulse or purge.
  • the substrate is loaded in a reaction chamber and is heated to a suitable deposition temperature, generally at lowered pressure.
  • Deposition temperatures are maintained below the precursor thermal decomposition temperature but at a high enough level to avoid condensation of reactants and to provide the activation energy for the desired surface reactions.
  • the appropriate temperature window for any given ALD reaction will depend upon the surface termination and reactant species involved.
  • the temperature is also maintained low enough to ensure the selectivity of the deposition process.
  • the temperature is below about 450° C., more preferably below about 350° C., as discussed in more detail below.
  • a first reactant is conducted into the chamber in the form of gas phase pulse and contacted with the surface of the substrate.
  • the deposition process is self-limiting.
  • conditions are selected such that no more than about one monolayer of the precursor is adsorbed on the substrate surface in a self-limiting manner. Excess first reactant and reaction byproducts, if any, are purged from the reaction chamber, often with a pulse of inert gas such as nitrogen or argon.
  • the second gaseous reactant is pulsed into the chamber where it reacts with the first reactant adsorbed to the surface. Excess second reactant and gaseous by-products of the surface reaction are purged out of the reaction chamber, preferably with the aid of an inert gas. The steps of pulsing and purging are repeated until a thin film of the desired thickness has been selectively formed on the substrate, with each cycle leaving no more than a molecular monolayer.
  • each pulse or phase of each cycle is preferably self-limiting.
  • An excess of reactant precursors is supplied in each phase to saturate the susceptible structure surfaces.
  • Surface saturation ensures reactant occupation of all available reactive sites (subject, for example, to physical size or “steric hindrance” restraints) and thus excellent step coverage.
  • a noble metal thin film is selectively deposited on a first surface of a substrate relative to a second surface by an ALD type process comprising multiple pulsing cycles, each cycle comprising:
  • the noble metal thin film typically comprises multiple monolayers of a single noble metal.
  • the final metal structure may comprise noble metal compounds or alloys comprising two or more different noble metals.
  • the growth can be started with the deposition of platinum and ended with the deposition of ruthenium metal.
  • Noble metals are preferably selected from the group consisting of Pt, Au, Ru, Rh, Ir, Pd and Ag.
  • the substrate can comprise various types of materials.
  • the substrate typically comprises a number of thin films with varying chemical and physical properties.
  • at least one surface of the substrate is insensitive to the vapor phase deposition reaction.
  • this surface comprises a form of silicon oxide or a silicon nitride, such as silicon oxynitride.
  • At least one other surface of the substrate is sensitive to the deposition reaction and may be, for example and without limitation, a dielectric layer, such as aluminum oxide or hafnium oxide, a metal, such as Ta, or a metal nitride, such as TaN.
  • the substrate surface may have been patterned and may comprise structures such as nodes, vias and trenches.
  • Suitable noble metal precursors may be selected by the skilled artisan.
  • metal compounds where the metal is bound or coordinated to oxygen, nitrogen, carbon or a combination thereof are preferred. More preferably metallocene compounds, beta-diketonate compounds and acetamidinato compounds are used.
  • a cyclopentadienyl precursor compound is used, preferably a bis(ethylcyclopentadienyl) compound.
  • preferred metal precursors may be selected from the group consisting of bis(cyclopentadienyl)ruthenium, tris(2,2,6,6-tetramethyl-3,5-heptanedionato)ruthenium and tris(N,N′-diisopropylacetamidinato)ruthenium(III) and their derivatives, such as bis(N,N′-diisopropylacetamidinato)ruthenium(II) dicarbonyl, bis(ethylcyclopentadienyl)ruthenium, bis(pentamethylcyclopentadienyl)ruthenium and bis(2,2,6,6-tetramethyl-3,5-heptanedionato)(1,5-cyclooctadiene)ruthenium(II).
  • the precursor is bis(ethylcyclopentadienyl) ruthenium (Ru(EtCp) 2 ).
  • preferred metal precursors include (trimethyl)methylcyclopentadienylplatinum(IV), platinum (II) acetylacetonato, bis(2,2,6,6-tetramethyl-3,5-heptanedionato)platinum(TI) and their derivatives.
  • ALD processes for depositing noble metal containing films typically comprise alternating pulses of a noble metal precursor and an oxygen-containing reactant.
  • the oxygen-containing reactant pulse may be provided, for example, by pulsing diatomic oxygen gas or a mixture of oxygen and another gas into the reaction chamber.
  • ammonia plasma products or ammonia is used as a second reactant.
  • oxygen is formed inside the reactor, such as by decomposing oxygen containing chemicals.
  • Oxygen containing chemicals that can be decomposed in the reactor to produce oxygen include, without limitation, H 2 O 2 , N 2 O and organic peroxides. Mixtures of such chemicals can also be used.
  • the catalytic formation of an oxygen containing pulse can be provided by introducing into the reactor a pulse of vaporized aqueous solution of H 2 O 2 and conducting the pulse over a catalytic surface inside the reactor and thereafter into the reaction chamber.
  • the catalytic surface is preferably a piece of platinum or palladium.
  • the oxygen-containing reagent comprises free-oxygen or ozone, more preferably molecular oxygen.
  • the oxygen-containing reagent is preferably pure molecular diatomic oxygen, but can also be a mixture of oxygen and inactive gas, for example, nitrogen or argon.
  • a preferred oxygen-containing reagent is air.
  • the noble metal precursor employed in the ALD type processes may be solid, liquid or gaseous material, provided that the metal precursor is in vapor phase before it is conducted into the reaction chamber and contacted with the substrate surface.
  • “Pulsing” a vaporized precursor onto the substrate means that the precursor vapor is conducted into the chamber for a limited period of time. Typically, the pulsing time is from about 0.05 to 10 seconds. However, depending on the substrate type and its surface area, the pulsing time may be even higher than 10 seconds
  • the noble metal precursor is pulsed for from 0.05 to 10 seconds, more preferably for from 0.5 to 3 seconds and most preferably for about 0.5 to 1.0 seconds.
  • the oxygen-containing precursor is preferably pulsed for from about 0.05 to 10 seconds, more preferably for from 1 to 5 seconds, most preferably about for from 2 to 3 seconds. Pulsing times can be on the order of minutes in some cases. The optimum pulsing time can be readily determined by the skilled artisan based on the particular circumstances.
  • the mass flow rate of the noble metal precursor can be determined by the skilled artisan. In one embodiment, for deposition on 300 mm wafers the flow rate of noble metal precursor is preferably between about 1 and 1000 sccm without limitation, more preferably between about 100 and 500 sccm.
  • the mass flow rate of the noble metal precursor is usually lower than the mass flow rate of oxygen, which is usually between about 10 and 10000 sccm without limitation, more preferably between about 100-2000 sccm and most preferably between 100-1000 sccm.
  • Purging the reaction chamber means that gaseous precursors and/or gaseous byproducts formed in the reaction between the precursors are removed from the reaction chamber, such as by evacuating the chamber with a vacuum pump and/or by replacing the gas inside the reactor with an inert gas such as argon or nitrogen.
  • Typical purging times are from about 0.05 to 20 seconds, more preferably between about 1 and 10, and still more preferably between about 1 and 2 seconds.
  • the pressure in the reaction space is typically between about 0.01 and 20 mbar, more preferably between about 1 and 10 mbar.
  • the substrate Before starting the deposition of the film, the substrate is typically heated to a suitable growth temperature.
  • the growth temperature of the metal thin film is between about 150° C. and about 450° C., more preferably between about 200° C. and about 400° C.
  • the preferred deposition temperature may vary depending on a number of factors such as, and without limitation, the reactant precursors, the pressure, flow rate, the arrangement of the reactor, and the composition of the substrate including the nature of the material to be deposited on and the nature of the material on which deposition is to be avoided.
  • the specific growth temperature may be selected by the skilled artisan using routine experimentation in view of the present disclosure to maximize the selectivity of the process.
  • the processing time depends on the thickness of the layer to be produced and the growth rate of the film.
  • the growth rate of a thin film is determined as thickness increase per one cycle.
  • One cycle consists of the pulsing and purging steps of the precursors and the duration of one cycle is typically between about 0.2 and 30 seconds, more preferably between about 1 and 10 seconds, but it can be on order of minutes or more in some cases.
  • ALD reactors many other kinds of reactors capable of ALD growth of thin films, including CVD reactors equipped with appropriate equipment and means for pulsing the precursors, can be employed for carrying out the processes of the present invention.
  • reactants are kept separate until reaching the reaction chamber, such that shared lines for the precursors are minimized.
  • other arrangements are possible, such as the use of a pre-reaction chamber as described in U.S. application No. 10/929,348, filed Aug. 30, 2004 and Ser. No. 09/836,674, filed Apr. 16, 2001, incorporated herein by reference.
  • the growth processes can optionally be carried out in a reactor or reaction space connected to a cluster tool.
  • a cluster tool because each reaction space is dedicated to one type of process, the temperature of the reaction space in each module can be kept constant, which clearly improves the throughput compared to a reactor in which is the substrate is heated up to the process temperature before each run.
  • a first surface such as a high-k material
  • a second surface such as a silicon oxide or a silicon nitride surface
  • FIGS. 1 through 21 Several embodiments are illustrated in FIGS. 1 through 21 . Other processes that take advantage of the ability to selectively deposit noble metals will be apparent to the skilled artisan.
  • a silicon substrate 10 is illustrated comprising a layer of native oxide 50 .
  • the native oxide 50 is removed by etching, leaving the bare substrate 10 as shown in FIG. 2 .
  • the surface of the substrate is then prepared for deposition of a high-k layer by ALD, such as by the deposition of a thin interfacial layer.
  • a thin chemical oxide or oxynitride may be formed on the surface.
  • a thermal oxide is grown on the substrate.
  • the thin interfacial layer is from about 2 to about 15 angstroms thick.
  • FIG. 3 illustrates a thin layer interfacial layer 100 of Silicon oxide grown over the substrate 10 .
  • a thin layer of high-k material 200 is subsequently deposited over the interfacial layer 100 to form the structure illustrated in FIG. 4 .
  • the high-k material 200 is then patterned such that it remains over the channel region 60 and not over the regions 70 that will become the source and drain, as illustrated in FIG. 5 .
  • a layer of Ru 300 is selectively deposited over the patterned high-k material 200 by a vapor deposition process, preferably ALD, and patterned (if necessary or desired) to form the structure illustrated in FIG. 6 .
  • the Ru forms the gate electrode.
  • another conductive material such as a metal or poly-Si, is deposited over the selectively deposited Ru.
  • the additional conductive material is selectively deposited over the ruthenium to form a gate electrode.
  • the additional conductive material may be patterned, if necessary or desired. Further processing steps, such as spacer deposition and source/drain implantation will be apparent to the skilled artisan.
  • FIGS. 7-9 Another process flow is illustrated in FIGS. 7-9 .
  • a layer of high-k material 200 is deposited over a silicon substrate 10 and patterned.
  • the substrate may have been treated prior to deposition of the high-k material 200 .
  • a layer of native oxide may have been removed and the surface treated to facilitate high-k deposition.
  • a layer of silicon oxide 100 is formed over the substrate 10 and covers the high-k material 200 , as illustrated in FIG. 8 .
  • the silicon oxide layer 100 is planarized to expose the underlying high-k layer 200 .
  • a layer of ruthenium 300 is selectively deposited over the high-k material 200 to form the gate electrode structure shown in FIG. 9 .
  • the Ru layer forms the gate electrode, while in other embodiments a further conductive material may be deposited over the Ru and patterned, if necessary or desired, to form the gate electrode.
  • FIG. 10 shows a silicon substrate 10 with a layer of native oxide 50 .
  • the native oxide 50 is removed by etching, leaving the bare silicon substrate 10 .
  • a silicon oxide or silicon nitride interface layer 100 with a thickness of about 2-15 ⁇ is formed over the bare substrate 10 to produce the structure illustrated in FIG. 12 .
  • a high-k layer 200 is deposited, preferably by ALD, over the interface layer 100 to form the structure of FIG. 13 . This is followed by deposition of a silicon oxide layer 400 ( FIG. 14 ).
  • the silicon oxide layer 400 is patterned to expose the underlying high-k layer 200 ( FIG. 15 ).
  • a layer of ruthenium or another noble metal 300 is subsequently deposited selectively over the exposed high-k layer 200 to form a gate electrode as illustrated in FIG. 16A . Further process steps, such as deposition of conductor or contact metals and patterning will be apparent to the skilled artisan.
  • the ruthenium layer 300 need not fill the space over the high-k layer 200 . That is, in some embodiments the ruthenium layer 300 may not reach the upper surface of the silicon oxide layer 400 as illustrated in FIG. 16B .
  • a conductor 320 is deposited over the ruthenium layer 300 ( FIG. 16C ). The conductor is subsequently polished or otherwise etched back to form the gate electrode (not shown).
  • a silicon substrate 10 covered with native oxide 50 is provided ( FIG. 17 ).
  • the native oxide 50 is optionally removed, followed by deposition of a layer of silicon oxide 100 over the substrate as shown in FIG. 18 .
  • the silicon oxide layer 100 is etched to form a trench and the exposed surface 25 ( FIG. 19 ) is prepared for deposition of a high-k dielectric layer by pretreatment or deposition of an interfacial layer 120 as shown in FIG. 20 .
  • the interfacial layer 120 may comprise, for example, a thermally or chemically grown ultrathin silicon oxide or silicon nitride.
  • a high-k layer 200 is then deposited by a vapor deposition process, preferably by an ALD process, over the entire structure ( FIG. 21 ).
  • the high-k material is removed from over the silicon oxide 100 to produce the structure illustrated in FIG. 22 . This may be accomplished, for example, by filling the space over the interface layer 120 with a resist material, planarizing or otherwise etching back the resulting structure down to the top of the silicon oxide layer 100 and removing the resist material (not shown). Finally, a ruthenium layer 300 is selectively deposited over the high-k layer 200 by atomic layer deposition ( FIG. 23 ).
  • ruthenium selectively deposits on the high-k material and not on the silicon oxide or oxynitride, it is not necessary to mask the oxide prior to deposition of the gate electrode material in each of these process flows.
  • noble metal deposition can be followed with a short wet etch or other clean up process to ensure removal of any small amount of noble metal or noble metal compound left on the low k insulator, such as if there is less than perfect selectivity.
  • the process flows can also save valuable and expensive materials and, depending on the particular circumstances, can avoid the sometimes difficult etching of noble metals or noble metal compounds.
  • the ruthenium may form the entire gate electrode.
  • the gate electrode comprises a further conductive material such as a metal or poly-silicon that has been deposited on the ruthenium.
  • the additional conductive material may be deposited by ALD or by another deposition process, such as by CVD or PVD. The deposition may be selective, or may be followed by patterning steps.
  • the high-k material is also deposited by an ALD process.
  • the high-k material preferably has a k value of greater than or equal to 5, more preferably greater than or equal to 10, and even more preferably greater than or equal to 20.
  • Exemplary high-k materials include HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , Ta 2 O 5 , Sc 2 O 3 , lanthanide oxides and mixtures thereof, and complex oxides such as silicates, yttria-stabilized zirconia (YSZ), barium strontium titanate (BST), strontium titanate (ST), strontium bismuth tantalate (SBT) and bismuth tantalate (BT).
  • YSZ yttria-stabilized zirconia
  • BST barium strontium titanate
  • ST strontium titanate
  • SBT strontium bismuth tantalate
  • BT bismuth tantalate
  • Ruthenium thin films were deposited on 300 mm wafers with various materials formed thereover from alternating pulses of bis(ethylcyclopentadienyl)ruthenium (Ru(EtCp) 2 ) and oxygen (O 2 ) at a temperature of about 370° C.
  • the pulse length of the evaporated ruthenium precursor was about 0.7 seconds and was followed by a purge with an inert gas that lasted from about 2 seconds.
  • the pulse length of the oxygen-containing reactant was about 2 seconds and the purge thereafter was about 2 seconds.
  • Ruthenium was found to grow using this process on TaN, Al 2 O 3 , Ta and HfO 2 surfaces.
  • the typical growth rate was about from 0.5 to 0.9 ⁇ /cycle on these surfaces, not counting incubation time.
  • the incubation time for Ru growth was found to be about 50-100 cycles on TaN, 50-100 cycles on Al 2 O 3 , about 50 cycles on Ta and virtually zero on HfO 2 .

Abstract

Processes are provided for selectively depositing thin films comprising one or more noble metals on a substrate by vapor deposition processes. In some embodiments, atomic layer deposition (ALD) processes are used to deposit a noble metal containing thin film on a high-k material, metal, metal nitride or other conductive metal compound while avoiding deposition on a lower k insulator such as silicon oxide. The ability to deposit on a first surface, such as a high-k material, while avoiding deposition on a second surface, such as a silicon oxide or silicon nitride surface, may be utilized, for example, in the formation of a gate electrode.

Description

    REFERENCE TO RELATED APPLICATIONS
  • The present application claims priority to U.S. provisional application No. 60/662,144, filed Mar. 15, 2005 and is related to U.S. provisional application No. 60/662,145, filed Mar. 15, 2005, each of which is hereby incorporated by reference in its entirety.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • Conductive thin films can be selectively deposited by vapor deposition processes, such as by atomic layer deposition type processes. Such films find use, for example, in integrated circuits (IC) and magnetic recording media.
  • 2. Description of the Related Art
  • Thin films of ruthenium and other noble metals can be used in a wide variety of applications including integrated circuits and magnetic recording media. For example, ruthenium may be used as an electrode material in transistors, particularly those where silicon oxide is replaced by high-k dielectrics. They can also be used as copper seed layers in metallization processes. Noble metals are advantageous because they tend not to oxidize or otherwise corrode.
  • Noble metal films can also be used for capacitor electrodes of dynamic random access memories (DRAMs). Noble metals are also a potential electrode material for nonvolatile ferroelectric memories.
  • In addition to electrode applications, thin noble metal films find potential use in magnetic recording technology. In anti-ferromagnetically coupled recording media, for example, a thin Ru film may be used for separating two ferromagnetic layers.
  • SUMMARY OF THE INVENTION
  • Thin films of noble metals can be selectively deposited using vapor deposition processes, such as atomic layer deposition (ALD). In some embodiments, a preferred ALD process comprises alternately contacting a first surface and a second surface of a substrate with a noble metal precursor and a second reactant, such that a thin noble metal film is selectively formed on the first surface relative to the second surface. The first surface may be, for example, a high-k material, a metal or a conductive metal compound, such as a metal nitride or metal oxide. The second surface preferably comprises a lower k insulator, such as a form of silicon oxide or silicon nitride. For example and without limitation, the second surface may comprise SiO2 or silicon oxynitride. The atomic layer deposition reactions are preferably carried out at a temperature less than about 400° C., more preferably less than about 350° C.
  • In some preferred embodiments, a gate electrode is formed by a method comprising depositing and patterning a gate dielectric layer and selectively depositing a noble metal such as ruthenium over the gate dielectric layer by a vapor phase deposition process, preferably an atomic layer deposition process.
  • In other preferred methods for forming a gate electrode on a silicon substrate, an interface layer is formed on the substrate. The interface layer may comprise, for example, silicon oxide or silicon nitride. A layer of high-k material is deposited over the interface layer and patterned. Ruthenium or another noble metal is selectively deposited over the high-k material by a vapor deposition process, more preferably an atomic layer deposition process.
  • ALD processes for depositing noble metal preferably comprise contacting the substrate with alternating and sequential pulses of a noble metal precursor, such as a ruthenium precursor, and a second reactant, such as an oxygen precursor. The noble metal precursor is preferably a cyclopentadienyl compound, more preferably an ethyl cyclopentadienyl compound, such as Ru(EtCp)2.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1-6 are schematic cross-sections of partially fabricated integrated circuits, illustrating a process flow for the formation of a gate electrode utilizing a selective noble metal deposition process.
  • FIGS. 7-9 are schematic cross-sections of partially fabricated integrated circuits, illustrating another process flow for the formation of a gate electrode utilizing a selective noble metal deposition process.
  • FIGS. 10-16 are schematic cross-sections of partially fabricated integrated circuits, illustrating a gate-last process flow for the formation of a gate electrode utilizing selective noble metal deposition.
  • FIGS. 17-23 are schematic cross-sections of partially fabricated integrated circuits, illustrating another gate-last process flow for the formation of a gate electrode utilizing selective noble metal deposition.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Ruthenium thin films and thin films comprising other noble metals can be selectively deposited on a substrate by vapor phase deposition processes, such as atomic layer deposition (ALD) type processes. The substrate includes at least a first surface and a second surface, which differ in material composition and properties. The first surface is preferably susceptible to the vapor phase deposition process, such as an ALD process, used to form the desired noble metal layer while the second surface is substantially insensitive to the same deposition process. As a result, the noble metal is selectively deposited on the first surface relative to the second surface. In some embodiments deposition occurs on the first surface but not on the second surface. However, although the film is deposited selectively on the first surface, some deposition on the second surface is possible. Thus, in other embodiments deposition occurs to a greater extent on the first surface than the second surface in a given time.
  • At temperatures less than 450° C., noble metals are readily deposited on many high-k materials, metals, metal nitrides, and other conductive metal compounds from vapor phase reactants. For example, they can be deposited by ALD. However, they are not readily deposited on lower k materials, such as silicon oxides and silicon nitrides. Thus, in particular embodiments, a thin film containing noble metal is selectively deposited on a first surface comprising a high-k material while avoiding deposition on a second surface comprising a lower k insulator such as a silicon oxide, silicon nitride, silicon oxynitride, fluorinated silica glass (FSG), carbon doped silicon oxide (SiOC) or material containing more than 50% of silicon oxide. In other embodiments the thin film comprising one or more noble metals is selectively deposited on a first surface comprising a metal, metal nitride, metal carbide, metal boride, other conductive metal compound or mixtures thereof, while avoiding deposition on a second surface comprising an insulating material., such as a low k insulator In preferred embodiments an ALD type process is employed to selectively deposit the noble metal containing film.
  • “High-k” generally refers to a dielectric material having a dielectric constant (k) value greater than that of silicon oxide. Preferably, the high-k material has a dielectric constant greater than 5, more preferably greater than about 10. Exemplary high-k materials include, without limitation, HfO2, ZrO2, Al2O3, TiO2, Ta2O5, lanthanide oxides and mixtures thereof, silicates and materials such as YSZ (yttria-stabilized zirconia), BST, BT, ST, and SBT.
  • Metals, metal nitrides, metal carbides, metal borides, conductive oxides and other conductive metal compounds that can serve as substrate materials over which noble metals can be selectively deposited may include, for example and without limitation, selected from the group consisting of Ta, TaN, TaCx, TaBx, Ti, TiN, TiCx, TiBx, Nb, NbN, NbCX, NbBx Mo, MoN, MoCx, MoBx, W, WN, WCx, WBx, V, Cr, Fe, Cu, Co, Ni, Cd, Zn, Al, Ag, Au, Ru, RuOx, Rh, Pt, Pd, Ir, IrOx and Os.
  • While illustrated in the context of formation of a gate electrode by ALD, the skilled artisan will readily find application for the principles and advantages disclosed herein in other contexts, particularly where selective deposition is desired with high step coverage.
  • ALD type processes are based on controlled, self-limiting surface reactions of the precursor chemicals. Gas phase reactions are avoided by feeding the precursors alternately and sequentially into the reaction chamber. Vapor phase reactants are separated from each other in the reaction chamber, for example, by removing excess reactants and/or reactant by-products from the reaction chamber between reactant pulses. This may be accomplished with an evacuation step and/or with an inactive gas pulse or purge.
  • Briefly, the substrate is loaded in a reaction chamber and is heated to a suitable deposition temperature, generally at lowered pressure. Deposition temperatures are maintained below the precursor thermal decomposition temperature but at a high enough level to avoid condensation of reactants and to provide the activation energy for the desired surface reactions. Of course, the appropriate temperature window for any given ALD reaction will depend upon the surface termination and reactant species involved. Here, the temperature is also maintained low enough to ensure the selectivity of the deposition process. Preferably, the temperature is below about 450° C., more preferably below about 350° C., as discussed in more detail below.
  • A first reactant is conducted into the chamber in the form of gas phase pulse and contacted with the surface of the substrate. Preferably the deposition process is self-limiting. For ALD embodiments, conditions are selected such that no more than about one monolayer of the precursor is adsorbed on the substrate surface in a self-limiting manner. Excess first reactant and reaction byproducts, if any, are purged from the reaction chamber, often with a pulse of inert gas such as nitrogen or argon.
  • For ALD embodiments, the second gaseous reactant is pulsed into the chamber where it reacts with the first reactant adsorbed to the surface. Excess second reactant and gaseous by-products of the surface reaction are purged out of the reaction chamber, preferably with the aid of an inert gas. The steps of pulsing and purging are repeated until a thin film of the desired thickness has been selectively formed on the substrate, with each cycle leaving no more than a molecular monolayer.
  • As mentioned above, each pulse or phase of each cycle is preferably self-limiting. An excess of reactant precursors is supplied in each phase to saturate the susceptible structure surfaces. Surface saturation ensures reactant occupation of all available reactive sites (subject, for example, to physical size or “steric hindrance” restraints) and thus excellent step coverage.
  • According to a preferred embodiment, a noble metal thin film is selectively deposited on a first surface of a substrate relative to a second surface by an ALD type process comprising multiple pulsing cycles, each cycle comprising:
      • pulsing a vaporized noble metal precursor into the reaction chamber to form a molecular layer of the metal precursor on the first surface of the substrate,
      • purging the reaction chamber to remove excess noble metal precursor and reaction by products, if any,
      • providing a pulse of a second reactant, such as an oxygen, ozone, ammonia or ammonia plasma product containing gas onto the substrate,
      • purging the reaction chamber to remove excess second reactant and any gaseous by-products formed in the reaction between the metal precursor layer on the first surface of the substrate and the second reactant, and
      • repeating the pulsing and purging steps until a noble metal thin film of the desired thickness has been formed.
  • The noble metal thin film typically comprises multiple monolayers of a single noble metal. However, in other embodiments, the final metal structure may comprise noble metal compounds or alloys comprising two or more different noble metals. For example, the growth can be started with the deposition of platinum and ended with the deposition of ruthenium metal. Noble metals are preferably selected from the group consisting of Pt, Au, Ru, Rh, Ir, Pd and Ag.
  • The substrate can comprise various types of materials. When manufacturing integrated circuits, the substrate typically comprises a number of thin films with varying chemical and physical properties. In preferred embodiments, at least one surface of the substrate is insensitive to the vapor phase deposition reaction. Preferably, this surface comprises a form of silicon oxide or a silicon nitride, such as silicon oxynitride. At least one other surface of the substrate is sensitive to the deposition reaction and may be, for example and without limitation, a dielectric layer, such as aluminum oxide or hafnium oxide, a metal, such as Ta, or a metal nitride, such as TaN. Further, the substrate surface may have been patterned and may comprise structures such as nodes, vias and trenches.
  • Suitable noble metal precursors may be selected by the skilled artisan. In general, metal compounds where the metal is bound or coordinated to oxygen, nitrogen, carbon or a combination thereof are preferred. More preferably metallocene compounds, beta-diketonate compounds and acetamidinato compounds are used. In some embodiments a cyclopentadienyl precursor compound is used, preferably a bis(ethylcyclopentadienyl) compound.
  • When depositing ruthenium (Ru) thin films, preferred metal precursors may be selected from the group consisting of bis(cyclopentadienyl)ruthenium, tris(2,2,6,6-tetramethyl-3,5-heptanedionato)ruthenium and tris(N,N′-diisopropylacetamidinato)ruthenium(III) and their derivatives, such as bis(N,N′-diisopropylacetamidinato)ruthenium(II) dicarbonyl, bis(ethylcyclopentadienyl)ruthenium, bis(pentamethylcyclopentadienyl)ruthenium and bis(2,2,6,6-tetramethyl-3,5-heptanedionato)(1,5-cyclooctadiene)ruthenium(II). In preferred embodiments, the precursor is bis(ethylcyclopentadienyl) ruthenium (Ru(EtCp)2).
  • When depositing platinum films, preferred metal precursors include (trimethyl)methylcyclopentadienylplatinum(IV), platinum (II) acetylacetonato, bis(2,2,6,6-tetramethyl-3,5-heptanedionato)platinum(TI) and their derivatives.
  • As mentioned above, ALD processes for depositing noble metal containing films typically comprise alternating pulses of a noble metal precursor and an oxygen-containing reactant. The oxygen-containing reactant pulse may be provided, for example, by pulsing diatomic oxygen gas or a mixture of oxygen and another gas into the reaction chamber. In one embodiment, ammonia plasma products or ammonia is used as a second reactant. In other embodiments, oxygen is formed inside the reactor, such as by decomposing oxygen containing chemicals. Oxygen containing chemicals that can be decomposed in the reactor to produce oxygen include, without limitation, H2O2, N2O and organic peroxides. Mixtures of such chemicals can also be used. In other embodiments, the catalytic formation of an oxygen containing pulse can be provided by introducing into the reactor a pulse of vaporized aqueous solution of H2O2 and conducting the pulse over a catalytic surface inside the reactor and thereafter into the reaction chamber. The catalytic surface is preferably a piece of platinum or palladium.
  • In preferred embodiments the oxygen-containing reagent comprises free-oxygen or ozone, more preferably molecular oxygen. The oxygen-containing reagent is preferably pure molecular diatomic oxygen, but can also be a mixture of oxygen and inactive gas, for example, nitrogen or argon.
  • A preferred oxygen-containing reagent is air.
  • The noble metal precursor employed in the ALD type processes may be solid, liquid or gaseous material, provided that the metal precursor is in vapor phase before it is conducted into the reaction chamber and contacted with the substrate surface. “Pulsing” a vaporized precursor onto the substrate means that the precursor vapor is conducted into the chamber for a limited period of time. Typically, the pulsing time is from about 0.05 to 10 seconds. However, depending on the substrate type and its surface area, the pulsing time may be even higher than 10 seconds Preferably, for a 300 mm wafer in a single wafer ALD reactor, the noble metal precursor is pulsed for from 0.05 to 10 seconds, more preferably for from 0.5 to 3 seconds and most preferably for about 0.5 to 1.0 seconds. The oxygen-containing precursor is preferably pulsed for from about 0.05 to 10 seconds, more preferably for from 1 to 5 seconds, most preferably about for from 2 to 3 seconds. Pulsing times can be on the order of minutes in some cases. The optimum pulsing time can be readily determined by the skilled artisan based on the particular circumstances.
  • The mass flow rate of the noble metal precursor can be determined by the skilled artisan. In one embodiment, for deposition on 300 mm wafers the flow rate of noble metal precursor is preferably between about 1 and 1000 sccm without limitation, more preferably between about 100 and 500 sccm. The mass flow rate of the noble metal precursor is usually lower than the mass flow rate of oxygen, which is usually between about 10 and 10000 sccm without limitation, more preferably between about 100-2000 sccm and most preferably between 100-1000 sccm.
  • Purging the reaction chamber means that gaseous precursors and/or gaseous byproducts formed in the reaction between the precursors are removed from the reaction chamber, such as by evacuating the chamber with a vacuum pump and/or by replacing the gas inside the reactor with an inert gas such as argon or nitrogen. Typical purging times are from about 0.05 to 20 seconds, more preferably between about 1 and 10, and still more preferably between about 1 and 2 seconds.
  • The pressure in the reaction space is typically between about 0.01 and 20 mbar, more preferably between about 1 and 10 mbar.
  • Before starting the deposition of the film, the substrate is typically heated to a suitable growth temperature. Preferably, the growth temperature of the metal thin film is between about 150° C. and about 450° C., more preferably between about 200° C. and about 400° C. The preferred deposition temperature may vary depending on a number of factors such as, and without limitation, the reactant precursors, the pressure, flow rate, the arrangement of the reactor, and the composition of the substrate including the nature of the material to be deposited on and the nature of the material on which deposition is to be avoided. The specific growth temperature may be selected by the skilled artisan using routine experimentation in view of the present disclosure to maximize the selectivity of the process.
  • The processing time depends on the thickness of the layer to be produced and the growth rate of the film. In ALD, the growth rate of a thin film is determined as thickness increase per one cycle. One cycle consists of the pulsing and purging steps of the precursors and the duration of one cycle is typically between about 0.2 and 30 seconds, more preferably between about 1 and 10 seconds, but it can be on order of minutes or more in some cases.
  • Examples of suitable reactors that may be used for the deposition of thin films according to the processes of the present invention include commercially available ALD equipment such as the F-120® reactor, Pulsar® reactor and EmerALD™ reactor, available from ASM America, Inc of Phoenix, Ariz. In addition to these ALD reactors, many other kinds of reactors capable of ALD growth of thin films, including CVD reactors equipped with appropriate equipment and means for pulsing the precursors, can be employed for carrying out the processes of the present invention. Preferably, reactants are kept separate until reaching the reaction chamber, such that shared lines for the precursors are minimized. However, other arrangements are possible, such as the use of a pre-reaction chamber as described in U.S. application No. 10/929,348, filed Aug. 30, 2004 and Ser. No. 09/836,674, filed Apr. 16, 2001, incorporated herein by reference.
  • The growth processes can optionally be carried out in a reactor or reaction space connected to a cluster tool. In a cluster tool, because each reaction space is dedicated to one type of process, the temperature of the reaction space in each module can be kept constant, which clearly improves the throughput compared to a reactor in which is the substrate is heated up to the process temperature before each run.
  • Formation of Gate Electrodes Using Selective Deposition
  • The ability to deposit on a first surface, such as a high-k material, while avoiding deposition on a second surface, such as a silicon oxide or a silicon nitride surface, can be utilized in the formation of a gate electrode.
  • Several embodiments are illustrated in FIGS. 1 through 21. Other processes that take advantage of the ability to selectively deposit noble metals will be apparent to the skilled artisan.
  • In FIG. 1, a silicon substrate 10 is illustrated comprising a layer of native oxide 50. The native oxide 50 is removed by etching, leaving the bare substrate 10 as shown in FIG. 2. The surface of the substrate is then prepared for deposition of a high-k layer by ALD, such as by the deposition of a thin interfacial layer. For example, a thin chemical oxide or oxynitride may be formed on the surface. In other embodiments a thermal oxide is grown on the substrate. In one embodiment the thin interfacial layer is from about 2 to about 15 angstroms thick. FIG. 3 illustrates a thin layer interfacial layer 100 of Silicon oxide grown over the substrate 10.
  • A thin layer of high-k material 200 is subsequently deposited over the interfacial layer 100 to form the structure illustrated in FIG. 4. The high-k material 200 is then patterned such that it remains over the channel region 60 and not over the regions 70 that will become the source and drain, as illustrated in FIG. 5. Finally, a layer of Ru 300 is selectively deposited over the patterned high-k material 200 by a vapor deposition process, preferably ALD, and patterned (if necessary or desired) to form the structure illustrated in FIG. 6.
  • In some embodiments the Ru forms the gate electrode. In other embodiments (not shown) another conductive material, such as a metal or poly-Si, is deposited over the selectively deposited Ru. In some embodiments the additional conductive material is selectively deposited over the ruthenium to form a gate electrode. The additional conductive material may be patterned, if necessary or desired. Further processing steps, such as spacer deposition and source/drain implantation will be apparent to the skilled artisan.
  • Another process flow is illustrated in FIGS. 7-9. In FIG. 7, a layer of high-k material 200 is deposited over a silicon substrate 10 and patterned. The substrate may have been treated prior to deposition of the high-k material 200. For example, a layer of native oxide may have been removed and the surface treated to facilitate high-k deposition.
  • A layer of silicon oxide 100 is formed over the substrate 10 and covers the high-k material 200, as illustrated in FIG. 8. The silicon oxide layer 100 is planarized to expose the underlying high-k layer 200. A layer of ruthenium 300 is selectively deposited over the high-k material 200 to form the gate electrode structure shown in FIG. 9. In some embodiments the Ru layer forms the gate electrode, while in other embodiments a further conductive material may be deposited over the Ru and patterned, if necessary or desired, to form the gate electrode.
  • A gate-last approach is illustrated in FIGS. 10-15. FIG. 10 shows a silicon substrate 10 with a layer of native oxide 50. In FIG. 11, the native oxide 50 is removed by etching, leaving the bare silicon substrate 10. A silicon oxide or silicon nitride interface layer 100 with a thickness of about 2-15 Åis formed over the bare substrate 10 to produce the structure illustrated in FIG. 12. A high-k layer 200 is deposited, preferably by ALD, over the interface layer 100 to form the structure of FIG. 13. This is followed by deposition of a silicon oxide layer 400 (FIG. 14). The silicon oxide layer 400 is patterned to expose the underlying high-k layer 200 (FIG. 15). A layer of ruthenium or another noble metal 300 is subsequently deposited selectively over the exposed high-k layer 200 to form a gate electrode as illustrated in FIG. 16A. Further process steps, such as deposition of conductor or contact metals and patterning will be apparent to the skilled artisan.
  • It will be understood by the skilled artisan that the ruthenium layer 300 need not fill the space over the high-k layer 200. That is, in some embodiments the ruthenium layer 300 may not reach the upper surface of the silicon oxide layer 400 as illustrated in FIG. 16B. In a further step, a conductor 320 is deposited over the ruthenium layer 300 (FIG. 16C). The conductor is subsequently polished or otherwise etched back to form the gate electrode (not shown).
  • In another gate last approach a silicon substrate 10 covered with native oxide 50 is provided (FIG. 17). The native oxide 50 is optionally removed, followed by deposition of a layer of silicon oxide 100 over the substrate as shown in FIG. 18. The silicon oxide layer 100 is etched to form a trench and the exposed surface 25 (FIG. 19) is prepared for deposition of a high-k dielectric layer by pretreatment or deposition of an interfacial layer 120 as shown in FIG. 20. The interfacial layer 120 may comprise, for example, a thermally or chemically grown ultrathin silicon oxide or silicon nitride. A high-k layer 200 is then deposited by a vapor deposition process, preferably by an ALD process, over the entire structure (FIG. 21). The high-k material is removed from over the silicon oxide 100 to produce the structure illustrated in FIG. 22. This may be accomplished, for example, by filling the space over the interface layer 120 with a resist material, planarizing or otherwise etching back the resulting structure down to the top of the silicon oxide layer 100 and removing the resist material (not shown). Finally, a ruthenium layer 300 is selectively deposited over the high-k layer 200 by atomic layer deposition (FIG. 23).
  • In each of the illustrated embodiments, additional processing is performed to produce the desired integrated circuit, as will be apparent to the skilled artisan.
  • Because ruthenium selectively deposits on the high-k material and not on the silicon oxide or oxynitride, it is not necessary to mask the oxide prior to deposition of the gate electrode material in each of these process flows. However, if necessary noble metal deposition can be followed with a short wet etch or other clean up process to ensure removal of any small amount of noble metal or noble metal compound left on the low k insulator, such as if there is less than perfect selectivity. The process flows can also save valuable and expensive materials and, depending on the particular circumstances, can avoid the sometimes difficult etching of noble metals or noble metal compounds.
  • As mentioned above, the ruthenium may form the entire gate electrode. However, in some embodiments the gate electrode comprises a further conductive material such as a metal or poly-silicon that has been deposited on the ruthenium. The additional conductive material may be deposited by ALD or by another deposition process, such as by CVD or PVD. The deposition may be selective, or may be followed by patterning steps. Preferably, the high-k material is also deposited by an ALD process.
  • The high-k material preferably has a k value of greater than or equal to 5, more preferably greater than or equal to 10, and even more preferably greater than or equal to 20. Exemplary high-k materials include HfO2, ZrO2, Al2O3, TiO2, Ta2O5, Sc2O3, lanthanide oxides and mixtures thereof, and complex oxides such as silicates, yttria-stabilized zirconia (YSZ), barium strontium titanate (BST), strontium titanate (ST), strontium bismuth tantalate (SBT) and bismuth tantalate (BT).
  • The following non-limiting examples will illustrate the invention in more detail.
  • EXAMPLE 1
  • Ruthenium thin films were deposited on 300 mm wafers with various materials formed thereover from alternating pulses of bis(ethylcyclopentadienyl)ruthenium (Ru(EtCp)2) and oxygen (O2) at a temperature of about 370° C.
  • The pulse length of the evaporated ruthenium precursor was about 0.7 seconds and was followed by a purge with an inert gas that lasted from about 2 seconds. The pulse length of the oxygen-containing reactant was about 2 seconds and the purge thereafter was about 2 seconds.
  • Ruthenium was found to grow using this process on TaN, Al2O3, Ta and HfO2 surfaces. The typical growth rate was about from 0.5 to 0.9 Å/cycle on these surfaces, not counting incubation time. The incubation time for Ru growth was found to be about 50-100 cycles on TaN, 50-100 cycles on Al2O3, about 50 cycles on Ta and virtually zero on HfO2.
  • However, even 450 cycles of the same Ru process did not produce a measurable and conductive film on a thermal silicon oxide surface produced by a wet oxide process.
  • Where deposition was observed, the rate was independent of the Ru(EtCp)2 dose, indicating that film growth proceeded in the self-limiting manner that is characteristic of ALD.
  • Although the foregoing invention has been described in terms of certain preferred embodiments, other embodiments will be apparent to those of ordinary skill in the art. Moreover, although illustrated in connection with particular process flows and structures, the skilled artisan will appreciate variations of such schemes for which the methods disclosed herein will have utility. Additionally, other combinations, omissions, substitutions and modification will be apparent to the skilled artisan, in view of the disclosure herein. Accordingly, the present invention is not intended to be limited by the recitation of the preferred embodiments, but is instead to be defined by reference to the appended claims.

Claims (37)

1. A method for selectively depositing a thin film comprising one or more noble metals on a substrate comprising a first surface and a second surface, the method comprising:
contacting the substrate with a gaseous noble metal precursor;
providing a second reactant gas pulse comprising oxygen to the reaction chamber; and
repeating until a thin film of a desired thickness is obtained selectively on the first surface,
wherein the second surface comprises a material selected from the group consisting of silicon oxides, silicon nitrides, silicon oxynitrides, fluorinated silica glass (FSG), carbon doped silicon oxide (SiOC) and materials containing more than about 50% silicon oxide and wherein the temperature is below about 400° C.
2. The process of claim 1, additionally comprising removing excess noble metal precursor from the reaction chamber after contacting the substrate with the noble metal precursor and prior to providing the second reactant gas pulse.
3. The process of claim 1, wherein the thin film is not formed on the second surface.
4. The process of claim 1, wherein the thin film that is obtained is thicker on the first surface than on the second surface.
5. The process of claim 1, wherein the second surface is SiO2.
6. The process of claim 1, wherein the second surface is silicon oxynitride.
7. The process of claim 1, wherein the noble metal is ruthenium.
8. The process of claim 7, wherein the noble metal precursor is Ru(EtCp)2.
9. The process of claim 1, wherein the first surface comprises a high-k material.
10. The process of claim 9, wherien the high-k material is selected from the group consisting of HfO2, ZrO2, Al2O3, TiO2, Ta2O5, Sc2O3, lanthanide oxides and mixtures thereof, silicates, yttria-stabilized zirconia (YSZ), barium strontium titanate (BST), strontium titanate (ST), strontium bismuth tantalate (SBT) and bismuth tantalate (BT).
11. The process of claim 9, wherein the high-k material is hafnium oxide (HfO2).
12. The process of claim 9, wherein the high-k material has a dielectric constant greater than 10.
13. The process of claim 1, wherein the first surface comprises a material selected from the group consisting of metals, metal nitrides, metal carbides, metal borides, conductive oxides and mixtures thereof.
14. The process of claim 13, wherein the first surface comprises a material selected from the group consisting of Ta, TaN, TaCx, TaBx, Ti, TiN, TiCx, TiBx, Nb, NbN, NbCx, NbBx Mo, MoN, MoCx, MoBx, W, WN, WCx, WBx, V, Cr, Fe, Cu, Co, Ni, Cd, Zn, Al, Ag, Au, Ru, RuOx, Rh, Pt, Pd, Ir, IrOx and Os.
15. The process of claim 1, wherein the second reactant gas is provided by pulsing oxygen into the reaction chamber.
16. A method of fabricating a semiconductor device, comprising
forming a patterned gate dielectric layer over a semiconductor substrate; and
forming a gate electrode over the gate dielectric layer,
wherein forming the gate electrode comprises selectively depositing a film comprising one or more noble metals over the gate dielectric layer by a vapor deposition process.
17. The process of claim 16, wherein the vapor deposition process is an atomic layer deposition process.
18. The method of claim 17, wherein the atomic layer deposition process comprises one or more deposition cycles, each cycle comprising a sequence of alternating and repeated exposure of the substrate to a ruthenium precursor compound.
19. The process of claim 17, wherein the atomic layer deposition process is carried out a temperature between about 150° C. and about 400° C.
20. The process of claim 16, wherein the film comprises ruthenium.
21. The method of claim 20, wherein forming the gate electrode additionally comprises depositing a different conductive material over the film comprising ruthenium.
22. The process of claim 16, wherein the dielectric layer comprises a high-k material.
23. The process of claim 22, wherein the high-k material is hafnium oxide (HfO2).
24. A method for forming a gate electrode on a silicon substrate comprising:
forming an interface layer on the substrate;
depositing a first thin film comprising a high k material, metal or conductive metal compound over the interface layer;
patterning the conductive material; and
selectively depositing a second thin film containing noble metal over the patterned conductive material by a vapor deposition process.
25. The method of claim 24, wherein the conductive metal compound is selected from the group consisting of metal nitrides, metal borides and conductive metal oxides.
26. The method of claim 25, wherein the first thin film comprises a high-k material.
27. The method of claim 24, wherein the vapor deposition process is an atomic layer deposition process.
28. The method of claim 27, wherein the atomic layer deposition process comprises alternate pulses of a ruthenium precursor and an oxygen-containing precursor.
29. The method of claim 28, wherein the ruthenium precursor is Ru(EtCp)2.
30. The method of claim 24, wherein the interface layer comprises a material selected from the group consisting of silicon oxides, silicon nitrides, silicon oxynitrides, fluorinated silica glass (FSG), carbon doped silicon oxide (SiOC) and materials containing more than 50% silicon oxide.
31. The method of claim 24, wherien the second thin film is not deposited on the interface layer.
32. The method of claim 24, wherein the first thin film is deposited by an atomic layer deposition process.
33. The method of claim 24, wherein the vapor deposition process is carried out at less than about 400° C.
34. The method of claim 24, wherein the interface layer has a thickness of between about 2 Å and 15 Å.
35. The method of claim 24, additionally comprising removing native oxide prior to forming the interface layer.
36. A method for selectively depositing a noble metal layer on a substrate comprising a first surface and a second insulating surface, the first surface comprising a high k material, metal, metal nitride or conductive metal oxide, the method comprising depositing a layer comprising a noble metal on the first surface relative to the second surface using an atomic layer deposition (ALD) process at a temperature of less than about 400° C.
37. The method of claim 36, wherein the insulating surface comprises a form of silicon oxide.
US11/376,704 2005-03-15 2006-03-14 Selective deposition of noble metal thin films Active 2026-09-28 US7666773B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US11/376,704 US7666773B2 (en) 2005-03-15 2006-03-14 Selective deposition of noble metal thin films
US12/649,817 US7985669B2 (en) 2005-03-15 2009-12-30 Selective deposition of noble metal thin films
US13/188,087 US8927403B2 (en) 2005-03-15 2011-07-21 Selective deposition of noble metal thin films
US14/557,874 US9469899B2 (en) 2005-03-15 2014-12-02 Selective deposition of noble metal thin films

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US66214405P 2005-03-15 2005-03-15
US66214505P 2005-03-15 2005-03-15
US11/376,704 US7666773B2 (en) 2005-03-15 2006-03-14 Selective deposition of noble metal thin films

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/649,817 Continuation US7985669B2 (en) 2005-03-15 2009-12-30 Selective deposition of noble metal thin films

Publications (3)

Publication Number Publication Date
US20070026654A1 US20070026654A1 (en) 2007-02-01
US20080200019A9 true US20080200019A9 (en) 2008-08-21
US7666773B2 US7666773B2 (en) 2010-02-23

Family

ID=37694930

Family Applications (4)

Application Number Title Priority Date Filing Date
US11/376,704 Active 2026-09-28 US7666773B2 (en) 2005-03-15 2006-03-14 Selective deposition of noble metal thin films
US12/649,817 Active US7985669B2 (en) 2005-03-15 2009-12-30 Selective deposition of noble metal thin films
US13/188,087 Active US8927403B2 (en) 2005-03-15 2011-07-21 Selective deposition of noble metal thin films
US14/557,874 Active US9469899B2 (en) 2005-03-15 2014-12-02 Selective deposition of noble metal thin films

Family Applications After (3)

Application Number Title Priority Date Filing Date
US12/649,817 Active US7985669B2 (en) 2005-03-15 2009-12-30 Selective deposition of noble metal thin films
US13/188,087 Active US8927403B2 (en) 2005-03-15 2011-07-21 Selective deposition of noble metal thin films
US14/557,874 Active US9469899B2 (en) 2005-03-15 2014-12-02 Selective deposition of noble metal thin films

Country Status (1)

Country Link
US (4) US7666773B2 (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070264837A1 (en) * 2006-05-09 2007-11-15 Willy Rachmady Thin transition layer between a group iii-v substrate and a high-k gate dielectric layer
US20090104777A1 (en) * 2007-10-17 2009-04-23 Asm Genitech Korea Ltd. Methods of depositing a ruthenium film
US7955979B2 (en) 2000-05-15 2011-06-07 Asm International N.V. Method of growing electrical conductors
US8025922B2 (en) 2005-03-15 2011-09-27 Asm International N.V. Enhanced deposition of noble metals
US8084104B2 (en) 2008-08-29 2011-12-27 Asm Japan K.K. Atomic composition controlled ruthenium alloy film formed by plasma-enhanced atomic layer deposition
US8133555B2 (en) 2008-10-14 2012-03-13 Asm Japan K.K. Method for forming metal film by ALD using beta-diketone metal complex
US8329569B2 (en) 2009-07-31 2012-12-11 Asm America, Inc. Deposition of ruthenium or ruthenium dioxide
US20140291760A1 (en) * 2013-03-28 2014-10-02 International Business Machines Corporation Fet semiconductor device with low resistance and enhanced metal fill
US8927403B2 (en) 2005-03-15 2015-01-06 Asm International N.V. Selective deposition of noble metal thin films
US9129897B2 (en) 2008-12-19 2015-09-08 Asm International N.V. Metal silicide, metal germanide, methods for making the same
US9379011B2 (en) 2008-12-19 2016-06-28 Asm International N.V. Methods for depositing nickel films and for making nickel silicide and nickel germanide
US9607842B1 (en) 2015-10-02 2017-03-28 Asm Ip Holding B.V. Methods of forming metal silicides
US10204790B2 (en) 2015-07-28 2019-02-12 Asm Ip Holding B.V. Methods for thin film deposition
US11421321B2 (en) 2015-07-28 2022-08-23 Asm Ip Holding B.V. Apparatuses for thin film deposition

Families Citing this family (230)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7491634B2 (en) * 2006-04-28 2009-02-17 Asm International N.V. Methods for forming roughened surfaces and applications thereof
US9139906B2 (en) * 2001-03-06 2015-09-22 Asm America, Inc. Doping with ALD technology
US7279423B2 (en) * 2002-10-31 2007-10-09 Intel Corporation Forming a copper diffusion barrier
US7476618B2 (en) * 2004-10-26 2009-01-13 Asm Japan K.K. Selective formation of metal layers in an integrated circuit
US20070014919A1 (en) * 2005-07-15 2007-01-18 Jani Hamalainen Atomic layer deposition of noble metal oxides
US8993055B2 (en) 2005-10-27 2015-03-31 Asm International N.V. Enhanced thin film deposition
US7435484B2 (en) * 2006-09-01 2008-10-14 Asm Japan K.K. Ruthenium thin film-formed structure
KR101427142B1 (en) * 2006-10-05 2014-08-07 에이에스엠 아메리카, 인코포레이티드 ALD of metal silicate films
US20080124484A1 (en) * 2006-11-08 2008-05-29 Asm Japan K.K. Method of forming ru film and metal wiring structure
WO2008140784A1 (en) 2007-05-11 2008-11-20 Sdc Materials, Inc. Nano-skeletal catalyst
US20090087339A1 (en) * 2007-09-28 2009-04-02 Asm Japan K.K. METHOD FOR FORMING RUTHENIUM COMPLEX FILM USING Beta-DIKETONE-COORDINATED RUTHENIUM PRECURSOR
US8507401B1 (en) 2007-10-15 2013-08-13 SDCmaterials, Inc. Method and system for forming plug and play metal catalysts
US7655564B2 (en) * 2007-12-12 2010-02-02 Asm Japan, K.K. Method for forming Ta-Ru liner layer for Cu wiring
KR20090067505A (en) * 2007-12-21 2009-06-25 에이에스엠지니텍코리아 주식회사 Method of depositing ruthenium film
US7799674B2 (en) * 2008-02-19 2010-09-21 Asm Japan K.K. Ruthenium alloy film for copper interconnects
US8545936B2 (en) 2008-03-28 2013-10-01 Asm International N.V. Methods for forming carbon nanotubes
US8288274B2 (en) * 2008-04-21 2012-10-16 Hynix Semiconductor Inc. Method of forming noble metal layer using ozone reaction gas
US20110020546A1 (en) * 2009-05-15 2011-01-27 Asm International N.V. Low Temperature ALD of Noble Metals
US9126191B2 (en) * 2009-12-15 2015-09-08 SDCmaterials, Inc. Advanced catalysts for automotive applications
US8652992B2 (en) 2009-12-15 2014-02-18 SDCmaterials, Inc. Pinning and affixing nano-active material
JP5562434B2 (en) 2010-11-19 2014-07-30 株式会社日立国際電気 Semiconductor device manufacturing method, substrate processing method, substrate processing apparatus, and program
US8669202B2 (en) 2011-02-23 2014-03-11 SDCmaterials, Inc. Wet chemical and plasma methods of forming stable PtPd catalysts
US11527774B2 (en) 2011-06-29 2022-12-13 Space Charge, LLC Electrochemical energy storage devices
US10601074B2 (en) 2011-06-29 2020-03-24 Space Charge, LLC Rugged, gel-free, lithium-free, high energy density solid-state electrochemical energy storage devices
US9853325B2 (en) 2011-06-29 2017-12-26 Space Charge, LLC Rugged, gel-free, lithium-free, high energy density solid-state electrochemical energy storage devices
US10658705B2 (en) 2018-03-07 2020-05-19 Space Charge, LLC Thin-film solid-state energy storage devices
US9223203B2 (en) 2011-07-08 2015-12-29 Asm International N.V. Microcontact printed films as an activation layer for selective atomic layer deposition
US20130023129A1 (en) 2011-07-20 2013-01-24 Asm America, Inc. Pressure transmitter for a semiconductor processing environment
US8525339B2 (en) 2011-07-27 2013-09-03 International Business Machines Corporation Hybrid copper interconnect structure and method of fabricating same
US8921228B2 (en) 2011-10-04 2014-12-30 Imec Method for selectively depositing noble metals on metal/metal nitride substrates
US9112003B2 (en) 2011-12-09 2015-08-18 Asm International N.V. Selective formation of metallic films on metallic surfaces
US8796853B2 (en) 2012-02-24 2014-08-05 International Business Machines Corporation Metallic capped interconnect structure with high electromigration resistance and low resistivity
US9156025B2 (en) 2012-11-21 2015-10-13 SDCmaterials, Inc. Three-way catalytic converter using nanoparticles
US9511352B2 (en) 2012-11-21 2016-12-06 SDCmaterials, Inc. Three-way catalytic converter using nanoparticles
JP6125279B2 (en) 2013-03-05 2017-05-10 株式会社日立国際電気 Semiconductor device manufacturing method, substrate processing apparatus, and program
US8609531B1 (en) 2013-03-06 2013-12-17 Globalfoundries Inc. Methods of selectively forming ruthenium liner layer
CN105592921A (en) 2013-07-25 2016-05-18 Sdc材料公司 Washcoats and coated substrates for catalytic converters and method for manufacturing and using same
MX2016004759A (en) 2013-10-22 2016-07-26 Sdcmaterials Inc Compositions of lean nox trap.
CN106061600A (en) 2013-10-22 2016-10-26 Sdc材料公司 Catalyst design for heavy-duty diesel combustion engines
US9873110B2 (en) * 2013-11-09 2018-01-23 Sensiran Method for deposition of noble metal nanoparticles on catalysts to promote same, and the compositions so produced
US9437711B2 (en) 2013-11-15 2016-09-06 Globalfoundries Inc. Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices
US9159617B2 (en) 2014-01-24 2015-10-13 Globalfoundries Inc. Structure and method of forming silicide on fins
US9895715B2 (en) 2014-02-04 2018-02-20 Asm Ip Holding B.V. Selective deposition of metals, metal oxides, and dielectrics
US9687811B2 (en) 2014-03-21 2017-06-27 SDCmaterials, Inc. Compositions for passive NOx adsorption (PNA) systems and methods of making and using same
US10047435B2 (en) 2014-04-16 2018-08-14 Asm Ip Holding B.V. Dual selective deposition
US10941490B2 (en) 2014-10-07 2021-03-09 Asm Ip Holding B.V. Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same
US9379209B2 (en) * 2014-11-07 2016-06-28 Globalfoundries Inc. Selectively forming a protective conductive cap on a metal gate electrode
US9754791B2 (en) * 2015-02-07 2017-09-05 Applied Materials, Inc. Selective deposition utilizing masks and directional plasma treatment
US9490145B2 (en) 2015-02-23 2016-11-08 Asm Ip Holding B.V. Removal of surface passivation
US10276355B2 (en) 2015-03-12 2019-04-30 Asm Ip Holding B.V. Multi-zone reactor, system including the reactor, and method of using the same
US10428421B2 (en) * 2015-08-03 2019-10-01 Asm Ip Holding B.V. Selective deposition on metal or metallic surfaces relative to dielectric surfaces
US10566185B2 (en) 2015-08-05 2020-02-18 Asm Ip Holding B.V. Selective deposition of aluminum and nitrogen containing material
US10121699B2 (en) 2015-08-05 2018-11-06 Asm Ip Holding B.V. Selective deposition of aluminum and nitrogen containing material
US10695794B2 (en) 2015-10-09 2020-06-30 Asm Ip Holding B.V. Vapor phase deposition of organic films
US10814349B2 (en) 2015-10-09 2020-10-27 Asm Ip Holding B.V. Vapor phase deposition of organic films
US10529554B2 (en) 2016-02-19 2020-01-07 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
US11081342B2 (en) 2016-05-05 2021-08-03 Asm Ip Holding B.V. Selective deposition using hydrophobic precursors
US11453943B2 (en) 2016-05-25 2022-09-27 Asm Ip Holding B.V. Method for forming carbon-containing silicon/metal oxide or nitride film by ALD using silicon precursor and hydrocarbon precursor
US10373820B2 (en) 2016-06-01 2019-08-06 Asm Ip Holding B.V. Deposition of organic films
US10453701B2 (en) 2016-06-01 2019-10-22 Asm Ip Holding B.V. Deposition of organic films
US9803277B1 (en) 2016-06-08 2017-10-31 Asm Ip Holding B.V. Reaction chamber passivation and selective deposition of metallic films
US10612137B2 (en) 2016-07-08 2020-04-07 Asm Ip Holdings B.V. Organic reactants for atomic layer deposition
US9859151B1 (en) 2016-07-08 2018-01-02 Asm Ip Holding B.V. Selective film deposition method to form air gaps
US9887082B1 (en) 2016-07-28 2018-02-06 Asm Ip Holding B.V. Method and apparatus for filling a gap
US9812320B1 (en) 2016-07-28 2017-11-07 Asm Ip Holding B.V. Method and apparatus for filling a gap
US11532757B2 (en) 2016-10-27 2022-12-20 Asm Ip Holding B.V. Deposition of charge trapping layers
US10714350B2 (en) 2016-11-01 2020-07-14 ASM IP Holdings, B.V. Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures
KR102546317B1 (en) 2016-11-15 2023-06-21 에이에스엠 아이피 홀딩 비.브이. Gas supply unit and substrate processing apparatus including the same
US11430656B2 (en) 2016-11-29 2022-08-30 Asm Ip Holding B.V. Deposition of oxide thin films
US11581186B2 (en) 2016-12-15 2023-02-14 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus
US11447861B2 (en) 2016-12-15 2022-09-20 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus and a method of forming a patterned structure
US11293093B2 (en) 2017-01-06 2022-04-05 Applied Materials Inc. Water assisted highly pure ruthenium thin film deposition
US11390950B2 (en) 2017-01-10 2022-07-19 Asm Ip Holding B.V. Reactor system and method to reduce residue buildup during a film deposition process
JP7169072B2 (en) 2017-02-14 2022-11-10 エーエスエム アイピー ホールディング ビー.ブイ. Selective passivation and selective deposition
US10468261B2 (en) 2017-02-15 2019-11-05 Asm Ip Holding B.V. Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures
JP6832776B2 (en) * 2017-03-30 2021-02-24 東京エレクトロン株式会社 Selective growth method
US11501965B2 (en) 2017-05-05 2022-11-15 Asm Ip Holding B.V. Plasma enhanced deposition processes for controlled formation of metal oxide thin films
US10770286B2 (en) 2017-05-08 2020-09-08 Asm Ip Holdings B.V. Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures
CN110651064B (en) 2017-05-16 2022-08-16 Asm Ip 控股有限公司 Selective PEALD of oxides on dielectrics
US11306395B2 (en) 2017-06-28 2022-04-19 Asm Ip Holding B.V. Methods for depositing a transition metal nitride film on a substrate by atomic layer deposition and related deposition apparatus
US10900120B2 (en) 2017-07-14 2021-01-26 Asm Ip Holding B.V. Passivation against vapor deposition
KR20190009245A (en) 2017-07-18 2019-01-28 에이에스엠 아이피 홀딩 비.브이. Methods for forming a semiconductor device structure and related semiconductor device structures
US10590535B2 (en) 2017-07-26 2020-03-17 Asm Ip Holdings B.V. Chemical treatment, deposition and/or infiltration apparatus and method for using the same
US10770336B2 (en) 2017-08-08 2020-09-08 Asm Ip Holding B.V. Substrate lift mechanism and reactor including same
US10692741B2 (en) 2017-08-08 2020-06-23 Asm Ip Holdings B.V. Radiation shield
US11769682B2 (en) 2017-08-09 2023-09-26 Asm Ip Holding B.V. Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
US11830730B2 (en) 2017-08-29 2023-11-28 Asm Ip Holding B.V. Layer forming method and apparatus
US11295980B2 (en) 2017-08-30 2022-04-05 Asm Ip Holding B.V. Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures
US10658205B2 (en) 2017-09-28 2020-05-19 Asm Ip Holdings B.V. Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber
JP6968993B2 (en) 2017-10-06 2021-11-24 アプライド マテリアルズ インコーポレイテッドApplied Materials, Incorporated Methods and precursors for selective deposition of metal films
CN111344522B (en) 2017-11-27 2022-04-12 阿斯莫Ip控股公司 Including clean mini-environment device
CN111316417B (en) 2017-11-27 2023-12-22 阿斯莫Ip控股公司 Storage device for storing wafer cassettes for use with batch ovens
TWI790320B (en) * 2017-12-16 2023-01-21 美商應用材料股份有限公司 Selective atomic layer deposition of ruthenium
US10872771B2 (en) 2018-01-16 2020-12-22 Asm Ip Holding B. V. Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures
TWI799494B (en) 2018-01-19 2023-04-21 荷蘭商Asm 智慧財產控股公司 Deposition method
WO2019142055A2 (en) 2018-01-19 2019-07-25 Asm Ip Holding B.V. Method for depositing a gap-fill layer by plasma-assisted deposition
US11081345B2 (en) 2018-02-06 2021-08-03 Asm Ip Holding B.V. Method of post-deposition treatment for silicon oxide film
EP3737779A1 (en) 2018-02-14 2020-11-18 ASM IP Holding B.V. A method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
US10896820B2 (en) 2018-02-14 2021-01-19 Asm Ip Holding B.V. Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
KR102636427B1 (en) 2018-02-20 2024-02-13 에이에스엠 아이피 홀딩 비.브이. Substrate processing method and apparatus
US11473195B2 (en) 2018-03-01 2022-10-18 Asm Ip Holding B.V. Semiconductor processing apparatus and a method for processing a substrate
US10847371B2 (en) 2018-03-27 2020-11-24 Asm Ip Holding B.V. Method of forming an electrode on a substrate and a semiconductor device structure including an electrode
KR102443580B1 (en) 2018-04-28 2022-09-16 어플라이드 머티어리얼스, 인코포레이티드 Gas pulsing-based shared precursor dispensing system and methods of use
JP7146690B2 (en) 2018-05-02 2022-10-04 エーエスエム アイピー ホールディング ビー.ブイ. Selective layer formation using deposition and removal
US10566194B2 (en) 2018-05-07 2020-02-18 Lam Research Corporation Selective deposition of etch-stop layer for enhanced patterning
KR102596988B1 (en) 2018-05-28 2023-10-31 에이에스엠 아이피 홀딩 비.브이. Method of processing a substrate and a device manufactured by the same
US11718913B2 (en) 2018-06-04 2023-08-08 Asm Ip Holding B.V. Gas distribution system and reactor system including same
US10797133B2 (en) 2018-06-21 2020-10-06 Asm Ip Holding B.V. Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures
KR102568797B1 (en) 2018-06-21 2023-08-21 에이에스엠 아이피 홀딩 비.브이. Substrate processing system
JP2021529254A (en) 2018-06-27 2021-10-28 エーエスエム・アイピー・ホールディング・ベー・フェー Periodic deposition methods for forming metal-containing materials and films and structures containing metal-containing materials
CN112292477A (en) 2018-06-27 2021-01-29 Asm Ip私人控股有限公司 Cyclic deposition methods for forming metal-containing materials and films and structures containing metal-containing materials
US10755922B2 (en) 2018-07-03 2020-08-25 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10388513B1 (en) 2018-07-03 2019-08-20 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US11430674B2 (en) 2018-08-22 2022-08-30 Asm Ip Holding B.V. Sensor array, apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods
US11488830B2 (en) * 2018-08-23 2022-11-01 Applied Materials, Inc. Oxygen free deposition of platinum group metal films
US10832963B2 (en) 2018-08-27 2020-11-10 International Business Machines Corporation Forming gate contact over active free of metal recess
US11024523B2 (en) 2018-09-11 2021-06-01 Asm Ip Holding B.V. Substrate processing apparatus and method
KR20200030162A (en) 2018-09-11 2020-03-20 에이에스엠 아이피 홀딩 비.브이. Method for deposition of a thin film
CN110970344A (en) 2018-10-01 2020-04-07 Asm Ip控股有限公司 Substrate holding apparatus, system including the same, and method of using the same
JP2020056104A (en) 2018-10-02 2020-04-09 エーエスエム アイピー ホールディング ビー.ブイ. Selective passivation and selective deposition
KR102592699B1 (en) 2018-10-08 2023-10-23 에이에스엠 아이피 홀딩 비.브이. Substrate support unit and apparatuses for depositing thin film and processing the substrate including the same
KR102546322B1 (en) 2018-10-19 2023-06-21 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus and substrate processing method
US11087997B2 (en) 2018-10-31 2021-08-10 Asm Ip Holding B.V. Substrate processing apparatus for processing substrates
CN112655078A (en) * 2018-10-31 2021-04-13 株式会社国际电气 Method for manufacturing semiconductor device, substrate processing apparatus, and program
KR20200051105A (en) 2018-11-02 2020-05-13 에이에스엠 아이피 홀딩 비.브이. Substrate support unit and substrate processing apparatus including the same
US11572620B2 (en) 2018-11-06 2023-02-07 Asm Ip Holding B.V. Methods for selectively depositing an amorphous silicon film on a substrate
US10818758B2 (en) 2018-11-16 2020-10-27 Asm Ip Holding B.V. Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures
TW202028504A (en) * 2018-12-03 2020-08-01 德商馬克專利公司 Method for highly selective deposition of metal films
KR102636428B1 (en) 2018-12-04 2024-02-13 에이에스엠 아이피 홀딩 비.브이. A method for cleaning a substrate processing apparatus
US11158513B2 (en) 2018-12-13 2021-10-26 Asm Ip Holding B.V. Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures
TW202037745A (en) 2018-12-14 2020-10-16 荷蘭商Asm Ip私人控股有限公司 Method of forming device structure, structure formed by the method and system for performing the method
TWI819180B (en) 2019-01-17 2023-10-21 荷蘭商Asm 智慧財產控股公司 Methods of forming a transition metal containing film on a substrate by a cyclical deposition process
US11482533B2 (en) 2019-02-20 2022-10-25 Asm Ip Holding B.V. Apparatus and methods for plug fill deposition in 3-D NAND applications
TW202044325A (en) 2019-02-20 2020-12-01 荷蘭商Asm Ip私人控股有限公司 Method of filling a recess formed within a surface of a substrate, semiconductor structure formed according to the method, and semiconductor processing apparatus
TW202104632A (en) 2019-02-20 2021-02-01 荷蘭商Asm Ip私人控股有限公司 Cyclical deposition method and apparatus for filling a recess formed within a substrate surface
TW202100794A (en) 2019-02-22 2021-01-01 荷蘭商Asm Ip私人控股有限公司 Substrate processing apparatus and method for processing substrate
KR20200108248A (en) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. STRUCTURE INCLUDING SiOCN LAYER AND METHOD OF FORMING SAME
KR20200108242A (en) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. Method for Selective Deposition of Silicon Nitride Layer and Structure Including Selectively-Deposited Silicon Nitride Layer
KR20200116033A (en) 2019-03-28 2020-10-08 에이에스엠 아이피 홀딩 비.브이. Door opener and substrate processing apparatus provided therewith
KR20200116855A (en) 2019-04-01 2020-10-13 에이에스엠 아이피 홀딩 비.브이. Method of manufacturing semiconductor device
KR20200123380A (en) 2019-04-19 2020-10-29 에이에스엠 아이피 홀딩 비.브이. Layer forming method and apparatus
KR20200125453A (en) 2019-04-24 2020-11-04 에이에스엠 아이피 홀딩 비.브이. Gas-phase reactor system and method of using same
KR20200130121A (en) 2019-05-07 2020-11-18 에이에스엠 아이피 홀딩 비.브이. Chemical source vessel with dip tube
KR20200130652A (en) 2019-05-10 2020-11-19 에이에스엠 아이피 홀딩 비.브이. Method of depositing material onto a surface and structure formed according to the method
JP2020188255A (en) 2019-05-16 2020-11-19 エーエスエム アイピー ホールディング ビー.ブイ. Wafer boat handling device, vertical batch furnace, and method
USD975665S1 (en) 2019-05-17 2023-01-17 Asm Ip Holding B.V. Susceptor shaft
USD947913S1 (en) 2019-05-17 2022-04-05 Asm Ip Holding B.V. Susceptor shaft
KR20200141002A (en) 2019-06-06 2020-12-17 에이에스엠 아이피 홀딩 비.브이. Method of using a gas-phase reactor system including analyzing exhausted gas
KR20200143254A (en) 2019-06-11 2020-12-23 에이에스엠 아이피 홀딩 비.브이. Method of forming an electronic structure using an reforming gas, system for performing the method, and structure formed using the method
KR20210005515A (en) 2019-07-03 2021-01-14 에이에스엠 아이피 홀딩 비.브이. Temperature control assembly for substrate processing apparatus and method of using same
JP2021015791A (en) 2019-07-09 2021-02-12 エーエスエム アイピー ホールディング ビー.ブイ. Plasma device and substrate processing method using coaxial waveguide
CN112216646A (en) 2019-07-10 2021-01-12 Asm Ip私人控股有限公司 Substrate supporting assembly and substrate processing device comprising same
KR20210010307A (en) 2019-07-16 2021-01-27 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
KR20210010820A (en) 2019-07-17 2021-01-28 에이에스엠 아이피 홀딩 비.브이. Methods of forming silicon germanium structures
KR20210010816A (en) 2019-07-17 2021-01-28 에이에스엠 아이피 홀딩 비.브이. Radical assist ignition plasma system and method
US11643724B2 (en) 2019-07-18 2023-05-09 Asm Ip Holding B.V. Method of forming structures using a neutral beam
CN112309843A (en) 2019-07-29 2021-02-02 Asm Ip私人控股有限公司 Selective deposition method for achieving high dopant doping
CN112309899A (en) 2019-07-30 2021-02-02 Asm Ip私人控股有限公司 Substrate processing apparatus
CN112309900A (en) 2019-07-30 2021-02-02 Asm Ip私人控股有限公司 Substrate processing apparatus
US11227782B2 (en) 2019-07-31 2022-01-18 Asm Ip Holding B.V. Vertical batch furnace assembly
US11587815B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
US11587814B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
CN112323048B (en) 2019-08-05 2024-02-09 Asm Ip私人控股有限公司 Liquid level sensor for chemical source container
USD965044S1 (en) 2019-08-19 2022-09-27 Asm Ip Holding B.V. Susceptor shaft
USD965524S1 (en) 2019-08-19 2022-10-04 Asm Ip Holding B.V. Susceptor support
JP2021031769A (en) 2019-08-21 2021-03-01 エーエスエム アイピー ホールディング ビー.ブイ. Production apparatus of mixed gas of film deposition raw material and film deposition apparatus
USD979506S1 (en) 2019-08-22 2023-02-28 Asm Ip Holding B.V. Insulator
KR20210024423A (en) 2019-08-22 2021-03-05 에이에스엠 아이피 홀딩 비.브이. Method for forming a structure with a hole
US11286558B2 (en) 2019-08-23 2022-03-29 Asm Ip Holding B.V. Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film
KR20210029090A (en) 2019-09-04 2021-03-15 에이에스엠 아이피 홀딩 비.브이. Methods for selective deposition using a sacrificial capping layer
KR20210029663A (en) 2019-09-05 2021-03-16 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US11562901B2 (en) 2019-09-25 2023-01-24 Asm Ip Holding B.V. Substrate processing method
CN112593212B (en) 2019-10-02 2023-12-22 Asm Ip私人控股有限公司 Method for forming topologically selective silicon oxide film by cyclic plasma enhanced deposition process
TW202129060A (en) 2019-10-08 2021-08-01 荷蘭商Asm Ip控股公司 Substrate processing device, and substrate processing method
KR20210043460A (en) 2019-10-10 2021-04-21 에이에스엠 아이피 홀딩 비.브이. Method of forming a photoresist underlayer and structure including same
KR20210045930A (en) 2019-10-16 2021-04-27 에이에스엠 아이피 홀딩 비.브이. Method of Topology-Selective Film Formation of Silicon Oxide
US11637014B2 (en) 2019-10-17 2023-04-25 Asm Ip Holding B.V. Methods for selective deposition of doped semiconductor material
KR20210047808A (en) 2019-10-21 2021-04-30 에이에스엠 아이피 홀딩 비.브이. Apparatus and methods for selectively etching films
US11646205B2 (en) 2019-10-29 2023-05-09 Asm Ip Holding B.V. Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same
US11139163B2 (en) 2019-10-31 2021-10-05 Asm Ip Holding B.V. Selective deposition of SiOC thin films
KR20210054983A (en) 2019-11-05 2021-05-14 에이에스엠 아이피 홀딩 비.브이. Structures with doped semiconductor layers and methods and systems for forming same
US11501968B2 (en) 2019-11-15 2022-11-15 Asm Ip Holding B.V. Method for providing a semiconductor device with silicon filled gaps
KR20210062561A (en) 2019-11-20 2021-05-31 에이에스엠 아이피 홀딩 비.브이. Method of depositing carbon-containing material on a surface of a substrate, structure formed using the method, and system for forming the structure
US11450529B2 (en) 2019-11-26 2022-09-20 Asm Ip Holding B.V. Methods for selectively forming a target film on a substrate comprising a first dielectric surface and a second metallic surface
CN112951697A (en) 2019-11-26 2021-06-11 Asm Ip私人控股有限公司 Substrate processing apparatus
CN112885693A (en) 2019-11-29 2021-06-01 Asm Ip私人控股有限公司 Substrate processing apparatus
CN112885692A (en) 2019-11-29 2021-06-01 Asm Ip私人控股有限公司 Substrate processing apparatus
JP2021090042A (en) 2019-12-02 2021-06-10 エーエスエム アイピー ホールディング ビー.ブイ. Substrate processing apparatus and substrate processing method
KR20210070898A (en) 2019-12-04 2021-06-15 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
JP2021097227A (en) 2019-12-17 2021-06-24 エーエスエム・アイピー・ホールディング・ベー・フェー Method of forming vanadium nitride layer and structure including vanadium nitride layer
KR20210080214A (en) 2019-12-19 2021-06-30 에이에스엠 아이피 홀딩 비.브이. Methods for filling a gap feature on a substrate and related semiconductor structures
KR20210095050A (en) 2020-01-20 2021-07-30 에이에스엠 아이피 홀딩 비.브이. Method of forming thin film and method of modifying surface of thin film
TW202130846A (en) 2020-02-03 2021-08-16 荷蘭商Asm Ip私人控股有限公司 Method of forming structures including a vanadium or indium layer
TW202146882A (en) 2020-02-04 2021-12-16 荷蘭商Asm Ip私人控股有限公司 Method of verifying an article, apparatus for verifying an article, and system for verifying a reaction chamber
US11776846B2 (en) 2020-02-07 2023-10-03 Asm Ip Holding B.V. Methods for depositing gap filling fluids and related systems and devices
US11781243B2 (en) 2020-02-17 2023-10-10 Asm Ip Holding B.V. Method for depositing low temperature phosphorous-doped silicon
KR20210116240A (en) 2020-03-11 2021-09-27 에이에스엠 아이피 홀딩 비.브이. Substrate handling device with adjustable joints
US11876356B2 (en) 2020-03-11 2024-01-16 Asm Ip Holding B.V. Lockout tagout assembly and system and method of using same
TW202140833A (en) 2020-03-30 2021-11-01 荷蘭商Asm Ip私人控股有限公司 Selective deposition of silicon oxide on dielectric surfaces relative to metal surfaces
TW202204658A (en) 2020-03-30 2022-02-01 荷蘭商Asm Ip私人控股有限公司 Simultaneous selective deposition of two different materials on two different surfaces
TW202140832A (en) 2020-03-30 2021-11-01 荷蘭商Asm Ip私人控股有限公司 Selective deposition of silicon oxide on metal surfaces
KR20210124042A (en) 2020-04-02 2021-10-14 에이에스엠 아이피 홀딩 비.브이. Thin film forming method
TW202146689A (en) 2020-04-03 2021-12-16 荷蘭商Asm Ip控股公司 Method for forming barrier layer and method for manufacturing semiconductor device
TW202145344A (en) 2020-04-08 2021-12-01 荷蘭商Asm Ip私人控股有限公司 Apparatus and methods for selectively etching silcon oxide films
US11821078B2 (en) 2020-04-15 2023-11-21 Asm Ip Holding B.V. Method for forming precoat film and method for forming silicon-containing film
TW202146831A (en) 2020-04-24 2021-12-16 荷蘭商Asm Ip私人控股有限公司 Vertical batch furnace assembly, and method for cooling vertical batch furnace
KR20210132600A (en) 2020-04-24 2021-11-04 에이에스엠 아이피 홀딩 비.브이. Methods and systems for depositing a layer comprising vanadium, nitrogen, and a further element
JP2021172884A (en) 2020-04-24 2021-11-01 エーエスエム・アイピー・ホールディング・ベー・フェー Method of forming vanadium nitride-containing layer and structure comprising vanadium nitride-containing layer
KR20210134869A (en) 2020-05-01 2021-11-11 에이에스엠 아이피 홀딩 비.브이. Fast FOUP swapping with a FOUP handler
KR20210141379A (en) 2020-05-13 2021-11-23 에이에스엠 아이피 홀딩 비.브이. Laser alignment fixture for a reactor system
TW202147383A (en) 2020-05-19 2021-12-16 荷蘭商Asm Ip私人控股有限公司 Substrate processing apparatus
KR20210145078A (en) 2020-05-21 2021-12-01 에이에스엠 아이피 홀딩 비.브이. Structures including multiple carbon layers and methods of forming and using same
TW202201602A (en) 2020-05-29 2022-01-01 荷蘭商Asm Ip私人控股有限公司 Substrate processing device
TW202218133A (en) 2020-06-24 2022-05-01 荷蘭商Asm Ip私人控股有限公司 Method for forming a layer provided with silicon
TW202217953A (en) 2020-06-30 2022-05-01 荷蘭商Asm Ip私人控股有限公司 Substrate processing method
TW202219628A (en) 2020-07-17 2022-05-16 荷蘭商Asm Ip私人控股有限公司 Structures and methods for use in photolithography
TW202204662A (en) 2020-07-20 2022-02-01 荷蘭商Asm Ip私人控股有限公司 Method and system for depositing molybdenum layers
TW202212623A (en) 2020-08-26 2022-04-01 荷蘭商Asm Ip私人控股有限公司 Method of forming metal silicon oxide layer and metal silicon oxynitride layer, semiconductor structure, and system
USD990534S1 (en) 2020-09-11 2023-06-27 Asm Ip Holding B.V. Weighted lift pin
USD1012873S1 (en) 2020-09-24 2024-01-30 Asm Ip Holding B.V. Electrode for semiconductor processing apparatus
TW202229613A (en) 2020-10-14 2022-08-01 荷蘭商Asm Ip私人控股有限公司 Method of depositing material on stepped structure
KR20220053482A (en) 2020-10-22 2022-04-29 에이에스엠 아이피 홀딩 비.브이. Method of depositing vanadium metal, structure, device and a deposition assembly
TW202223136A (en) 2020-10-28 2022-06-16 荷蘭商Asm Ip私人控股有限公司 Method for forming layer on substrate, and semiconductor processing system
KR20220076343A (en) 2020-11-30 2022-06-08 에이에스엠 아이피 홀딩 비.브이. an injector configured for arrangement within a reaction chamber of a substrate processing apparatus
CN112647059B (en) * 2020-12-14 2021-10-22 江南大学 Rapid growth of Ni by utilizing atomic layer deposition technologyxMethod for forming C film
TW202231903A (en) 2020-12-22 2022-08-16 荷蘭商Asm Ip私人控股有限公司 Transition metal deposition method, transition metal layer, and deposition assembly for depositing transition metal on substrate
USD980814S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas distributor for substrate processing apparatus
USD981973S1 (en) 2021-05-11 2023-03-28 Asm Ip Holding B.V. Reactor wall for substrate processing apparatus
USD980813S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas flow control plate for substrate processing apparatus
USD990441S1 (en) 2021-09-07 2023-06-27 Asm Ip Holding B.V. Gas flow control plate

Citations (92)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4670110A (en) * 1979-07-30 1987-06-02 Metallurgical, Inc. Process for the electrolytic deposition of aluminum using a composite anode
US4902551A (en) * 1987-12-14 1990-02-20 Hitachi Chemical Company, Ltd. Process for treating copper surface
US5106454A (en) * 1990-11-01 1992-04-21 Shipley Company Inc. Process for multilayer printed circuit board manufacture
US5382333A (en) * 1990-07-30 1995-01-17 Mitsubishi Gas Chemical Company, Inc. Process for producing copper clad laminate
US5391517A (en) * 1993-09-13 1995-02-21 Motorola Inc. Process for forming copper interconnect structure
US5637533A (en) * 1995-05-17 1997-06-10 Hyundai Electronics Industries Co., Ltd. Method for fabricating a diffusion barrier metal layer in a semiconductor device
US5711811A (en) * 1994-11-28 1998-01-27 Mikrokemia Oy Method and equipment for growing thin films
US5731634A (en) * 1992-07-31 1998-03-24 Kabushiki Kaisha Toshiba Semiconductor device having a metal film formed in a groove in an insulating film
US5865365A (en) * 1991-02-19 1999-02-02 Hitachi, Ltd. Method of fabricating an electronic circuit device
US5884009A (en) * 1997-08-07 1999-03-16 Tokyo Electron Limited Substrate treatment system
US5916365A (en) * 1996-08-16 1999-06-29 Sherman; Arthur Sequential chemical vapor deposition
US5923056A (en) * 1996-10-10 1999-07-13 Lucent Technologies Inc. Electronic components with doped metal oxide dielectric materials and a process for making electronic components with doped metal oxide dielectric materials
US6015986A (en) * 1995-12-22 2000-01-18 Micron Technology, Inc. Rugged metal electrodes for metal-insulator-metal capacitors
US6033584A (en) * 1997-12-22 2000-03-07 Advanced Micro Devices, Inc. Process for reducing copper oxide during integrated circuit fabrication
US6040243A (en) * 1999-09-20 2000-03-21 Chartered Semiconductor Manufacturing Ltd. Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion
US6063705A (en) * 1998-08-27 2000-05-16 Micron Technology, Inc. Precursor chemistries for chemical vapor deposition of ruthenium and ruthenium oxide
US6066892A (en) * 1997-05-08 2000-05-23 Applied Materials, Inc. Copper alloy seed layer for copper metallization in an integrated circuit
US6074945A (en) * 1998-08-27 2000-06-13 Micron Technology, Inc. Methods for preparing ruthenium metal films
US6171910B1 (en) * 1999-07-21 2001-01-09 Motorola Inc. Method for forming a semiconductor device
US6203613B1 (en) * 1999-10-19 2001-03-20 International Business Machines Corporation Atomic layer deposition with nitrate containing precursors
US20010003064A1 (en) * 1999-12-02 2001-06-07 Nec Corporation Method for fabricating semiconductor device and apparatus for fabricating same
US6268291B1 (en) * 1995-12-29 2001-07-31 International Business Machines Corporation Method for forming electromigration-resistant structures by doping
US6335280B1 (en) * 1997-01-13 2002-01-01 Asm America, Inc. Tungsten silicide deposition process
US20020004293A1 (en) * 2000-05-15 2002-01-10 Soininen Pekka J. Method of growing electrical conductors
US20020006711A1 (en) * 1995-09-08 2002-01-17 Semiconductor Energy Laboratory Co., Ltd. Japanese Corporation Method of manufacturing a semiconductor device
US6342277B1 (en) * 1996-08-16 2002-01-29 Licensee For Microelectronics: Asm America, Inc. Sequential chemical vapor deposition
US20020013487A1 (en) * 2000-04-03 2002-01-31 Norman John Anthony Thomas Volatile precursors for deposition of metals and metal-containing films
US6346151B1 (en) * 1999-02-24 2002-02-12 Micron Technology, Inc. Method and apparatus for electroless plating a contact pad
US20020027286A1 (en) * 1999-09-30 2002-03-07 Srinivasan Sundararajan Low leakage current silicon carbonitride prepared using methane, ammonia and silane for copper diffusion barrier, etchstop and passivation applications
US6359159B1 (en) * 1999-05-19 2002-03-19 Research Foundation Of State University Of New York MOCVD precursors based on organometalloid ligands
US6380080B2 (en) * 2000-03-08 2002-04-30 Micron Technology, Inc. Methods for preparing ruthenium metal films
US6391785B1 (en) * 1999-08-24 2002-05-21 Interuniversitair Microelektronica Centrum (Imec) Method for bottomless deposition of barrier layers in integrated circuit metallization schemes
US6395650B1 (en) * 2000-10-23 2002-05-28 International Business Machines Corporation Methods for forming metal oxide layers with enhanced purity
US6403191B1 (en) * 1999-09-21 2002-06-11 Strata-Tac, Inc. Laminate with integrated compact disk label and methods
US6403414B2 (en) * 1998-09-03 2002-06-11 Micron Technology, Inc. Method for producing low carbon/oxygen conductive layers
US6420189B1 (en) * 2001-04-27 2002-07-16 Advanced Micro Devices, Inc. Superconducting damascene interconnected for integrated circuit
US20030013302A1 (en) * 2000-03-07 2003-01-16 Tue Nguyen Multilayered copper structure for improving adhesion property
US6511539B1 (en) * 1999-09-08 2003-01-28 Asm America, Inc. Apparatus and method for growth of a thin film
US6534395B2 (en) * 2000-03-07 2003-03-18 Asm Microchemistry Oy Method of forming graded thin films using alternating pulses of vapor phase reactants
US6541067B1 (en) * 1998-08-27 2003-04-01 Micron Technology, Inc. Solvated ruthenium precursors for direct liquid injection of ruthenium and ruthenium oxide and method of using same
US6551399B1 (en) * 2000-01-10 2003-04-22 Genus Inc. Fully integrated process for MIM capacitors using atomic layer deposition
US6576053B1 (en) * 1999-10-06 2003-06-10 Samsung Electronics Co., Ltd. Method of forming thin film using atomic layer deposition method
US6593656B2 (en) * 2001-02-05 2003-07-15 Micron Technology, Inc. Multilevel copper interconnects for ultra large scale integration
US20040005753A1 (en) * 2000-05-15 2004-01-08 Juhana Kostamo Method of growing electrical conductors
US6679951B2 (en) * 2000-05-15 2004-01-20 Asm Intenational N.V. Metal anneal with oxidation prevention
US6680540B2 (en) * 2000-03-08 2004-01-20 Hitachi, Ltd. Semiconductor device having cobalt alloy film with boron
US20040053496A1 (en) * 2002-09-17 2004-03-18 Eun-Seok Choi Method for forming metal films
US6720262B2 (en) * 1999-12-15 2004-04-13 Genitech, Inc. Method of forming copper interconnections and thin films using chemical vapor deposition with catalyst
US20040082125A1 (en) * 2002-10-29 2004-04-29 Taiwan Semiconductor Manufacturing Company Novel dual gate dielectric scheme: SiON for high performance devices and high k for low power devices
US20040087143A1 (en) * 2002-11-05 2004-05-06 Norman John Anthony Thomas Process for atomic layer deposition of metal films
US20040105934A1 (en) * 2002-06-04 2004-06-03 Mei Chang Ruthenium layer formation for copper film deposition
US20040118697A1 (en) * 2002-10-01 2004-06-24 Applied Materials, Inc. Metal deposition process with pre-cleaning before electrochemical deposition
US20040126944A1 (en) * 2002-12-31 2004-07-01 Pacheco Rotondaro Antonio Luis Methods for forming interfacial layer for deposition of high-k dielectrics
US6759325B2 (en) * 2000-05-15 2004-07-06 Asm Microchemistry Oy Sealing porous structures
US20040142558A1 (en) * 2002-12-05 2004-07-22 Granneman Ernst H. A. Apparatus and method for atomic layer deposition on substrates
US6842740B1 (en) * 1999-12-20 2005-01-11 Hewlett-Packard Development Company, L.P. Method for providing automatic payment when making duplicates of copyrighted material
US20050009325A1 (en) * 2003-06-18 2005-01-13 Hua Chung Atomic layer deposition of barrier materials
US20050020060A1 (en) * 2002-01-29 2005-01-27 Titta Aaltonen Process for producing metal thin films by ALD
US6849122B1 (en) * 2001-01-19 2005-02-01 Novellus Systems, Inc. Thin layer metal chemical vapor deposition
US20050048794A1 (en) * 2003-08-28 2005-03-03 Brask Justin K. Method for making a semiconductor device having a high-k gate dielectric
US6878628B2 (en) * 2000-05-15 2005-04-12 Asm International Nv In situ reduction of copper oxide prior to silicon carbide deposition
US6881260B2 (en) * 2002-06-25 2005-04-19 Micron Technology, Inc. Process for direct deposition of ALD RhO2
US6881437B2 (en) * 2003-06-16 2005-04-19 Blue29 Llc Methods and system for processing a microelectronic topography
US20050085031A1 (en) * 2003-10-15 2005-04-21 Applied Materials, Inc. Heterogeneous activation layers formed by ionic and electroless reactions used for IC interconnect capping layers
US20050082587A1 (en) * 2002-08-29 2005-04-21 Micron Technology, Inc. Platinum stuffed with silicon oxide as a diffusion oxygen barrier for semiconductor devices
US20050089632A1 (en) * 2003-10-28 2005-04-28 Marko Vehkamaki Process for producing oxide films
US20050087879A1 (en) * 2003-10-28 2005-04-28 Samsung Electronics Co., Ltd. Logic device having vertically extending metal-insulator-metal capacitor between interconnect layers and method of fabricating the same
US20050092247A1 (en) * 2003-08-29 2005-05-05 Schmidt Ryan M. Gas mixer and manifold assembly for ALD reactor
US20050098440A1 (en) * 2003-11-10 2005-05-12 Kailasam Sridhar K. Methods for the electrochemical deposition of copper onto a barrier layer of a work piece
US20050124154A1 (en) * 2001-12-28 2005-06-09 Hyung-Sang Park Method of forming copper interconnections for semiconductor integrated circuits on a substrate
US6984591B1 (en) * 2000-04-20 2006-01-10 International Business Machines Corporation Precursor source mixtures
US20060013955A1 (en) * 2004-07-09 2006-01-19 Yoshihide Senzaki Deposition of ruthenium and/or ruthenium oxide films
US20060026654A1 (en) * 2004-07-27 2006-02-02 Samsung Electronics Co., Ltd. Live content management method, source device, and sink device
US20060035462A1 (en) * 2004-08-13 2006-02-16 Micron Technology, Inc. Systems and methods for forming metal-containing layers using vapor deposition processes
US7011981B2 (en) * 2000-11-13 2006-03-14 Lg.Philips Lcd Co., Ltd. Method for forming thin film and method for fabricating liquid crystal display using the same
US20060073276A1 (en) * 2004-10-04 2006-04-06 Eric Antonissen Multi-zone atomic layer deposition apparatus and method
US20060093848A1 (en) * 2002-10-15 2006-05-04 Senkevich John J Atomic layer deposition of noble metals
US20060121733A1 (en) * 2004-10-26 2006-06-08 Kilpela Olli V Selective formation of metal layers in an integrated circuit
US20060118968A1 (en) * 2004-12-07 2006-06-08 Johnston Steven W Alloyed underlayer for microelectronic interconnects
US20060128150A1 (en) * 2004-12-10 2006-06-15 Applied Materials, Inc. Ruthenium as an underlayer for tungsten film deposition
US7067407B2 (en) * 2003-08-04 2006-06-27 Asm International, N.V. Method of growing electrical conductors
US20060137608A1 (en) * 2004-12-28 2006-06-29 Choi Seung W Atomic layer deposition apparatus
US20070026654A1 (en) * 2005-03-15 2007-02-01 Hannu Huotari Systems and methods for avoiding base address collisions
US20070036892A1 (en) * 2005-03-15 2007-02-15 Haukka Suvi P Enhanced deposition of noble metals
US20070059502A1 (en) * 2005-05-05 2007-03-15 Applied Materials, Inc. Integrated process for sputter deposition of a conductive barrier layer, especially an alloy of ruthenium and tantalum, underlying copper or copper alloy seed layer
US20070082132A1 (en) * 2005-10-07 2007-04-12 Asm Japan K.K. Method for forming metal wiring structure
US7220669B2 (en) * 2000-11-30 2007-05-22 Asm International N.V. Thin films for magnetic device
US20080038465A1 (en) * 2004-09-28 2008-02-14 Christian Dussarrat Precursor For Film Formation And Method For Forming Ruthenium-Containing Film
US20080054472A1 (en) * 2006-09-01 2008-03-06 Asm Japan K.K. Method of forming ruthenium film for metal wiring structure
US20080124484A1 (en) * 2006-11-08 2008-05-29 Asm Japan K.K. Method of forming ru film and metal wiring structure
US20090087339A1 (en) * 2007-09-28 2009-04-02 Asm Japan K.K. METHOD FOR FORMING RUTHENIUM COMPLEX FILM USING Beta-DIKETONE-COORDINATED RUTHENIUM PRECURSOR
US20090104777A1 (en) * 2007-10-17 2009-04-23 Asm Genitech Korea Ltd. Methods of depositing a ruthenium film

Family Cites Families (125)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE410873C (en) 1923-08-18 1925-03-26 Neufeldt & Kuhnke Fa Asynchronous machine with capacitors to generate the magnetizing current
GB368850A (en) 1930-06-07 1932-03-14 Westinghouse Brake & Signal Improvements relating to electric current rectifying devices
US6482262B1 (en) 1959-10-10 2002-11-19 Asm Microchemistry Oy Deposition of transition metal carbides
US4210608A (en) 1974-05-13 1980-07-01 Uop Inc. Manufacture of linear primary aldehydes and alcohols
SE393967B (en) 1974-11-29 1977-05-31 Sateko Oy PROCEDURE AND PERFORMANCE OF LAYING BETWEEN THE STORAGE IN A LABOR PACKAGE
BE843167A (en) 1975-06-24 1976-10-18 COOLING AND PICKLING OF A CONTINUOUS ROLLED MACHINE WIRE
US4477296A (en) 1982-09-30 1984-10-16 E. I. Du Pont De Nemours And Company Method for activating metal particles
US4891050A (en) 1985-11-08 1990-01-02 Fuel Tech, Inc. Gasoline additives and gasoline containing soluble platinum group metal compounds and use in internal combustion engines
US4604118A (en) 1985-08-13 1986-08-05 Corning Glass Works Method for synthesizing MgO--Al2 O3 --SiO2 glasses and ceramics
FR2596070A1 (en) 1986-03-21 1987-09-25 Labo Electronique Physique DEVICE COMPRISING A PLANAR SUSCEPTOR ROTATING PARALLEL TO A REFERENCE PLANE AROUND A PERPENDICULAR AXIS AT THIS PLAN
JPH0779136B2 (en) 1986-06-06 1995-08-23 株式会社日立製作所 Semiconductor device
US5820664A (en) 1990-07-06 1998-10-13 Advanced Technology Materials, Inc. Precursor compositions for chemical vapor deposition, and ligand exchange resistant metal-organic precursor solutions comprising same
US5453494A (en) 1990-07-06 1995-09-26 Advanced Technology Materials, Inc. Metal complex source reagents for MOCVD
JPH0485024A (en) 1990-07-30 1992-03-18 Mitsubishi Gas Chem Co Inc Manufacture of copper-clad laminated sheet
EP0469470B1 (en) 1990-07-30 1996-10-09 Mitsubishi Gas Chemical Company, Inc. Process for producing multilayered printed board
WO1993010652A1 (en) 1991-11-22 1993-05-27 Electrochemicals, Inc. Process for improved adhesion between a metallic oxide and a polymer surface
US5637373A (en) 1992-11-19 1997-06-10 Semiconductor Energy Laboratory Co., Ltd. Magnetic recording medium
US6090701A (en) 1994-06-21 2000-07-18 Kabushiki Kaisha Toshiba Method for production of semiconductor device
US6006763A (en) 1995-01-11 1999-12-28 Seiko Epson Corporation Surface treatment method
US5874600A (en) 1995-11-22 1999-02-23 Firmenich Sa Ruthenium catalysts and their use in the asymmetric hydrogenation of cyclopentenones
NL1003538C2 (en) 1996-07-08 1998-01-12 Advanced Semiconductor Mat Method and device for contactless treatment of a disc-shaped semiconductor substrate.
US5695810A (en) 1996-11-20 1997-12-09 Cornell Research Foundation, Inc. Use of cobalt tungsten phosphide as a barrier material for copper metallization
JP3150095B2 (en) 1996-12-12 2001-03-26 日本電気株式会社 Method of manufacturing multilayer wiring structure
US6124189A (en) 1997-03-14 2000-09-26 Kabushiki Kaisha Toshiba Metallization structure and method for a semiconductor device
US5939334A (en) 1997-05-22 1999-08-17 Sharp Laboratories Of America, Inc. System and method of selectively cleaning copper substrate surfaces, in-situ, to remove copper oxides
JPH10340994A (en) 1997-06-06 1998-12-22 Toshiba Corp Manufacture of semiconductor device
KR100269306B1 (en) 1997-07-31 2000-10-16 윤종용 Integrate circuit device having buffer layer containing metal oxide stabilized by low temperature treatment and fabricating method thereof
US5983644A (en) 1997-09-29 1999-11-16 Applied Materials, Inc. Integrated bake and chill plate
KR100274603B1 (en) 1997-10-01 2001-01-15 윤종용 Method and apparatus for fabricating semiconductor device
US6320213B1 (en) 1997-12-19 2001-11-20 Advanced Technology Materials, Inc. Diffusion barriers between noble metal electrodes and metallization layers, and integrated circuit and semiconductor devices comprising same
US5998048A (en) 1998-03-02 1999-12-07 Lucent Technologies Inc. Article comprising anisotropic Co-Fe-Cr-N soft magnetic thin films
JP3116897B2 (en) 1998-03-18 2000-12-11 日本電気株式会社 Fine wiring formation method
DE19815275B4 (en) 1998-04-06 2009-06-25 Evonik Degussa Gmbh Alkylidene complexes of ruthenium with N-heterocyclic carbene ligands and their use as highly active, selective catalysts for olefin metathesis
US6323131B1 (en) 1998-06-13 2001-11-27 Agere Systems Guardian Corp. Passivated copper surfaces
US6130123A (en) 1998-06-30 2000-10-10 Intel Corporation Method for making a complementary metal gate electrode technology
US6461675B2 (en) 1998-07-10 2002-10-08 Cvc Products, Inc. Method for forming a copper film on a substrate
KR100275738B1 (en) 1998-08-07 2000-12-15 윤종용 Method for producing thin film using atomatic layer deposition
US6133159A (en) 1998-08-27 2000-10-17 Micron Technology, Inc. Methods for preparing ruthenium oxide films
US6108937A (en) 1998-09-10 2000-08-29 Asm America, Inc. Method of cooling wafers
US6153443A (en) 1998-12-21 2000-11-28 Motorola, Inc. Method of fabricating a magnetic random access memory
US6294836B1 (en) 1998-12-22 2001-09-25 Cvc Products Inc. Semiconductor chip interconnect barrier material and fabrication method
US6444868B1 (en) 1999-02-17 2002-09-03 Exxon Mobil Chemical Patents Inc. Process to control conversion of C4+ and heavier stream to lighter products in oxygenate conversion reactions
US6136163A (en) 1999-03-05 2000-10-24 Applied Materials, Inc. Apparatus for electro-chemical deposition with thermal anneal chamber
US6305314B1 (en) 1999-03-11 2001-10-23 Genvs, Inc. Apparatus and concept for minimizing parasitic chemical vapor deposition during atomic layer deposition
US20020000665A1 (en) 1999-04-05 2002-01-03 Alexander L. Barr Semiconductor device conductive bump and interconnect barrier
US6297539B1 (en) * 1999-07-19 2001-10-02 Sharp Laboratories Of America, Inc. Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same
US6478931B1 (en) 1999-08-06 2002-11-12 University Of Virginia Patent Foundation Apparatus and method for intra-layer modulation of the material deposition and assist beam and the multilayer structure produced therefrom
US6290880B1 (en) 1999-12-01 2001-09-18 The United States Of America As Represented By The Secretary Of The Navy Electrically conducting ruthenium dioxide-aerogel composite
NL1013984C2 (en) 1999-12-29 2001-07-02 Asm Int Method and device for treating substrates.
TW490718B (en) 2000-01-25 2002-06-11 Toshiba Corp Semiconductor device and the manufacturing method thereof
US7419903B2 (en) 2000-03-07 2008-09-02 Asm International N.V. Thin films
WO2001071713A1 (en) 2000-03-22 2001-09-27 Nve Corporation Read heads in planar monolithic integrated circuit chips
FI117978B (en) 2000-04-14 2007-05-15 Asm Int Method and apparatus for constructing a thin film on a substrate
US6482733B2 (en) 2000-05-15 2002-11-19 Asm Microchemistry Oy Protective layers prior to alternating layer deposition
KR100403611B1 (en) * 2000-06-07 2003-11-01 삼성전자주식회사 Metal-insulator-metal capacitor and manufacturing method thereof
US6429127B1 (en) 2000-06-08 2002-08-06 Micron Technology, Inc. Methods for forming rough ruthenium-containing layers and structures/methods using same
WO2001099166A1 (en) * 2000-06-08 2001-12-27 Genitech Inc. Thin film forming method
AU2001275978A1 (en) 2000-07-24 2002-02-05 Motorola, Inc. Spin valve structure
AU2001276980A1 (en) 2000-07-24 2002-02-05 Motorola, Inc. Semiconductor structure including a magnetic tunnel junction
JP3574383B2 (en) 2000-07-31 2004-10-06 富士通株式会社 Semiconductor device and manufacturing method thereof
US6455424B1 (en) 2000-08-07 2002-09-24 Micron Technology, Inc. Selective cap layers over recessed polysilicon plugs
US6602653B1 (en) 2000-08-25 2003-08-05 Micron Technology, Inc. Conductive material patterning methods
US6461909B1 (en) * 2000-08-30 2002-10-08 Micron Technology, Inc. Process for fabricating RuSixOy-containing adhesion layers
US6617173B1 (en) 2000-10-11 2003-09-09 Genus, Inc. Integration of ferromagnetic films with ultrathin insulating film using atomic layer deposition
JP3598055B2 (en) 2000-11-08 2004-12-08 田中貴金属工業株式会社 Method for producing bis (alkylcyclopentadienyl) ruthenium and method for producing bis (alkylcyclopentadienyl) ruthenium and ruthenium thin film or ruthenium compound thin film produced by the method
KR100386034B1 (en) 2000-12-06 2003-06-02 에이에스엠 마이크로케미스트리 리미티드 Method of Fabricating Semiconductor Device Employing Copper Interconnect Structure Having Diffusion Barrier Stuffed with Metal Oxide
US6479100B2 (en) 2001-04-05 2002-11-12 Applied Materials, Inc. CVD ruthenium seed for CVD ruthenium deposition
KR100406534B1 (en) 2001-05-03 2003-11-20 주식회사 하이닉스반도체 Method for fabricating ruthenium thin film
US7700454B2 (en) 2001-07-24 2010-04-20 Samsung Electronics Co., Ltd. Methods of forming integrated circuit electrodes and capacitors by wrinkling a layer that includes a high percentage of impurities
KR100721504B1 (en) 2001-08-02 2007-05-23 에이에스엠지니텍코리아 주식회사 Plasma enhanced atomic layer deposition equipment and method of forming a thin film using the same
EP1421606A4 (en) 2001-08-06 2008-03-05 Genitech Co Ltd Plasma enhanced atomic layer deposition (peald) equipment and method of forming a conducting thin film using the same thereof
KR100427030B1 (en) 2001-08-27 2004-04-14 주식회사 하이닉스반도체 Method for forming film with muli-elements and fabricating capacitor using the same
KR100727372B1 (en) 2001-09-12 2007-06-12 토소가부시키가이샤 Ruthenium complex, manufacturing process thereof and the method for forming thin-film using the complex
US20030059535A1 (en) 2001-09-25 2003-03-27 Lee Luo Cycling deposition of low temperature films in a cold wall single wafer process chamber
US7780785B2 (en) 2001-10-26 2010-08-24 Applied Materials, Inc. Gas delivery apparatus for atomic layer deposition
JP2003133531A (en) 2001-10-26 2003-05-09 Fujitsu Ltd Electronic device and manufacturing method therefor
EP1446408A1 (en) 2001-11-09 2004-08-18 Yun Chi Volatile noble metal organometallic complexes
KR100422597B1 (en) 2001-11-27 2004-03-16 주식회사 하이닉스반도체 Method of forming semiconductor device with capacitor and metal-interconnection in damascene process
KR20030043380A (en) 2001-11-28 2003-06-02 주식회사 하이닉스반도체 Method of manufacturing capacitor for semiconductor device
US6656748B2 (en) 2002-01-31 2003-12-02 Texas Instruments Incorporated FeRAM capacitor post stack etch clean/repair
KR100468847B1 (en) 2002-04-02 2005-01-29 삼성전자주식회사 Chemical vapor deposition method using alcohols for forming metal-oxide thin film
US6586330B1 (en) 2002-05-07 2003-07-01 Tokyo Electron Limited Method for depositing conformal nitrified tantalum silicide films by thermal CVD
US6784101B1 (en) * 2002-05-16 2004-08-31 Advanced Micro Devices Inc Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation
JP2003332426A (en) 2002-05-17 2003-11-21 Renesas Technology Corp Method for manufacturing semiconductor device and semiconductor device
US7404985B2 (en) 2002-06-04 2008-07-29 Applied Materials, Inc. Noble metal layer formation for copper film deposition
JP4614639B2 (en) 2002-06-10 2011-01-19 アイメック Enhancement of dielectric constant (k value) of Hf-containing composition
US7524766B2 (en) 2002-07-15 2009-04-28 Hitachi Kokusai Electric Inc. Method for manufacturing semiconductor device and substrate processing apparatus
US6861355B2 (en) 2002-08-29 2005-03-01 Micron Technology, Inc. Metal plating using seed film
DE10255841A1 (en) 2002-11-29 2004-06-17 Infineon Technologies Ag Process for structuring ruthenium or ruthenium (IV) oxide layers used for a trench capacitor comprises depositing ruthenium or ruthenium (IV) oxide on sections of a substrate, depositing a covering layer, and further processing
JP4009550B2 (en) 2003-03-27 2007-11-14 エルピーダメモリ株式会社 Method for forming metal oxide film
KR100505680B1 (en) 2003-03-27 2005-08-03 삼성전자주식회사 Method for manufacturing semiconductor memory device having ruthenium film and apparatus for manufacturing the ruthenium film
US6955986B2 (en) 2003-03-27 2005-10-18 Asm International N.V. Atomic layer deposition methods for forming a multi-layer adhesion-barrier layer for integrated circuits
US6737313B1 (en) 2003-04-16 2004-05-18 Micron Technology, Inc. Surface treatment of an oxide layer to enhance adhesion of a ruthenium metal layer
US7601223B2 (en) 2003-04-29 2009-10-13 Asm International N.V. Showerhead assembly and ALD methods
KR101090895B1 (en) 2003-05-09 2011-12-08 에이에스엠 아메리카, 인코포레이티드 Reactor surface passivation through chemical deactivation
US7107998B2 (en) * 2003-10-16 2006-09-19 Novellus Systems, Inc. Method for preventing and cleaning ruthenium-containing deposits in a CVD apparatus
US7015093B2 (en) 2003-10-30 2006-03-21 Texas Instruments Incorporated Capacitor integration at top-metal level with a protection layer for the copper surface
US7074719B2 (en) 2003-11-28 2006-07-11 International Business Machines Corporation ALD deposition of ruthenium
US7273526B2 (en) 2004-04-15 2007-09-25 Asm Japan K.K. Thin-film deposition apparatus
KR20050103373A (en) 2004-04-26 2005-10-31 삼성전자주식회사 Apparatus of rotating pad conditioning disk
JP2005314713A (en) 2004-04-27 2005-11-10 L'air Liquide Sa Pour L'etude & L'exploitation Des Procede S Georges Claude Method for manufacturing ruthenium film or ruthenium oxide film
US7312165B2 (en) 2004-05-05 2007-12-25 Jursich Gregory M Codeposition of hafnium-germanium oxides on substrates used in or for semiconductor devices
US20050252449A1 (en) 2004-05-12 2005-11-17 Nguyen Son T Control of gas flow and delivery to suppress the formation of particles in an MOCVD/ALD system
US7211509B1 (en) 2004-06-14 2007-05-01 Novellus Systems, Inc, Method for enhancing the nucleation and morphology of ruthenium films on dielectric substrates using amine containing compounds
US7241686B2 (en) 2004-07-20 2007-07-10 Applied Materials, Inc. Atomic layer deposition of tantalum-containing materials using the tantalum precursor TAIMATA
US7300869B2 (en) 2004-09-20 2007-11-27 Lsi Corporation Integrated barrier and seed layer for copper interconnect technology
US7438949B2 (en) 2005-01-27 2008-10-21 Applied Materials, Inc. Ruthenium containing layer deposition method
US7408747B2 (en) 2005-02-01 2008-08-05 Hitachi Global Storage Technologies Netherlands B.V. Enhanced anti-parallel-pinned sensor using thin ruthenium spacer and high magnetic field annealing
US20060177601A1 (en) 2005-02-10 2006-08-10 Hyung-Sang Park Method of forming a ruthenium thin film using a plasma enhanced atomic layer deposition apparatus and the method thereof
WO2006091510A1 (en) 2005-02-22 2006-08-31 Asm America, Inc. Plasma pre-treating surfaces for atomic layer deposition
US7273814B2 (en) 2005-03-16 2007-09-25 Tokyo Electron Limited Method for forming a ruthenium metal layer on a patterned substrate
US7220671B2 (en) 2005-03-31 2007-05-22 Intel Corporation Organometallic precursors for the chemical phase deposition of metal films in interconnect applications
WO2006134930A1 (en) 2005-06-13 2006-12-21 Hitachi Kokusai Electric Inc. Process for production of semiconductor device and apparatus for treatment of substrate
US20070014919A1 (en) 2005-07-15 2007-01-18 Jani Hamalainen Atomic layer deposition of noble metal oxides
US7968437B2 (en) 2005-11-18 2011-06-28 Hitachi Kokusai Electric Inc. Semiconductor device manufacturing method and substrate processing apparatus
KR101379015B1 (en) 2006-02-15 2014-03-28 한국에이에스엠지니텍 주식회사 METHOD OF DEPOSITING Ru FILM USING PEALD AND DENSE Ru FILM
US20080296768A1 (en) 2006-12-14 2008-12-04 Chebiam Ramanan V Copper nucleation in interconnects having ruthenium layers
US20080171436A1 (en) 2007-01-11 2008-07-17 Asm Genitech Korea Ltd. Methods of depositing a ruthenium film
CN101617065B (en) 2007-02-21 2011-11-23 乔治洛德方法研究和开发液化空气有限公司 Methods for forming a ruthenium-based film on a substrate
US7786006B2 (en) 2007-02-26 2010-08-31 Tokyo Electron Limited Interconnect structures with a metal nitride diffusion barrier containing ruthenium and method of forming
KR100817090B1 (en) 2007-02-28 2008-03-26 삼성전자주식회사 Method of fabricating a semiconductor device
DE602008002578D1 (en) 2007-04-03 2010-10-28 Firmenich & Cie 1,4-HYDROGENATION OF SORBOL WITH RU COMPLEXES
US7615480B2 (en) 2007-06-20 2009-11-10 Lam Research Corporation Methods of post-contact back end of the line through-hole via integration
US7655564B2 (en) 2007-12-12 2010-02-02 Asm Japan, K.K. Method for forming Ta-Ru liner layer for Cu wiring
DE102008026284A1 (en) 2008-06-02 2009-12-03 Umicore Ag & Co. Kg Process for the preparation of ruthenium-dienyl complexes

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4670110A (en) * 1979-07-30 1987-06-02 Metallurgical, Inc. Process for the electrolytic deposition of aluminum using a composite anode
US4902551A (en) * 1987-12-14 1990-02-20 Hitachi Chemical Company, Ltd. Process for treating copper surface
US5382333A (en) * 1990-07-30 1995-01-17 Mitsubishi Gas Chemical Company, Inc. Process for producing copper clad laminate
US5106454A (en) * 1990-11-01 1992-04-21 Shipley Company Inc. Process for multilayer printed circuit board manufacture
US5865365A (en) * 1991-02-19 1999-02-02 Hitachi, Ltd. Method of fabricating an electronic circuit device
US5731634A (en) * 1992-07-31 1998-03-24 Kabushiki Kaisha Toshiba Semiconductor device having a metal film formed in a groove in an insulating film
US5391517A (en) * 1993-09-13 1995-02-21 Motorola Inc. Process for forming copper interconnect structure
US5711811A (en) * 1994-11-28 1998-01-27 Mikrokemia Oy Method and equipment for growing thin films
US5637533A (en) * 1995-05-17 1997-06-10 Hyundai Electronics Industries Co., Ltd. Method for fabricating a diffusion barrier metal layer in a semiconductor device
US20020006711A1 (en) * 1995-09-08 2002-01-17 Semiconductor Energy Laboratory Co., Ltd. Japanese Corporation Method of manufacturing a semiconductor device
US6015986A (en) * 1995-12-22 2000-01-18 Micron Technology, Inc. Rugged metal electrodes for metal-insulator-metal capacitors
US6268291B1 (en) * 1995-12-29 2001-07-31 International Business Machines Corporation Method for forming electromigration-resistant structures by doping
US5916365A (en) * 1996-08-16 1999-06-29 Sherman; Arthur Sequential chemical vapor deposition
US6342277B1 (en) * 1996-08-16 2002-01-29 Licensee For Microelectronics: Asm America, Inc. Sequential chemical vapor deposition
US5923056A (en) * 1996-10-10 1999-07-13 Lucent Technologies Inc. Electronic components with doped metal oxide dielectric materials and a process for making electronic components with doped metal oxide dielectric materials
US6335280B1 (en) * 1997-01-13 2002-01-01 Asm America, Inc. Tungsten silicide deposition process
US6066892A (en) * 1997-05-08 2000-05-23 Applied Materials, Inc. Copper alloy seed layer for copper metallization in an integrated circuit
US5884009A (en) * 1997-08-07 1999-03-16 Tokyo Electron Limited Substrate treatment system
US6033584A (en) * 1997-12-22 2000-03-07 Advanced Micro Devices, Inc. Process for reducing copper oxide during integrated circuit fabrication
US6074945A (en) * 1998-08-27 2000-06-13 Micron Technology, Inc. Methods for preparing ruthenium metal films
US6541067B1 (en) * 1998-08-27 2003-04-01 Micron Technology, Inc. Solvated ruthenium precursors for direct liquid injection of ruthenium and ruthenium oxide and method of using same
US6063705A (en) * 1998-08-27 2000-05-16 Micron Technology, Inc. Precursor chemistries for chemical vapor deposition of ruthenium and ruthenium oxide
US6403414B2 (en) * 1998-09-03 2002-06-11 Micron Technology, Inc. Method for producing low carbon/oxygen conductive layers
US6346151B1 (en) * 1999-02-24 2002-02-12 Micron Technology, Inc. Method and apparatus for electroless plating a contact pad
US6359159B1 (en) * 1999-05-19 2002-03-19 Research Foundation Of State University Of New York MOCVD precursors based on organometalloid ligands
US6171910B1 (en) * 1999-07-21 2001-01-09 Motorola Inc. Method for forming a semiconductor device
US6391785B1 (en) * 1999-08-24 2002-05-21 Interuniversitair Microelektronica Centrum (Imec) Method for bottomless deposition of barrier layers in integrated circuit metallization schemes
US6852635B2 (en) * 1999-08-24 2005-02-08 Interuniversitair Nizroelecmica Method for bottomless deposition of barrier layers in integrated circuit metallization schemes
US6511539B1 (en) * 1999-09-08 2003-01-28 Asm America, Inc. Apparatus and method for growth of a thin film
US6040243A (en) * 1999-09-20 2000-03-21 Chartered Semiconductor Manufacturing Ltd. Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion
US6403191B1 (en) * 1999-09-21 2002-06-11 Strata-Tac, Inc. Laminate with integrated compact disk label and methods
US20020027286A1 (en) * 1999-09-30 2002-03-07 Srinivasan Sundararajan Low leakage current silicon carbonitride prepared using methane, ammonia and silane for copper diffusion barrier, etchstop and passivation applications
US6576053B1 (en) * 1999-10-06 2003-06-10 Samsung Electronics Co., Ltd. Method of forming thin film using atomic layer deposition method
US6203613B1 (en) * 1999-10-19 2001-03-20 International Business Machines Corporation Atomic layer deposition with nitrate containing precursors
US20010003064A1 (en) * 1999-12-02 2001-06-07 Nec Corporation Method for fabricating semiconductor device and apparatus for fabricating same
US6720262B2 (en) * 1999-12-15 2004-04-13 Genitech, Inc. Method of forming copper interconnections and thin films using chemical vapor deposition with catalyst
US6842740B1 (en) * 1999-12-20 2005-01-11 Hewlett-Packard Development Company, L.P. Method for providing automatic payment when making duplicates of copyrighted material
US6551399B1 (en) * 2000-01-10 2003-04-22 Genus Inc. Fully integrated process for MIM capacitors using atomic layer deposition
US6703708B2 (en) * 2000-03-07 2004-03-09 Asm International N.V. Graded thin films
US20030013302A1 (en) * 2000-03-07 2003-01-16 Tue Nguyen Multilayered copper structure for improving adhesion property
US6534395B2 (en) * 2000-03-07 2003-03-18 Asm Microchemistry Oy Method of forming graded thin films using alternating pulses of vapor phase reactants
US6380080B2 (en) * 2000-03-08 2002-04-30 Micron Technology, Inc. Methods for preparing ruthenium metal films
US6680540B2 (en) * 2000-03-08 2004-01-20 Hitachi, Ltd. Semiconductor device having cobalt alloy film with boron
US20020013487A1 (en) * 2000-04-03 2002-01-31 Norman John Anthony Thomas Volatile precursors for deposition of metals and metal-containing films
US20030135061A1 (en) * 2000-04-03 2003-07-17 Norman John Anthony Thomas Volatile precursors for deposition of metals and metal-containing films
US6984591B1 (en) * 2000-04-20 2006-01-10 International Business Machines Corporation Precursor source mixtures
US20040038529A1 (en) * 2000-05-15 2004-02-26 Soininen Pekka Juha Process for producing integrated circuits
US20080146042A1 (en) * 2000-05-15 2008-06-19 Asm International N.V. Method of growing electrical conductors
US20040005753A1 (en) * 2000-05-15 2004-01-08 Juhana Kostamo Method of growing electrical conductors
US20020004293A1 (en) * 2000-05-15 2002-01-10 Soininen Pekka J. Method of growing electrical conductors
US6878628B2 (en) * 2000-05-15 2005-04-12 Asm International Nv In situ reduction of copper oxide prior to silicon carbide deposition
US7494927B2 (en) * 2000-05-15 2009-02-24 Asm International N.V. Method of growing electrical conductors
US6679951B2 (en) * 2000-05-15 2004-01-20 Asm Intenational N.V. Metal anneal with oxidation prevention
US6887795B2 (en) * 2000-05-15 2005-05-03 Asm International N.V. Method of growing electrical conductors
US6759325B2 (en) * 2000-05-15 2004-07-06 Asm Microchemistry Oy Sealing porous structures
US6395650B1 (en) * 2000-10-23 2002-05-28 International Business Machines Corporation Methods for forming metal oxide layers with enhanced purity
US7011981B2 (en) * 2000-11-13 2006-03-14 Lg.Philips Lcd Co., Ltd. Method for forming thin film and method for fabricating liquid crystal display using the same
US7220669B2 (en) * 2000-11-30 2007-05-22 Asm International N.V. Thin films for magnetic device
US6849122B1 (en) * 2001-01-19 2005-02-01 Novellus Systems, Inc. Thin layer metal chemical vapor deposition
US6593656B2 (en) * 2001-02-05 2003-07-15 Micron Technology, Inc. Multilevel copper interconnects for ultra large scale integration
US6420189B1 (en) * 2001-04-27 2002-07-16 Advanced Micro Devices, Inc. Superconducting damascene interconnected for integrated circuit
US20050124154A1 (en) * 2001-12-28 2005-06-09 Hyung-Sang Park Method of forming copper interconnections for semiconductor integrated circuits on a substrate
US20050020060A1 (en) * 2002-01-29 2005-01-27 Titta Aaltonen Process for producing metal thin films by ALD
US20040105934A1 (en) * 2002-06-04 2004-06-03 Mei Chang Ruthenium layer formation for copper film deposition
US6881260B2 (en) * 2002-06-25 2005-04-19 Micron Technology, Inc. Process for direct deposition of ALD RhO2
US20050082587A1 (en) * 2002-08-29 2005-04-21 Micron Technology, Inc. Platinum stuffed with silicon oxide as a diffusion oxygen barrier for semiconductor devices
US20040053496A1 (en) * 2002-09-17 2004-03-18 Eun-Seok Choi Method for forming metal films
US20040118697A1 (en) * 2002-10-01 2004-06-24 Applied Materials, Inc. Metal deposition process with pre-cleaning before electrochemical deposition
US20060093848A1 (en) * 2002-10-15 2006-05-04 Senkevich John J Atomic layer deposition of noble metals
US20040082125A1 (en) * 2002-10-29 2004-04-29 Taiwan Semiconductor Manufacturing Company Novel dual gate dielectric scheme: SiON for high performance devices and high k for low power devices
US20040087143A1 (en) * 2002-11-05 2004-05-06 Norman John Anthony Thomas Process for atomic layer deposition of metal films
US20040142558A1 (en) * 2002-12-05 2004-07-22 Granneman Ernst H. A. Apparatus and method for atomic layer deposition on substrates
US20040126944A1 (en) * 2002-12-31 2004-07-01 Pacheco Rotondaro Antonio Luis Methods for forming interfacial layer for deposition of high-k dielectrics
US6881437B2 (en) * 2003-06-16 2005-04-19 Blue29 Llc Methods and system for processing a microelectronic topography
US20050009325A1 (en) * 2003-06-18 2005-01-13 Hua Chung Atomic layer deposition of barrier materials
US7067407B2 (en) * 2003-08-04 2006-06-27 Asm International, N.V. Method of growing electrical conductors
US20050048794A1 (en) * 2003-08-28 2005-03-03 Brask Justin K. Method for making a semiconductor device having a high-k gate dielectric
US20050092247A1 (en) * 2003-08-29 2005-05-05 Schmidt Ryan M. Gas mixer and manifold assembly for ALD reactor
US20050085031A1 (en) * 2003-10-15 2005-04-21 Applied Materials, Inc. Heterogeneous activation layers formed by ionic and electroless reactions used for IC interconnect capping layers
US20050089632A1 (en) * 2003-10-28 2005-04-28 Marko Vehkamaki Process for producing oxide films
US20050087879A1 (en) * 2003-10-28 2005-04-28 Samsung Electronics Co., Ltd. Logic device having vertically extending metal-insulator-metal capacitor between interconnect layers and method of fabricating the same
US20050098440A1 (en) * 2003-11-10 2005-05-12 Kailasam Sridhar K. Methods for the electrochemical deposition of copper onto a barrier layer of a work piece
US20060013955A1 (en) * 2004-07-09 2006-01-19 Yoshihide Senzaki Deposition of ruthenium and/or ruthenium oxide films
US20060026654A1 (en) * 2004-07-27 2006-02-02 Samsung Electronics Co., Ltd. Live content management method, source device, and sink device
US20060035462A1 (en) * 2004-08-13 2006-02-16 Micron Technology, Inc. Systems and methods for forming metal-containing layers using vapor deposition processes
US20080038465A1 (en) * 2004-09-28 2008-02-14 Christian Dussarrat Precursor For Film Formation And Method For Forming Ruthenium-Containing Film
US20060073276A1 (en) * 2004-10-04 2006-04-06 Eric Antonissen Multi-zone atomic layer deposition apparatus and method
US20060121733A1 (en) * 2004-10-26 2006-06-08 Kilpela Olli V Selective formation of metal layers in an integrated circuit
US20060118968A1 (en) * 2004-12-07 2006-06-08 Johnston Steven W Alloyed underlayer for microelectronic interconnects
US20060128150A1 (en) * 2004-12-10 2006-06-15 Applied Materials, Inc. Ruthenium as an underlayer for tungsten film deposition
US20060137608A1 (en) * 2004-12-28 2006-06-29 Choi Seung W Atomic layer deposition apparatus
US20070036892A1 (en) * 2005-03-15 2007-02-15 Haukka Suvi P Enhanced deposition of noble metals
US20070026654A1 (en) * 2005-03-15 2007-02-01 Hannu Huotari Systems and methods for avoiding base address collisions
US20070059502A1 (en) * 2005-05-05 2007-03-15 Applied Materials, Inc. Integrated process for sputter deposition of a conductive barrier layer, especially an alloy of ruthenium and tantalum, underlying copper or copper alloy seed layer
US20070082132A1 (en) * 2005-10-07 2007-04-12 Asm Japan K.K. Method for forming metal wiring structure
US20080054472A1 (en) * 2006-09-01 2008-03-06 Asm Japan K.K. Method of forming ruthenium film for metal wiring structure
US20080124484A1 (en) * 2006-11-08 2008-05-29 Asm Japan K.K. Method of forming ru film and metal wiring structure
US20090087339A1 (en) * 2007-09-28 2009-04-02 Asm Japan K.K. METHOD FOR FORMING RUTHENIUM COMPLEX FILM USING Beta-DIKETONE-COORDINATED RUTHENIUM PRECURSOR
US20090104777A1 (en) * 2007-10-17 2009-04-23 Asm Genitech Korea Ltd. Methods of depositing a ruthenium film

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7955979B2 (en) 2000-05-15 2011-06-07 Asm International N.V. Method of growing electrical conductors
US8536058B2 (en) 2000-05-15 2013-09-17 Asm International N.V. Method of growing electrical conductors
US8927403B2 (en) 2005-03-15 2015-01-06 Asm International N.V. Selective deposition of noble metal thin films
US8025922B2 (en) 2005-03-15 2011-09-27 Asm International N.V. Enhanced deposition of noble metals
US9587307B2 (en) 2005-03-15 2017-03-07 Asm International N.V. Enhanced deposition of noble metals
US8501275B2 (en) 2005-03-15 2013-08-06 Asm International N.V. Enhanced deposition of noble metals
US9469899B2 (en) 2005-03-15 2016-10-18 Asm International N.V. Selective deposition of noble metal thin films
US7879739B2 (en) * 2006-05-09 2011-02-01 Intel Corporation Thin transition layer between a group III-V substrate and a high-k gate dielectric layer
US20070264837A1 (en) * 2006-05-09 2007-11-15 Willy Rachmady Thin transition layer between a group iii-v substrate and a high-k gate dielectric layer
US20090104777A1 (en) * 2007-10-17 2009-04-23 Asm Genitech Korea Ltd. Methods of depositing a ruthenium film
US8273408B2 (en) 2007-10-17 2012-09-25 Asm Genitech Korea Ltd. Methods of depositing a ruthenium film
US8084104B2 (en) 2008-08-29 2011-12-27 Asm Japan K.K. Atomic composition controlled ruthenium alloy film formed by plasma-enhanced atomic layer deposition
US8133555B2 (en) 2008-10-14 2012-03-13 Asm Japan K.K. Method for forming metal film by ALD using beta-diketone metal complex
US9129897B2 (en) 2008-12-19 2015-09-08 Asm International N.V. Metal silicide, metal germanide, methods for making the same
US9379011B2 (en) 2008-12-19 2016-06-28 Asm International N.V. Methods for depositing nickel films and for making nickel silicide and nickel germanide
US9634106B2 (en) 2008-12-19 2017-04-25 Asm International N.V. Doped metal germanide and methods for making the same
US10553440B2 (en) 2008-12-19 2020-02-04 Asm International N.V. Methods for depositing nickel films and for making nickel silicide and nickel germanide
US8329569B2 (en) 2009-07-31 2012-12-11 Asm America, Inc. Deposition of ruthenium or ruthenium dioxide
US10043880B2 (en) 2011-04-22 2018-08-07 Asm International N.V. Metal silicide, metal germanide, methods for making the same
US9059217B2 (en) * 2013-03-28 2015-06-16 International Business Machines Corporation FET semiconductor device with low resistance and enhanced metal fill
US20140291760A1 (en) * 2013-03-28 2014-10-02 International Business Machines Corporation Fet semiconductor device with low resistance and enhanced metal fill
US10204790B2 (en) 2015-07-28 2019-02-12 Asm Ip Holding B.V. Methods for thin film deposition
US11421321B2 (en) 2015-07-28 2022-08-23 Asm Ip Holding B.V. Apparatuses for thin film deposition
US9607842B1 (en) 2015-10-02 2017-03-28 Asm Ip Holding B.V. Methods of forming metal silicides
US10199234B2 (en) 2015-10-02 2019-02-05 Asm Ip Holding B.V. Methods of forming metal silicides

Also Published As

Publication number Publication date
US20150315703A1 (en) 2015-11-05
US20070026654A1 (en) 2007-02-01
US20100136776A1 (en) 2010-06-03
US20120009773A1 (en) 2012-01-12
US7985669B2 (en) 2011-07-26
US7666773B2 (en) 2010-02-23
US9469899B2 (en) 2016-10-18
US8927403B2 (en) 2015-01-06

Similar Documents

Publication Publication Date Title
US9469899B2 (en) Selective deposition of noble metal thin films
US9587307B2 (en) Enhanced deposition of noble metals
US10847361B2 (en) Selective deposition of aluminum and nitrogen containing material
US11174550B2 (en) Selective deposition on metal or metallic surfaces relative to dielectric surfaces
US10903113B2 (en) Selective deposition of aluminum and nitrogen containing material
KR20230044373A (en) Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures
US7217615B1 (en) Capacitor fabrication methods including forming a conductive layer
KR100985352B1 (en) Process for producing metal thin films by ald
US20070014919A1 (en) Atomic layer deposition of noble metal oxides
US20050238808A1 (en) Methods for producing ruthenium film and ruthenium oxide film
JP2006257551A (en) Enhanced deposition of noble metal by ald
US9981286B2 (en) Selective formation of metal silicides
US7435678B2 (en) Method of depositing noble metal electrode using oxidation-reduction reaction
KR102470043B1 (en) Selective deposition of aluminum and nitrogen containing material

Legal Events

Date Code Title Description
AS Assignment

Owner name: ASM INTERNATIONAL N.V.,NETHERLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HUOTARI, HANNU;TUOMINEN, MARKO;LEINIKKA, MIIKA;SIGNING DATES FROM 20060918 TO 20060920;REEL/FRAME:018351/0697

Owner name: ASM INTERNATIONAL N.V., NETHERLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HUOTARI, HANNU;TUOMINEN, MARKO;LEINIKKA, MIIKA;SIGNING DATES FROM 20060918 TO 20060920;REEL/FRAME:018351/0697

Owner name: ASM INTERNATIONAL N.V., NETHERLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HUOTARI, HANNU;TUOMINEN, MARKO;LEINIKKA, MIIKA;REEL/FRAME:018351/0697;SIGNING DATES FROM 20060918 TO 20060920

STCF Information on status: patent grant

Free format text: PATENTED CASE

CC Certificate of correction
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12