US20080169518A1 - Semiconductor structure with field shield and method of forming the structure. - Google Patents
Semiconductor structure with field shield and method of forming the structure. Download PDFInfo
- Publication number
- US20080169518A1 US20080169518A1 US11/623,164 US62316407A US2008169518A1 US 20080169518 A1 US20080169518 A1 US 20080169518A1 US 62316407 A US62316407 A US 62316407A US 2008169518 A1 US2008169518 A1 US 2008169518A1
- Authority
- US
- United States
- Prior art keywords
- isolation layer
- conductive pad
- conductor
- doped
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 107
- 238000000034 method Methods 0.000 title description 14
- 238000002955 isolation Methods 0.000 claims abstract description 90
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 230000005669 field effect Effects 0.000 claims abstract description 23
- 239000004020 conductor Substances 0.000 claims description 48
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 abstract description 5
- 230000001681 protective effect Effects 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 26
- 125000006850 spacer group Chemical group 0.000 description 25
- 235000012431 wafers Nutrition 0.000 description 23
- 239000002019 doping agent Substances 0.000 description 21
- 239000000377 silicon dioxide Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 12
- 235000012239 silicon dioxide Nutrition 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910021332 silicide Inorganic materials 0.000 description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 229910052787 antimony Inorganic materials 0.000 description 6
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 6
- 229910052785 arsenic Inorganic materials 0.000 description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
Definitions
- the embodiments of the invention generally relate to semiconductor devices and, more particularly, to a semiconductor structure that incorporates a semiconductor device coupled to a field shield.
- Silicon-on-insulator (SOI) technology and, particularly, partially depleted SOI technology, is often subject to damage during wafer processing in the back-end of the line (BEOL) sectors.
- charging of metal lines in processing tools can pass a current from the on-wafer wires through semiconductor devices and into the buried oxide (BOX) before exiting the substrate wafer.
- BOX buried oxide
- the presence of this current in the BOX can lead to a trapped electronic charge.
- the trapped electronic charge in the BOX can alter the electrical properties of the semiconductor devices and, thereby, degrade yield and/or reliability of circuits. Therefore, there is a need in the art for a semiconductor structure and a method of forming the structure that avoids the build up of an electric charge in the BOX during BEOL processing.
- a field shield below a semiconductor device e.g., below a field effect transistor (FET) or a diode.
- the field shield is sandwiched between upper and lower isolation layers on a wafer.
- a local interconnect extends through the upper isolation layer and connects the field shield to a doped semiconductor region of the semiconductor device (e.g., a source/drain region of a FET or a cathode or anode of a diode).
- Current that passes into the device during back-end of the line (BEOL) charging is shunted by the local interconnect away from the upper isolation layer and into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds into the lower isolation layer and into the substrate below.
- This field shield further functions as a protective barrier from any electric charge that is trapped within the lower isolation layer or substrate.
- embodiments of the semiconductor structure of the invention comprise a first isolation layer on a substrate, a conductive pad (i.e., a field shield) on the first isolation layer and a second isolation layer on the conductive pad.
- the conductive pad is electrically isolated from the substrate.
- the structure can further comprise a device above the second isolation layer.
- the device can comprise doped semiconductor regions and one of these doped semiconductor regions can be electrically coupled to the conductive pad by a local interconnect.
- the device can comprise a field effect transistor with doped source/drain regions and one of the source/drain regions can be electrically coupled to the conductive pad.
- the device can comprise a pn junction diode with a doped anode and a doped cathode and either the anode or the cathode can be electrically coupled to the conductive pad.
- the local interconnect can comprise a conductor. Specifically, this conductor can be located adjacent to a selected doped semiconductor region (i.e., adjacent to a source/drain region of a field effect transistor or adjacent to an anode or cathode of a diode) and can extend vertically through the second isolation layer to the conductive pad such that it electrically couples the conductive pad to the selected doped semiconductor region.
- This local interconnect i.e., the conductor
- the conductive pad will further protect the device from any electric charge that is built up in the first isolation layer and the substrate.
- the conductive pad and the conductor can each comprise a suitable conductive material, for example, a doped polysilicon or a conductive metal.
- the structure can comprise a metal strap that bridges both the conductor and the doped semiconductor region, thereby allowing current to flow easily between the device and local interconnect to the field shield even if the conductor and the adjacent doped semiconductor region of the device are doped with different type dopants.
- Embodiments of a method of forming a semiconductor structure comprise providing a wafer with a first isolation layer on a substrate, a conductive layer on the first isolation layer, a second isolation layer on the conductive layer and a semiconductor layer on the second isolation layer.
- a trench is patterned and etched in the wafer through the semiconductor layer to the first isolation layer so as to form a stack, including the semiconductor layer, the second isolation layer and conductive layer, on the first isolation layer.
- a sidewall spacer is formed adjacent to a sidewall of the stack.
- the sidewall spacer can be formed with a dielectric material. After the dielectric sidewall spacer is formed, the remaining portion of the trench is filled with another different dielectric material. The dielectric sidewall spacer is then selectively removed to create an opening adjacent to a selected sidewall of the stack and a conductor (e.g., a doped polysilicon or a conductive metal) is deposited to fill the opening. Alternatively, the sidewall spacer can be formed with a conductor (e.g., a doped polysilicon) and then, the remaining portion of the trench is filled with a dielectric material.
- a conductor e.g., a doped polysilicon
- a semiconductor device e.g., a field effect transistor or a diode
- a semiconductor device is formed so that a doped semiconductor region of the device is formed in the semiconductor layer adjacent to the conductor.
- a field effect transistor can be formed with doped source/drain regions in the semiconductor layer such that one of the source/drain regions is adjacent to the conductor.
- a diode can be formed with a doped anode and a doped cathode in the semiconductor layer such that either the anode or the cathode is adjacent to the conductor.
- a metal strap can be formed above both the conductor and the doped semiconductor region providing a bridge for current flow.
- FIG. 1 is a schematic diagram illustrating a semiconductor structure
- FIG. 2 is a schematic diagram illustrating an embodiment of the semiconductor structure of the invention
- FIG. 3 is a schematic diagram illustrating another embodiment of the semiconductor structure of the invention.
- FIG. 4 is a flow diagram illustrating embodiment of a method of the invention.
- FIG. 5 is a schematic diagram illustrating a partially completed structure of the invention.
- FIG. 6 is a schematic diagram illustrating a partially completed structure of the invention.
- FIG. 7 is a schematic diagram illustrating a partially completed structure of the invention.
- FIG. 8 is a schematic diagram illustrating a partially completed structure of the invention.
- FIG. 9 is a schematic diagram illustrating a partially completed structure of the invention.
- FIG. 10 is a schematic diagram illustrating a partially completed structure of the invention.
- FIG. 11 is a schematic diagram illustrating a partially completed structure of the invention.
- FIG. 12 is a schematic diagram illustrating a partially completed structure of the invention.
- silicon-on-insulator (SOI) technology and, particularly, partially depleted SOI technology is often subject to damage during wafer processing in the back-end of the line (BEOL) sectors.
- semiconductor devices 100 e.g., field effect transistors (as shown), pn junction diodes, etc.
- charging of metal lines in processing tools can pass a current 160 from on-wafer wires 150 through the semiconductor devices 100 and, particularly, through the doped semiconductor regions of the devices 100 (e.g., through the source/drain regions 111 and 112 of a field effect transistor (as shown) or the anode and cathode of a pn junction diode) and into the buried oxide (BOX) layer 102 below before exiting the substrate wafer 101 .
- the presence of this current in the BOX 102 can lead to a trapped electronic charge 120 .
- the trapped electronic charge 120 can alter the electrical properties of the semiconductor devices 100 and, thereby degrade yield and/or reliability
- field shields have been incorporated into semiconductor devices in order to “harden” them against radiation strikes.
- the state of semiconductor devices e.g., transistors or diodes
- Field shields have been incorporated into such devices in order to resist state changes due to such radiation strikes.
- a semiconductor structure that improves circuit yield and reliability by incorporating a field shield configured to both avoid the build up of an electric charge in the isolation layer immediately below the device during BEOL processing and to protect the device from charges trapped in the wafer substrate.
- the embodiments of the semiconductor structure of the invention incorporate a field shield below a semiconductor device (e.g., below a field effect transistor (FET) or a pn junction diode).
- FET field effect transistor
- pn junction diode a field shield below a semiconductor device
- the field shield is sandwiched between upper and lower isolation layers on a wafer.
- a local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the semiconductor device (e.g., a source/drain region of a FET or a cathode or anode of a pn junction diode).
- a selected doped semiconductor region of the semiconductor device e.g., a source/drain region of a FET or a cathode or anode of a pn junction diode.
- Current that passes into the device for example, during back-end of the line (BEOL) charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below.
- This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate.
- embodiments of the semiconductor structure of the invention comprise a first isolation layer 203 on a substrate 201 , a conductive pad 230 (i.e., a field shield) on the first isolation layer 203 and a second isolation layer 204 on the conductive pad 230 .
- the structure 200 , 300 can further comprise a device (e.g., see a field effect transistor 275 of FIG. 2 or a pn junction diode 375 of FIG. 3 ) above the second isolation layer 204 .
- the device can comprise doped semiconductor regions and one of these doped semiconductor regions can be electrically coupled to the conductive pad 230 by a local interconnect 235 .
- Shallow trench isolation structures 205 border the sides of the device and extend through the pad conductive pad 230 to the first isolation layer 203 , thereby electrically isolating the device and the conductive pad 230 from the substrate 201 .
- the device 275 can comprise an n-type or p-type field effect transistor (FET) with a semiconductor layer (e.g., within a silicon layer) above the second isolation layer 204 .
- the semiconductor layer can comprise doped source/drain regions 211 - 212 adjacent to a channel region 213 .
- a p-type field effect transistor can comprise a channel region 213 that is lightly doped with an n-type dopant (e.g., phosphorus (P), arsenic (As) or antimony (Sb)) and source/drain regions 211 - 212 that are heavily doped with p-type dopant (e.g., boron (B)).
- P phosphorus
- As arsenic
- Sb antimony
- an n-type field effect transistor can comprise a channel region 213 that is lightly doped with a p-type dopant (e.g., boron (B)), and source/drain regions 211 - 311 that are heavily doped with an n-type dopant (e.g., phosphorus (P), arsenic (As) or antimony (Sb)).
- a p-type dopant e.g., boron (B)
- source/drain regions 211 - 311 that are heavily doped with an n-type dopant (e.g., phosphorus (P), arsenic (As) or antimony (Sb)).
- P phosphorus
- As arsenic
- Sb antimony
- the FET 275 can further comprise a gate 280 (i.e., a gate dielectric and gate conductor stack) above the channel region 213 of the semiconductor layer.
- the device 375 can comprise a pn junction diode with an anode and a cathode ( 311 - 312 ) within a semiconductor layer (e.g., within a silicon layer) above the second isolation layer 204 . That is, the diode 375 can comprise a semiconductor layer with two adjacent semiconductor regions 311 - 312 that are doped with different type dopants.
- One region can comprise a cathode region that is doped with an n-type dopant (e.g., phosphorus (P), arsenic (As) or antimony (Sb)) and another region can comprise an anode region that is doped with a p-type dopant (e.g., boron (B)).
- an n-type dopant e.g., phosphorus (P), arsenic (As) or antimony (Sb)
- an anode region e.g., boron (B)
- Either the anode or the cathode e.g., see region 311 )
- the FET 375 can further comprise an isolation structure 380 (e.g., a non-functional gate, nitride pad, etc.). Those skilled in the art will recognize that, during the formation process, this isolation structure 380 allows for multi-step masked doping of the anode and cathode regions.
- the local interconnect 235 can comprise a conductor. Specifically, this conductor 235 can be located adjacent to a selected one of the doped semiconductor regions. That is, the conductor 235 can be adjacent to one of the source/drain regions 211 - 212 of a field effect transistor 275 of FIG. 2 or adjacent to an anode or cathode 311 - 312 of a diode 375 of FIG. 3 .
- the conductor 235 can further extend vertically through the second isolation layer 204 to the conductive pad 230 such that it electrically couples the conductive pad 230 to the selected doped semiconductor region.
- This local interconnect 235 i.e., the conductor
- This local interconnect 235 will shunt current (as illustrated by arrows 260 ) that passes into the device (e.g., into the FET 275 of FIG. 2 or diode 375 of FIG. 3 ) to the conductive pad 230 so as to prevent build up of an electric charge 220 in the second isolation layer 204 .
- the device e.g., into the FET 275 of FIG. 2 or diode 375 of FIG. 3
- the current 260 passes from the local interconnect 235 into the field shield 230 and is allowed to bleed off into the first isolation layer 203 and into the substrate 201 .
- electric charge 220 is only allowed to build up in the first isolation layer 203 .
- the conductive pad 230 will further protect the device (e.g., the FET 275 of FIG. 2 or diode 375 of FIG. 3 ) from any electric charge 220 that may be built up in the first isolation layer 203 and/or the substrate 201 (i.e., provides a protective barrier from such a trapped electric charge 220 ) during BEOL processing or by any other means.
- the isolation layers 203 and 204 can comprise, for example, buried oxide layers, such as silicon dioxide (SiO 2 ) layers within bonded silicon-on-insulator (SOI) wafers.
- buried oxide layers such as silicon dioxide (SiO 2 ) layers within bonded silicon-on-insulator (SOI) wafers.
- the conductive pad 230 and the conductor 235 can each comprise a suitable conductive material, for example, a doped (n-type or p-type) polysilicon or a conductive metal (e.g., tungsten (W), etc.).
- the structure 200 of FIG. 2 or 300 of FIG. 3 can comprise a metal strap 215 (e.g., a metal silicide strap, such as a nickel, titanium or cobalt silicide strap) that bridges both the conductor 235 and the adjacent doped semiconductor region (i.e., region 211 of FIG. 2 or 311 of FIG. 3 ), thereby allowing current 260 to flow easily between the device (i.e., FET 275 of FIG. 2 or diode 375 of FIG.
- a metal strap 215 e.g., a metal silicide strap, such as a nickel, titanium or cobalt silicide strap
- such a metal strap 215 avoids the blockage of current flow that results if the conductor 235 and the adjacent semiconductor region 211 , 311 comprise are doped with different type dopants, thereby creating a diode.
- each FET of a complementary metal oxide semiconductor (CMOS) device can be electrically coupled to a corresponding field shield in order to increase yield and reliability.
- CMOS complementary metal oxide semiconductor
- embodiments of a method of forming a semiconductor structure 200 or 300 of the invention comprise providing a wafer with a first isolation layer 203 on a substrate 201 (e.g., a silicon substrate), a conductive layer 230 on the first isolation layer 203 , a second isolation layer 204 on the conductive layer 230 and a semiconductor layer 270 on the second isolation layer 204 ( 402 , see FIG. 5 ).
- the isolation layers 203 - 204 can, for example, comprise silicon dioxide (SiO 2 ) layers.
- the conductive layer 230 can, for example, comprise a conductive material, such as a polysilicon layer heavily doped with an n-type or p-type dopant or a conductive metal layer.
- Such a wafer can be formed using known processing techniques to bond the insulator layers of two silicon-on-insulator wafers with a doped polysilicon layer.
- two wafers can be provided, each of which comprises a silicon dioxide (SiO 2 ) layer on a silicon (Si) substrate.
- a polysilicon layer can be deposited followed by a second silicon dioxide layer.
- the two wafers can be bonded such that cohesive forces hold the top silicon dioxide layers from each wafer together.
- the silicon surface of one of the wafers can be polished to a desired silicon film thickness.
- a trench 207 is patterned and etched in the wafer through the semiconductor layer 270 to the first isolation layer 203 so as to form a stack 208 , including the semiconductor layer 270 , the second isolation layer 204 and conductive layer 230 , on the first isolation layer 203 ( 404 , see FIG. 6 ).
- the trench 207 can be formed, for example, using conventional lithographic patterning techniques and a multi-step reactive ion etching (RIE) process.
- RIE reactive ion etching
- a dielectric sidewall spacer 231 can be formed adjacent to a selected sidewall 232 of the stack 208 ( 406 , see FIG. 7 ).
- the sidewall spacer 231 can be formed with a first dielectric material (e.g., a nitride or any other suitable dielectric material).
- This sidewall spacer 231 may be formed by first forming sidewall spacers on all of the sidewalls within the trench 207 .
- a mask layer is then formed above the structure such that all of the formed sidewall spacers within the trench 207 other than the sidewall spacer 231 that is adjacent to the selected sidewall 232 of the stack 208 are exposed.
- the exposed sidewalls spacers are then selectively removed, followed by removal of the mask layer.
- a shallow trench isolation (STI) structure 205 is formed around the stack 208 and adjacent to the spacer 231 on one side of the stack 208 .
- the STI 205 in combination with the first isolation layer 203 isolates the semiconductor layer 270 from the substrate 201 .
- the sidewall spacer 231 is then removed (e.g., using a selective etch process) to create an opening 233 adjacent to the selected sidewall 232 of the stack ( 410 , see FIG. 9 ).
- a conductive material e.g., a doped polysilicon or a conductive metal
- a conductor 235 that contacts the conductive pad 230 with the stack 208 ( 412 , see FIG. 10 ).
- a conductive material e.g., a doped polysilicon or conductive metal
- a conductive sidewall spacer i.e., conductor 235
- the conductive sidewall spacer 235 may be formed adjacent to the selected sidewall 232 of the stack 208 by first forming conductive sidewall spacers on all of the sidewalls within the trench 207 .
- a mask layer is then formed above the structure such that all of the trench sidewall spacers other the spacer that is adjacent to the selected sidewall 232 of the stack 208 are exposed. The exposed sidewalls spacers are then selectively removed, followed by removal of the mask layer.
- a dielectric layer e.g., an oxide, such as silicon dioxide (SiO 2 )
- SiO 2 silicon dioxide
- a shallow trench isolation (STI) structure 205 is formed around the stack 208 and adjacent to the conductor 235 on one side of the stack 208 .
- the STI 205 in combination with the first isolation layer 203 isolates the semiconductor layer 270 from the substrate 201 .
- a semiconductor device is formed above the second isolation layer 204 ( 418 , see FIGS. 2 and 3 ). Specifically, a semiconductor device is formed (e.g., using conventional processing techniques) so that a doped semiconductor region of the device is formed in the semiconductor layer 270 adjacent to the conductor.
- a field effect transistor 275 can be formed ( 420 ) by forming a gate 280 above a channel region 213 within the semiconductor layer 270 .
- Doped source/drain regions 211 - 212 can be formed on either side of the channel region 213 within the semiconductor layer 270 .
- the semiconductor layer 270 in the wafer can be lightly doped with an n-type dopant (e.g., phosphorus (P), arsenic (As) or antimony (Sb)).
- P phosphorus
- As arsenic
- Sb antimony
- the semiconductor layer 270 on either side of the gate and, thus, on either side of the channel region 213 is implanted with a high concentration of a p-type dopant (e.g., boron (B)). Consequently, the p-type source/drain regions 211 - 212 are formed such that one of the source/drain regions (e.g., 211 ) is adjacent to the conductor 235 .
- the semiconductor layer 270 in the wafer can be lightly doped with a p-type dopant (e.g., boron (B)).
- n-type dopant e.g., phosphorus (P), arsenic (As) or antimony (Sb)
- n-type source/drain regions 211 - 212 are formed such that one of the source/drain regions (e.g., 211 ) is adjacent to the conductor 235 .
- a diode 375 can be formed ( 422 ) by forming an isolation structure 380 (e.g., a non-functional gate, a nitride pad, etc.) over a center portion of the semiconductor layer 270 .
- Adjacent regions 311 , 312 within the semiconductor layer 270 can be doped with high concentrations of different type dopants, e.g., using a masked implantation process.
- a cathode region can be formed by implanting a high concentration of n-type dopants (e.g., phosphorus (P), arsenic (As) or antimony (Sb)) into one portion of the semiconductor layer 270 and an anode region can be formed by implanting a high concentration of p-type dopants (e.g., boron (B)) into an adjacent portion of in the semiconductor layer 270 .
- n-type dopants e.g., phosphorus (P), arsenic (As) or antimony (Sb)
- an anode region can be formed by implanting a high concentration of p-type dopants (e.g., boron (B)) into an adjacent portion of in the semiconductor layer 270 .
- p-type dopants e.g., boron (B)
- the conductor 235 comprises polysilicon doped with one type of dopant (e.g., a p-type dopant) and the adjacent doped semiconductor region (e.g., region 211 of FIG. 2 or region 311 of FIG. 3 ) is doped with a different type dopant (e.g., an n-type dopant), then a diode is formed which will obstruct current flow to the field shield. Therefore, in order to ensure that current 260 is allowed to flow easily between the doped semiconductor region (e.g., region 211 of FIG. 2 or region 311 of FIG. 3 ) and the adjacent conductor 235 , a metal strap or bridge 215 can be formed.
- dopant e.g., a p-type dopant
- a different type dopant e.g., an n-type dopant
- a metal silicide e.g., a titanium, nickel or cobalt silicide
- a metal silicide can be formed above both the doped semiconductor regions of the FET or diode and above the doped polysilicon conductor (i.e., above the local interconnect).
- a self-aligned metal silicide process can be performed. That is, a metal (e.g., Ni, Ti, Co, etc.) can be deposited over the structure and, particularly, over the exposed top surface of the doped semiconductor regions (e.g., over regions 211 - 212 of FIG. 2 or regions 311 - 312 of FIG.
- the doped polysilicon conductor 235 and over the gate/isolation structure e.g., over the gate 280 of FIG. 2 or the isolation structure 380 of FIG. 3 ).
- the metal is annealed causing a reaction which forms the metal silicide at the silicon/metal junctions above the doped semiconductor regions, above the polysilicon conductor and also above the gate/isolation structure, if that structure comprises polysilicon. Any unreacted metal and byproducts are then removed.
- the embodiments of the semiconductor structure of the invention incorporate a field shield below a semiconductor device (e.g., below a field effect transistor (FET) or a pn junction diode).
- the field shield is sandwiched between upper and lower isolation layers on a wafer.
- a local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the semiconductor device (e.g., a source/drain region of a FET or a cathode or anode of a pn junction diode).
- a selected doped semiconductor region of the semiconductor device e.g., a source/drain region of a FET or a cathode or anode of a pn junction diode.
- Current that passes into the device, for example, during back-end of the line (BEOL) charging is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below.
- This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate. Thus, it is ideally suited for any charge inducing environment.
Abstract
Description
- 1. Field of the Invention
- The embodiments of the invention generally relate to semiconductor devices and, more particularly, to a semiconductor structure that incorporates a semiconductor device coupled to a field shield.
- 2. Description of the Related Art
- Silicon-on-insulator (SOI) technology and, particularly, partially depleted SOI technology, is often subject to damage during wafer processing in the back-end of the line (BEOL) sectors. Specifically, charging of metal lines in processing tools can pass a current from the on-wafer wires through semiconductor devices and into the buried oxide (BOX) before exiting the substrate wafer. The presence of this current in the BOX can lead to a trapped electronic charge. The trapped electronic charge in the BOX can alter the electrical properties of the semiconductor devices and, thereby, degrade yield and/or reliability of circuits. Therefore, there is a need in the art for a semiconductor structure and a method of forming the structure that avoids the build up of an electric charge in the BOX during BEOL processing.
- In view of the foregoing, disclosed herein are embodiments of a semiconductor structure that incorporate a field shield below a semiconductor device (e.g., below a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a doped semiconductor region of the semiconductor device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device during back-end of the line (BEOL) charging is shunted by the local interconnect away from the upper isolation layer and into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds into the lower isolation layer and into the substrate below. This field shield further functions as a protective barrier from any electric charge that is trapped within the lower isolation layer or substrate.
- More particularly, embodiments of the semiconductor structure of the invention comprise a first isolation layer on a substrate, a conductive pad (i.e., a field shield) on the first isolation layer and a second isolation layer on the conductive pad. The conductive pad is electrically isolated from the substrate. The structure can further comprise a device above the second isolation layer. The device can comprise doped semiconductor regions and one of these doped semiconductor regions can be electrically coupled to the conductive pad by a local interconnect.
- For example, the device can comprise a field effect transistor with doped source/drain regions and one of the source/drain regions can be electrically coupled to the conductive pad. Alternatively, the device can comprise a pn junction diode with a doped anode and a doped cathode and either the anode or the cathode can be electrically coupled to the conductive pad.
- The local interconnect can comprise a conductor. Specifically, this conductor can be located adjacent to a selected doped semiconductor region (i.e., adjacent to a source/drain region of a field effect transistor or adjacent to an anode or cathode of a diode) and can extend vertically through the second isolation layer to the conductive pad such that it electrically couples the conductive pad to the selected doped semiconductor region. This local interconnect (i.e., the conductor) will shunt current that passes into the device to the conductive pad so as to prevent the build up of an electric charge in the second isolation layer. The conductive pad will further protect the device from any electric charge that is built up in the first isolation layer and the substrate.
- The conductive pad and the conductor can each comprise a suitable conductive material, for example, a doped polysilicon or a conductive metal. Additionally, the structure can comprise a metal strap that bridges both the conductor and the doped semiconductor region, thereby allowing current to flow easily between the device and local interconnect to the field shield even if the conductor and the adjacent doped semiconductor region of the device are doped with different type dopants.
- Embodiments of a method of forming a semiconductor structure, as described above, comprise providing a wafer with a first isolation layer on a substrate, a conductive layer on the first isolation layer, a second isolation layer on the conductive layer and a semiconductor layer on the second isolation layer.
- A trench is patterned and etched in the wafer through the semiconductor layer to the first isolation layer so as to form a stack, including the semiconductor layer, the second isolation layer and conductive layer, on the first isolation layer.
- A sidewall spacer is formed adjacent to a sidewall of the stack. In one embodiment of the invention the sidewall spacer can be formed with a dielectric material. After the dielectric sidewall spacer is formed, the remaining portion of the trench is filled with another different dielectric material. The dielectric sidewall spacer is then selectively removed to create an opening adjacent to a selected sidewall of the stack and a conductor (e.g., a doped polysilicon or a conductive metal) is deposited to fill the opening. Alternatively, the sidewall spacer can be formed with a conductor (e.g., a doped polysilicon) and then, the remaining portion of the trench is filled with a dielectric material.
- Then, a semiconductor device (e.g., a field effect transistor or a diode) is formed in the stack above the second isolation layer. Specifically, a semiconductor device is formed so that a doped semiconductor region of the device is formed in the semiconductor layer adjacent to the conductor. For example, a field effect transistor can be formed with doped source/drain regions in the semiconductor layer such that one of the source/drain regions is adjacent to the conductor. Alternatively, a diode can be formed with a doped anode and a doped cathode in the semiconductor layer such that either the anode or the cathode is adjacent to the conductor.
- Additionally, to ensure that current passing into the device is allowed to flow easily between the conductor and the adjacent doped semiconductor region, a metal strap can be formed above both the conductor and the doped semiconductor region providing a bridge for current flow.
- These and other aspects of the embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments of the invention and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments of the invention without departing from the spirit thereof, and the embodiments of the invention include all such modifications.
- The embodiments of the invention will be better understood from the following detailed description with reference to the drawings, in which:
-
FIG. 1 is a schematic diagram illustrating a semiconductor structure; -
FIG. 2 is a schematic diagram illustrating an embodiment of the semiconductor structure of the invention; -
FIG. 3 is a schematic diagram illustrating another embodiment of the semiconductor structure of the invention; -
FIG. 4 is a flow diagram illustrating embodiment of a method of the invention; -
FIG. 5 is a schematic diagram illustrating a partially completed structure of the invention; -
FIG. 6 is a schematic diagram illustrating a partially completed structure of the invention; -
FIG. 7 is a schematic diagram illustrating a partially completed structure of the invention; -
FIG. 8 is a schematic diagram illustrating a partially completed structure of the invention; -
FIG. 9 is a schematic diagram illustrating a partially completed structure of the invention; -
FIG. 10 is a schematic diagram illustrating a partially completed structure of the invention; -
FIG. 11 is a schematic diagram illustrating a partially completed structure of the invention; and -
FIG. 12 is a schematic diagram illustrating a partially completed structure of the invention. - The embodiments of the invention and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments of the invention. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments of the invention may be practiced and to further enable those of skill in the art to practice the embodiments of the invention. Accordingly, the examples should not be construed as limiting the scope of the embodiments of the invention.
- As mentioned, silicon-on-insulator (SOI) technology and, particularly, partially depleted SOI technology, is often subject to damage during wafer processing in the back-end of the line (BEOL) sectors. Specifically, referring to
FIG. 1 , during fabrication of semiconductor devices 100 (e.g., field effect transistors (as shown), pn junction diodes, etc.), charging of metal lines in processing tools can pass a current 160 from on-wafer wires 150 through thesemiconductor devices 100 and, particularly, through the doped semiconductor regions of the devices 100 (e.g., through the source/drain regions layer 102 below before exiting thesubstrate wafer 101. The presence of this current in theBOX 102 can lead to a trappedelectronic charge 120. The trappedelectronic charge 120 can alter the electrical properties of thesemiconductor devices 100 and, thereby degrade yield and/or reliability of integrated circuits. - Previously, field shields have been incorporated into semiconductor devices in order to “harden” them against radiation strikes. Specifically, the state of semiconductor devices (e.g., transistors or diodes) can change due to radiation strikes at a sensitive node. Field shields have been incorporated into such devices in order to resist state changes due to such radiation strikes.
- Disclosed herein are embodiments of a semiconductor structure that improves circuit yield and reliability by incorporating a field shield configured to both avoid the build up of an electric charge in the isolation layer immediately below the device during BEOL processing and to protect the device from charges trapped in the wafer substrate. Specifically, the embodiments of the semiconductor structure of the invention incorporate a field shield below a semiconductor device (e.g., below a field effect transistor (FET) or a pn junction diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the semiconductor device (e.g., a source/drain region of a FET or a cathode or anode of a pn junction diode). Current that passes into the device, for example, during back-end of the line (BEOL) charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate.
- More particularly, embodiments of the semiconductor structure of the invention (see
structure 200 ofFIG. 2 andstructure 300 ofFIG. 3 ) comprise afirst isolation layer 203 on asubstrate 201, a conductive pad 230 (i.e., a field shield) on thefirst isolation layer 203 and asecond isolation layer 204 on theconductive pad 230. Thestructure field effect transistor 275 ofFIG. 2 or apn junction diode 375 ofFIG. 3 ) above thesecond isolation layer 204. The device can comprise doped semiconductor regions and one of these doped semiconductor regions can be electrically coupled to theconductive pad 230 by alocal interconnect 235. Shallowtrench isolation structures 205 border the sides of the device and extend through the padconductive pad 230 to thefirst isolation layer 203, thereby electrically isolating the device and theconductive pad 230 from thesubstrate 201. - Specifically, referring to
FIG. 2 , thedevice 275 can comprise an n-type or p-type field effect transistor (FET) with a semiconductor layer (e.g., within a silicon layer) above thesecond isolation layer 204. The semiconductor layer can comprise doped source/drain regions 211-212 adjacent to achannel region 213. Specifically, a p-type field effect transistor can comprise achannel region 213 that is lightly doped with an n-type dopant (e.g., phosphorus (P), arsenic (As) or antimony (Sb)) and source/drain regions 211-212 that are heavily doped with p-type dopant (e.g., boron (B)). Whereas, an n-type field effect transistor can comprise achannel region 213 that is lightly doped with a p-type dopant (e.g., boron (B)), and source/drain regions 211-311 that are heavily doped with an n-type dopant (e.g., phosphorus (P), arsenic (As) or antimony (Sb)). Regardless of whether the FET comprises an n-FET or p-FET, one of these source/drain regions (e.g., see source/drain region 211) can be electrically coupled to theconductive pad 230. TheFET 275 can further comprise a gate 280 (i.e., a gate dielectric and gate conductor stack) above thechannel region 213 of the semiconductor layer. - Alternatively, referring to
FIG. 3 , thedevice 375 can comprise a pn junction diode with an anode and a cathode (311-312) within a semiconductor layer (e.g., within a silicon layer) above thesecond isolation layer 204. That is, thediode 375 can comprise a semiconductor layer with two adjacent semiconductor regions 311-312 that are doped with different type dopants. One region can comprise a cathode region that is doped with an n-type dopant (e.g., phosphorus (P), arsenic (As) or antimony (Sb)) and another region can comprise an anode region that is doped with a p-type dopant (e.g., boron (B)). Either the anode or the cathode (e.g., see region 311)) can be electrically coupled to theconductive pad 230. TheFET 375 can further comprise an isolation structure 380 (e.g., a non-functional gate, nitride pad, etc.). Those skilled in the art will recognize that, during the formation process, thisisolation structure 380 allows for multi-step masked doping of the anode and cathode regions. - The
local interconnect 235 can comprise a conductor. Specifically, thisconductor 235 can be located adjacent to a selected one of the doped semiconductor regions. That is, theconductor 235 can be adjacent to one of the source/drain regions 211-212 of afield effect transistor 275 ofFIG. 2 or adjacent to an anode or cathode 311-312 of adiode 375 ofFIG. 3 . Theconductor 235 can further extend vertically through thesecond isolation layer 204 to theconductive pad 230 such that it electrically couples theconductive pad 230 to the selected doped semiconductor region. This local interconnect 235 (i.e., the conductor) will shunt current (as illustrated by arrows 260) that passes into the device (e.g., into theFET 275 ofFIG. 2 ordiode 375 ofFIG. 3 ) to theconductive pad 230 so as to prevent build up of anelectric charge 220 in thesecond isolation layer 204. As discussed above, without such a field shield current passing into the device would bleed into the isolation layer immediately below the device, thereby trapping an electric charge in the isolation layer and effecting circuit yield and reliability. Rather with thefield shield 230 of the present invention, the current 260 passes from thelocal interconnect 235 into thefield shield 230 and is allowed to bleed off into thefirst isolation layer 203 and into thesubstrate 201. Thus,electric charge 220 is only allowed to build up in thefirst isolation layer 203. Theconductive pad 230 will further protect the device (e.g., theFET 275 ofFIG. 2 ordiode 375 ofFIG. 3 ) from anyelectric charge 220 that may be built up in thefirst isolation layer 203 and/or the substrate 201 (i.e., provides a protective barrier from such a trapped electric charge 220) during BEOL processing or by any other means. - The isolation layers 203 and 204 can comprise, for example, buried oxide layers, such as silicon dioxide (SiO2) layers within bonded silicon-on-insulator (SOI) wafers.
- The
conductive pad 230 and theconductor 235 can each comprise a suitable conductive material, for example, a doped (n-type or p-type) polysilicon or a conductive metal (e.g., tungsten (W), etc.). Additionally, thestructure 200 ofFIG. 2 or 300 ofFIG. 3 can comprise a metal strap 215 (e.g., a metal silicide strap, such as a nickel, titanium or cobalt silicide strap) that bridges both theconductor 235 and the adjacent doped semiconductor region (i.e.,region 211 ofFIG. 2 or 311 ofFIG. 3 ), thereby allowing current 260 to flow easily between the device (i.e.,FET 275 ofFIG. 2 ordiode 375 ofFIG. 3 ) andlocal interconnect 235 to thefield shield 230. Specifically, such ametal strap 215 avoids the blockage of current flow that results if theconductor 235 and theadjacent semiconductor region - It is further anticipated that the
structure - Referring to
FIG. 4 , embodiments of a method of forming asemiconductor structure FIGS. 2 and 3 , respectively, comprise providing a wafer with afirst isolation layer 203 on a substrate 201 (e.g., a silicon substrate), aconductive layer 230 on thefirst isolation layer 203, asecond isolation layer 204 on theconductive layer 230 and asemiconductor layer 270 on the second isolation layer 204 (402, seeFIG. 5 ). The isolation layers 203-204 can, for example, comprise silicon dioxide (SiO2) layers. Theconductive layer 230 can, for example, comprise a conductive material, such as a polysilicon layer heavily doped with an n-type or p-type dopant or a conductive metal layer. - Such a wafer can be formed using known processing techniques to bond the insulator layers of two silicon-on-insulator wafers with a doped polysilicon layer. For example, two wafers can be provided, each of which comprises a silicon dioxide (SiO2) layer on a silicon (Si) substrate. Onto the silicon dioxide layer of one of the wafers a polysilicon layer can be deposited followed by a second silicon dioxide layer. Then, the two wafers can be bonded such that cohesive forces hold the top silicon dioxide layers from each wafer together. Then, the silicon surface of one of the wafers can be polished to a desired silicon film thickness.
- A
trench 207 is patterned and etched in the wafer through thesemiconductor layer 270 to thefirst isolation layer 203 so as to form astack 208, including thesemiconductor layer 270, thesecond isolation layer 204 andconductive layer 230, on the first isolation layer 203 (404, seeFIG. 6 ). Thetrench 207 can be formed, for example, using conventional lithographic patterning techniques and a multi-step reactive ion etching (RIE) process. - A
dielectric sidewall spacer 231 can be formed adjacent to a selectedsidewall 232 of the stack 208 (406, seeFIG. 7 ). Thesidewall spacer 231 can be formed with a first dielectric material (e.g., a nitride or any other suitable dielectric material). Thissidewall spacer 231 may be formed by first forming sidewall spacers on all of the sidewalls within thetrench 207. A mask layer is then formed above the structure such that all of the formed sidewall spacers within thetrench 207 other than thesidewall spacer 231 that is adjacent to the selectedsidewall 232 of thestack 208 are exposed. The exposed sidewalls spacers are then selectively removed, followed by removal of the mask layer. - After the
dielectric spacer 231 is formed, another dielectric layer (e.g., an oxide, such as silicon dioxide (SiO2) or another dielectric material that is different from that used to form the dielectric sidewall spacer 231) is deposited and planarized such that the remaining portion of thetrench 207 is filled (408, seeFIG. 8 ). Thus, a shallow trench isolation (STI)structure 205 is formed around thestack 208 and adjacent to thespacer 231 on one side of thestack 208. TheSTI 205 in combination with thefirst isolation layer 203 isolates thesemiconductor layer 270 from thesubstrate 201. Thesidewall spacer 231 is then removed (e.g., using a selective etch process) to create anopening 233 adjacent to the selectedsidewall 232 of the stack (410, seeFIG. 9 ). Once thespacer 231 is selectively removed, a conductive material (e.g., a doped polysilicon or a conductive metal) is deposited and planarized, thereby filling theopening 233 with aconductor 235 that contacts theconductive pad 230 with the stack 208 (412, seeFIG. 10 ). - Alternatively, a conductive material (e.g., a doped polysilicon or conductive metal) can be used to form a conductive sidewall spacer (i.e., conductor 235) directly on a selected
sidewall 232 of the stack 208 (414, seeFIG. 1 1). As with thespacer 231 described above, theconductive sidewall spacer 235 may be formed adjacent to the selectedsidewall 232 of thestack 208 by first forming conductive sidewall spacers on all of the sidewalls within thetrench 207. A mask layer is then formed above the structure such that all of the trench sidewall spacers other the spacer that is adjacent to the selectedsidewall 232 of thestack 208 are exposed. The exposed sidewalls spacers are then selectively removed, followed by removal of the mask layer. - After the conductive sidewall spacer 235 (i.e., the conductor) is formed adjacent to a selected
sidewall 232 of thestack 208, a dielectric layer (e.g., an oxide, such as silicon dioxide (SiO2)) is deposited and planarized such that the remaining portion of thetrench 207 is filled (416, seeFIG. 12 ). Thus, a shallow trench isolation (STI)structure 205 is formed around thestack 208 and adjacent to theconductor 235 on one side of thestack 208. TheSTI 205 in combination with thefirst isolation layer 203 isolates thesemiconductor layer 270 from thesubstrate 201. - Then, a semiconductor device is formed above the second isolation layer 204 (418, see
FIGS. 2 and 3 ). Specifically, a semiconductor device is formed (e.g., using conventional processing techniques) so that a doped semiconductor region of the device is formed in thesemiconductor layer 270 adjacent to the conductor. - For example, as illustrated in
FIG. 2 , afield effect transistor 275 can be formed (420) by forming agate 280 above achannel region 213 within thesemiconductor layer 270. Doped source/drain regions 211-212 can be formed on either side of thechannel region 213 within thesemiconductor layer 270. Specifically, for a p-type field effect transistor, thesemiconductor layer 270 in the wafer can be lightly doped with an n-type dopant (e.g., phosphorus (P), arsenic (As) or antimony (Sb)). Then, thesemiconductor layer 270 on either side of the gate and, thus, on either side of thechannel region 213 is implanted with a high concentration of a p-type dopant (e.g., boron (B)). Consequently, the p-type source/drain regions 211-212 are formed such that one of the source/drain regions (e.g., 211) is adjacent to theconductor 235. Similarly, for an n-type field effect transistor, thesemiconductor layer 270 in the wafer can be lightly doped with a p-type dopant (e.g., boron (B)). Then, thesemiconductor layer 270 on either side of the gate and, thus, on either side of thechannel region 213 is implanted with a high concentration of an n-type dopant (e.g., phosphorus (P), arsenic (As) or antimony (Sb)). Consequently, n-type source/drain regions 211-212 are formed such that one of the source/drain regions (e.g., 211) is adjacent to theconductor 235. - Alternatively, as illustrated in
FIG. 3 , adiode 375 can be formed (422) by forming an isolation structure 380 (e.g., a non-functional gate, a nitride pad, etc.) over a center portion of thesemiconductor layer 270.Adjacent regions semiconductor layer 270 can be doped with high concentrations of different type dopants, e.g., using a masked implantation process. That is, a cathode region can be formed by implanting a high concentration of n-type dopants (e.g., phosphorus (P), arsenic (As) or antimony (Sb)) into one portion of thesemiconductor layer 270 and an anode region can be formed by implanting a high concentration of p-type dopants (e.g., boron (B)) into an adjacent portion of in thesemiconductor layer 270. One of these doped semiconductor regions (i.e., either the anode or the cathode) can be formed adjacent to theconductor 235. - Additionally, those skilled in the art will recognize that if the
conductor 235 comprises polysilicon doped with one type of dopant (e.g., a p-type dopant) and the adjacent doped semiconductor region (e.g.,region 211 ofFIG. 2 orregion 311 ofFIG. 3 ) is doped with a different type dopant (e.g., an n-type dopant), then a diode is formed which will obstruct current flow to the field shield. Therefore, in order to ensure that current 260 is allowed to flow easily between the doped semiconductor region (e.g.,region 211 ofFIG. 2 orregion 311 ofFIG. 3 ) and theadjacent conductor 235, a metal strap or bridge 215 can be formed. - For example, a metal silicide (e.g., a titanium, nickel or cobalt silicide) can be formed above both the doped semiconductor regions of the FET or diode and above the doped polysilicon conductor (i.e., above the local interconnect). To form the metal silicide, a self-aligned metal silicide process can be performed. That is, a metal (e.g., Ni, Ti, Co, etc.) can be deposited over the structure and, particularly, over the exposed top surface of the doped semiconductor regions (e.g., over regions 211-212 of
FIG. 2 or regions 311-312 ofFIG. 3 ), over the dopedpolysilicon conductor 235 and over the gate/isolation structure (e.g., over thegate 280 ofFIG. 2 or theisolation structure 380 ofFIG. 3 ). The metal is annealed causing a reaction which forms the metal silicide at the silicon/metal junctions above the doped semiconductor regions, above the polysilicon conductor and also above the gate/isolation structure, if that structure comprises polysilicon. Any unreacted metal and byproducts are then removed. - Therefore, disclosed above are embodiments of a semiconductor structure that improve circuit yield and reliability by incorporating a field shield configured to both avoid the build up of an electric charge in the isolation layer immediately below the device during BEOL processing and to protect the device from charges trapped in the wafer substrate. Specifically, the embodiments of the semiconductor structure of the invention incorporate a field shield below a semiconductor device (e.g., below a field effect transistor (FET) or a pn junction diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the semiconductor device (e.g., a source/drain region of a FET or a cathode or anode of a pn junction diode). Current that passes into the device, for example, during back-end of the line (BEOL) charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate. Thus, it is ideally suited for any charge inducing environment.
- The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, those skilled in the art will recognize that the described embodiments of the invention can be practiced with modification within the spirit and scope of the appended claims.
Claims (11)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/623,164 US7400015B1 (en) | 2007-01-15 | 2007-01-15 | Semiconductor structure with field shield and method of forming the structure |
JP2008001417A JP5505895B2 (en) | 2007-01-15 | 2008-01-08 | Semiconductor structure |
CN2008100015887A CN101226923B (en) | 2007-01-15 | 2008-01-14 | Semiconductor structure with field shield and method of forming the structure |
US12/127,850 US20090127595A1 (en) | 2007-01-15 | 2008-05-28 | Semiconductor structure with field shield and method of forming the structure |
US12/127,849 US20080265316A1 (en) | 2007-01-15 | 2008-05-28 | Semiconductor structure with field shield and method of forming the structure |
US12/610,563 US7932134B2 (en) | 2007-01-15 | 2009-11-02 | Method of forming a semiconductor structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/623,164 US7400015B1 (en) | 2007-01-15 | 2007-01-15 | Semiconductor structure with field shield and method of forming the structure |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/127,849 Continuation US20080265316A1 (en) | 2007-01-15 | 2008-05-28 | Semiconductor structure with field shield and method of forming the structure |
US12/127,850 Division US20090127595A1 (en) | 2007-01-15 | 2008-05-28 | Semiconductor structure with field shield and method of forming the structure |
Publications (2)
Publication Number | Publication Date |
---|---|
US7400015B1 US7400015B1 (en) | 2008-07-15 |
US20080169518A1 true US20080169518A1 (en) | 2008-07-17 |
Family
ID=39596676
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/623,164 Active US7400015B1 (en) | 2007-01-15 | 2007-01-15 | Semiconductor structure with field shield and method of forming the structure |
US12/127,849 Abandoned US20080265316A1 (en) | 2007-01-15 | 2008-05-28 | Semiconductor structure with field shield and method of forming the structure |
US12/127,850 Abandoned US20090127595A1 (en) | 2007-01-15 | 2008-05-28 | Semiconductor structure with field shield and method of forming the structure |
US12/610,563 Expired - Fee Related US7932134B2 (en) | 2007-01-15 | 2009-11-02 | Method of forming a semiconductor structure |
Family Applications After (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/127,849 Abandoned US20080265316A1 (en) | 2007-01-15 | 2008-05-28 | Semiconductor structure with field shield and method of forming the structure |
US12/127,850 Abandoned US20090127595A1 (en) | 2007-01-15 | 2008-05-28 | Semiconductor structure with field shield and method of forming the structure |
US12/610,563 Expired - Fee Related US7932134B2 (en) | 2007-01-15 | 2009-11-02 | Method of forming a semiconductor structure |
Country Status (3)
Country | Link |
---|---|
US (4) | US7400015B1 (en) |
JP (1) | JP5505895B2 (en) |
CN (1) | CN101226923B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10418985B2 (en) | 2015-10-07 | 2019-09-17 | Inter-University Research Institute Corporation | Radiation-damage-compensation-circuit and SOI-MOSFET |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4157403B2 (en) * | 2003-03-19 | 2008-10-01 | 株式会社日立製作所 | Packet communication device |
US7355249B2 (en) * | 2005-04-28 | 2008-04-08 | International Business Machines Corporation | Silicon-on-insulator based radiation detection device and method |
US7400015B1 (en) * | 2007-01-15 | 2008-07-15 | International Business Machines Corporation | Semiconductor structure with field shield and method of forming the structure |
US8741773B2 (en) * | 2010-01-08 | 2014-06-03 | International Business Machines Corporation | Nickel-silicide formation with differential Pt composition |
US8525271B2 (en) | 2011-03-03 | 2013-09-03 | Suvolta, Inc. | Semiconductor structure with improved channel stack and method for fabrication thereof |
US8476704B2 (en) * | 2011-08-19 | 2013-07-02 | Nan Ya Technology Corporation | Circuit structure with vertical double gate |
US10644140B2 (en) * | 2016-06-30 | 2020-05-05 | Intel Corporation | Integrated circuit die having back-end-of-line transistors |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5606188A (en) * | 1995-04-26 | 1997-02-25 | International Business Machines Corporation | Fabrication process and structure for a contacted-body silicon-on-insulator dynamic random access memory |
US6107660A (en) * | 1999-05-19 | 2000-08-22 | Worldwide Semiconductor Manufacturing Corp. | Vertical thin film transistor |
US6190985B1 (en) * | 1999-08-17 | 2001-02-20 | Advanced Micro Devices, Inc. | Practical way to remove heat from SOI devices |
US6483223B2 (en) * | 2001-03-01 | 2002-11-19 | Institute Of Microelectronics | Method to prevent charging effects in electrostatic devices |
US6847114B2 (en) * | 2001-11-09 | 2005-01-25 | Turnstone Systems, Inc. | Micro-scale interconnect device with internal heat spreader and method for fabricating same |
US20050121734A1 (en) * | 2003-11-07 | 2005-06-09 | Georgia Tech Research Corporation | Combination catheter devices, methods, and systems |
US20080067613A1 (en) * | 2006-09-15 | 2008-03-20 | Anderson Brent A | Field effect transistor with raised source/drain fin straps |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5343067A (en) * | 1987-02-26 | 1994-08-30 | Kabushiki Kaisha Toshiba | High breakdown voltage semiconductor device |
US5306942A (en) * | 1989-10-11 | 1994-04-26 | Nippondenso Co., Ltd. | Semiconductor device having a shield which is maintained at a reference potential |
JP2822656B2 (en) * | 1990-10-17 | 1998-11-11 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
JP3293871B2 (en) * | 1991-01-31 | 2002-06-17 | 株式会社東芝 | High voltage semiconductor device |
JP3254007B2 (en) * | 1992-06-09 | 2002-02-04 | 株式会社半導体エネルギー研究所 | Thin film semiconductor device and method for manufacturing the same |
US5666002A (en) * | 1993-06-22 | 1997-09-09 | Kabushiki Kaisha Toshiba | Semiconductor device with wiring layer in tunnel in semiconductor substrate |
JPH0846145A (en) * | 1994-08-04 | 1996-02-16 | Nippondenso Co Ltd | Semiconductor circuit device |
JPH08335684A (en) * | 1995-06-08 | 1996-12-17 | Toshiba Corp | Semiconductor device |
JPH1041511A (en) * | 1996-07-19 | 1998-02-13 | Hitachi Ltd | Soi wafer and semiconductor integrated circuit device using the wafer and its manufacturing method |
JPH11195712A (en) * | 1997-11-05 | 1999-07-21 | Denso Corp | Semiconductor device and manufacture thereof |
US6696707B2 (en) * | 1999-04-23 | 2004-02-24 | Ccp. Clare Corporation | High voltage integrated switching devices on a bonded and trenched silicon substrate |
KR100340864B1 (en) * | 1999-11-04 | 2002-06-20 | 박종섭 | Method of fabricating silicon on insulator using bird's beak |
US20020031909A1 (en) * | 2000-05-11 | 2002-03-14 | Cyril Cabral | Self-aligned silicone process for low resistivity contacts to thin film silicon-on-insulator mosfets |
KR100396469B1 (en) * | 2001-06-29 | 2003-09-02 | 삼성전자주식회사 | Method of forming the gate electrode in semiconductor device and Method of manufacturing the non-volatile memory device comprising the same |
US6645796B2 (en) * | 2001-11-21 | 2003-11-11 | International Business Machines Corporation | Method and semiconductor structure for implementing reach through buried interconnect for silicon-on-insulator (SOI) devices |
US6610576B2 (en) * | 2001-12-13 | 2003-08-26 | International Business Machines Corporation | Method for forming asymmetric dual gate transistor |
US7019342B2 (en) * | 2003-07-03 | 2006-03-28 | American Semiconductor, Inc. | Double-gated transistor circuit |
US7015547B2 (en) * | 2003-07-03 | 2006-03-21 | American Semiconductor, Inc. | Multi-configurable independently multi-gated MOSFET |
US6974741B2 (en) * | 2004-01-06 | 2005-12-13 | Nanya Technology Corporatiion | Method for forming shallow trench in semiconductor device |
US7400015B1 (en) * | 2007-01-15 | 2008-07-15 | International Business Machines Corporation | Semiconductor structure with field shield and method of forming the structure |
-
2007
- 2007-01-15 US US11/623,164 patent/US7400015B1/en active Active
-
2008
- 2008-01-08 JP JP2008001417A patent/JP5505895B2/en not_active Expired - Fee Related
- 2008-01-14 CN CN2008100015887A patent/CN101226923B/en not_active Expired - Fee Related
- 2008-05-28 US US12/127,849 patent/US20080265316A1/en not_active Abandoned
- 2008-05-28 US US12/127,850 patent/US20090127595A1/en not_active Abandoned
-
2009
- 2009-11-02 US US12/610,563 patent/US7932134B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5606188A (en) * | 1995-04-26 | 1997-02-25 | International Business Machines Corporation | Fabrication process and structure for a contacted-body silicon-on-insulator dynamic random access memory |
US6107660A (en) * | 1999-05-19 | 2000-08-22 | Worldwide Semiconductor Manufacturing Corp. | Vertical thin film transistor |
US6190985B1 (en) * | 1999-08-17 | 2001-02-20 | Advanced Micro Devices, Inc. | Practical way to remove heat from SOI devices |
US6483223B2 (en) * | 2001-03-01 | 2002-11-19 | Institute Of Microelectronics | Method to prevent charging effects in electrostatic devices |
US6847114B2 (en) * | 2001-11-09 | 2005-01-25 | Turnstone Systems, Inc. | Micro-scale interconnect device with internal heat spreader and method for fabricating same |
US20050121734A1 (en) * | 2003-11-07 | 2005-06-09 | Georgia Tech Research Corporation | Combination catheter devices, methods, and systems |
US20080067613A1 (en) * | 2006-09-15 | 2008-03-20 | Anderson Brent A | Field effect transistor with raised source/drain fin straps |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10418985B2 (en) | 2015-10-07 | 2019-09-17 | Inter-University Research Institute Corporation | Radiation-damage-compensation-circuit and SOI-MOSFET |
Also Published As
Publication number | Publication date |
---|---|
US20090127595A1 (en) | 2009-05-21 |
JP5505895B2 (en) | 2014-05-28 |
US20100047972A1 (en) | 2010-02-25 |
US7932134B2 (en) | 2011-04-26 |
JP2008172238A (en) | 2008-07-24 |
US20080265316A1 (en) | 2008-10-30 |
US7400015B1 (en) | 2008-07-15 |
CN101226923A (en) | 2008-07-23 |
CN101226923B (en) | 2012-03-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7932134B2 (en) | Method of forming a semiconductor structure | |
CN107887387B (en) | Semiconductor device, method of manufacturing the same, and electronic apparatus including the same | |
US10522532B2 (en) | Through via extending through a group III-V layer | |
US11616064B2 (en) | Semiconductor structure | |
US20030203546A1 (en) | SOI transistor element having an improved backside contact and method of forming the same | |
US9064972B2 (en) | Method of forming a gated diode structure for eliminating RIE damage from cap removal | |
US10957776B2 (en) | Method of fabricating MOSFET | |
US7166876B2 (en) | MOSFET with electrostatic discharge protection structure and method of fabrication | |
US7638376B2 (en) | Method for forming SOI device | |
US9190445B2 (en) | Semiconductor device | |
US10276582B2 (en) | High coupling ratio split gate memory cell | |
US9871032B2 (en) | Gate-grounded metal oxide semiconductor device | |
JP2009532885A (en) | Protection from charging damage in hybrid alignment transistors. | |
US20130057991A1 (en) | Silicon controlled rectifier structure with improved junction breakdown and leakage control | |
US20150069522A1 (en) | Efficient integration of cmos with poly resistor | |
US8581347B2 (en) | Forming bipolar transistor through fast EPI-growth on polysilicon | |
TWI690025B (en) | Semiconductor-on-insulator (soi)substrate, method for forming thereof, and integrated circuit | |
CN114613851A (en) | Semiconductor structure with in-device high resistivity polycrystalline semiconductor element and method | |
US9646962B1 (en) | Low leakage gate controlled vertical electrostatic discharge protection device integration with a planar FinFET | |
TWI788755B (en) | Avalanche-protected transistors using a bottom breakdown current path and methods of forming the same | |
TW202111817A (en) | Extended-drain field-effect transistors including a floating gate | |
US8772876B2 (en) | High-voltage silicon-on-insulator transistors and methods of manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CLARK, WILLIAM F., JR.;NOWAK, EDWARD J.;REEL/FRAME:018758/0274 Effective date: 20061130 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, DELAWARE Free format text: SECURITY AGREEMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049490/0001 Effective date: 20181127 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:054633/0001 Effective date: 20201022 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001 Effective date: 20201117 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001 Effective date: 20201117 |