US20080113503A1 - Low fabrication cost, high performance, high reliability chip scale package - Google Patents

Low fabrication cost, high performance, high reliability chip scale package Download PDF

Info

Publication number
US20080113503A1
US20080113503A1 US11/930,220 US93022007A US2008113503A1 US 20080113503 A1 US20080113503 A1 US 20080113503A1 US 93022007 A US93022007 A US 93022007A US 2008113503 A1 US2008113503 A1 US 2008113503A1
Authority
US
United States
Prior art keywords
layer
metal layer
metal
over
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US11/930,220
Other versions
US8481418B2 (en
US20090137110A9 (en
Inventor
Jin Yuan Lee
Ming Ta Lei
Ching-Cheng Huang
Chuen-Jye Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Megica Corp
Original Assignee
Megica Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Megica Corp filed Critical Megica Corp
Priority to US11/930,220 priority Critical patent/US8481418B2/en
Assigned to MEGICA CORPORATION reassignment MEGICA CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUANG, CHING-CHENG, LEE, JIN-YUAN, LEI, MING-TA, LIN, CHUEN-JYE
Publication of US20080113503A1 publication Critical patent/US20080113503A1/en
Publication of US20090137110A9 publication Critical patent/US20090137110A9/en
Application granted granted Critical
Publication of US8481418B2 publication Critical patent/US8481418B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69Spread spectrum techniques
    • H04B1/707Spread spectrum techniques using direct sequence modulation
    • H04B1/7097Interference-related aspects
    • H04B1/711Interference-related aspects the interference being multi-path interference
    • H04B1/7113Determination of path profile
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0231Manufacturing methods of the redistribution layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1183Reworking, e.g. shaping
    • H01L2224/11831Reworking, e.g. shaping involving a chemical process, e.g. etching the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/119Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13017Shape in side view being non uniform along the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13083Three-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00013Fully indexed content
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01041Niobium [Nb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01042Molybdenum [Mo]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01073Tantalum [Ta]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01084Polonium [Po]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049Nitrides composed of metals from groups of the periodic table
    • H01L2924/04944th Group
    • H01L2924/04941TiN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30105Capacitance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69Spread spectrum techniques
    • H04B1/707Spread spectrum techniques using direct sequence modulation
    • H04B1/7097Interference-related aspects
    • H04B1/711Interference-related aspects the interference being multi-path interference
    • H04B1/7115Constructive combining of multi-path signals, i.e. RAKE receivers
    • H04B1/712Weighting of fingers for combining, e.g. amplitude control or phase rotation using an inner loop

Definitions

  • the invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and package for semiconductor devices.
  • IC Integrated Circuits
  • Semiconductor device packaging typically mounts a device on a substrate, such as semiconductor substrates, printed circuit boards, flex circuits, metallized substrates, glass substrates and semiconductor device mounting support.
  • a substrate can be a relative complex structure, having multiple payers of interconnect metal distributed throughout the height of the substrate in addition to having interconnect traces created on one or both surfaces of the substrate.
  • contact pads such as bond pads are typically provided over at least one of the surfaces of a substrate.
  • a semiconductor device is mounted on a substrate and connected to interconnect metal that is part of the substrate, the first level substrate may be further mounted over the surface of a larger substrate from which the device is interconnected to surrounding circuitry or electrical components.
  • Limitations that are imposed on this method of packaging are typically limitations of electrical performance that is imposed on the device by the packaging interface. For instance, of key concerns are RC delays in the transmission of signals over the various interconnect traces. This places a restraint of size and therefore packaging density on the package. Also of concern are considerations of parasitic capacitance and inductance that are introduced by the package since these parameters have a negative impact on device performance, a more serious impact on high frequency device performance. These parasitic components must therefore be minimized or suppressed to the maximum extent possible.
  • solder bump One or the more conventional methods of connecting a semiconductor device to surrounding points of interconnect is the use of a solder bump.
  • a semiconductor device will be provided on the active surface of the device with points of electrical interconnect which electrically access the device.
  • solder bumps are provided on the surface of the circuit board that align with the points of electrical contact of the device.
  • the creation of this interface is also subject to requirements imposed by electrical performance of the completed package, by requirements of package miniaturization, reliability, cost performance and the like.
  • the invention provides a package that addresses these packaging concerns in addition to others.
  • a principle objective of the invention is to provide a high-pillar solder bump that sustains a high stand-off of the complete solder bump while maintaining high bump reliability and minimizing damage caused by mismatching of thermal stress factors between the interfacing surfaces.
  • Another objective of the invention is to provide a method that further improves bump reliability by reducing mechanical and thermal stress.
  • Yet another objective of the invention is to provide re-distribution bumps which enable the creation of a flip-chip package without requiring a change in the design of the Integrated Circuit and without modifying the pad pitch, the performance of the package is improved and the package size does not need to be modified.
  • a still further objective of the invention is to provide a chip scale package using one UBM layer of metal, significantly reducing costs of fabrication and materials.
  • a still further objective of the invention is to provide a chip scale package whereby the solder ball is removed from the semiconductor device, eliminating the need for low-alpha solder, thus reducing fabrication cost and concerns of soft-error occurrence.
  • a new method and chip scale package is provided.
  • the inventions starts with a substrate over which a contact point is provided, the contact point and the surface of the substrate are protected by a layer of passivation, the contact point is exposed through an opening created in the layer of passivation.
  • a layer of polymer or elastomer is deposited over the layer of passivation, an opening is created through the layer of polymer or elastomer that aligns with the contact point (contact pad), exposing the contact pad.
  • a barrier/seed layer is deposited over the surface of the layer of polymer or elastomer, including the inside surfaces of the opening created through the layer of polymer or elastomer and the exposed surface of the contact pad.
  • a first photoresist mask is created over the surface of the barrier/seed layer, the first photoresist mask exposes the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad.
  • the exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces.
  • the first photoresist mask is removed from the surface of the barrier/seed layer, a second photoresist mask is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad.
  • the second photoresist mask defines that solder bump.
  • the solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer.
  • the exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.
  • FIG. 1 shows a cross section of a conventional mini-BGA package.
  • FIG. 2 shows a cross section of a conventional re-routing bump.
  • FIGS. 3 through 8 detail the process flow of the invention, as follows:
  • FIG. 3 shows a cross section of a silicon substrate, a top metal contact pad has been provided, a layer of passivation and a layer of polymer or elastomer have been deposited and patterned over the surface of the BGA substrate.
  • FIG. 4 shows a cross section after a barrier/seed layer has been deposited.
  • FIG. 5 shows a cross section after a first photoresist mask has been created over the surface of the barrier/seed layer, electroplating has been applied for the deposition of metal for the formation of interconnect traces.
  • FIG. 6 shows a cross section after the first photoresist mask has been removed from the surface of the barrier/seed layer.
  • FIG. 7 shows a cross section after a second photoresist mask has been created over the surface of the barrier/seed layer, including the surface of the electroplated interconnect metal; the second photoresist mask defines the solder bump.
  • FIG. 8 shows a cross section after the solder bump has been electroplated in accordance with the second photoresist mask.
  • FIG. 9 shows a cross section after removal of the second photoresist mask, exposing the surface of the barrier/seed layer and the electroplated interconnect metal.
  • FIG. 10 shows a cross section after the barrier/seed layer has been etched in accordance with the layer of interconnect metal.
  • FIG. 11 shows a cross section of the package of the invention with a molding compound as encapsulant.
  • FIG. 12 shows a cross section of the package of the invention with underfill as encapsulant.
  • FIG. 13 shows a cross section of the package of the invention using both molding and an underfill.
  • FIG. 14 shows a cross section of the package of the invention as a bare die that can be directly attached to a next level substrate.
  • FIGS. 1 and 2 Two prior art applications are shown in the cross sections of FIGS. 1 and 2 , specifically in the cross section of FIG. 1 are shown:
  • FIG. 2 shows a cross section of a conventional re-routing bump
  • the re-routing applies since the solder bump that is shown in cross section in FIG. 2 does not align with the contact pad with which the solder bump is connected.
  • the elements that are highlighted in the cross section of FIG. 2 are the following:
  • FIGS. 3 through 9 will now be used to describe the invention. Referring specifically to the cross section that is shown in FIG. 3 , there is shown:
  • polyimide polyimide
  • parylene or teflon electron resist
  • solid organics or inorganics BCB (bisbenzocyclobutene)
  • PMMA poly-methyl-methacrylate
  • teflon which is a polymer made from PTFE (polytetrafluoroethylene), also polycarbonate (PC), polysterene (PS), polyoxide (PO) and poly polooxide (PPO).
  • the semiconductor supporting surface 10 can be semiconductor substrates, printed circuit boards, flex circuits, metallized substrates, glass substrates and semiconductor device mounting support, whereby the semiconductor substrate can selected from the group of substrates consisting of semiconductor substrates, ceramic substrates, glass substrates, gallium arsenide substrates, silicon on insulator (SOI) substrates and silicon on sapphire (SOS) substrates.
  • semiconductor substrates consisting of semiconductor substrates, ceramic substrates, glass substrates, gallium arsenide substrates, silicon on insulator (SOI) substrates and silicon on sapphire (SOS) substrates.
  • FIG. 4 shows a cross section of the semiconductor substrate after a layer 46 of barrier/seed material has been deposited over the surface of layer 44 of polymer or elastomer; inside surface of opening 41 have also been covered with the layer 46 of barrier/seed material.
  • a typical barrier layer 46 is deposited using rf. sputtering of titanium nitride, tantalum, tungsten, niobium, molybdenum, Ti/TiN or Ti/W and is more preferably formed from TiN.
  • the barrier layer 46 can also be used to improve the adhesion of a subsequent overlying metal layers.
  • a barrier layer is preferably about 100 and 1000 angstrom thick.
  • a seed layer is deposited over the barrier layer.
  • a seed layer can be deposited using a sputter chamber or an Ion Metal Plasma (IMP) chamber at a temperature of between about 0 and 300 degrees C. and a pressure of between about 1 and 100 mTorr, using copper or a copper alloy as the source at a flow rate of between about 10 and 400 sccm and using argon as an ambient gas.
  • IMP Ion Metal Plasma
  • the minimum thickness of a seed layer is about 5,000 Angstrom, this thickness is required achieve a reliable gap fill.
  • FIG. 5 shows a cross section after:
  • the process of deposition and patterning a layer of photoresist uses conventional methods of photolithography and masking.
  • Layer 48 of photoresist can be etched by applying O 2 plasma and then wet stripping by using H 2 SO 4 , H 2 O 2 and NH 4 OH solution.
  • Sulfuric acid (H 2 SO 4 ) and mixtures of H 2 SO 4 with other oxidizing agents such as hydrogen peroxide (H 2 O 2 ) are widely used in stripping photoresist after the photoresist has been stripped by other means.
  • Wafers to be stripped can be immersed in the mixture at a temperature between about 100 degrees C. and about 150 degrees C. for 5 to 10 minutes and then subjected to a thorough cleaning with deionized water and dried by dry nitrogen.
  • Inorganic resist strippers such as the sulfuric acid mixtures, are very effective in the residual free removal of highly postbaked resist. They are more effective than organic strippers and the longer the immersion time, the cleaner and more residue free wafer surface can be obtained.
  • the opening 43 that is in this manner created in the layer 48 of photoresist exposes the surface of the layer 44 of barrier/seed material over a surface area where re-routing metal has to be created.
  • solder bump material can be selected as:
  • the solder bump is essentially complete.
  • the second solder mask 52 FIG. 8 , is therefore removed from the surface of the barrier/seed layer 46 and the surface of the interconnect metal 50 , see FIG. 9 , exposing the barrier/seed layer 46 and the interconnect metal 50 , a pattern of barrier/seed material overlying the barrier/seed layer 46 .
  • the barrier/seed layer 46 can now be etched using the patterned layer 50 of interconnect metal as a mask, which leads to the cross section that is shown in FIG. 10 .
  • Reflow can optionally be applied the layer 58 of solder compound, creating a spherical layer 58 of solder which forms the solder bump (not shown).
  • the diameter of the UBM layer 54 is, during and as a consequence of the etching of the barrier/seed layer 46 , reduced in diameter. This allows the solder ball 58 to be removed from the surface of the substrate by a relatively large distance. From this follows the advantage that it is no longer required that low-alpha solder is used for the solder compound of solder ball 58 reducing manufacturing cost in addition to reducing concerns of memory soft-error conditions.
  • Layer 56 of UBM may contain multiple layers of metal such as a layer of chrome, followed by a layer of copper, followed by a layer of gold. From the latter it is apparent that layer 56 of UBM may comprise several layers of metal that are successively deposited.
  • FIGS. 11 and 12 Examples of the application of the package of the invention are shown in cross section in FIGS. 11 and 12 . Highlighted in FIG. 11 are:
  • Shown in cross section in FIG. 12 is another application of the invention.
  • the elements that have been applied above under FIG. 11 are valid for the cross section shown in FIG. 12 with the exception of element 74 , which in the cross section of FIG. 12 is an underfill that has been applied under semiconductor device 64 and that replaces layer 66 of molding compound in FIG. 11 as the means for encapsulating the device 64 .
  • FIGS. 13 and 14 show additional applications of the invention with FIG. 13 showing a cross section of the package of the invention using both molding and an underfill while FIG. 14 shows a cross section of the package of the invention as a bare die that can be directly attached to a next level substrate. All elements of the cross sections that are shown in FIGS. 13 and 14 have previously been described and need therefore not been further highlighted at this time.
  • the invention provides a method to create a solder bump having a high metal pillar and a solder ball. Seed/barrier layer deposition is limited to one deposition, a first metal plating step defines the re-routing metal, a second metal plating step creates the solder bump. The need for additional layers of passivation or solder mask has been removed.

Abstract

The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

Description

  • This application is a continuation of application Ser. No. 10/136,650, filed on May 24, 2005, now pending, which is a division of application Ser. No. 10/638,454, filed on Aug. 11, 2003, now U.S. Pat. No. 6,917,119, which is a division of application Ser. No. 09/953,525, filed on Sep. 17, 2001, now U.S. Pat. No. 6,642,136.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and package for semiconductor devices.
  • 2. Description of the Prior Art
  • The creation of semiconductor devices, also referred to as Integrated Circuits (IC) has been made possible by the rapid development of supporting technologies such as photolithography and methods of etching. Most of these technologies have over the years had to address concerns created by a continued decrease in device dimensions and increase in device densities. This effort of creating improved performance devices does is not limited in its impact on the device itself but extends into the methods and packages that are used to further interconnect semiconductor devices and to protect these devices from environmental damage. This latter issue has created a packaging technology that is also driven by continuing demands of device miniaturization and denser packaging of devices, this at no penalty to device performance and in a cost-effective manner.
  • Semiconductor device packaging typically mounts a device on a substrate, such as semiconductor substrates, printed circuit boards, flex circuits, metallized substrates, glass substrates and semiconductor device mounting support. Such a substrate can be a relative complex structure, having multiple payers of interconnect metal distributed throughout the height of the substrate in addition to having interconnect traces created on one or both surfaces of the substrate. In addition, in order to enable the mounting of semiconductor over the surface of the substrate, contact pads such as bond pads are typically provided over at least one of the surfaces of a substrate. For more complex packages, several levels of packaging may be applied whereby a semiconductor device is mounted on a substrate and connected to interconnect metal that is part of the substrate, the first level substrate may be further mounted over the surface of a larger substrate from which the device is interconnected to surrounding circuitry or electrical components. Limitations that are imposed on this method of packaging are typically limitations of electrical performance that is imposed on the device by the packaging interface. For instance, of key concerns are RC delays in the transmission of signals over the various interconnect traces. This places a restraint of size and therefore packaging density on the package. Also of concern are considerations of parasitic capacitance and inductance that are introduced by the package since these parameters have a negative impact on device performance, a more serious impact on high frequency device performance. These parasitic components must therefore be minimized or suppressed to the maximum extent possible.
  • One or the more conventional methods of connecting a semiconductor device to surrounding points of interconnect is the use of a solder bump. Typically a semiconductor device will be provided on the active surface of the device with points of electrical interconnect which electrically access the device. To connect these points of interconnect to for instance a printer circuit board, solder bumps are provided on the surface of the circuit board that align with the points of electrical contact of the device. The creation of this interface is also subject to requirements imposed by electrical performance of the completed package, by requirements of package miniaturization, reliability, cost performance and the like. The invention provides a package that addresses these packaging concerns in addition to others.
  • U.S. Pat. No. 6,181,569 (Charkravorty) shows a solder bump process and structure that includes trace formation and bump plating.
  • U.S. Pat. No. 6,107,180 (Munroe et al.) shows a bump process using UBM and solder bumps.
  • U.S. Pat. No. 5,879,964 (Paik et al.) shows a related bump and interconnect process.
  • SUMMARY OF THE INVENTION
  • A principle objective of the invention is to provide a high-pillar solder bump that sustains a high stand-off of the complete solder bump while maintaining high bump reliability and minimizing damage caused by mismatching of thermal stress factors between the interfacing surfaces.
  • Another objective of the invention is to provide a method that further improves bump reliability by reducing mechanical and thermal stress.
  • Yet another objective of the invention is to provide re-distribution bumps which enable the creation of a flip-chip package without requiring a change in the design of the Integrated Circuit and without modifying the pad pitch, the performance of the package is improved and the package size does not need to be modified.
  • A still further objective of the invention is to provide a chip scale package using one UBM layer of metal, significantly reducing costs of fabrication and materials.
  • A still further objective of the invention is to provide a chip scale package whereby the solder ball is removed from the semiconductor device, eliminating the need for low-alpha solder, thus reducing fabrication cost and concerns of soft-error occurrence.
  • In accordance with the objectives of the invention a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point and the surface of the substrate are protected by a layer of passivation, the contact point is exposed through an opening created in the layer of passivation. A layer of polymer or elastomer is deposited over the layer of passivation, an opening is created through the layer of polymer or elastomer that aligns with the contact point (contact pad), exposing the contact pad. A barrier/seed layer is deposited over the surface of the layer of polymer or elastomer, including the inside surfaces of the opening created through the layer of polymer or elastomer and the exposed surface of the contact pad. A first photoresist mask is created over the surface of the barrier/seed layer, the first photoresist mask exposes the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer, a second photoresist mask is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The second photoresist mask defines that solder bump. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a cross section of a conventional mini-BGA package.
  • FIG. 2 shows a cross section of a conventional re-routing bump.
  • FIGS. 3 through 8 detail the process flow of the invention, as follows:
  • FIG. 3 shows a cross section of a silicon substrate, a top metal contact pad has been provided, a layer of passivation and a layer of polymer or elastomer have been deposited and patterned over the surface of the BGA substrate.
  • FIG. 4 shows a cross section after a barrier/seed layer has been deposited.
  • FIG. 5 shows a cross section after a first photoresist mask has been created over the surface of the barrier/seed layer, electroplating has been applied for the deposition of metal for the formation of interconnect traces.
  • FIG. 6 shows a cross section after the first photoresist mask has been removed from the surface of the barrier/seed layer.
  • FIG. 7 shows a cross section after a second photoresist mask has been created over the surface of the barrier/seed layer, including the surface of the electroplated interconnect metal; the second photoresist mask defines the solder bump.
  • FIG. 8 shows a cross section after the solder bump has been electroplated in accordance with the second photoresist mask.
  • FIG. 9 shows a cross section after removal of the second photoresist mask, exposing the surface of the barrier/seed layer and the electroplated interconnect metal.
  • FIG. 10 shows a cross section after the barrier/seed layer has been etched in accordance with the layer of interconnect metal.
  • FIG. 11 shows a cross section of the package of the invention with a molding compound as encapsulant.
  • FIG. 12 shows a cross section of the package of the invention with underfill as encapsulant.
  • FIG. 13 shows a cross section of the package of the invention using both molding and an underfill.
  • FIG. 14 shows a cross section of the package of the invention as a bare die that can be directly attached to a next level substrate.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Two prior art applications are shown in the cross sections of FIGS. 1 and 2, specifically in the cross section of FIG. 1 are shown:
      • 11, a BGA substrate such as a printed circuit board and the like
      • 12, a semiconductor device or die
      • 14, a molding compound that is used to encapsulate the die 12
      • 16, solder balls that form the electrical interface between the package shown in cross section in FIG. 1 and surrounding circuitry; these solder balls can for instance be further connected to contact pads on the surface of a Printed Circuit Board (PCB)
      • 18, bond wires used to connect points of electrical contact (not shown) on the active surface of die 12 with contact pads (not shown) on the second or upper surface of BGA substrate 11.
  • FIG. 2 shows a cross section of a conventional re-routing bump, the re-routing applies since the solder bump that is shown in cross section in FIG. 2 does not align with the contact pad with which the solder bump is connected. The elements that are highlighted in the cross section of FIG. 2 are the following:
      • 10, a device supporting silicon substrate
      • 20, a solder ball
      • 22, top metal contact point
      • 24, a layer of passivation, applied for the protection of the underlying surface and the surface of the layer 22 of top metal
      • 26, a layer of dielectric material
      • 28, a layer of passivation, applied for the protection of the underlying layer 26 of dielectric and the surface of the layer 32 of re-routing metal
      • 30, a seed and/or barrier layer
      • 32, a patterned layer of re-routing metal
      • 33, a seed layer, and
      • 34, a layer of UBM metal.
  • FIGS. 3 through 9 will now be used to describe the invention. Referring specifically to the cross section that is shown in FIG. 3, there is shown:
      • 10, a semiconductor supporting surface such as the surface of a silicon substrate
      • 40, a contact pad or top metal pad that has been provided in or on the surface of the substrate layer 10
      • 42, a layer of passivation deposited over the surface of layer 10; the layer 42 of passivation has been patterned and etched, creating on opening 41 through the layer 42 of passivation that aligns with the contact pad 40
      • 44, a layer of polymer or elastomer that has been deposited over the surface of the layer 42 of passivation; the layer 44 of polymer or elastomer has been patterned and etched, creating on opening 41 through the layer 42 of polymer or elastomer that aligns with the contact pad 40. Contact pad 40 can comprise aluminum or copper or a compound thereof.
  • As materials that can be used as a polymer for the deposition of layer 44 can be cited polyimide, parylene or teflon, electron resist, solid organics or inorganics, BCB (bisbenzocyclobutene), PMMA (poly-methyl-methacrylate), teflon which is a polymer made from PTFE (polytetrafluoroethylene), also polycarbonate (PC), polysterene (PS), polyoxide (PO) and poly polooxide (PPO).
  • The semiconductor supporting surface 10 can be semiconductor substrates, printed circuit boards, flex circuits, metallized substrates, glass substrates and semiconductor device mounting support, whereby the semiconductor substrate can selected from the group of substrates consisting of semiconductor substrates, ceramic substrates, glass substrates, gallium arsenide substrates, silicon on insulator (SOI) substrates and silicon on sapphire (SOS) substrates.
  • FIG. 4 shows a cross section of the semiconductor substrate after a layer 46 of barrier/seed material has been deposited over the surface of layer 44 of polymer or elastomer; inside surface of opening 41 have also been covered with the layer 46 of barrier/seed material.
  • A typical barrier layer 46 is deposited using rf. sputtering of titanium nitride, tantalum, tungsten, niobium, molybdenum, Ti/TiN or Ti/W and is more preferably formed from TiN. The barrier layer 46 can also be used to improve the adhesion of a subsequent overlying metal layers. A barrier layer is preferably about 100 and 1000 angstrom thick.
  • To further enhance the adhesion of a copper interconnect line to the surrounding layer of dielectric or insulation, a seed layer is deposited over the barrier layer. A seed layer can be deposited using a sputter chamber or an Ion Metal Plasma (IMP) chamber at a temperature of between about 0 and 300 degrees C. and a pressure of between about 1 and 100 mTorr, using copper or a copper alloy as the source at a flow rate of between about 10 and 400 sccm and using argon as an ambient gas. The minimum thickness of a seed layer is about 5,000 Angstrom, this thickness is required achieve a reliable gap fill.
  • FIG. 5 shows a cross section after:
      • 48, a first photoresist mask has been formed over the surface of barrier/seed layer 46, exposing the surface of the barrier/seed layer 46, and
      • 50, a layer 50 of metal has been over the exposed surface of the barrier/seed layer 46 in accordance with the opening 43 created in the first photoresist mask.
  • The process of deposition and patterning a layer of photoresist uses conventional methods of photolithography and masking. Layer 48 of photoresist can be etched by applying O2 plasma and then wet stripping by using H2SO4, H2O2 and NH4OH solution. Sulfuric acid (H2SO4) and mixtures of H2SO4 with other oxidizing agents such as hydrogen peroxide (H2O2) are widely used in stripping photoresist after the photoresist has been stripped by other means. Wafers to be stripped can be immersed in the mixture at a temperature between about 100 degrees C. and about 150 degrees C. for 5 to 10 minutes and then subjected to a thorough cleaning with deionized water and dried by dry nitrogen. Inorganic resist strippers, such as the sulfuric acid mixtures, are very effective in the residual free removal of highly postbaked resist. They are more effective than organic strippers and the longer the immersion time, the cleaner and more residue free wafer surface can be obtained. The opening 43 that is in this manner created in the layer 48 of photoresist exposes the surface of the layer 44 of barrier/seed material over a surface area where re-routing metal has to be created.
  • Removal of the first photoresist mask 48 from the surface of the barrier/seed layer 46 results in the cross section that is shown in FIG. 6.
  • The invention continues with the cross section that is shown in FIG. 7, shown are:
      • 52, a second photoresist mask is created over the surface of the barrier/seed layer 46, including the surface of the interconnect metal layer 50, and
      • 51 opening created in the second layer 52 of photoresist, exposing the surface of layer 50 of interconnect metal; opening 51 defined the location and size (diameter) of the to be created solder bump.
  • The cross section that is shown in FIG. 8 is after the opening 51 created in the second layer of dielectric has been filled with solder bump material. These materials can be selected as:
      • layer 54 being a first layer of metal, typically comprising copper, deposited to a thickness between about 10 and 100 μm, and more preferably to a thickness of about 50 μm
      • layer 56 being an UBM layer, typically comprising nickel, deposited to a thickness between about 1 and 10 μm, and more preferably to a thickness of about 5 μm, forming an integral part of the pedestal of the to be created interconnect bump, and
      • layer 58 is a layer of solder compound, deposited to a thickness between about 10 and 100 μm, and more preferably to a thickness of about 50 μm.
  • With the completion of the electroplating of these three layers, the solder bump is essentially complete. The second solder mask 52, FIG. 8, is therefore removed from the surface of the barrier/seed layer 46 and the surface of the interconnect metal 50, see FIG. 9, exposing the barrier/seed layer 46 and the interconnect metal 50, a pattern of barrier/seed material overlying the barrier/seed layer 46.
  • It is good practice and can be of benefit in the creation of the layers 54, 56 and 58 of metal to perform, prior to the electroplating of these layers of metal, an in-situ sputter clean of the exposed surface (exposed through opening 51) of the layer 50 of re-routing metal.
  • The barrier/seed layer 46 can now be etched using the patterned layer 50 of interconnect metal as a mask, which leads to the cross section that is shown in FIG. 10.
  • It is further good practice to oxidize the surface of the UBM and pillar metal by chemical or thermal oxidation. The chemical oxidation could be an H2O2 oxidation process, at a temperature in excess of about 150 degrees C. These processing steps can further help prevent wetting of the solder bump to the metal traces.
  • Reflow can optionally be applied the layer 58 of solder compound, creating a spherical layer 58 of solder which forms the solder bump (not shown). It must be noted in the cross section that is shown in FIG. 10 that the diameter of the UBM layer 54 is, during and as a consequence of the etching of the barrier/seed layer 46, reduced in diameter. This allows the solder ball 58 to be removed from the surface of the substrate by a relatively large distance. From this follows the advantage that it is no longer required that low-alpha solder is used for the solder compound of solder ball 58 reducing manufacturing cost in addition to reducing concerns of memory soft-error conditions.
  • Layer 56 of UBM may contain multiple layers of metal such as a layer of chrome, followed by a layer of copper, followed by a layer of gold. From the latter it is apparent that layer 56 of UBM may comprise several layers of metal that are successively deposited.
  • Examples of the application of the package of the invention are shown in cross section in FIGS. 11 and 12. Highlighted in FIG. 11 are:
      • 60, a polymer or elastomer layer provided by the invention, similar to layer 44 of FIG. 3 e.a.
      • 62, a BGA substrate over which a semiconductor device is to be mounted
      • 64, a semiconductor device
      • 66, a molding compound applied to encapsulate the device 64
      • 68, contact balls to the package of the invention
      • 70, pillar metal, similar to layers 54 and 56 of FIG. 8 e.a., and
      • 72, a solder bump, similar to layer 58 of FIG. 8 after thermal reflow has been applied to this layer.
  • Shown in cross section in FIG. 12 is another application of the invention. The elements that have been applied above under FIG. 11 are valid for the cross section shown in FIG. 12 with the exception of element 74, which in the cross section of FIG. 12 is an underfill that has been applied under semiconductor device 64 and that replaces layer 66 of molding compound in FIG. 11 as the means for encapsulating the device 64.
  • FIGS. 13 and 14 show additional applications of the invention with FIG. 13 showing a cross section of the package of the invention using both molding and an underfill while FIG. 14 shows a cross section of the package of the invention as a bare die that can be directly attached to a next level substrate. All elements of the cross sections that are shown in FIGS. 13 and 14 have previously been described and need therefore not been further highlighted at this time.
  • In order to better highlight the differences between the prior art solder bump, as shown in cross section in FIG. 2, and the solder bump of the invention, as shown in the cross section of FIG. 10, the processing steps to create these two solder bumps are listed below. These steps are easier to follow if it is realized that both methods require and apply two metal fill plating steps, the first of these two step is to create a patterned layer of re-routing metal, the second is to create the solder bump. The processing sequences are as follows:
    • 1. the prior art starts with a device support substrate, a contact pad has been created over the surface of the substrate, layers of passivation and dielectric have been deposited over the surface of the substrate and patterned to expose the contact pad; the invention starts with the same structure
    • 2. the prior art deposits a first seed layer over the surface of the layer of dielectric; the invention does the same
    • 3. the prior art performs a first metal fill over the first seed layer by creating a layer of metal that serves as re-routing metal; the invention does the same
    • 4. the prior art etches the first seed layer; the instant invention does not perform this step at this time
    • 5. the prior art deposits and patterns a layer of passivation, exposing the surface of the layer of re-routing metal, the patterned second layer of passivation serves as a mask for the reflow of the solder bump; the instant invention does not perform this step because the solder bump structure will not wet to the re-routing metal
    • 6. the prior art deposits a second seed layer over the surface of the layer of passivation; the instant invention does not deposit a second seed layer
    • 7. the prior art plates a layer of UBM over which a layer of solder compound is plated; the instant invention deposits a layer of UBM and two metal plating steps, the first metal plating step plating a layer of metal, such as copper or nickel that forms an integral part of the pedestal of the to be created interconnect bump, the second metal plating step depositing a solder compound
    • 8. the prior art performs reflow of the solder compound; the instant invention does the same
    • 9. the prior art etches the second seed layer using the solder ball as a mask; the instant invention etches the first seed layer using the patterned re-routing metal as a mask.
  • The essential differences between the prior art and the instant invention is provided by the two plating steps and can, for easy reference be summarized as follows:
  • Prior Art Instant Invention
    First plating step
    1st seed layer dep. 1st seed layer dep.
    plate re-routing metal plate re-routing metal
    etch
    1st seed layer (no equivalent step)
    Second plating step
    2st seed layer dep. (no equivalent step)
    plate UBM + solder plate UBM + metal + solder
    etch 2st seed layer etch 1st seed layer
  • The advantages of the instant invention can be summarized as follows:
    • 1. the height of the metal pillar (layers 54 and 56, FIG. 10) allows for high stand-off between the surface of substrate 10, thereby reducing impact of mismatching of thermal fatigue between interfacing surfaces such as the surface of the substrate 10 and the layers of metal that are part of the solder bump
    • 2. the layer 44 has been highlighted as being a layer of or polymer or elastomer and is selected for its ability to provide stress release between overlying surfaces and thus to enhance solder bump reliability
    • 3. the re-distribution solder bump of the invention allows for creating a flip-chip package without the need for semiconductor device redesign or changes in the pitch of the contact points of the package (the pitch of contact balls 72 and 68, FIGS. 11 and 12); the package size can also remain constant while still being able to package die of different dimensions (due to the flexibility of the routing of the re-routing metal layer 50, FIG. 50, FIG. 10)
    • 4. the method of creating the solder pillar and the solder bump, that is plating a layer of UBM over which metal is plated twice, contributes a significant cost saving in both materials used and in the manufacturing cost; the need for separate UBM plating and etching, for separate plating and etching the pillar metal and for separate plating and etching the solder compound is reduced to using one photoresist mask that is applied for all three steps
    • 5. by creating a relatively high layer of pillar metal, the solder ball is removed from the surface of the substrate; from this follows that low-alpha solder is no longer required as a solder compound for the solder bump, reducing manufacturing costs; from this further follows that soft-error concerns that typically apply to memory chip designs are less valid using the solder bump of the invention
    • 6. by creating a relatively high layer of pillar metal, the solder ball of the instant invention will not wet to the re-routing metal trace. Thus, the second layer of passivation material, which typically serves as a solder mask, is no longer required and, consequently, processing cost is reduced.
  • In sum: the invention provides a method to create a solder bump having a high metal pillar and a solder ball. Seed/barrier layer deposition is limited to one deposition, a first metal plating step defines the re-routing metal, a second metal plating step creates the solder bump. The need for additional layers of passivation or solder mask has been removed.
  • Although the invention has been described and illustrated with reference to specific illustrative embodiments thereof, it is not intended that the invention be limited to those illustrative embodiments. Those skilled in the art will recognize that variations and modifications can be made without departing from the spirit of the invention. It is therefore intended to include within the invention all such variations and modifications which fall within the scope of the appended claims and equivalents thereof.

Claims (20)

What is claimed is:
1. A method for fabricating a metal bump over a device, comprising:
providing a silicon substrate, a copper pad over said silicon substrate, a passivation layer over said silicon substrate, and a polymer layer on said passivation layer, wherein an opening in said passivation layer and in said polymer layer exposes said copper pad;
forming a first metal layer over said copper pad and over said polymer layer;
forming a first photoresist layer on said first metal layer, an opening in said first photoresist layer exposes said first metal layer;
forming a second metal layer on said first metal layer exposed by said opening in said first photoresist layer;
removing said first photoresist layer;
forming a second photoresist layer on said second metal layer, wherein an opening in said second photoresist layer exposes said second metal layer;
electroplating a copper pillar over said second metal layer exposed by said opening in said second photoresist layer, wherein said copper pillar has a height between 10 and 100 micrometers;
electroplating a nickel layer over said copper pillar in said opening in said second photoresist layer, wherein said nickel layer has a thickness between 1 and 10 micrometers;
electroplating a solder layer directly on said nickel layer in said opening in said second photoresist layer, wherein said solder layer has a thickness between 10 and 100 micrometers;
removing said second photoresist layer; and
reducing a transverse dimension of said copper pillar to be smaller that said height of said copper pillar and removing said first metal layer not under said second metal layer.
2. The method of claim 1, wherein said polymer layer comprises polyimide.
3. The method of claim 1, wherein said first metal layer comprises titanium.
4. The method of claim 1, wherein said first metal layer comprises tantalum.
5. The method of claim 1, wherein said first metal layer comprises copper.
6. The method of claim 1, wherein said forming said first metal layer comprises a sputtering process.
7. The method of claim 1, wherein said forming said second metal layer comprises an electroplating process.
8. A method for fabricating a metal bump over a device, comprising:
providing a silicon substrate, a copper pad over said silicon substrate, and a passivation layer over said silicon substrate, wherein an opening in said passivation layer exposes said copper pad;
forming a first metal layer over said copper pad and over said passivation layer;
forming a first photoresist layer on said first metal layer, an opening in said first photoresist layer exposes said first metal layer;
forming a second metal layer on said first metal layer exposed by said opening in said first photoresist layer;
removing said first photoresist layer;
forming a second photoresist layer on said second metal layer, wherein an opening in said second photoresist layer exposes said second metal layer;
electroplating a copper pillar over said second metal layer exposed by said opening in said second photoresist layer, wherein said copper pillar has a height between 10 and 100 micrometers;
electroplating a nickel layer over said copper pillar in said opening in said second photoresist layer, wherein said nickel layer has a thickness between 1 and 10 micrometers;
electroplating a solder layer directly on said nickel layer in said opening in said second photoresist layer, wherein said solder layer has a thickness between 10 and 100 micrometers;
removing said second photoresist layer; and
reducing a transverse dimension of said copper pillar to be smaller that said height of said copper pillar and removing said first metal layer not under said second metal layer.
9. The method of claim 8, wherein said first metal layer comprises titanium.
10. The method of claim 8, wherein said first metal layer comprises tantalum.
11. The method of claim 8, wherein said first metal layer comprises copper.
12. The method of claim 8, wherein said forming said first metal layer comprises a sputtering process.
13. The method of claim 8, wherein said forming said second metal layer comprises an electroplating process.
14. A method for fabricating a metal bump over a device, comprising:
providing a silicon substrate, a copper pad over said silicon substrate, a passivation layer over said silicon substrate, and a polymer layer on said passivation layer, wherein an opening in said passivation layer and in said polymer layer exposes said copper pad;
forming a first metal layer over said copper pad and over said polymer layer;
forming a first photoresist layer on said first metal layer, an opening in said first photoresist layer exposes said first metal layer;
forming a second metal layer on said first metal layer exposed by said opening in said first photoresist layer;
removing said first photoresist layer;
forming a second photoresist layer on said second metal layer, wherein an opening in said second photoresist layer exposes said second metal layer;
electroplating a copper pillar over said second metal layer exposed by said opening in said second photoresist layer, wherein said copper pillar has a height between 10 and 100 micrometers;
electroplating a solder layer over said copper pillar in said opening in said second photoresist layer, wherein said solder layer has a thickness between 10 and 100 micrometers;
removing said second photoresist layer;
reducing a transverse dimension of said copper pillar to be smaller than said height of said copper pillar and removing said first metal layer not under said second metal layer.
15. The method of claim 16, wherein said polymer layer comprises polyimide.
16. The method of claim 16, wherein said first metal layer comprises titanium.
17. The method of claim 16, wherein said first metal layer comprises tantalum.
18. The method of claim 16, wherein said first metal layer comprises copper.
19. The method of claim 16, wherein said forming said first metal layer comprises a sputtering process.
20. The method of claim 16, wherein said forming said second metal layer comprises an electroplating process.
US11/930,220 2002-05-01 2007-10-31 Low fabrication cost, high performance, high reliability chip scale package Expired - Lifetime US8481418B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/930,220 US8481418B2 (en) 2002-05-01 2007-10-31 Low fabrication cost, high performance, high reliability chip scale package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/136,650 US7099293B2 (en) 2002-05-01 2002-05-01 Buffer-less de-skewing for symbol combination in a CDMA demodulator
US11/930,220 US8481418B2 (en) 2002-05-01 2007-10-31 Low fabrication cost, high performance, high reliability chip scale package

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
US10/136,650 Continuation US7099293B2 (en) 2001-09-17 2002-05-01 Buffer-less de-skewing for symbol combination in a CDMA demodulator
US11/136,650 Continuation US7338890B2 (en) 1998-03-31 2005-05-24 Low fabrication cost, high performance, high reliability chip scale package

Publications (3)

Publication Number Publication Date
US20080113503A1 true US20080113503A1 (en) 2008-05-15
US20090137110A9 US20090137110A9 (en) 2009-05-28
US8481418B2 US8481418B2 (en) 2013-07-09

Family

ID=29215675

Family Applications (4)

Application Number Title Priority Date Filing Date
US10/136,650 Active 2024-12-13 US7099293B2 (en) 2001-09-17 2002-05-01 Buffer-less de-skewing for symbol combination in a CDMA demodulator
US11/930,224 Abandoned US20080113504A1 (en) 2002-05-01 2007-10-31 Low fabrication cost, high performance, high reliability chip scale package
US11/930,213 Expired - Lifetime US9369175B2 (en) 2001-09-17 2007-10-31 Low fabrication cost, high performance, high reliability chip scale package
US11/930,220 Expired - Lifetime US8481418B2 (en) 2002-05-01 2007-10-31 Low fabrication cost, high performance, high reliability chip scale package

Family Applications Before (3)

Application Number Title Priority Date Filing Date
US10/136,650 Active 2024-12-13 US7099293B2 (en) 2001-09-17 2002-05-01 Buffer-less de-skewing for symbol combination in a CDMA demodulator
US11/930,224 Abandoned US20080113504A1 (en) 2002-05-01 2007-10-31 Low fabrication cost, high performance, high reliability chip scale package
US11/930,213 Expired - Lifetime US9369175B2 (en) 2001-09-17 2007-10-31 Low fabrication cost, high performance, high reliability chip scale package

Country Status (3)

Country Link
US (4) US7099293B2 (en)
EP (1) EP1359682A3 (en)
JP (1) JP2004007636A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080308929A1 (en) * 2007-06-13 2008-12-18 Himax Technologies Limited Semiconductor device, chip package and method of fabricating the same
US9369175B2 (en) 2001-09-17 2016-06-14 Qualcomm Incorporated Low fabrication cost, high performance, high reliability chip scale package

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7490092B2 (en) 2000-07-06 2009-02-10 Streamsage, Inc. Method and system for indexing and searching timed media information based upon relevance intervals
TWI313507B (en) * 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US8365230B2 (en) 2001-09-19 2013-01-29 Tvworks, Llc Interactive user interface for television applications
US8042132B2 (en) 2002-03-15 2011-10-18 Tvworks, Llc System and method for construction, delivery and display of iTV content
US7703116B1 (en) 2003-07-11 2010-04-20 Tvworks, Llc System and method for construction, delivery and display of iTV applications that blend programming information of on-demand and broadcast service offerings
US7801085B1 (en) * 2002-06-03 2010-09-21 Ericsson Ab System and method of processing CDMA signals
US8220018B2 (en) 2002-09-19 2012-07-10 Tvworks, Llc System and method for preferred placement programming of iTV content
US7260165B2 (en) 2002-11-27 2007-08-21 Broadcom Corporation Method for synchronization through accelerated advance of counters
US8578411B1 (en) 2003-03-14 2013-11-05 Tvworks, Llc System and method for controlling iTV application behaviors through the use of application profile filters
US11381875B2 (en) 2003-03-14 2022-07-05 Comcast Cable Communications Management, Llc Causing display of user-selectable content types
US8819734B2 (en) 2003-09-16 2014-08-26 Tvworks, Llc Contextual navigational control for digital television
US7645397B2 (en) 2004-01-15 2010-01-12 Nanosys, Inc. Nanocrystal doped matrixes
US20060215567A1 (en) * 2005-03-25 2006-09-28 Arun Raghunath Method and apparatus for monitoring path statistics
US7818667B2 (en) 2005-05-03 2010-10-19 Tv Works Llc Verification of semantic constraints in multimedia data and in its announcement, signaling and interchange
DE102005045767B4 (en) * 2005-09-23 2012-03-29 Infineon Technologies Ag Method for producing a semiconductor device with plastic housing composition
JP5130469B2 (en) * 2006-08-10 2013-01-30 楽天Edy株式会社 Information processing apparatus, information processing method, and information processing program
US11832024B2 (en) 2008-11-20 2023-11-28 Comcast Cable Communications, Llc Method and apparatus for delivering video and video-related content at sub-asset level
US8713016B2 (en) 2008-12-24 2014-04-29 Comcast Interactive Media, Llc Method and apparatus for organizing segments of media assets and determining relevance of segments to a query
US9442933B2 (en) 2008-12-24 2016-09-13 Comcast Interactive Media, Llc Identification of segments within audio, video, and multimedia items
US9129955B2 (en) * 2009-02-04 2015-09-08 Texas Instruments Incorporated Semiconductor flip-chip system having oblong connectors and reduced trace pitches
US10714436B2 (en) * 2012-12-12 2020-07-14 Lam Research Corporation Systems and methods for achieving uniformity across a redistribution layer
US10880609B2 (en) 2013-03-14 2020-12-29 Comcast Cable Communications, Llc Content event messaging
US9059092B2 (en) 2013-09-17 2015-06-16 Taiwan Semiconductor Manufacturing Company Limited Chemical dielectric formation for semiconductor device fabrication
US11783382B2 (en) 2014-10-22 2023-10-10 Comcast Cable Communications, Llc Systems and methods for curating content metadata
US9583462B2 (en) * 2015-01-22 2017-02-28 Qualcomm Incorporated Damascene re-distribution layer (RDL) in fan out split die application
TWI572257B (en) * 2015-10-19 2017-02-21 欣興電子股份有限公司 Pillar structure and manufacturing method thereof
JP2017216443A (en) * 2016-05-20 2017-12-07 ラム リサーチ コーポレーションLam Research Corporation System and method for achieving uniformity across redistribution layer
US10797012B2 (en) 2017-08-25 2020-10-06 Dialog Semiconductor (Uk) Limited Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devices
US11749616B2 (en) 2017-10-05 2023-09-05 Texas Instruments Incorporated Industrial chip scale package for microelectronic device
CN112514050A (en) 2018-07-26 2021-03-16 朗姆研究公司 Alternative integration for redistribution layer processes
US20200066626A1 (en) * 2018-08-21 2020-02-27 Intel Corporation Pocket structures, materials, and methods for integrated circuit package supports
US11652031B2 (en) * 2018-12-13 2023-05-16 Intel Corporation Shrinkable package assembly
DE102019103355A1 (en) 2019-02-11 2020-08-13 Infineon Technologies Ag A semiconductor device having a copper pillar interconnection structure
US11469216B2 (en) * 2020-03-27 2022-10-11 Nanya Technology Corporation Dual-die semiconductor package and manufacturing method thereof
US11682607B2 (en) * 2021-02-01 2023-06-20 Qualcomm Incorporated Package having a substrate comprising surface interconnects aligned with a surface of the substrate

Citations (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3668484A (en) * 1970-10-28 1972-06-06 Rca Corp Semiconductor device with multi-level metalization and method of making the same
US4087314A (en) * 1976-09-13 1978-05-02 Motorola, Inc. Bonding pedestals for semiconductor devices
US4652336A (en) * 1984-09-20 1987-03-24 Siemens Aktiengesellschaft Method of producing copper platforms for integrated circuits
US4726991A (en) * 1986-07-10 1988-02-23 Eos Technologies Inc. Electrical overstress protection material and process
US4811237A (en) * 1987-06-19 1989-03-07 General Electric Company Structured design method for generating a mesh power bus structure in high density layout of VLSI chips
US4825276A (en) * 1986-06-19 1989-04-25 Nec Corporation Integrated circuit semiconductor device having improved wiring structure
US5046161A (en) * 1988-02-23 1991-09-03 Nec Corporation Flip chip type semiconductor device
US5061985A (en) * 1988-06-13 1991-10-29 Hitachi, Ltd. Semiconductor integrated circuit device and process for producing the same
US5083187A (en) * 1990-05-16 1992-01-21 Texas Instruments Incorporated Integrated circuit device having bumped power supply buses over active surface areas and method of manufacture thereof
US5108950A (en) * 1987-11-18 1992-04-28 Casio Computer Co., Ltd. Method for forming a bump electrode for a semiconductor device
US5132775A (en) * 1987-12-11 1992-07-21 Texas Instruments Incorporated Methods for and products having self-aligned conductive pillars on interconnects
US5134460A (en) * 1986-08-11 1992-07-28 International Business Machines Corporation Aluminum bump, reworkable bump, and titanium nitride structure for tab bonding
US5137845A (en) * 1990-07-31 1992-08-11 International Business Machines Corporation Method of forming metal contact pads and terminals on semiconductor chips
US5223454A (en) * 1988-01-29 1993-06-29 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit device
US5226232A (en) * 1990-05-18 1993-07-13 Hewlett-Packard Company Method for forming a conductive pattern on an integrated circuit
US5244833A (en) * 1989-07-26 1993-09-14 International Business Machines Corporation Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer
US5541135A (en) * 1995-05-30 1996-07-30 Motorola, Inc. Method of fabricating a flip chip semiconductor device having an inductor
US5598348A (en) * 1994-09-22 1997-01-28 Sun Microsystems, Inc. Method and apparatus for analyzing the power network of a VLSI circuit
US5629241A (en) * 1995-07-07 1997-05-13 Hughes Aircraft Company Microwave/millimeter wave circuit structure with discrete flip-chip mounted elements, and method of fabricating the same
US5656863A (en) * 1993-02-18 1997-08-12 Mitsubishi Denki Kabushiki Kaisha Resin seal semiconductor package
US5756370A (en) * 1996-02-08 1998-05-26 Micron Technology, Inc. Compliant contact system with alignment structure for testing unpackaged semiconductor dice
US5767010A (en) * 1995-03-20 1998-06-16 Mcnc Solder bump fabrication methods and structure including a titanium barrier layer
US5808900A (en) * 1996-04-30 1998-09-15 Lsi Logic Corporation Memory having direct strap connection to power supply
US5882957A (en) * 1997-06-09 1999-03-16 Compeq Manufacturing Company Limited Ball grid array packaging method for an integrated circuit and structure realized by the method
US5892273A (en) * 1994-10-03 1999-04-06 Kabushiki Kaisha Toshiba Semiconductor package integral with semiconductor chip
US5933358A (en) * 1997-09-30 1999-08-03 Synopsys, Inc. Method and system of performing voltage drop analysis for power supply networks of VLSI circuits
US5937320A (en) * 1998-04-08 1999-08-10 International Business Machines Corporation Barrier layers for electroplated SnPb eutectic solder joints
US6013571A (en) * 1997-06-16 2000-01-11 Motorola, Inc. Microelectronic assembly including columnar interconnections and method for forming same
US6015505A (en) * 1997-10-30 2000-01-18 International Business Machines Corporation Process improvements for titanium-tungsten etching in the presence of electroplated C4's
US6042953A (en) * 1996-03-21 2000-03-28 Matsushita Electric Industrial Co., Ltd. Substrate on which bumps are formed and method of forming the same
US6043672A (en) * 1998-05-13 2000-03-28 Lsi Logic Corporation Selectable power supply lines for isolating defects in integrated circuits
US6051450A (en) * 1997-07-01 2000-04-18 Sony Corporation Lead frame, manufacturing method of a lead frame, semiconductor device, assembling method of a semiconductor device, and electronic apparatus
US6075290A (en) * 1998-02-26 2000-06-13 National Semiconductor Corporation Surface mount die: wafer level chip-scale package and process for making the same
US6093964A (en) * 1996-06-27 2000-07-25 International Business Machines Corporation Connection structure utilizing a metal bump and metal bump manufacturing method
US6177731B1 (en) * 1998-01-19 2001-01-23 Citizen Watch Co., Ltd. Semiconductor package
US6180265B1 (en) * 1997-06-27 2001-01-30 Delco Electronics Corporation Flip chip solder bump pad
US6198169B1 (en) * 1998-12-17 2001-03-06 Shinko Electric Industries Co., Ltd. Semiconductor device and process for producing same
US6202191B1 (en) * 1999-06-15 2001-03-13 International Business Machines Corporation Electromigration resistant power distribution network
US6202196B1 (en) * 1998-02-03 2001-03-13 Lsi Logic Corporation Method for optimizing routing mesh segment width
US6250541B1 (en) * 1997-06-23 2001-06-26 Visteon Global Technologies, Inc. Method of forming interconnections on electronic modules
US6258705B1 (en) * 2000-08-21 2001-07-10 Siliconeware Precision Industries Co., Ltd. Method of forming circuit probing contact points on fine pitch peripheral bond pads on flip chip
US6268662B1 (en) * 1998-10-14 2001-07-31 Texas Instruments Incorporated Wire bonded flip-chip assembly of semiconductor devices
US20010026021A1 (en) * 2000-02-21 2001-10-04 Hirokazu Honda Flip-chip type semiconductor device and method of manufacturing the same
US6308307B1 (en) * 1998-01-29 2001-10-23 Texas Instruments Incorporated Method for power routing and distribution in an integrated circuit with multiple interconnect layers
US6311147B1 (en) * 1995-04-17 2001-10-30 Synopsys, Inc. Integrated circuit power net analysis
US6348401B1 (en) * 2000-11-10 2002-02-19 Siliconware Precision Industries Co., Ltd. Method of fabricating solder bumps with high coplanarity for flip-chip application
US6405357B1 (en) * 2000-05-02 2002-06-11 Advanced Semiconductor Engineering, Inc. Method for positioning bond pads in a semiconductor die
US6414390B2 (en) * 1998-03-27 2002-07-02 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board and electronic instrument
US6426281B1 (en) * 2001-01-16 2002-07-30 Taiwan Semiconductor Manufacturing Company Method to form bump in bumping technology
US6429531B1 (en) * 2000-04-18 2002-08-06 Motorola, Inc. Method and apparatus for manufacturing an interconnect structure
US6446245B1 (en) * 2000-01-05 2002-09-03 Sun Microsystems, Inc. Method and apparatus for performing power routing in ASIC design
US20020121709A1 (en) * 2000-12-28 2002-09-05 Fujitsu Limited External connection terminal and semiconductor device
US6467674B1 (en) * 1999-12-09 2002-10-22 Casio Computer Co., Ltd. Method of manufacturing semiconductor device having sealing film on its surface
US6510539B1 (en) * 1999-10-29 2003-01-21 International Business Machines Corporation System and method for physically modeling electronic modules wiring
US6518092B2 (en) * 2000-07-13 2003-02-11 Oki Electric Industry Co., Ltd. Semiconductor device and method for manufacturing
US6523154B2 (en) * 2000-12-14 2003-02-18 International Business Machines Corporation Method for supply voltage drop analysis during placement phase of chip design
US6573598B2 (en) * 1999-04-06 2003-06-03 Oki Electric Industry Co, Ltd. Semiconductor device and method of fabricating the same
US6578754B1 (en) * 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6592019B2 (en) * 2000-04-27 2003-07-15 Advanpack Solutions Pte. Ltd Pillar connections for semiconductor chips and method of manufacture
US6598206B2 (en) * 2001-05-10 2003-07-22 International Business Machines Corporation Method and system of modifying integrated circuit power rails
US20030140327A1 (en) * 2001-12-18 2003-07-24 Glenn Lai Method of designing power vias in an IC layout
US6600234B2 (en) * 1999-02-03 2003-07-29 Casio Computer Co., Ltd. Mounting structure having columnar electrodes and a sealing film
US6627988B2 (en) * 2000-04-06 2003-09-30 Oki Electric Industry Co, Ltd. Semiconductor device and method for manufacturing the same
US6675139B1 (en) * 1999-03-16 2004-01-06 Lsi Logic Corporation Floor plan-based power bus analysis and design tool for integrated circuits
US6683380B2 (en) * 2000-07-07 2004-01-27 Texas Instruments Incorporated Integrated circuit with bonding layer over active circuitry
US20040080630A1 (en) * 2002-10-10 2004-04-29 Hynix Semiconductor Inc. Pixel array, image sensor having the pixel array and method for removing flicker noise of the image sensor
US6731003B2 (en) * 2002-03-12 2004-05-04 Fairchild Semiconductor Corporation Wafer-level coated copper stud bumps
US6732913B2 (en) * 2001-04-26 2004-05-11 Advanpack Solutions Pte Ltd. Method for forming a wafer level chip scale package, and package formed thereby
US20040163054A1 (en) * 2003-02-19 2004-08-19 Frank Mark D. System and method for evaluating vias per pad in a package design
US6861742B2 (en) * 2001-01-18 2005-03-01 Renesas Technology Corp. Wafer level chip size package having rerouting layers
US20050050502A1 (en) * 2003-08-27 2005-03-03 Fujitsu Limited Method and apparatus for designing semiconductor integrated circuit
US20050090916A1 (en) * 2003-08-25 2005-04-28 Majid Aghababazadeh Intra-chip power and test signal generation for use with test structures on wafers
US6917119B2 (en) * 2001-09-17 2005-07-12 Megic Corporation Low fabrication cost, high performance, high reliability chip scale package
US6917106B2 (en) * 2002-10-24 2005-07-12 Intel Corporation Selective ball-limiting metallurgy etching processes for fabrication of electroplated tin bumps
US6940169B2 (en) * 2002-05-21 2005-09-06 Stats Chippac Ltd. Torch bump
US6991961B2 (en) * 2003-06-18 2006-01-31 Medtronic, Inc. Method of forming a high-voltage/high-power die package
US6998710B2 (en) * 2003-12-24 2006-02-14 Fujitsu Limited High-frequency device
US7008867B2 (en) * 2003-02-21 2006-03-07 Aptos Corporation Method for forming copper bump antioxidation surface
US20060095872A1 (en) * 2002-07-29 2006-05-04 Mcelvain Kenneth S Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
US7043389B2 (en) * 2004-02-18 2006-05-09 James Francis Plusquellic Method and system for identifying and locating defects in an integrated circuit
US7095105B2 (en) * 2004-03-23 2006-08-22 Texas Instruments Incorporated Vertically stacked semiconductor device
US7111265B1 (en) * 2002-12-23 2006-09-19 Altera Corporation I/O pin placement for a programmable logic device
US7196001B2 (en) * 2001-09-21 2007-03-27 Intel Corporation Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
US7224056B2 (en) * 2003-09-26 2007-05-29 Tessera, Inc. Back-face and edge interconnects for lidded package
US7265440B2 (en) * 2003-06-16 2007-09-04 Tessera Technologies Hungary Kft. Methods and apparatus for packaging integrated circuit devices
US7268438B2 (en) * 2002-02-07 2007-09-11 Nec Corporation Semiconductor element including a wet prevention film
US7314819B2 (en) * 2005-06-30 2008-01-01 Intel Corporation Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same
US7335536B2 (en) * 2005-09-01 2008-02-26 Texas Instruments Incorporated Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices
US20080111236A1 (en) * 2001-09-17 2008-05-15 Megica Corporation Low fabrication cost, high performance, high reliability chip scale package
US7479690B2 (en) * 2005-07-22 2009-01-20 Oki Electric Industry Co., Ltd. Semiconductor device
US7479398B2 (en) * 2003-07-03 2009-01-20 Tessera Technologies Hungary Kft. Methods and apparatus for packaging integrated circuit devices

Family Cites Families (166)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4179802A (en) 1978-03-27 1979-12-25 International Business Machines Corporation Studded chip attachment process
JPS60217646A (en) 1984-04-13 1985-10-31 Toshiba Corp Manufacture of bump electrode type semiconductor device
JPS62160744U (en) 1986-03-31 1987-10-13
JPH0322437Y2 (en) 1986-12-27 1991-05-16
US4880708A (en) 1988-07-05 1989-11-14 Motorola, Inc. Metallization scheme providing adhesion and barrier properties
JP2785338B2 (en) 1989-06-19 1998-08-13 日本電気株式会社 Method for manufacturing semiconductor device
US5071518A (en) 1989-10-24 1991-12-10 Microelectronics And Computer Technology Corporation Method of making an electrical multilayer interconnect
US5261155A (en) 1991-08-12 1993-11-16 International Business Machines Corporation Method for bonding flexible circuit to circuitized substrate to provide electrical connection therebetween using different solders
US5239447A (en) 1991-09-13 1993-08-24 International Business Machines Corporation Stepped electronic device package
US5326709A (en) 1991-12-19 1994-07-05 Samsung Electronics Co., Ltd. Wafer testing process of a semiconductor device comprising a redundancy circuit
US5268072A (en) 1992-08-31 1993-12-07 International Business Machines Corporation Etching processes for avoiding edge stress in semiconductor chip solder bumps
EP0595021A1 (en) 1992-10-28 1994-05-04 International Business Machines Corporation Improved lead frame package for electronic devices
US5535101A (en) * 1992-11-03 1996-07-09 Motorola, Inc. Leadless integrated circuit package
US5300461A (en) 1993-01-25 1994-04-05 Intel Corporation Process for fabricating sealed semiconductor chip using silicon nitride passivation film
JP3258740B2 (en) 1993-01-29 2002-02-18 三菱電機株式会社 Method for manufacturing semiconductor device having bump electrode
KR950004464A (en) 1993-07-15 1995-02-18 김광호 Manufacturing method of chip bump
JP3361881B2 (en) 1994-04-28 2003-01-07 株式会社東芝 Semiconductor device and manufacturing method thereof
US5503286A (en) 1994-06-28 1996-04-02 International Business Machines Corporation Electroplated solder terminal
US5554940A (en) 1994-07-05 1996-09-10 Motorola, Inc. Bumped semiconductor device and method for probing the same
JPH0837190A (en) 1994-07-22 1996-02-06 Nec Corp Semiconductor device
US5656858A (en) 1994-10-19 1997-08-12 Nippondenso Co., Ltd. Semiconductor device with bump structure
US5468984A (en) 1994-11-02 1995-11-21 Texas Instruments Incorporated ESD protection structure using LDMOS diodes with thick copper interconnect
US5534465A (en) 1995-01-10 1996-07-09 At&T Corp. Method for making multichip circuits using active semiconductor substrates
US5654979A (en) * 1995-01-13 1997-08-05 Qualcomm Incorporated Cell site demodulation architecture for a spread spectrum multiple access communication systems
JPH08213422A (en) 1995-02-07 1996-08-20 Mitsubishi Electric Corp Semiconductor device and bonding pad structure thereof
US5547740A (en) * 1995-03-23 1996-08-20 Delco Electronics Corporation Solderable contacts for flip chip integrated circuit devices
US5545927A (en) 1995-05-12 1996-08-13 International Business Machines Corporation Capped copper electrical interconnects
JPH0997791A (en) 1995-09-27 1997-04-08 Internatl Business Mach Corp <Ibm> Bump structure, formation of bump and installation connection body
KR100327442B1 (en) 1995-07-14 2002-06-29 구본준, 론 위라하디락사 Bump structure of semiconductor device and fabricating method thereof
US5874781A (en) 1995-08-16 1999-02-23 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US5751015A (en) * 1995-11-17 1998-05-12 Micron Technology, Inc. Semiconductor reliability test chip
US5726502A (en) 1996-04-26 1998-03-10 Motorola, Inc. Bumped semiconductor device with alignment features and method for making the same
US5949654A (en) * 1996-07-03 1999-09-07 Kabushiki Kaisha Toshiba Multi-chip module, an electronic device, and production method thereof
US5883435A (en) 1996-07-25 1999-03-16 International Business Machines Corporation Personalization structure for semiconductor devices
KR100213209B1 (en) 1996-07-29 1999-08-02 윤종용 Manufacturing method of semiconductor devices
US5664642A (en) 1996-08-26 1997-09-09 Williams; Bernard Fire evacuation kit
US5866949A (en) 1996-12-02 1999-02-02 Minnesota Mining And Manufacturing Company Chip scale ball grid array for integrated circuit packaging
US5946590A (en) 1996-12-10 1999-08-31 Citizen Watch Co., Ltd. Method for making bumps
JPH10190528A (en) * 1996-12-25 1998-07-21 Matsushita Electric Ind Co Ltd Spread spectrum receiver
TW448524B (en) 1997-01-17 2001-08-01 Seiko Epson Corp Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment
JP3587019B2 (en) 1997-04-08 2004-11-10 ソニー株式会社 Method for manufacturing semiconductor device
TW397933B (en) 1997-05-09 2000-07-11 Ind Tech Res Inst Surface screen print
JP3611948B2 (en) 1997-05-16 2005-01-19 日本テキサス・インスツルメンツ株式会社 Semiconductor device and manufacturing method thereof
US6028363A (en) 1997-06-04 2000-02-22 Taiwan Semiconductor Manufacturing Company Vertical via/contact
US6144100A (en) 1997-06-05 2000-11-07 Texas Instruments Incorporated Integrated circuit with bonding layer over active circuitry
KR100253116B1 (en) 1997-07-07 2000-04-15 윤덕용 Method of manufacturing chip size package using the method
US6002589A (en) 1997-07-21 1999-12-14 Rambus Inc. Integrated circuit package for coupling to a printed circuit board
US6144390A (en) 1997-08-04 2000-11-07 Lucent Technologies Inc. Display composition technique
US6441487B2 (en) 1997-10-20 2002-08-27 Flip Chip Technologies, L.L.C. Chip scale package using large ductile solder balls
US6162562A (en) 1997-10-28 2000-12-19 Pioneer Electronic Corporation Secondary cell comprising a positive electrode containing polyaniline and 4 diazo compound
JPH11219984A (en) 1997-11-06 1999-08-10 Sharp Corp Semiconductor device package, its manufacture and circuit board therefor
US5903343A (en) 1997-12-23 1999-05-11 Siemens Aktiengesellschaft Method for detecting under-etched vias
US6162652A (en) 1997-12-31 2000-12-19 Intel Corporation Process for sort testing C4 bumped wafers
US6107180A (en) 1998-01-30 2000-08-22 Motorola, Inc. Method for forming interconnect bumps on a semiconductor die
US5977632A (en) * 1998-02-02 1999-11-02 Motorola, Inc. Flip chip bump structure and method of making
US6057169A (en) 1998-04-17 2000-05-02 Lsi Logic Corporation Method for I/O device layout during integrated circuit design
JPH11307389A (en) 1998-04-24 1999-11-05 Mitsubishi Electric Corp Pattern capacitor
SG75841A1 (en) 1998-05-02 2000-10-24 Eriston Invest Pte Ltd Flip chip assembly with via interconnection
US5985765A (en) 1998-05-11 1999-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing bonding pad loss using a capping layer when etching bonding pad passivation openings
US5943597A (en) 1998-06-15 1999-08-24 Motorola, Inc. Bumped semiconductor device having a trench for stress relief
US5977640A (en) 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
TW396419B (en) 1998-06-30 2000-07-01 Tsmc Acer Semiconductor Mfg Co A method of manufacturing resistors with high ESD resistance and salicide CMOS transistor
JP3420703B2 (en) 1998-07-16 2003-06-30 株式会社東芝 Method for manufacturing semiconductor device
US6077726A (en) 1998-07-30 2000-06-20 Motorola, Inc. Method and apparatus for stress relief in solder bump formation on a semiconductor device
KR100268427B1 (en) 1998-08-10 2000-10-16 윤종용 Method for forming of contact of semiconductor device
US6103552A (en) * 1998-08-10 2000-08-15 Lin; Mou-Shiung Wafer scale packaging scheme
US6998711B1 (en) 1998-08-14 2006-02-14 Micron Technology, Inc. Method of forming a micro solder ball for use in C4 bonding process
JP3420076B2 (en) 1998-08-31 2003-06-23 新光電気工業株式会社 Method for manufacturing flip-chip mounting board, flip-chip mounting board, and flip-chip mounting structure
US6187680B1 (en) 1998-10-07 2001-02-13 International Business Machines Corporation Method/structure for creating aluminum wirebound pad on copper BEOL
US6477200B1 (en) * 1998-11-09 2002-11-05 Broadcom Corporation Multi-pair gigabit ethernet transceiver
US6249544B1 (en) * 1998-11-13 2001-06-19 Broadcom Corporation System and method for high-speed decoding and ISI compensation in a multi-pair transceiver system
SG93278A1 (en) 1998-12-21 2002-12-17 Mou Shiung Lin Top layers of metal for high performance ics
US6383916B1 (en) 1998-12-21 2002-05-07 M. S. Lin Top layers of metal for high performance IC's
US6479900B1 (en) * 1998-12-22 2002-11-12 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
JP2000260803A (en) 1999-01-05 2000-09-22 Citizen Watch Co Ltd Semiconductor device and manufacture thereof
AU2512300A (en) * 1999-01-20 2000-08-07 Broadcom Corporation Trellis decoder with correction of pair swaps, for use in gigabit ethernet transceivers
KR100687548B1 (en) 1999-01-27 2007-02-27 신꼬오덴기 고교 가부시키가이샤 Semiconductor wafer and semiconductor device provided with columnar electrodes and methods of producing the wafer and device
JP3483490B2 (en) 1999-02-16 2004-01-06 シャープ株式会社 Method for manufacturing semiconductor device
US6707159B1 (en) 1999-02-18 2004-03-16 Rohm Co., Ltd. Semiconductor chip and production process therefor
US6197613B1 (en) 1999-03-23 2001-03-06 Industrial Technology Research Institute Wafer level packaging method and devices formed
TW418470B (en) 1999-03-30 2001-01-11 Ind Tech Res Inst Method for forming solder bumps on flip chips and devices formed
US6271107B1 (en) 1999-03-31 2001-08-07 Fujitsu Limited Semiconductor with polymeric layer
US6332988B1 (en) 1999-06-02 2001-12-25 International Business Machines Corporation Rework process
US6181569B1 (en) 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6166444A (en) 1999-06-21 2000-12-26 United Microelectronics Corp. Cascade-type chip module
KR100301064B1 (en) 1999-08-06 2001-11-01 윤종용 method for manufacturing cylinder-type storage electrode of semiconductor device
SG87046A1 (en) 1999-08-17 2002-03-19 Micron Technology Inc Multi-chip module with stacked dice
US6709985B1 (en) 1999-08-26 2004-03-23 Advanced Micro Devices, Inc. Arrangement and method for providing an imaging path using a silicon-crystal damaging laser
TW419764B (en) 1999-09-03 2001-01-21 Ind Tech Res Inst Manufacturing method and structure of wafer size packaging
TW419765B (en) 1999-09-30 2001-01-21 Taiwan Semiconductor Mfg Manufacturing method of flip chip solder bumps
US6372622B1 (en) 1999-10-26 2002-04-16 Motorola, Inc. Fine pitch bumping with improved device standoff and bump volume
JP3287346B2 (en) 1999-11-29 2002-06-04 カシオ計算機株式会社 Semiconductor device
TW434857B (en) 1999-12-01 2001-05-16 Huang Jr Gung Chip scale package
US6331227B1 (en) 1999-12-14 2001-12-18 Epion Corporation Enhanced etching/smoothing of dielectric surfaces
KR20010064907A (en) 1999-12-20 2001-07-11 마이클 디. 오브라이언 wire bonding method and semiconductor package using it
KR100386081B1 (en) 2000-01-05 2003-06-09 주식회사 하이닉스반도체 Semiconductor package and fabricating method thereof
US6369448B1 (en) 2000-01-21 2002-04-09 Lsi Logic Corporation Vertically integrated flip chip semiconductor package
JP3768761B2 (en) 2000-01-31 2006-04-19 株式会社日立製作所 Semiconductor device and manufacturing method thereof
JP3772066B2 (en) 2000-03-09 2006-05-10 沖電気工業株式会社 Semiconductor device
US6806578B2 (en) * 2000-03-16 2004-10-19 International Business Machines Corporation Copper pad structure
JP3548082B2 (en) 2000-03-30 2004-07-28 三洋電機株式会社 Semiconductor device and manufacturing method thereof
JP3535804B2 (en) * 2000-04-28 2004-06-07 Necマイクロシステム株式会社 Method for designing flip-chip type semiconductor device
JP3968554B2 (en) * 2000-05-01 2007-08-29 セイコーエプソン株式会社 Bump forming method and semiconductor device manufacturing method
US6362087B1 (en) * 2000-05-05 2002-03-26 Aptos Corporation Method for fabricating a microelectronic fabrication having formed therein a redistribution structure
JP2002016096A (en) 2000-06-27 2002-01-18 Citizen Watch Co Ltd Semiconductor device and its manufacturing method
US7034402B1 (en) 2000-06-28 2006-04-25 Intel Corporation Device with segmented ball limiting metallurgy
US6521996B1 (en) 2000-06-30 2003-02-18 Intel Corporation Ball limiting metallurgy for input/outputs and methods of fabrication
TW464927B (en) 2000-08-29 2001-11-21 Unipac Optoelectronics Corp Metal bump with an insulating sidewall and method of fabricating thereof
TW452950B (en) 2000-09-19 2001-09-01 Siliconware Precision Industries Co Ltd Packaging structure of bonding pad with increased space height
TW449813B (en) 2000-10-13 2001-08-11 Advanced Semiconductor Eng Semiconductor device with bump electrode
JP2002198374A (en) 2000-10-16 2002-07-12 Sharp Corp Semiconductor device and its fabrication method
WO2002039629A2 (en) * 2000-10-31 2002-05-16 Igor Anatolievich Abrosimov Channel time calibration means
US6462426B1 (en) 2000-12-14 2002-10-08 National Semiconductor Corporation Barrier pad for wafer level chip scale packages
TW577152B (en) 2000-12-18 2004-02-21 Hitachi Ltd Semiconductor integrated circuit device
US6319846B1 (en) 2001-01-05 2001-11-20 Taiwan Semiconductor Manufacturing Company, Ltd Method for removing solder bodies from a semiconductor wafer
US6426556B1 (en) 2001-01-16 2002-07-30 Megic Corporation Reliable metal bumps on top of I/O pads with test probe marks
JP2002222823A (en) 2001-01-29 2002-08-09 Sharp Corp Semiconductor integrated device and its manufacturing method
US6518089B2 (en) * 2001-02-02 2003-02-11 Texas Instruments Incorporated Flip chip semiconductor device in a molded chip scale package (CSP) and method of assembly
US6815324B2 (en) 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US6495397B2 (en) 2001-03-28 2002-12-17 Intel Corporation Fluxless flip chip interconnection
US6653563B2 (en) 2001-03-30 2003-11-25 Intel Corporation Alternate bump metallurgy bars for power and ground routing
US6555296B2 (en) * 2001-04-04 2003-04-29 Siliconware Precision Industries Co., Ltd. Fine pitch wafer bumping process
JP4092890B2 (en) 2001-05-31 2008-05-28 株式会社日立製作所 Multi-chip module
KR100456064B1 (en) 2001-07-06 2004-11-08 한국과학기술원 Anisotropic conductive film for ultra-fine pitch COG application
US20030006062A1 (en) 2001-07-06 2003-01-09 Stone William M. Interconnect system and method of fabrication
US20030020163A1 (en) 2001-07-25 2003-01-30 Cheng-Yu Hung Bonding pad structure for copper/low-k dielectric material BEOL process
US6372619B1 (en) 2001-07-30 2002-04-16 Taiwan Semiconductor Manufacturing Company, Ltd Method for fabricating wafer level chip scale package with discrete package encapsulation
US6734568B2 (en) 2001-08-29 2004-05-11 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6762122B2 (en) 2001-09-27 2004-07-13 Unitivie International Limited Methods of forming metallurgy structures for wire and solder bonding
JP3850261B2 (en) 2001-10-25 2006-11-29 イビデン株式会社 Semiconductor chip
EP1306898A1 (en) 2001-10-29 2003-05-02 Dialog Semiconductor GmbH Sub-milliohm on-chip interconnection
US7245686B2 (en) * 2001-12-17 2007-07-17 Mysticom Ltd. Fast skew detector
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US6774475B2 (en) 2002-01-24 2004-08-10 International Business Machines Corporation Vertically stacked memory chips in FBGA packages
US6541847B1 (en) 2002-02-04 2003-04-01 International Business Machines Corporation Packaging for multi-processor shared-memory system
JP3759909B2 (en) 2002-02-22 2006-03-29 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
JP3603890B2 (en) 2002-03-06 2004-12-22 セイコーエプソン株式会社 Electronic device, method of manufacturing the same, and electronic apparatus
JP3856304B2 (en) 2002-03-25 2006-12-13 株式会社リコー Resistance element in CSP and semiconductor device having CSP
US6617655B1 (en) 2002-04-05 2003-09-09 Fairchild Semiconductor Corporation MOSFET device with multiple gate contacts offset from gate contact area and over source area
US20030218246A1 (en) 2002-05-22 2003-11-27 Hirofumi Abe Semiconductor device passing large electric current
US20040007779A1 (en) 2002-07-15 2004-01-15 Diane Arbuthnot Wafer-level method for fine-pitch, high aspect ratio chip interconnect
US6661100B1 (en) 2002-07-30 2003-12-09 International Business Machines Corporation Low impedance power distribution structure for a semiconductor chip package
JP2004140037A (en) 2002-10-15 2004-05-13 Oki Electric Ind Co Ltd Semiconductor device and its manufacturing process
US7373561B2 (en) 2002-10-29 2008-05-13 Broadcom Corporation Integrated packet bit error rate tester for 10G SERDES
TW578292B (en) 2002-11-22 2004-03-01 Via Tech Inc Chip to eliminate noise and manufacturing method thereof
JP3969295B2 (en) 2002-12-02 2007-09-05 セイコーエプソン株式会社 SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, CIRCUIT BOARD, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC DEVICE
JPWO2004077556A1 (en) * 2003-02-26 2006-06-08 三洋電機株式会社 Semiconductor integrated circuit device and power supply wiring method thereof
JP4318935B2 (en) 2003-03-05 2009-08-26 綜研化学株式会社 Manufacturing method of color display member and reflective color image display device using the manufacturing method
US7203916B2 (en) * 2003-06-24 2007-04-10 International Business Machines Corporation System, method and program product for positioning I/O pads on a chip
US6977435B2 (en) * 2003-09-09 2005-12-20 Intel Corporation Thick metal layer integrated process flow to improve power delivery and mechanical buffering
US6864165B1 (en) 2003-09-15 2005-03-08 International Business Machines Corporation Method of fabricating integrated electronic chip with an interconnect device
US20050113503A1 (en) * 2003-10-03 2005-05-26 Zumbrunnen David A. Composites with oriented particles and particle networks with method
US7462942B2 (en) 2003-10-09 2008-12-09 Advanpack Solutions Pte Ltd Die pillar structures and a method of their formation
US7603641B2 (en) 2003-11-02 2009-10-13 Mentor Graphics Corporation Power/ground wire routing correction and optimization
EP1536469A1 (en) 2003-11-28 2005-06-01 EM Microelectronic-Marin SA Semiconductor device with connecting bumps
JP4278543B2 (en) 2004-03-19 2009-06-17 マルホン工業株式会社 Game machine
JP4119866B2 (en) 2004-05-12 2008-07-16 富士通株式会社 Semiconductor device
JP2006128662A (en) 2004-09-30 2006-05-18 Taiyo Yuden Co Ltd Semiconductor and its mounting body
JP2006147810A (en) 2004-11-19 2006-06-08 Casio Comput Co Ltd Semiconductor device and method of manufacturing the same
US7135766B1 (en) 2004-11-30 2006-11-14 Rf Micro Devices, Inc. Integrated power devices and signal isolation structure
US7119002B2 (en) * 2004-12-14 2006-10-10 Taiwan Semiconductor Manufacturing Co., Ltd. Solder bump composition for flip chip
US7084660B1 (en) 2005-04-04 2006-08-01 International Business Machines Corporation System and method for accelerated detection of transient particle induced soft error rates in integrated circuits
US7505284B2 (en) 2005-05-12 2009-03-17 International Business Machines Corporation System for assembling electronic components of an electronic system
JP4221606B2 (en) 2005-06-28 2009-02-12 セイコーエプソン株式会社 Manufacturing method of semiconductor device
US7074050B1 (en) 2005-11-17 2006-07-11 International Business Machines Corporation Socket assembly with incorporated memory structure
US20080284037A1 (en) 2007-05-15 2008-11-20 Andry Paul S Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3668484A (en) * 1970-10-28 1972-06-06 Rca Corp Semiconductor device with multi-level metalization and method of making the same
US4087314A (en) * 1976-09-13 1978-05-02 Motorola, Inc. Bonding pedestals for semiconductor devices
US4652336A (en) * 1984-09-20 1987-03-24 Siemens Aktiengesellschaft Method of producing copper platforms for integrated circuits
US4825276A (en) * 1986-06-19 1989-04-25 Nec Corporation Integrated circuit semiconductor device having improved wiring structure
US4726991A (en) * 1986-07-10 1988-02-23 Eos Technologies Inc. Electrical overstress protection material and process
US5134460A (en) * 1986-08-11 1992-07-28 International Business Machines Corporation Aluminum bump, reworkable bump, and titanium nitride structure for tab bonding
US4811237A (en) * 1987-06-19 1989-03-07 General Electric Company Structured design method for generating a mesh power bus structure in high density layout of VLSI chips
US5108950A (en) * 1987-11-18 1992-04-28 Casio Computer Co., Ltd. Method for forming a bump electrode for a semiconductor device
US5132775A (en) * 1987-12-11 1992-07-21 Texas Instruments Incorporated Methods for and products having self-aligned conductive pillars on interconnects
US5223454A (en) * 1988-01-29 1993-06-29 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit device
US5046161A (en) * 1988-02-23 1991-09-03 Nec Corporation Flip chip type semiconductor device
US5061985A (en) * 1988-06-13 1991-10-29 Hitachi, Ltd. Semiconductor integrated circuit device and process for producing the same
US5244833A (en) * 1989-07-26 1993-09-14 International Business Machines Corporation Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer
US5083187A (en) * 1990-05-16 1992-01-21 Texas Instruments Incorporated Integrated circuit device having bumped power supply buses over active surface areas and method of manufacture thereof
US5226232A (en) * 1990-05-18 1993-07-13 Hewlett-Packard Company Method for forming a conductive pattern on an integrated circuit
US5137845A (en) * 1990-07-31 1992-08-11 International Business Machines Corporation Method of forming metal contact pads and terminals on semiconductor chips
US5656863A (en) * 1993-02-18 1997-08-12 Mitsubishi Denki Kabushiki Kaisha Resin seal semiconductor package
US5598348A (en) * 1994-09-22 1997-01-28 Sun Microsystems, Inc. Method and apparatus for analyzing the power network of a VLSI circuit
US5892273A (en) * 1994-10-03 1999-04-06 Kabushiki Kaisha Toshiba Semiconductor package integral with semiconductor chip
US5767010A (en) * 1995-03-20 1998-06-16 Mcnc Solder bump fabrication methods and structure including a titanium barrier layer
US6311147B1 (en) * 1995-04-17 2001-10-30 Synopsys, Inc. Integrated circuit power net analysis
US5541135A (en) * 1995-05-30 1996-07-30 Motorola, Inc. Method of fabricating a flip chip semiconductor device having an inductor
US5757074A (en) * 1995-07-07 1998-05-26 Hughes Electronics Corporation Microwave/millimeter wave circuit structure with discrete flip-chip mounted elements
US5629241A (en) * 1995-07-07 1997-05-13 Hughes Aircraft Company Microwave/millimeter wave circuit structure with discrete flip-chip mounted elements, and method of fabricating the same
US5756370A (en) * 1996-02-08 1998-05-26 Micron Technology, Inc. Compliant contact system with alignment structure for testing unpackaged semiconductor dice
US6042953A (en) * 1996-03-21 2000-03-28 Matsushita Electric Industrial Co., Ltd. Substrate on which bumps are formed and method of forming the same
US5808900A (en) * 1996-04-30 1998-09-15 Lsi Logic Corporation Memory having direct strap connection to power supply
US6093964A (en) * 1996-06-27 2000-07-25 International Business Machines Corporation Connection structure utilizing a metal bump and metal bump manufacturing method
US5882957A (en) * 1997-06-09 1999-03-16 Compeq Manufacturing Company Limited Ball grid array packaging method for an integrated circuit and structure realized by the method
US6013571A (en) * 1997-06-16 2000-01-11 Motorola, Inc. Microelectronic assembly including columnar interconnections and method for forming same
US6250541B1 (en) * 1997-06-23 2001-06-26 Visteon Global Technologies, Inc. Method of forming interconnections on electronic modules
US6180265B1 (en) * 1997-06-27 2001-01-30 Delco Electronics Corporation Flip chip solder bump pad
US6051450A (en) * 1997-07-01 2000-04-18 Sony Corporation Lead frame, manufacturing method of a lead frame, semiconductor device, assembling method of a semiconductor device, and electronic apparatus
US5933358A (en) * 1997-09-30 1999-08-03 Synopsys, Inc. Method and system of performing voltage drop analysis for power supply networks of VLSI circuits
US6015505A (en) * 1997-10-30 2000-01-18 International Business Machines Corporation Process improvements for titanium-tungsten etching in the presence of electroplated C4's
US6177731B1 (en) * 1998-01-19 2001-01-23 Citizen Watch Co., Ltd. Semiconductor package
US20020013931A1 (en) * 1998-01-29 2002-01-31 Cano Francisco A. Method for power routing and distribution in an integrated circuit with multiple interconnect layers
US6308307B1 (en) * 1998-01-29 2001-10-23 Texas Instruments Incorporated Method for power routing and distribution in an integrated circuit with multiple interconnect layers
US6202196B1 (en) * 1998-02-03 2001-03-13 Lsi Logic Corporation Method for optimizing routing mesh segment width
US6075290A (en) * 1998-02-26 2000-06-13 National Semiconductor Corporation Surface mount die: wafer level chip-scale package and process for making the same
US6414390B2 (en) * 1998-03-27 2002-07-02 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board and electronic instrument
US7338890B2 (en) * 1998-03-31 2008-03-04 Megica Corporation Low fabrication cost, high performance, high reliability chip scale package
US5937320A (en) * 1998-04-08 1999-08-10 International Business Machines Corporation Barrier layers for electroplated SnPb eutectic solder joints
US6043672A (en) * 1998-05-13 2000-03-28 Lsi Logic Corporation Selectable power supply lines for isolating defects in integrated circuits
US6268662B1 (en) * 1998-10-14 2001-07-31 Texas Instruments Incorporated Wire bonded flip-chip assembly of semiconductor devices
US6380061B1 (en) * 1998-12-17 2002-04-30 Shinko Electric Industries Co., Ltd. Process for fabricating bump electrode
US6198169B1 (en) * 1998-12-17 2001-03-06 Shinko Electric Industries Co., Ltd. Semiconductor device and process for producing same
US6600234B2 (en) * 1999-02-03 2003-07-29 Casio Computer Co., Ltd. Mounting structure having columnar electrodes and a sealing film
US6675139B1 (en) * 1999-03-16 2004-01-06 Lsi Logic Corporation Floor plan-based power bus analysis and design tool for integrated circuits
US6573598B2 (en) * 1999-04-06 2003-06-03 Oki Electric Industry Co, Ltd. Semiconductor device and method of fabricating the same
US6202191B1 (en) * 1999-06-15 2001-03-13 International Business Machines Corporation Electromigration resistant power distribution network
US6510539B1 (en) * 1999-10-29 2003-01-21 International Business Machines Corporation System and method for physically modeling electronic modules wiring
US6467674B1 (en) * 1999-12-09 2002-10-22 Casio Computer Co., Ltd. Method of manufacturing semiconductor device having sealing film on its surface
US6446245B1 (en) * 2000-01-05 2002-09-03 Sun Microsystems, Inc. Method and apparatus for performing power routing in ASIC design
US20010026021A1 (en) * 2000-02-21 2001-10-04 Hirokazu Honda Flip-chip type semiconductor device and method of manufacturing the same
US6627988B2 (en) * 2000-04-06 2003-09-30 Oki Electric Industry Co, Ltd. Semiconductor device and method for manufacturing the same
US6429531B1 (en) * 2000-04-18 2002-08-06 Motorola, Inc. Method and apparatus for manufacturing an interconnect structure
US6592019B2 (en) * 2000-04-27 2003-07-15 Advanpack Solutions Pte. Ltd Pillar connections for semiconductor chips and method of manufacture
US6578754B1 (en) * 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6405357B1 (en) * 2000-05-02 2002-06-11 Advanced Semiconductor Engineering, Inc. Method for positioning bond pads in a semiconductor die
US6683380B2 (en) * 2000-07-07 2004-01-27 Texas Instruments Incorporated Integrated circuit with bonding layer over active circuitry
US6518092B2 (en) * 2000-07-13 2003-02-11 Oki Electric Industry Co., Ltd. Semiconductor device and method for manufacturing
US6258705B1 (en) * 2000-08-21 2001-07-10 Siliconeware Precision Industries Co., Ltd. Method of forming circuit probing contact points on fine pitch peripheral bond pads on flip chip
US6348401B1 (en) * 2000-11-10 2002-02-19 Siliconware Precision Industries Co., Ltd. Method of fabricating solder bumps with high coplanarity for flip-chip application
US6523154B2 (en) * 2000-12-14 2003-02-18 International Business Machines Corporation Method for supply voltage drop analysis during placement phase of chip design
US20020121709A1 (en) * 2000-12-28 2002-09-05 Fujitsu Limited External connection terminal and semiconductor device
US6426281B1 (en) * 2001-01-16 2002-07-30 Taiwan Semiconductor Manufacturing Company Method to form bump in bumping technology
US6861742B2 (en) * 2001-01-18 2005-03-01 Renesas Technology Corp. Wafer level chip size package having rerouting layers
US6732913B2 (en) * 2001-04-26 2004-05-11 Advanpack Solutions Pte Ltd. Method for forming a wafer level chip scale package, and package formed thereby
US6598206B2 (en) * 2001-05-10 2003-07-22 International Business Machines Corporation Method and system of modifying integrated circuit power rails
US20080111236A1 (en) * 2001-09-17 2008-05-15 Megica Corporation Low fabrication cost, high performance, high reliability chip scale package
US7355288B2 (en) * 2001-09-17 2008-04-08 Megica Corporation Low fabrication cost, high performance, high reliability chip scale package
US20080099928A1 (en) * 2001-09-17 2008-05-01 Megica Corporation Low fabrication cost, high performance, high reliability chip scale package
US6917119B2 (en) * 2001-09-17 2005-07-12 Megic Corporation Low fabrication cost, high performance, high reliability chip scale package
US7196001B2 (en) * 2001-09-21 2007-03-27 Intel Corporation Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
US20030140327A1 (en) * 2001-12-18 2003-07-24 Glenn Lai Method of designing power vias in an IC layout
US7268438B2 (en) * 2002-02-07 2007-09-11 Nec Corporation Semiconductor element including a wet prevention film
US6731003B2 (en) * 2002-03-12 2004-05-04 Fairchild Semiconductor Corporation Wafer-level coated copper stud bumps
US20080113504A1 (en) * 2002-05-01 2008-05-15 Megica Corporation Low fabrication cost, high performance, high reliability chip scale package
US6940169B2 (en) * 2002-05-21 2005-09-06 Stats Chippac Ltd. Torch bump
US20060095872A1 (en) * 2002-07-29 2006-05-04 Mcelvain Kenneth S Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
US20040080630A1 (en) * 2002-10-10 2004-04-29 Hynix Semiconductor Inc. Pixel array, image sensor having the pixel array and method for removing flicker noise of the image sensor
US6917106B2 (en) * 2002-10-24 2005-07-12 Intel Corporation Selective ball-limiting metallurgy etching processes for fabrication of electroplated tin bumps
US7111265B1 (en) * 2002-12-23 2006-09-19 Altera Corporation I/O pin placement for a programmable logic device
US20040163054A1 (en) * 2003-02-19 2004-08-19 Frank Mark D. System and method for evaluating vias per pad in a package design
US7008867B2 (en) * 2003-02-21 2006-03-07 Aptos Corporation Method for forming copper bump antioxidation surface
US7265440B2 (en) * 2003-06-16 2007-09-04 Tessera Technologies Hungary Kft. Methods and apparatus for packaging integrated circuit devices
US6991961B2 (en) * 2003-06-18 2006-01-31 Medtronic, Inc. Method of forming a high-voltage/high-power die package
US7479398B2 (en) * 2003-07-03 2009-01-20 Tessera Technologies Hungary Kft. Methods and apparatus for packaging integrated circuit devices
US7495341B2 (en) * 2003-07-03 2009-02-24 Tessera Technologies Hungary Kft. Methods and apparatus for packaging integrated circuit devices
US20050090916A1 (en) * 2003-08-25 2005-04-28 Majid Aghababazadeh Intra-chip power and test signal generation for use with test structures on wafers
US20050050502A1 (en) * 2003-08-27 2005-03-03 Fujitsu Limited Method and apparatus for designing semiconductor integrated circuit
US7224056B2 (en) * 2003-09-26 2007-05-29 Tessera, Inc. Back-face and edge interconnects for lidded package
US6998710B2 (en) * 2003-12-24 2006-02-14 Fujitsu Limited High-frequency device
US7043389B2 (en) * 2004-02-18 2006-05-09 James Francis Plusquellic Method and system for identifying and locating defects in an integrated circuit
US7095105B2 (en) * 2004-03-23 2006-08-22 Texas Instruments Incorporated Vertically stacked semiconductor device
US7314819B2 (en) * 2005-06-30 2008-01-01 Intel Corporation Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same
US7479690B2 (en) * 2005-07-22 2009-01-20 Oki Electric Industry Co., Ltd. Semiconductor device
US7335536B2 (en) * 2005-09-01 2008-02-26 Texas Instruments Incorporated Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9369175B2 (en) 2001-09-17 2016-06-14 Qualcomm Incorporated Low fabrication cost, high performance, high reliability chip scale package
US20080308929A1 (en) * 2007-06-13 2008-12-18 Himax Technologies Limited Semiconductor device, chip package and method of fabricating the same
US7858438B2 (en) * 2007-06-13 2010-12-28 Himax Technologies Limited Semiconductor device, chip package and method of fabricating the same

Also Published As

Publication number Publication date
US9369175B2 (en) 2016-06-14
EP1359682A2 (en) 2003-11-05
US8481418B2 (en) 2013-07-09
US7099293B2 (en) 2006-08-29
EP1359682A3 (en) 2005-02-09
US20080111236A1 (en) 2008-05-15
JP2004007636A (en) 2004-01-08
US20030206560A1 (en) 2003-11-06
US20090137110A9 (en) 2009-05-28
US20080113504A1 (en) 2008-05-15

Similar Documents

Publication Publication Date Title
US7338890B2 (en) Low fabrication cost, high performance, high reliability chip scale package
US8481418B2 (en) Low fabrication cost, high performance, high reliability chip scale package
US8258055B2 (en) Method of forming semiconductor die
US6426556B1 (en) Reliable metal bumps on top of I/O pads with test probe marks
US6936923B2 (en) Method to form very a fine pitch solder bump using methods of electroplating
CN102157473B (en) Semiconductor device and manufacturing method thereof
US6756294B1 (en) Method for improving bump reliability for flip chip devices
TWI594385B (en) Semiconductor devices and fabrication method thereof
US8405199B2 (en) Conductive pillar for semiconductor substrate and method of manufacture
US6818545B2 (en) Low fabrication cost, fine pitch and high reliability solder bump
US6593220B1 (en) Elastomer plating mask sealed wafer level package method
US20060211233A1 (en) Method for fabricating a wafer level package having through wafer vias for external package connectivity and related structure
US20070120251A1 (en) Semiconductor wafer, semiconductor device and method of manufacturing the same, circuit board, and electronic equipment
JP2004048012A (en) Fin pitch and high aspect ratio wiring structure and interconnection method for the same
KR20070096016A (en) Interconnect structures with bond-pads and methods of forming bump sites on bond-pads
JP2001110831A (en) External connecting protrusion and its forming method, semiconductor chip, circuit board and electronic equipment
US7271095B2 (en) Process for producing metallic interconnects and contact surfaces on electronic components
KR19990063359A (en) Dual Damask Processes with Bonding Pads
US6479376B1 (en) Process improvement for the creation of aluminum contact bumps
US8377816B2 (en) Method of forming electrical connections
JP2006332694A (en) Method for forming metal bumps on semiconductor surface
CN115627508A (en) Manufacturing process and application thereof
CN117219601A (en) Rewiring layer, packaging structure and corresponding preparation method
KR100592783B1 (en) Method for manufacturing wafer level chip scale package
KR20100053828A (en) Methods of manufacturing a bump with improved the performance of connection between bonding pad metal

Legal Events

Date Code Title Description
AS Assignment

Owner name: MEGICA CORPORATION, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, JIN-YUAN;LEI, MING-TA;HUANG, CHING-CHENG;AND OTHERS;REEL/FRAME:020126/0026

Effective date: 20010801

STCF Information on status: patent grant

Free format text: PATENTED CASE

AS Assignment

Owner name: MEGIC CORPORATION, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, JIN-YUAN;LEI, MING-TA;HUANG, CHING-CHENG;AND OTHERS;REEL/FRAME:030764/0496

Effective date: 20010801

Owner name: MEGICA CORPORATION, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MEGICA CORPORATION;REEL/FRAME:030770/0876

Effective date: 20060428

AS Assignment

Owner name: MEGICA CORPORATION, TAIWAN

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY NAME NEEDS TO CHANGE FROM MEGICA TO MEGIC PREVIOUSLY RECORDED ON REEL 030770 FRAME 0876. ASSIGNOR(S) HEREBY CONFIRMS THE MEGIC CORPORATION TO MEGICA CORPORATION;ASSIGNOR:MEGIC CORPORATION;REEL/FRAME:030997/0336

Effective date: 20060428

AS Assignment

Owner name: MEGIT ACQUISITION CORP., CALIFORNIA

Free format text: MERGER;ASSIGNOR:MEGICA CORPORATION;REEL/FRAME:031283/0198

Effective date: 20130611

AS Assignment

Owner name: QUALCOMM INCORPORATED, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MEGIT ACQUISITION CORP.;REEL/FRAME:033303/0124

Effective date: 20140709

FPAY Fee payment

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8