US20080087984A1 - Compound semiconductor modified surface by use of pulsed electron beam and ion implantation through a deposited metal layer - Google Patents

Compound semiconductor modified surface by use of pulsed electron beam and ion implantation through a deposited metal layer Download PDF

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US20080087984A1
US20080087984A1 US11/998,961 US99896107A US2008087984A1 US 20080087984 A1 US20080087984 A1 US 20080087984A1 US 99896107 A US99896107 A US 99896107A US 2008087984 A1 US2008087984 A1 US 2008087984A1
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H01L21/26546Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
    • H01L21/26553Through-implantation
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10Inorganic compounds or compositions
    • C30B29/40AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B31/00Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor
    • C30B31/20Doping by irradiation with electromagnetic waves or by particle radiation
    • C30B31/22Doping by irradiation with electromagnetic waves or by particle radiation by ion-implantation
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/0242Crystalline insulating materials
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02458Nitrides
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02614Transformation of metal, e.g. oxidation, nitridation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S117/00Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10S117/903Dendrite or web or cage technique
    • Y10S117/904Laser beam
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S117/00Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10S117/905Electron beam

Definitions

  • This application relates to the product of the use of a pulsed electron beam by itself or in combination with other steps to perform semiconductor processes particularly on compound semiconductors of the Groups III-V and II-VI, as well as IV-IV, of the Periodic Chart of the elements.
  • These crystalline materials are normally synthesized at high temperatures and even very high pressures (Reference #1).
  • the partial pressure of the Group V (or VI) element is high, such that special precautions are required to keep the crystalline imperfections low.
  • the partial pressure of Nitrogen over the liquid GaN is approximately ten thousand atmospheres (Reference #5), an exceedingly difficult condition to achieve on a practical scale. This is also important in the case of epitaxial layer growth of compound semiconductors, where typically temperatures of 600-1000 C. are used to form many technologically important alloys and devices (Reference #2).
  • any technique which must improve the crystal quality needs to be very fast and below the time it takes to break apart a molecular bond, or typically below a microsecond.
  • Light energy transfer techniques such as from a flash lamp are slow compared to a pulsed electron beam and produce undesirable temperature rise in the entire substrate.
  • Pulsed electron beams have been used in the past to anneal ion implantation damage in Silicon wafers as large as 100 mm OD.
  • the pulsed electron beam melts the Silicon wafer surface at 1410 C. and the crystallinity of the top micron or so is repaired.
  • the pulsed electron beam is typically of 0.1 microseconds in duration, produced by a capacitor discharge where the electron beam is accelerated through a high voltage field and directed to the substrate.
  • Alternative pulse generation systems may also be used.
  • the beam total is in the range of thousands of amperes and the electrons acquire 10 to 200 KeV energy while a high degree of control is possible.
  • Ion implantation into a compound semiconductor crystal material is well known that at levels in the 10 +16 /cm 2 range and higher will result in an amorphous phase (Reference 4).
  • this amorphous phase will recrystallize into a polycrystalline material at annealing temperatures below about 1100 C. It is necessary though to anneal out the implantation damage at temperatures exceeding two thirds the extrapolated melting point of GaN which is 2518 C. and at ten thousand atmospheres of Nitrogen pressure (Reference #5). So, not only is a high temperature required but also a high volatile component (in the case of GaN it is Nitrogen) overpressure corresponding to the phase diagram.
  • a metal is first deposited. That is, in the case of thermally sensitive at melting point temperature materials, a protective layer, and for these materials and the pulsed electron beam, most appropriately, a metal is used. In this unique combination, the metal caps the material during the high temperature produced by exposure to the pulsed electron beam, and does not allow it to decompose.
  • Blue LED's and lasers are of particular importance to not only to complete the optical spectrum but for very high density Digital Video Disk and other optical storage applications.
  • a particularly difficult problem for these materials relates to the substrate necessary to grow thin layers that comprise the laser, L.E.D or other electronic or optoelectronic device (Reference 3).
  • the substrate performs several functions from providing the mechanical support, to thermal management, to allowing epitaxy to take place through its crystal structure and dimensions, to being either electrically active through impurity doping or insulating again possibly through impurity doping.
  • Group III-Nitride substrates are the ideal materials for homoepitaxy of these materials. It is known that the growth of large (over a few mm in diameter) single crystal substrates, is extraordinarily difficult to achieve compared to GaAs or InP, for example, which are commercially available to 150 mm Outside Diameter (OD).
  • HVPE Hydride Vapor Phase Epitaxy
  • MOVPE Metal Organic Vapor Phase Epitaxy
  • MBE Molecular Beam Epitaxy
  • metal component layer comprises Aluminum, other Group III, or Group I, or Group II, or transition or lanthanide or any other metal element of the Periodic Chart. Additionally, more than one metal element may be used together as one layer over another.
  • the pulsed electron beam comprises an energy of a range approximately 0.01 Joule per cm 2 to 2 Joules/cm 2 , of a pulse duration of less than a microsecond and a diameter of at least 3 mm.
  • the pulsed electron beam may be used sequentially more than once and may be moved over the surface of said layers in a controlled manner. Finally, said pulsed electron beam is stationary and said layers are exposed to said electron beam by moving said layers in a controlled manner.
  • FIG. 1 Modified Compound Semiconductor Surface block diagram.
  • the pulsed electron beam process requires a conductive surface in order to be highly uniform. This is done by evaporating a metal such as Aluminum or other Group III metal or other metal such as a noble metal in the range of a ten to a thousand, or more, nanometers ( FIG. 1 ). This provides the basis to improve the crystallinity of a Group III-Nitride, other Group III-V, Group II-VI or Group IV-IV layer or substrate surface but also to alter the electrical properties of the substrate or layer as follows:
  • the use of Aluminum is significant not only because it is a Group III metal and highly conductive but also because Al x Ga 1-x N layer alloy can be produced. At concentrations below about 1 atomic percent, the Aluminum will not alter significantly the material properties of GaN.
  • a pulsed electron beam as wide as 100 mmOD, generated by capacitor discharge.
  • an electric field of approximately 10 to 100 KiloVolt is used, a total of 1-50 Kilo Amperes, with a pulse width under a microsecond, typically of 80 to 500 nanoseconds, resulting in an energy fluence from 0.1 to 10 Joules per cm 2 .
  • the electron beam pulse may be repeated as necessary to optimize the results.
  • the result of the pulsed electron beam is to raise the surface temperature from ambient to approximately 2300 Celcius, the boiling point of Aluminum metal. As the surface temperature rises by the energy transfer, a portion of the Aluminum may evaporate while another portion of the Aluminum atoms move from the surface into the underlying material. In the case of Aluminum, given its reactivity, it can alloy with the Group III-Nitride substrate material. Since the pulse is sufficiently short, decomposition does not occur and is further controlled by the capping Aluminum layer.
  • any remaining Aluminum layer or even the alloy generated at the top surface can be etched off leaving an improved crystalline surface and more suitable for example for high yield laser layer deposition.
  • Example 1 A variation of Example 1 is where Indium metal is used instead of Aluminum. This is particularly important since in this case, the resulting In x Ga 1-x N layer, which has a larger crystal lattice further improves the GaN crystal structure by expansion.
  • Example 1 Another variation of Example 1 is to use Boron which has the advantage to produce a better metal contact due to the higher energy bandgap than Gallium Nitride itself.
  • a dopant metal element for a Group III-Nitride such as Group II metals Magnesium, Zinc, Cadmium or Beryllium and Group VI metallic Tellurium.
  • a two metal system may be used with a Group III deposited on top of and either Group II or Group VI metal.
  • the dopant element Upon pulsed electron beam exposure the dopant element is driven into the substrate at some depth and as necessary, through multiple pulses to achieve better distribution uniformity. Additionally, given the very surface temperature achieved by the pulsed electron beam the dopant concentration may reach a higher level as well as higher electrical activation and greater depth than by any other thermal technique.
  • a dose of Nitrogen is ion implanted through the Aluminum (or Indium) layer.
  • the dose is chosen to be sufficient to provide additional Nitrogen to bond with vacant Gallium to Nitrogen bonds as well as the additional deposited Aluminum or Indium and thus again fill the voids by expanding the crystal lattice.
  • Ga x In 1-x N y As 1-y alloys are technologically important for laser used optical fiber systems but are extremely difficult to produce with high Nitrogen content due to the thermodynamic instability at reversible growth conditions.
  • the pulsed electron beam process can affect such high Nitrogen content alloy formation since it is not an equilibrium growth process.
  • Ga x In 1-x N y As 1-y alloys start with a GaN substrate and deposit a layer of Arsenic and a layer of Indium and then follow the above steps in Process I with a pulsed electron beam process. This forms a top layer with high Nitrogen content which can then be used for epitaxy of these alloys.
  • a pulsed electron beam is used to improve the crystallinity of various Group II-VI materials such as Zinc Selenide, Zinc Oxide and others as well as to effect doping p or n type by depositing the proper metal.
  • a Group I or Group V metal may be used to effect p-type doping.
  • Group IV-IV materials are becoming technologically very important for even more stringent applications than Group III-V semiconductors.
  • Silicon Carbide has greater radiation tolerance and higher operating temperature and voltage range than the Group III-V semiconductors.
  • SiC single crystals formed by expensive sublimation processes have undesirable micro defects, known as micro pipes, which reduce the yield of processed devices.
  • a pulsed electron beam process as described above these defects may be reduced.
  • a dopant element such as Boron or Aluminum or a Group V and exposing to a pulsed electron beam the Group IV-IV can be doped more easily than by thermal processing as in a furnace.
  • ion implantation may be used to further improve dopant level by using Silicon ion for example.
  • Metal contacts to compound semiconductor materials need to be ohmic, as low as possible electrical resistance and adherent. Additionally the surface only where the contacts are must be heated not the entire device structure with the substrate, which is not possible in a furnace. These problems are overcome by use of the process. This is achieved by first depositing the metal(s) and then exposing to the pulsed electron beam at the correct fluence to reach high enough surface temperature to reduce series resistance and improve adhesion.

Abstract

Thermally sensitive at elevated, near melting point temperature, compound semiconductor materials single crystals including Group III-Nitride, other Group III-V, Group II-VI and Group IV-IV are produced by a variety of methods. When produced as single crystal layers by epitaxy methods or is necessary to expose them to elevated temperatures or ion implanted to the non crystalline state, or their electrical or optical properties are modified, large numbers of crystal defects on the atomic or macro scale may be produced, which limit the yield and performance of opto- and electronic devices constructed out of and grown on top of these layers. It is necessary to be able to improve the crystal quality of such materials after being exposed to elevated temperature or ion implanted or modified by the presence of impurities. It is necessary, particularly for opto- and electronic devices that only the surface of such materials is processed, improved and thus the modified surface product. Generally, as shown in FIG. 1, the thermally sensitive compound semiconductor layer is first coated with a metal layer of approximate thickness of 0.1 microns. Next, the volatile component of the compound semiconductor is ion implanted through the metal layer so as to occupy mostly the top 0.1 to 0.5 microns of the compound semiconductor layer. Co-implantation may be used as well to improve the surface. Finally, through a pulsed directed energy beam of electrons with a fluence of approximately 1 Joule /cm2, the top approximately 0.5 microns acquire a level of the deposited metal and are converted into a single crystal with improved properties such as reduced defect density and or electrical dopant (FIG. 1).

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This is a Divisional Application related to patent application Ser. No. 11/014,304 filed 2004, Dec. 16 and to Provisional Patent Application No. 60/531,001 filed on Dec. 19, 2003
  • BACKGROUND ART
  • This application relates to the product of the use of a pulsed electron beam by itself or in combination with other steps to perform semiconductor processes particularly on compound semiconductors of the Groups III-V and II-VI, as well as IV-IV, of the Periodic Chart of the elements. These crystalline materials are normally synthesized at high temperatures and even very high pressures (Reference #1). Typically at the melting point and standard pressure, the partial pressure of the Group V (or VI) element is high, such that special precautions are required to keep the crystalline imperfections low. For example, in the case of GaN, at the extrapolated melting point of 2518 C., the partial pressure of Nitrogen over the liquid GaN is approximately ten thousand atmospheres (Reference #5), an exceedingly difficult condition to achieve on a practical scale. This is also important in the case of epitaxial layer growth of compound semiconductors, where typically temperatures of 600-1000 C. are used to form many technologically important alloys and devices (Reference #2).
  • Given that these compound semiconductors are sensitive and prone to decomposition at higher than ambient temperatures, any technique which must improve the crystal quality needs to be very fast and below the time it takes to break apart a molecular bond, or typically below a microsecond. Light energy transfer techniques such as from a flash lamp are slow compared to a pulsed electron beam and produce undesirable temperature rise in the entire substrate.
  • Pulsed electron beams have been used in the past to anneal ion implantation damage in Silicon wafers as large as 100 mm OD. The pulsed electron beam melts the Silicon wafer surface at 1410 C. and the crystallinity of the top micron or so is repaired. The pulsed electron beam is typically of 0.1 microseconds in duration, produced by a capacitor discharge where the electron beam is accelerated through a high voltage field and directed to the substrate. Alternative pulse generation systems may also be used. The beam total is in the range of thousands of amperes and the electrons acquire 10 to 200 KeV energy while a high degree of control is possible.
  • At the other extreme such as when the pulsed electron beam is highly focused, it can lead to very rapid and localized temperature rise and thus to vaporization and consequently deposition of the target material on a substrate (Reference #6). However this is the opposite process and not as likely to lead to a single crystalline material, particularly for compound semiconductors which do not have a defined melting point and may decompose on heating.
  • Ion implantation into a compound semiconductor crystal material is well known that at levels in the 10+16/cm2 range and higher will result in an amorphous phase (Reference 4). In the case of GaN, this amorphous phase will recrystallize into a polycrystalline material at annealing temperatures below about 1100 C. It is necessary though to anneal out the implantation damage at temperatures exceeding two thirds the extrapolated melting point of GaN which is 2518 C. and at ten thousand atmospheres of Nitrogen pressure (Reference #5). So, not only is a high temperature required but also a high volatile component (in the case of GaN it is Nitrogen) overpressure corresponding to the phase diagram. Additionally, through ion implantation it is possible to reach very high, non equilibrium concentrations to allow certain alloys to form that are not possible for example in furnace. For example the atomic percent of Nitrogen into GaAs or Arsenic into GaN are limited. Through ion implantation, these compositional limits may be extended.
  • It is a basic part of the method used and the achieved resulting surfaces that a metal is first deposited. That is, in the case of thermally sensitive at melting point temperature materials, a protective layer, and for these materials and the pulsed electron beam, most appropriately, a metal is used. In this unique combination, the metal caps the material during the high temperature produced by exposure to the pulsed electron beam, and does not allow it to decompose.
  • Blue LED's and lasers are of particular importance to not only to complete the optical spectrum but for very high density Digital Video Disk and other optical storage applications. A particularly difficult problem for these materials relates to the substrate necessary to grow thin layers that comprise the laser, L.E.D or other electronic or optoelectronic device (Reference 3). The substrate performs several functions from providing the mechanical support, to thermal management, to allowing epitaxy to take place through its crystal structure and dimensions, to being either electrically active through impurity doping or insulating again possibly through impurity doping. Group III-Nitride substrates are the ideal materials for homoepitaxy of these materials. It is known that the growth of large (over a few mm in diameter) single crystal substrates, is extraordinarily difficult to achieve compared to GaAs or InP, for example, which are commercially available to 150 mm Outside Diameter (OD).
  • SUMMARY OF THE INVENTION
  • The product of a method of modifying the crystal quality of a compound semiconductor material which is comprised of the following:
  • A. Provide a layer of a compound semiconductor material, wherein compound semiconductor material comprises a metal component and a non-metal volatile component and layer comprises a top surface;
  • B. Place said layer of said compound semiconductor material into a metal deposition tool and deposit a layer of metal upon said top surface;
  • C. Place said layer of said compound semiconductor with said deposited layer of said metal into an ion implantation tool and implant non metal component into said layers;
  • D. Place said layer of said compound semiconductor with said deposited metal layer and said implanted non-metal component into a pulsed electron beam tool and expose said layers to a pulsed electron beam.
  • Additionally:
  • The product of method above A-D, wherein said compound semiconductor layer is deposited on a foreign substrate.
  • The product of method above A-D, wherein said compound semiconductor layer comprises Group III-Nitrides, other Group III-V, Group II-VI or Group IV-IV.
  • The product of method above A-D, wherein said compound semiconductor layer is deposited by an epitaxial deposition method selected from a group consisting of Hydride Vapor Phase Epitaxy, (HVPE), Metal Organic Vapor Phase Epitaxy (MOVPE), Molecular Beam Epitaxy (MBE) or similar technologies.
  • The product of method above A-D, wherein said metal component layer comprises Aluminum, other Group III, or Group I, or Group II, or transition or lanthanide or any other metal element of the Periodic Chart. Additionally, more than one metal element may be used together as one layer over another.
  • The product of method above A-D wherein said implanted non-metal component comprises of Nitrogen ions, or other volatile element.
  • The product of the method of above A-D, wherein the energy of said implanted non-metal component is selected to be sufficient so as to go through said deposited metal component layer.
  • The product of method above A-D, wherein the amount of said implanted non-metal component is selected to be sufficient to provide an excess of said non-metal component into said compound semiconductor layer.
  • The pulsed electron beam comprises an energy of a range approximately 0.01 Joule per cm2 to 2 Joules/cm2, of a pulse duration of less than a microsecond and a diameter of at least 3 mm. The pulsed electron beam may be used sequentially more than once and may be moved over the surface of said layers in a controlled manner. Finally, said pulsed electron beam is stationary and said layers are exposed to said electron beam by moving said layers in a controlled manner.
  • The product of method above A-D, wherein said exposing of said layers to said electron beam occurs under a background gas pressure and wherein said gas comprises Nitrogen, or Oxygen or other gas.
  • LIST OF FIGURES
  • FIG. 1. Modified Compound Semiconductor Surface block diagram.
  • DESCRIPTION OF THE INVENTION EXAMPLES
  • The pulsed electron beam process requires a conductive surface in order to be highly uniform. This is done by evaporating a metal such as Aluminum or other Group III metal or other metal such as a noble metal in the range of a ten to a thousand, or more, nanometers (FIG. 1). This provides the basis to improve the crystallinity of a Group III-Nitride, other Group III-V, Group II-VI or Group IV-IV layer or substrate surface but also to alter the electrical properties of the substrate or layer as follows:
  • Example 1 Pulsed Electron Beam Through Deposited Aluminum Layer
  • A. Deposit a high purity layer of Aluminum metal in the range of 0.01 to several micrometers thick. This can be by ebeam evaporation or by a Chemical Vapor Deposition or other technique, as long as high purity is achieved. The use of Aluminum is significant not only because it is a Group III metal and highly conductive but also because AlxGa1-xN layer alloy can be produced. At concentrations below about 1 atomic percent, the Aluminum will not alter significantly the material properties of GaN.
  • B. Use a pulsed electron beam as wide as 100 mmOD, generated by capacitor discharge. Typically, an electric field of approximately 10 to 100 KiloVolt is used, a total of 1-50 Kilo Amperes, with a pulse width under a microsecond, typically of 80 to 500 nanoseconds, resulting in an energy fluence from 0.1 to 10 Joules per cm2. The electron beam pulse may be repeated as necessary to optimize the results.
  • C. The result of the pulsed electron beam is to raise the surface temperature from ambient to approximately 2300 Celcius, the boiling point of Aluminum metal. As the surface temperature rises by the energy transfer, a portion of the Aluminum may evaporate while another portion of the Aluminum atoms move from the surface into the underlying material. In the case of Aluminum, given its reactivity, it can alloy with the Group III-Nitride substrate material. Since the pulse is sufficiently short, decomposition does not occur and is further controlled by the capping Aluminum layer.
  • D. The resulting AlxGa1-xN alloy as well as the surface to some depth, is now of lower EPD as a result of filling the voids and other defects and defect annihilation by solid state diffusion and alloying. By use of higher energy, such as going from under 20 KV to up to 1 MV or multiple pulses, the depth of Aluminum diffusion, defect annihilation and alloying can be controlled as needed for electrical or optoelectronic device applications
  • E. Any remaining Aluminum layer or even the alloy generated at the top surface, can be etched off leaving an improved crystalline surface and more suitable for example for high yield laser layer deposition.
  • Example 2 Pulsed Electron Beam Through Deposited Indium Layer
  • A variation of Example 1 is where Indium metal is used instead of Aluminum. This is particularly important since in this case, the resulting InxGa1-xN layer, which has a larger crystal lattice further improves the GaN crystal structure by expansion.
  • Example 3 Pulsed Electron Beam Through Deposited Boron Layer on Group III-Nitride
  • Another variation of Example 1 is to use Boron which has the advantage to produce a better metal contact due to the higher energy bandgap than Gallium Nitride itself.
  • Example 4 Pulsed Electron Beam Through Deposited Dopant Layer
  • An important variation of this process is to deposit a dopant metal element for a Group III-Nitride such as Group II metals Magnesium, Zinc, Cadmium or Beryllium and Group VI metallic Tellurium. A two metal system may be used with a Group III deposited on top of and either Group II or Group VI metal. Upon pulsed electron beam exposure the dopant element is driven into the substrate at some depth and as necessary, through multiple pulses to achieve better distribution uniformity. Additionally, given the very surface temperature achieved by the pulsed electron beam the dopant concentration may reach a higher level as well as higher electrical activation and greater depth than by any other thermal technique.
  • Example 5 Pulsed Electron Beam Through Aluminum (or Indium) after Nitrogen Ion Implantation
  • In an additional effort to repair the GaN crystal structure after step 1 above and prior to use of the pulsed electron beam, a dose of Nitrogen is ion implanted through the Aluminum (or Indium) layer. The dose is chosen to be sufficient to provide additional Nitrogen to bond with vacant Gallium to Nitrogen bonds as well as the additional deposited Aluminum or Indium and thus again fill the voids by expanding the crystal lattice.
  • Example 6 Nitrogen Containing Alloy Formation
  • GaxIn1-xNyAs1-y alloys are technologically important for laser used optical fiber systems but are extremely difficult to produce with high Nitrogen content due to the thermodynamic instability at reversible growth conditions. The pulsed electron beam process can affect such high Nitrogen content alloy formation since it is not an equilibrium growth process.
  • In order to produce GaxIn1-xNyAs1-y alloys, start with a GaN substrate and deposit a layer of Arsenic and a layer of Indium and then follow the above steps in Process I with a pulsed electron beam process. This forms a top layer with high Nitrogen content which can then be used for epitaxy of these alloys.
  • Example 7 Pulsed Electron Beam Processing of Group II-VI Materials
  • As in the above Process I to III a pulsed electron beam is used to improve the crystallinity of various Group II-VI materials such as Zinc Selenide, Zinc Oxide and others as well as to effect doping p or n type by depositing the proper metal. For example, a Group I or Group V metal may be used to effect p-type doping.
  • Example 8 Pulsed Electron Beam of Group IV-IV Materials
  • Group IV-IV materials are becoming technologically very important for even more stringent applications than Group III-V semiconductors. Silicon Carbide has greater radiation tolerance and higher operating temperature and voltage range than the Group III-V semiconductors. Typically SiC single crystals formed by expensive sublimation processes have undesirable micro defects, known as micro pipes, which reduce the yield of processed devices. By using a pulsed electron beam process as described above these defects may be reduced. Additionally, by depositing a dopant element such as Boron or Aluminum or a Group V and exposing to a pulsed electron beam the Group IV-IV can be doped more easily than by thermal processing as in a furnace. Finally, ion implantation may be used to further improve dopant level by using Silicon ion for example.
  • Example 9 Pulsed Electron Beam of Metal Contacts
  • Metal contacts to compound semiconductor materials need to be ohmic, as low as possible electrical resistance and adherent. Additionally the surface only where the contacts are must be heated not the entire device structure with the substrate, which is not possible in a furnace. These problems are overcome by use of the process. This is achieved by first depositing the metal(s) and then exposing to the pulsed electron beam at the correct fluence to reach high enough surface temperature to reduce series resistance and improve adhesion.
  • PREFERRED EMBODIMENTS
    • 1. This application, in part, relates to currently available growth process which produce free-standing GaN, other Group III-V, Group II-VI and Group IV-IV substrates. These crystals are temperature sensitive particularly at or above their melting point. When grown by lack of availability or other requirement on a lattice mismatched material, the crystal defects are very large in number, i.e. 10+8-10+10/cm2. In the case when epitaxy is required to grow Group III-Nitride devices such as lasers, the yields are very poor. The product of method in application Ser. No. 11/014,304 is the reduction by at least two orders of magnitude of surface defects that is necessary to produce commercially useful substrates of this type.
    • 2. The use of deposited metal as an encapsulating and material modifying layer is important in several ways. First, it is necessary to spread out the electron beam. Second it is sacrificial and can be sputtered off during volatile element implantation or blown off by pulsed electron beam. Third it can be reacted out to the metal containing alloy. Fourth, during the volatile element implantation, the entire substrate may be heated to about 500 C., which reduces the radiation damage. Fifth, the use of the metal layer effectively slows down the implanted Nitrogen ions and thus the radiation damage is minimized. And, Sixth, in the case of a dopant element such as a Group II for Group III-V or a transition or rare earth, the electrical as well as optical crystals may be altered.
    • 3. The use of ion implantation is standard in semiconductor technology. However, it is also well known that radiation damage due to high energy of the implantation process requires a high enough temperature to anneal out, which is estimated at ⅔ of the melting point (Reference 5). In the case of Gallium Nitride that is around 1650 Celcius. Additionally, N+ implantation may result in a porous, amorphous material with gaseous inclusions due to decomposition and therefore not obvious. Even higher levels of N+ implantation may result in a higher concentration of interstitial Nitrogen, which would produce a higher Nitrogen overpressure which is necessary to anneal out the defects to a greater degree but then at an even higher temperature. By exposing only the top surface to the pulsed electron beam, the rest of the material is not heated which is an advantage in processing devices.
    • 4. Given that these compound semiconductors are sensitive and prone to decomposition at higher than ambient temperatures, any technique which can improve the crystal defects of grown wafers as compared to a boule, needs to be very fast, at sub microsecond duration, such as the pulsed electron or laser techniques.
    • 5. In the case of ion implantation damage, a directed energy beam such as a pulsed electron beam has been demonstrated to anneal out the damage, at the appropriate energy level or fluence, as energy per cm2. The voltage used as well as the energy fluence, in Joules per cm2, affect the charachteristics of the beam such as surface penetration. Additionally, the beam must be controlled to be as uniform as possible to achieve uniformity of heating and thus crystallinity repair. The fluence required for this application is in the order of 1 Joule per cm2.
    • 6. When the pulsed electron beam is highly focused, such as approximately 1 mm2, the highly focused beam can lead to very rapid and localized temperature rise and thus to vaporization and consequently deposition of the target material on a substrate (Reference 6). In this application, a wide beam of the necessary fluence, is required to produce annealing and reaction to relieve the radiation damage on a larger scale and be of commercial value. The result of the directed energy beam such as the pulsed electron beam is to raise the surface temperature from ambient to well over 1000 C. depending on the fluence and other factors such as energy coupling to the surface. As the surface temperature rises by the energy transfer, the Aluminum or other metal atoms from the deposited and melted Aluminum or other metal layer on the surface, diffuse rapidly into the underlying material. In this case, Aluminum, given its reactivity, it can alloy with the Gallium Nitride substrate material and in the process compress the interstitial Nitrogen to very high pressure and temperature. Since the pulse is sufficiently short, decomposition does not occur and is further controlled by the capping Aluminum Nitride and Aluminum layer. This AlGaN alloy formed from the surface to some depth, is now of lower crystal defect density as a result of filling the voids and other defects and defect annihilation by solid state diffusion, alloying and very high temperature and pressure. This is effectively then is also a surface polishing technique.
    • 7. By use of multiple directed energy pulses, in the case of AlGaN by HVPE, the temperature rise as well as depth of Aluminum diffusion, increase. This leads to greater defect annihilation and the crystallite size increases by several fold and the X Ray Diffraction half width decreases compared to the single pulsed layers.
    • 8. By use of a dopant metal layer alone or in combination with Aluminum for example in a Group III-Nitride material, the electrical and or optical properties of the material may be modified. Again this is achieved only at the surface without exposing the entire device structure to the high temperature. Furthermore, the impurity level may be controlled and reach a higher level than that achieved from a furnace, due to the higher temperature achieved by the pulsed electron beam.
    • 9. In the case of metal contact treatment by the pulsed electron beam the top surface only is exposed avoiding the possible decomposition problems of furnace treatment.
    • 10. In the case of alloy formation where by ion implantation of the volatile non metal component a higher concentration and improved crystal quality may be achieved than by another growth technique.
  • While the invention has been described in terms of certain preferred embodiments and material systems, modifications obvious to those with ordinary skill in the art may be made without departing from the scope of the invention.
  • REFERENCES (Already Provided in application Ser. No. 11/014,304)
    • 1. Gallium Arsenide Technology, D. K. Ferry, Editor, Howard W. Sams & Co. publishers, 1985, p. 47-105.
    • 2. Organometallic Vapor-Phase Epitaxy, Theory and Practice, by Gerald Stringfellow, Academic Press, Inc. publishers, 1989, p. 1-14.
    • 3. Geppert, L., “The Great Gallium Nitride Gamble”, IEEE Spectrum, January 2004, pp. 52-59.
    • 4. Tan, H. H., et. al., “Annealing of ion implanted gallium nitride”, Applied Physics Letters, V.72, Number 10, p. 1190-2
    • 5. Williams, J. S., Rep. Prog. Phys. 49, p. 491, (1986).
    • 6. Pulsed Electron Deposition System by NEOCERA, Beltsville, Md., 20705

Claims (19)

1. A top surface modified compound semiconductor material product formed by a method comprising:
providing a layer of said compound semiconductor material, wherein said compound semiconductor material comprises a metal component and a non-metal component and said layer comprises a top surface;
placing said layer of said compound semiconductor material into a metal deposition tool and depositing a layer of metal component upon said top surface;
placing said layer of said compound semiconductor with said deposited layer of said metal component into an ion implantation tool and implanting non metal component into and through said metal layer;
placing said layer of said compound semiconductor with said deposited metal layer and said implanted non-metal component into a directed pulsed electron beam tool and exposing said layers to said energy beam.
2. The product of claim 1 wherein the said semiconductor material is a Group III-V material.
3. The product of claim 1 wherein the said semiconductor material is a Group II-VI material.
4. The product of claim 1 wherein the said semiconductor material is a Group IV-IV material.
5. The product of claim 1 wherein the said metal layer is a Group III element.
6. The product of claim 1 wherein the said metal layer is a Group I element.
7. The product of claim 1 wherein the said metal layer is a Group II element.
8. The product of claim 1 wherein the said metal layer is a transition metal.
9. The product of claim 1 wherein the said metal layer is a lanthanide metal.
10. The product of claim 1 wherein the said metal layer is any other metal in the periodic chart of elements.
11. The product of claim 1 wherein the said metal layer is a combination of two or more metals.
12. The product of claim 1 wherein the said metal layer is a combination of Group II and Group III on a Group III-V material.
13. The product of claim 1 wherein the said metal layer is a combination of Group I and Group II on a Group II-VI material.
14. The product of claim 1 wherein the implanted element is a non metal.
15. The product of claim 1 wherein the said implanted element is Nitrogen.
16. The product of claim 1 wherein the said implanted element is Carbon.
17. The product of claim 1 wherein the said implanted element is Silicon.
18. The product of claim 1 wherein the said implanted element is Oxygen.
19. The product of claim 1 wherein the said implanted element is any other nonmetal element of the periodic chart of elements.
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Publication number Priority date Publication date Assignee Title
US20080182092A1 (en) * 2007-01-17 2008-07-31 Crystal Is, Inc. Defect reduction in seeded aluminum nitride crystal growth
US20090178276A1 (en) * 2008-01-16 2009-07-16 Fukui Precision Component (Shenzhen) Co., Ltd. Method for forming circuit in making printed circuit board
US20100187541A1 (en) * 2005-12-02 2010-07-29 Crystal Is, Inc. Doped Aluminum Nitride Crystals and Methods of Making Them
US20110008621A1 (en) * 2006-03-30 2011-01-13 Schujman Sandra B Aluminum nitride bulk crystals having high transparency to ultraviolet light and methods of forming them
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5578839A (en) * 1992-11-20 1996-11-26 Nichia Chemical Industries, Ltd. Light-emitting gallium nitride-based compound semiconductor device
US5625202A (en) * 1995-06-08 1997-04-29 University Of Central Florida Modified wurtzite structure oxide compounds as substrates for III-V nitride compound semiconductor epitaxial thin film growth
US5656832A (en) * 1994-03-09 1997-08-12 Kabushiki Kaisha Toshiba Semiconductor heterojunction device with ALN buffer layer of 3nm-10nm average film thickness
US5670798A (en) * 1995-03-29 1997-09-23 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact non-nitride buffer layer and methods of fabricating same
US5679965A (en) * 1995-03-29 1997-10-21 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact, non-nitride buffer layer and methods of fabricating same
US5740192A (en) * 1994-12-19 1998-04-14 Kabushiki Kaisha Toshiba Semiconductor laser
US5786606A (en) * 1995-12-15 1998-07-28 Kabushiki Kaisha Toshiba Semiconductor light-emitting device
US5990495A (en) * 1995-08-25 1999-11-23 Kabushiki Kaisha Toshiba Semiconductor light-emitting element and method for manufacturing the same
US6090300A (en) * 1998-05-26 2000-07-18 Xerox Corporation Ion-implantation assisted wet chemical etching of III-V nitrides and alloys
US6599133B2 (en) * 1997-11-18 2003-07-29 Technologies And Devices International, Inc. Method for growing III-V compound semiconductor structures with an integral non-continuous quantum dot layer utilizing HVPE techniques

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4151008A (en) * 1974-11-15 1979-04-24 Spire Corporation Method involving pulsed light processing of semiconductor devices
US4154625A (en) * 1977-11-16 1979-05-15 Bell Telephone Laboratories, Incorporated Annealing of uncapped compound semiconductor materials by pulsed energy deposition
JP4307635B2 (en) * 1999-06-22 2009-08-05 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US7192827B2 (en) * 2001-01-05 2007-03-20 Micron Technology, Inc. Methods of forming capacitor structures

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5578839A (en) * 1992-11-20 1996-11-26 Nichia Chemical Industries, Ltd. Light-emitting gallium nitride-based compound semiconductor device
US5734182A (en) * 1992-11-20 1998-03-31 Nichia Chemical Industries Ltd. Light-emitting gallium nitride-based compound semiconducor device
US5656832A (en) * 1994-03-09 1997-08-12 Kabushiki Kaisha Toshiba Semiconductor heterojunction device with ALN buffer layer of 3nm-10nm average film thickness
US5740192A (en) * 1994-12-19 1998-04-14 Kabushiki Kaisha Toshiba Semiconductor laser
US5998810A (en) * 1994-12-19 1999-12-07 Kabushiki Kaisha Toshiba Semiconductor light-emitting diode having a p-type semiconductor layer formed on a light-emitting layer
US5670798A (en) * 1995-03-29 1997-09-23 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact non-nitride buffer layer and methods of fabricating same
US5679965A (en) * 1995-03-29 1997-10-21 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact, non-nitride buffer layer and methods of fabricating same
US5625202A (en) * 1995-06-08 1997-04-29 University Of Central Florida Modified wurtzite structure oxide compounds as substrates for III-V nitride compound semiconductor epitaxial thin film growth
US5990495A (en) * 1995-08-25 1999-11-23 Kabushiki Kaisha Toshiba Semiconductor light-emitting element and method for manufacturing the same
US5786606A (en) * 1995-12-15 1998-07-28 Kabushiki Kaisha Toshiba Semiconductor light-emitting device
US6599133B2 (en) * 1997-11-18 2003-07-29 Technologies And Devices International, Inc. Method for growing III-V compound semiconductor structures with an integral non-continuous quantum dot layer utilizing HVPE techniques
US6090300A (en) * 1998-05-26 2000-07-18 Xerox Corporation Ion-implantation assisted wet chemical etching of III-V nitrides and alloys

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US9447521B2 (en) 2001-12-24 2016-09-20 Crystal Is, Inc. Method and apparatus for producing large, single-crystals of aluminum nitride
US9525032B2 (en) 2005-12-02 2016-12-20 Crystal Is, Inc. Doped aluminum nitride crystals and methods of making them
US20100187541A1 (en) * 2005-12-02 2010-07-29 Crystal Is, Inc. Doped Aluminum Nitride Crystals and Methods of Making Them
US8747552B2 (en) 2005-12-02 2014-06-10 Crystal Is, Inc. Doped aluminum nitride crystals and methods of making them
US9034103B2 (en) 2006-03-30 2015-05-19 Crystal Is, Inc. Aluminum nitride bulk crystals having high transparency to ultraviolet light and methods of forming them
US20110008621A1 (en) * 2006-03-30 2011-01-13 Schujman Sandra B Aluminum nitride bulk crystals having high transparency to ultraviolet light and methods of forming them
US9447519B2 (en) 2006-03-30 2016-09-20 Crystal Is, Inc. Aluminum nitride bulk crystals having high transparency to untraviolet light and methods of forming them
US8323406B2 (en) * 2007-01-17 2012-12-04 Crystal Is, Inc. Defect reduction in seeded aluminum nitride crystal growth
US9771666B2 (en) 2007-01-17 2017-09-26 Crystal Is, Inc. Defect reduction in seeded aluminum nitride crystal growth
US20080182092A1 (en) * 2007-01-17 2008-07-31 Crystal Is, Inc. Defect reduction in seeded aluminum nitride crystal growth
US9670591B2 (en) 2007-01-17 2017-06-06 Crystal Is, Inc. Defect reduction in seeded aluminum nitride crystal growth
US9624601B2 (en) 2007-01-17 2017-04-18 Crystal Is, Inc. Defect reduction in seeded aluminum nitride crystal growth
US10446391B2 (en) 2007-01-26 2019-10-15 Crystal Is, Inc. Thick pseudomorphic nitride epitaxial layers
US20090178276A1 (en) * 2008-01-16 2009-07-16 Fukui Precision Component (Shenzhen) Co., Ltd. Method for forming circuit in making printed circuit board
US9028612B2 (en) 2010-06-30 2015-05-12 Crystal Is, Inc. Growth of large aluminum nitride single crystals with thermal-gradient control
US9580833B2 (en) 2010-06-30 2017-02-28 Crystal Is, Inc. Growth of large aluminum nitride single crystals with thermal-gradient control
US10074784B2 (en) 2011-07-19 2018-09-11 Crystal Is, Inc. Photon extraction from nitride ultraviolet light-emitting devices
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US9299880B2 (en) 2013-03-15 2016-03-29 Crystal Is, Inc. Pseudomorphic electronic and optoelectronic devices having planar contacts

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