US20070235763A1 - Substrate band gap engineered multi-gate pMOS devices - Google Patents

Substrate band gap engineered multi-gate pMOS devices Download PDF

Info

Publication number
US20070235763A1
US20070235763A1 US11/393,168 US39316806A US2007235763A1 US 20070235763 A1 US20070235763 A1 US 20070235763A1 US 39316806 A US39316806 A US 39316806A US 2007235763 A1 US2007235763 A1 US 2007235763A1
Authority
US
United States
Prior art keywords
gate
upper portion
band gap
fin
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/393,168
Inventor
Brian Doyle
Been-Yih Jin
Jack Kavalieros
Suman Datta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to US11/393,168 priority Critical patent/US20070235763A1/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JIN, BEEN-YIH, DATTA, SUMAN, DOYLE, BRIAN S., KAVALIEROS, JACK T.
Publication of US20070235763A1 publication Critical patent/US20070235763A1/en
Priority to US12/757,917 priority patent/US8169027B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H01L29/78687Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Definitions

  • the present invention relates to the field of semiconductor devices and more specifically to controlling short-channel effects in multi-gate devices.
  • Multi-gate devices enable better control of the transistor channel than do planar transistors with a single gate.
  • the use of more than one gate in the channel region of the transistor allows more control over the current flow within the channel.
  • the better control over the channel minimizes short-channel effects.
  • the multi-gate devices are less efficient at controlling the electric fields from the source and drain regions.
  • the electric fields from the source and drain regions result in short-channel effects such as an increased leakage current at a given gate voltage in the subthreshold region of device operation.
  • prior solutions to minimize this leakage current includes utilizing dopants in the channel that have unwanted effects such as increasing the threshold voltage of the transistor.
  • a multi-gate transistor and a method of forming a multi-gate transistor including a fin having an upper portion and a lower portion.
  • the upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion.
  • the multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.
  • FIG. 1 is an illustration of a perspective view of an embodiment of a multi-gate pMOS device using substrate band gap engineering.
  • FIG. 2 is an illustration of a perspective view of an embodiment of a multi-gate pMOS device on an insulating substrate using substrate band gap engineering.
  • FIG. 3A-3F is an illustration of perspective views of a method of fabricating an embodiment of a multi-gate pMOS device using substrate band gap engineering.
  • FIG. 4A-4D is an illustration of perspective views of a method of fabricating an embodiment of a multi-gate pMOS device on an insulating substrate using substrate band gap engineering.
  • Embodiments of the present invention include band gap engineered multi-gate pMOS devices.
  • the device is fabricated with a fin or body formed from a layer of material deposited over a substrate and a portion of the substrate.
  • the layer of material deposited over a substrate and the substrate are selected such that the band gap of the material deposited over the substrate is narrower than that of the substrate.
  • the difference in the band gap creates a band gap offset between the valence bands of the two layers, which adds an extra barrier for the holes to mount in order to move into the substrate.
  • the result of the band gap offset is to minimize the leakage current into the substrate.
  • Another aspect of embodiments of a pMOS device according to the present invention includes forming a source region and a drain region fully contained within the layer of material deposited over the substrate. Because the source region and drain region are fully contained within the layer of material deposited over a substrate the leakage current in the substrate is minimized.
  • Embodiments of the present invention also include a gate structure that is electrically coupled with the layer of material deposited over a substrate and at least a part of the substrate portion of the fin.
  • the band gap offset between the materials of the fin changes the flat-band voltage of this part of the device.
  • the result is a lower threshold voltage in the material deposited over the substrate than the threshold voltage of the substrate portion of the fin because of the band gap offset between the two materials.
  • the higher threshold voltage in the substrate portion of the fin helps to further minimize the leakage current. Minimizing the transistor leakage current provides for lower power, high performance transistors. Moreover, the ability to better control the leakage current allows the transistor to be scaled to smaller dimensions.
  • FIG. 1 shows an embodiment of a substrate band gap engineered multi-gate pMOS device 100 .
  • a fin or body 105 is formed from two materials.
  • the fin 105 has a lower portion 110 formed from a substrate and an upper portion 115 formed from a semiconductor material that has a band gap at least 0.3 electron volts (eV) narrower than the substrate portion 110 .
  • the materials for the upper portion 115 and the lower portion 110 are selected such that the band gap offset between the upper portion 115 and the lower portion 110 is equal to or greater than 0.3 eV.
  • the materials of the upper portion 115 and the lower portion 110 are selected such that the band gap of the upper portion 115 is approximately 0.3 eV narrower than that of the material selected for the lower portion 110 .
  • the band-gap offset between the upper portion 115 and the lower portion 110 is approximately 0.4 eV.
  • the difference in the band gap of the lower portion 110 and an upper portion 115 creates an extra barrier for holes to overcome before escaping into the lower portion 110 .
  • This extra barrier results in reducing the number of holes that can travel from the upper portion to the lower portion; therefore, the leakage current is reduced.
  • Having a lower portion 110 with a band gap equal to or greater than 0.3 eV larger than an upper portion 115 also creates a lower threshold voltage in the upper portion 115 than in the lower portion 110 .
  • the difference in the threshold voltages between the upper portion 115 and the lower portion 110 increases in the same amount as the band-gap offset between the two portions. The resulting higher flat-band voltage in the lower portion 110 further minimizes the leakage current in the lower portion 110 .
  • an epitaxial semiconductor layer forms an upper portion 115 having a band gap approximately 0.3 eV to approximately 0.4 eV narrower than the band gap of the lower portion 110 that is positioned over the lower portion 110 .
  • the upper portion 115 is formed from a composition of silicon-germanium.
  • One embodiment of the pMOS device 100 includes the use of silicon-germanium with 20-50 atomic percent of germanium for the upper portion 115 and silicon for the lower portion 110 . In an embodiment using silicon-germanium, the silicon-germanium includes 30 atomic percent of germanium.
  • pMOS device 100 using silicon-germanium contains 20 atomic percent of germanium in the silicon-germanium upper portion 115 .
  • a substrate 107 may be formed of any semiconductor material having a band gap equal to or greater than 0.3 eV than an upper portion 115 .
  • the thickness of the upper portion 115 is 3 to 20 times thicker than the lower portion 110 . In one embodiment the thickness of the upper portion 115 is between approximately 200 angstroms ( ⁇ ) and 800 ⁇ .
  • Embodiments of a pMOS device 100 according to the present invention include the lower portion 110 having a thickness between approximately 10 ⁇ and 200 ⁇ .
  • An embodiment of the pMOS device 100 includes an upper portion 115 having a thickness of approximately 450 ⁇ and a lower portion have a thickness of 50 ⁇ .
  • a gate structure 120 resides over a gate insulator 125 .
  • Some embodiments of a substrate band gap engineered multi-gate pMOS device 100 include a gate insulator 125 positioned over shallow trench isolation (STI) regions 130 formed on a substrate 107 .
  • a gate structure 120 may be fabricated as illustrated in FIG. 1 such that the substrate band gap engineered multi-gate pMOS device 100 is a tri-gate transistor. In a tri-gate transistor embodiment the gate structure 120 is formed on the top surface of a fin 105 and on the sidewalls of a fin 105 .
  • the gate structure 120 is formed on laterally opposite sidewalls of a fin 105 .
  • a gate structure 120 may be fabricated in such a manner as to form other dual-gate or omega-gate devices.
  • FIG. 2 illustrates another embodiment of a substrate band gap engineered multi-gate pMOS device 100 fabricated in a semiconductor-on-insulator (SOI) configuration but is otherwise similar to the FIG. 1 embodiment.
  • substrate 205 is formed from an insulator 210 and a carrier 215 .
  • the insulator 210 may be any dielectric material such as silicon dioxide.
  • the carrier 215 of an SOI configuration may be any semiconductor, insulator, or metallic material.
  • the multi-gate pMOS device 100 has a gate insulator 125 .
  • Other embodiments according to the present invention include a pMOS device 100 without a gate insulator 125 .
  • the gate structure 120 is in direct contact with the fin 105 .
  • the gate insulator 125 covers the top and the sidewalls of the fin 105 .
  • a gate dielectric layer 125 is only formed on the sidewalls of the fin 105 .
  • Gate insulator 125 may be made of any dielectric material compatible with materials forming a fin 105 and materials forming a gate structure 120 .
  • the gate dielectric layer 125 may be formed from a silicon dioxide (SiO 2 ), a silicon oxynitride (SiO x N y ), or a silicon nitride (Si 3 N 4 ) dielectric layer.
  • the gate dielectric layer 125 is formed from a silicon oxynitride layer formed to a thickness of 5-20 ⁇ .
  • a gate dielectric layer 125 is formed from a high K gate dielectric layer such as a metal oxide dielectric, including but not limited to tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, or aluminum oxide.
  • Gate dielectric layer 125 may also be formed from materials including other types of high K dielectrics, such as lead zirconium titanate (PZT).
  • a gate structure 120 is formed on and adjacent to the gate dielectric layer 125 .
  • a gate structure 120 has a pair of laterally opposite sidewalls separated by a distance defining the gate length (L g ) of the pMOS device 100 .
  • the gate electrode may be formed of any material having an appropriate work function.
  • a gate structure 120 in an embodiment of the pMOS device 100 of the present invention is formed from a metal gate electrode, such as tungsten, tantalum nitride, titanium silicide, nickel silicide, or cobalt silicide.
  • Another embodiment of the present invention includes a gate structure 120 fabricated from a composite stack of thin films such as a metal/polycrystalline silicon electrode.
  • Embodiments of the pMOS device 100 include a gate structure 120 formed to couple with the top of fin 105 , the sidewalls of an upper portion 115 , and the sidewalls of a lower portion 110 .
  • the gate structure 120 covers the top of a fin 105 and extends between approximately 5 ⁇ and 200 ⁇ below the top of a lower portion 110 .
  • the gate structure 120 extends 25 ⁇ below the top of a lower portion 110 .
  • only the sidewall portion of a gate structure 120 is used; therefore, the top of a fin 105 is not covered by a portion of a gate structure.
  • a gate structure in a FinFET embodiment of a pMOS device 100 according to the present invention includes sidewalls to electrically couple to an upper portion 115 and a lower portion 110 .
  • One FinFET embodiment of the pMOS device 100 includes a gate structure that extends approximately 5 ⁇ and 200 ⁇ below the top of the lower portion 110 .
  • a gate structure extends 25 ⁇ below the top of a lower portion 110 .
  • FIGS. 1 and 2 also include a source region 135 and a drain region 140 formed in the upper portion 115 on opposite sides of a gate structure 120 .
  • a source region 135 and a drain region 140 are fully contained within an upper portion 115 . Fully containing a source region 135 and a drain region 140 within an upper portion 115 also aids in minimizing the leakage current in a lower portion 110 .
  • Some embodiments of the present invention have a doping concentration of 1 ⁇ 10 19 -1 ⁇ 10 21 atoms/cm 3 .
  • An embodiment of the pMOS device 100 includes a source region 135 and a drain region 140 formed of a uniform doping concentration.
  • a source region 135 and a drain region 140 include subregions of different doping concentrations or doping profiles such as tip regions. In an embodiment including tip regions, sidewall spacers are used to create tip regions.
  • a source region 135 and a drain region 140 define a channel region in the fin 105 of the pMOS device.
  • a channel region is undoped.
  • Another embodiment of the pMOS device 100 includes a channel region doped to a concentration as high as 1 ⁇ 10 19 atoms/cm 3 .
  • Some embodiments of the present invention include halo implants implanted below the channel region of a half order magnitude greater than the doping concentration of the channel region and the same conductivity type as the channel region. The halo implants work to further minimize the leakage of a pMOS device 100 .
  • Other embodiments of the present invention include punchthrough implants or other techniques to combat short-channel effects.
  • FIGS. 3A-3F A method of fabricating a pMOS device 100 on a substrate in accordance with an embodiment of the present invention as shown in FIG. 1 is illustrated in FIGS. 3A-3F .
  • the substrate 107 of FIG. 3A can be a semiconductor layer, such as a silicon monocrystalline substrate.
  • an upper portion layer 305 is deposited over a substrate 107 .
  • the upper portion layer 305 is formed from part of the substrate 107 .
  • Another embodiment of the pMOS device 100 includes an upper portion layer 305 that is an epitaxial layer formed on substrate 107 .
  • the upper portion layer 305 is formed to a thickness between approximately 200 ⁇ and 800 ⁇ .
  • the pMOS device 100 includes an upper portion layer 305 formed to a thickness of approximately 450 ⁇ . Another embodiment of the pMOS device 100 includes the pMOS device 100 including an upper portion layer 305 formed to a thickness of approximately 600 ⁇ .
  • the upper portion layer 305 is a composition of a silicon-germanium alloy having a band gap at least 0.3 eV narrower than the substrate 107 .
  • the upper portion layer 305 includes an epitaxial region with p-type conductivity with an impurity concentration level between 1 ⁇ 10 16 -1 ⁇ 10 19 atoms/cm 3 .
  • the upper portion layer 305 is an undoped silicon-germanium alloy layer having a band gap at least 0.4 eV narrower than the band gap of the substrate 107 .
  • well regions of upper portion layer 305 are doped to p-type conductivity with a concentration level between about 1 ⁇ 10 16 -1 ⁇ 10 19 atoms/cm 3 .
  • Upper portion layer 305 can be doped by, for example, ion-implantation. The doping level of the upper portion layer 305 at this point may determine the doping level of the channel region of a pMOS device 100 .
  • a masking layer 310 is used to define the active regions of the pMOS device 100 on the upper portion layer 305 .
  • a masking layer 310 is used to define the active regions of an embodiment of a pMOS device 100 of the present invention.
  • the masking layer 310 may be any material suitable for defining an upper portion layer 305 and a substrate 107 .
  • masking layer 310 is a lithographically defined photo resist.
  • masking layer 310 is formed of a dielectric material that has been lithographically defined and then etched.
  • masking layer 310 is a hard mask.
  • masking layer 310 may be a composite stack of materials, such as an oxide/nitride stack.
  • a fin or body 105 is then defined, as shown in FIG. 3C , by an etching technique.
  • the fin 105 having an upper portion 115 and a lower portion 110 .
  • anisotropic plasma etch, or RIE is used to define a fin 105 .
  • FIG. 3C shows the upper portion layer 305 and a portion of the substrate 107 etched to form recesses or trenches 320 on the substrate 107 in alignment with the outside edges of masking portion 310 .
  • the trenches 320 are etched to a depth sufficient to isolate an adjacent transistor from the other. In an embodiment of the pMOS device 100 the trench 320 between approximately 500 ⁇ and 2000 ⁇ deep in the substrate 107 . In one embodiment the trench 320 is etched to a depth of 1500 ⁇ in the substrate 107 .
  • the trenches 320 are filled with a dielectric to form STI regions 130 on substrate 107 .
  • a liner of oxide or nitride on the bottom and sidewalls of the trenches 320 is formed.
  • the trenches 320 are filled by blanket depositing an oxide over the liner by, for example, a high-density plasma (HDP) chemical vapor deposition process. The deposition process will also form dielectric on the top surfaces of the mask portions 310 .
  • the fill dielectric layer can then be removed from the top of mask portions 310 by chemical, mechanical, or electrochemical, polishing techniques. The polishing is continued until the mask portions 310 are revealed, forming STI regions 130 .
  • the mask portions 310 are selectively removed. In other embodiments, the mask portions 310 are retained through subsequent processes.
  • the STI regions 130 are etched back or recessed to form the sidewalls of the fin 105 .
  • STI regions 130 are etched back with an etchant, which does not significantly etch the fin 105 .
  • STI regions 130 are recessed such that the amount of the lower portion 110 that is exposed is within a range between 200 ⁇ and 800 ⁇ .
  • STI regions 130 are recessed using an anisotropic etch followed by an isotropic etch to remove the STI dielectric from the sidewalls of a fin 105 until 500 ⁇ of the substrate 107 is exposed.
  • STI regions 130 are recessed by an amount dependent on the desired channel width of the pMOS device 100 formed.
  • a gate dielectric layer 125 is formed on each upper portion 115 and lower portion 110 of fin 105 in a manner dependent on the type of device (dual-gate, tri-gate, etc.).
  • a gate dielectric layer 125 is formed on the top surface of an upper portion 115 , as well as on the laterally opposite sidewalls of a fin 105 .
  • the gate dielectric 125 is not formed on the top surface of the upper portion 115 , but on the top surface of hard mask.
  • the gate dielectric layer 125 can be a deposited dielectric or a grown dielectric.
  • the gate dielectric layer 125 is a silicon dioxide dielectric film grown with a dry/wet oxidation process.
  • the gate dielectric film 125 is a deposited high dielectric constant (high-K) metal oxide dielectric, such as tantalum pentaoxide, titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, or another high-K dielectric, such as barium strontium titanate (BST).
  • high-K metal oxide dielectric such as tantalum pentaoxide, titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, or another high-K dielectric, such as barium strontium titanate (BST).
  • a high-K film can be formed by well-known techniques, such as chemical vapor deposition (CVD) and atomic layer deposition (ALD).
  • a gate structure 120 is formed on the pMOS device 100 .
  • the gate structure 120 is formed on the gate dielectric layer 125 formed on and adjacent to the top surface of the upper portion 115 and is formed on and adjacent to the gate dielectric 125 formed on and adjacent to the sidewalls of fin 105 , which includes the sidewalls of the upper portion 115 and the lower portion 110 .
  • the gate structure 120 may be formed to a thickness between 200-3000 ⁇ . In an embodiment, the gate structure 120 has a thickness of at least three times the height of a fin 105 .
  • the gate electrode is a mid-gap metal gate electrode such as, tungsten, tantalum nitride, titanium nitride or titanium silicide, nickel silicide, or cobalt silicide.
  • gate structure 120 is formed by techniques including but not limited to blanket depositing a gate structure 120 material over the substrate 107 and then patterning the gate electrode material through photolithography and etch. In other embodiments of the present invention, “replacement gate” methods are used to form the gate structure 120 .
  • Source region 135 and drain region 140 for the transistor are formed in upper portion 115 on opposite sides of gate structure 120 , as shown in FIG. 3F .
  • a source region 135 and a drain region 140 resides on opposite sides of a channel.
  • the source region 135 and drain region 140 region are completely contained in the upper portion 115 .
  • a source region 135 and a drain region 140 include tip or source/drain extension regions.
  • an upper portion 115 is doped to a p-type conductivity and to a concentration between 1 ⁇ 10 19 -1 ⁇ 10 21 atoms/cm 3 . At this point an embodiment of a pMOS device 100 according to the present invention is substantially complete and only device interconnection remains.
  • FIGS. 4A-4D A method of fabricating a substrate band gap engineered pMOS device 100 on an insulating substrate in accordance with an embodiment of the present invention as shown in FIG. 2 is illustrated in FIGS. 4A-4D .
  • Forming a pMOS device 100 on an insulating substrate according to an embodiment of the present invention may use similar techniques and materials as described for the embodiments illustrated by FIGS. 3A-3F .
  • the SOI substrate 205 includes an insulating layer 210 , such as a silicon dioxide film or silicon nitride film, formed over a lower silicon carrier 215 .
  • Insulating layer 210 isolates lower portion layer 410 and upper portion layer 305 from carrier 205 , and in an embodiment is formed to a thickness between 200-2000 ⁇ . In an embodiment, insulating layer 210 is sometimes referred to as a “buried oxide” layer.
  • the upper portion layer 305 is ideally a silicon-germanium alloy (SiGe), other types of semiconductor films may be used so long as the band gap of the upper portion layer 305 is at least 0.3 eV narrower than that of the lower portion layer 410 .
  • Such semiconductor films may include compositions of any III-V semiconductor compounds that results in at least a 0.3 eV narrower band gap than that of the lower portion layer 410 .
  • upper portion layer 305 is an intrinsic (i.e., undoped) silicon germanium alloy film having 30 atomic percent of germanium. In other embodiments, upper portion layer 305 is doped to p-type conductivity with a concentration level between 1 ⁇ 10 16 -1 ⁇ 10 19 atoms/cm 3 . Upper portion layer 305 can be in-situ doped (i.e., doped while it is deposited) or doped after it is formed on substrate 107 by for example ion-implantation. The doping level of the upper body layer 305 at this point can determine the doping level of the channel region of the device. Upper body layer 305 may be formed on insulator 210 in any well-known method.
  • SOI substrates In one method of forming a silicon-on-insulator substrate, known as the separation by implantation of oxygen (SIMOX) technique.
  • SIMOX separation by implantation of oxygen
  • Another technique currently used to form SOI substrates is an epitaxial silicon film transfer technique generally referred to as bonded SOI or SMARTCUT.
  • a masking layer 310 is used to define the active regions of a pMOS device 100 .
  • a fin 105 is then defined by an etching technique to expose the sidewalls of a body portion 115 and a substrate portion 110 .
  • masking layer 310 is removed from the upper portion 115 . In other embodiments, such as for particular dual-gate or FinFET designs, masking layer 310 is not removed.
  • the upper portion 115 is a silicon-germanium layer having an atomic percent of germanium within a range of about 20 atomic percent to about 50 atomic percent. In an embodiment the amount of germanium in a silicon-germanium upper portion 115 is within a range of about 25 to 35 atomic percent. In other embodiments, the germanium concentration is about 50 percent.
  • the formation process for creating the silicon germanium layer is capable of producing a single crystalline upper portion 115 . As in the process described in FIGS. 3A-3F , the upper portion 115 is grown to the desired thickness, some embodiments include in-situ impurity doping.
  • a SiGe is grown to a thickness in the range of approximately 200 ⁇ and 800 ⁇ .
  • One embodiment of the pMOS device 100 includes an upper portion layer 305 formed to a thickness of approximately 450 ⁇ .
  • various regions over the substrate are selectively and iteratively masked and different devices such as nMOS devices, other pMOS devices, or other circuit components may be formed.
  • a gate insulator 125 , gate structure 120 , source regions 135 , and drain regions 140 are formed following embodiments analogous to those previously described above.
  • an embodiment of a pMOS device 100 of the present invention formed on a SOI substrate is substantially complete and only device interconnection remains.

Abstract

A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to the field of semiconductor devices and more specifically to controlling short-channel effects in multi-gate devices.
  • 2. Discussion of Related Art
  • During the past two decades, the physical dimensions of MOSFETs have been aggressively scaled for low-power, high-performance applications. The need for faster switching transistors requires shorter channel lengths. The continued decreasing size and need for low-power transistors makes overcoming the short channel effects of transistors necessary. However, as the dimensions of the transistors decrease the ability to control the leakage current becomes more difficult. To limit the amount of leakage current in a transistor current solutions involve strictly controlling the placement of the source and drain dopants within the active region of the transistor. Other techniques to combat the leakage current include implants in and around the channel such as halo and punchthrough implants. However, the use of such implants results in degraded performance of the transistor such as increasing the threshold voltage.
  • Multi-gate devices enable better control of the transistor channel than do planar transistors with a single gate. The use of more than one gate in the channel region of the transistor allows more control over the current flow within the channel. The better control over the channel minimizes short-channel effects. Despite the better control over the channel, the multi-gate devices are less efficient at controlling the electric fields from the source and drain regions. The electric fields from the source and drain regions result in short-channel effects such as an increased leakage current at a given gate voltage in the subthreshold region of device operation. As mentioned above, prior solutions to minimize this leakage current includes utilizing dopants in the channel that have unwanted effects such as increasing the threshold voltage of the transistor.
  • SUMMARY
  • A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is an illustration of a perspective view of an embodiment of a multi-gate pMOS device using substrate band gap engineering.
  • FIG. 2 is an illustration of a perspective view of an embodiment of a multi-gate pMOS device on an insulating substrate using substrate band gap engineering.
  • FIG. 3A-3F is an illustration of perspective views of a method of fabricating an embodiment of a multi-gate pMOS device using substrate band gap engineering.
  • FIG. 4A-4D is an illustration of perspective views of a method of fabricating an embodiment of a multi-gate pMOS device on an insulating substrate using substrate band gap engineering.
  • DETAILED DESCRIPTION
  • In the following description of substrate band gap engineered multi-gate pMOS devices numerous specific details are set forth in order to provide an understanding of the claims. One of ordinary skill in the art will appreciate that these specific details are not necessary in order to practice the disclosure. In other instances, well-known semiconductor fabrication processes and techniques have not been set forth in particular detail in order to prevent obscuring the present invention.
  • Embodiments of the present invention include band gap engineered multi-gate pMOS devices. In particular embodiments of the multi-gate pMOS device, the device is fabricated with a fin or body formed from a layer of material deposited over a substrate and a portion of the substrate. The layer of material deposited over a substrate and the substrate are selected such that the band gap of the material deposited over the substrate is narrower than that of the substrate. The difference in the band gap creates a band gap offset between the valence bands of the two layers, which adds an extra barrier for the holes to mount in order to move into the substrate. The result of the band gap offset is to minimize the leakage current into the substrate. Another aspect of embodiments of a pMOS device according to the present invention includes forming a source region and a drain region fully contained within the layer of material deposited over the substrate. Because the source region and drain region are fully contained within the layer of material deposited over a substrate the leakage current in the substrate is minimized.
  • Embodiments of the present invention also include a gate structure that is electrically coupled with the layer of material deposited over a substrate and at least a part of the substrate portion of the fin. The band gap offset between the materials of the fin changes the flat-band voltage of this part of the device. The result is a lower threshold voltage in the material deposited over the substrate than the threshold voltage of the substrate portion of the fin because of the band gap offset between the two materials. The higher threshold voltage in the substrate portion of the fin helps to further minimize the leakage current. Minimizing the transistor leakage current provides for lower power, high performance transistors. Moreover, the ability to better control the leakage current allows the transistor to be scaled to smaller dimensions.
  • FIG. 1 shows an embodiment of a substrate band gap engineered multi-gate pMOS device 100. In the FIG. 1 embodiment, a fin or body 105 is formed from two materials. In an embodiment, the fin 105 has a lower portion 110 formed from a substrate and an upper portion 115 formed from a semiconductor material that has a band gap at least 0.3 electron volts (eV) narrower than the substrate portion 110. In embodiments of the pMOS device 100 according to the present invention the materials for the upper portion 115 and the lower portion 110 are selected such that the band gap offset between the upper portion 115 and the lower portion 110 is equal to or greater than 0.3 eV. For example, in one embodiment the materials of the upper portion 115 and the lower portion 110 are selected such that the band gap of the upper portion 115 is approximately 0.3 eV narrower than that of the material selected for the lower portion 110. In another embodiment, the band-gap offset between the upper portion 115 and the lower portion 110 is approximately 0.4 eV.
  • The difference in the band gap of the lower portion 110 and an upper portion 115 creates an extra barrier for holes to overcome before escaping into the lower portion 110. This extra barrier results in reducing the number of holes that can travel from the upper portion to the lower portion; therefore, the leakage current is reduced. Having a lower portion 110 with a band gap equal to or greater than 0.3 eV larger than an upper portion 115 also creates a lower threshold voltage in the upper portion 115 than in the lower portion 110. The difference in the threshold voltages between the upper portion 115 and the lower portion 110 increases in the same amount as the band-gap offset between the two portions. The resulting higher flat-band voltage in the lower portion 110 further minimizes the leakage current in the lower portion 110.
  • In an embodiment of a multi-gate pMOS device 100 according to the present invention, an epitaxial semiconductor layer forms an upper portion 115 having a band gap approximately 0.3 eV to approximately 0.4 eV narrower than the band gap of the lower portion 110 that is positioned over the lower portion 110. In an embodiment of the present invention the upper portion 115 is formed from a composition of silicon-germanium. One embodiment of the pMOS device 100 includes the use of silicon-germanium with 20-50 atomic percent of germanium for the upper portion 115 and silicon for the lower portion 110. In an embodiment using silicon-germanium, the silicon-germanium includes 30 atomic percent of germanium. Another embodiment of pMOS device 100 using silicon-germanium contains 20 atomic percent of germanium in the silicon-germanium upper portion 115. In other embodiments of a pMOS device 100 of the present invention, a substrate 107 may be formed of any semiconductor material having a band gap equal to or greater than 0.3 eV than an upper portion 115.
  • In some embodiments the thickness of the upper portion 115 is 3 to 20 times thicker than the lower portion 110. In one embodiment the thickness of the upper portion 115 is between approximately 200 angstroms (Å) and 800 Å. Embodiments of a pMOS device 100 according to the present invention include the lower portion 110 having a thickness between approximately 10 Å and 200 Å. An embodiment of the pMOS device 100 includes an upper portion 115 having a thickness of approximately 450 Å and a lower portion have a thickness of 50 Å.
  • The embodiment illustrated in FIG. 1 of a substrate band gap engineered multi-gate pMOS device 100 further includes a gate structure 120. In an embodiment, a gate structure 120 resides over a gate insulator 125. Some embodiments of a substrate band gap engineered multi-gate pMOS device 100 include a gate insulator 125 positioned over shallow trench isolation (STI) regions 130 formed on a substrate 107. In an embodiment, a gate structure 120 may be fabricated as illustrated in FIG. 1 such that the substrate band gap engineered multi-gate pMOS device 100 is a tri-gate transistor. In a tri-gate transistor embodiment the gate structure 120 is formed on the top surface of a fin 105 and on the sidewalls of a fin 105. In a FinFET embodiment of the pMOS device 100 according to the present invention, the gate structure 120 is formed on laterally opposite sidewalls of a fin 105. In other embodiments, a gate structure 120 may be fabricated in such a manner as to form other dual-gate or omega-gate devices.
  • FIG. 2 illustrates another embodiment of a substrate band gap engineered multi-gate pMOS device 100 fabricated in a semiconductor-on-insulator (SOI) configuration but is otherwise similar to the FIG. 1 embodiment. In an embodiment of an SOI configuration, substrate 205 is formed from an insulator 210 and a carrier 215. The insulator 210 may be any dielectric material such as silicon dioxide. The carrier 215 of an SOI configuration may be any semiconductor, insulator, or metallic material.
  • In the embodiments depicted in FIGS. 1 and 2, the multi-gate pMOS device 100 has a gate insulator 125. Other embodiments according to the present invention include a pMOS device 100 without a gate insulator 125. In one embodiment the gate structure 120 is in direct contact with the fin 105. In the tri-gate embodiments as illustrated in FIGS. 1 and 2 the gate insulator 125 covers the top and the sidewalls of the fin 105. In other embodiments, such as FinFET, a gate dielectric layer 125 is only formed on the sidewalls of the fin 105. Gate insulator 125 may be made of any dielectric material compatible with materials forming a fin 105 and materials forming a gate structure 120. In an embodiment of the present invention, the gate dielectric layer 125 may be formed from a silicon dioxide (SiO2), a silicon oxynitride (SiOxNy), or a silicon nitride (Si3N4) dielectric layer. In one particular embodiment of the pMOS device 100, the gate dielectric layer 125 is formed from a silicon oxynitride layer formed to a thickness of 5-20 Å. In another embodiment, a gate dielectric layer 125 is formed from a high K gate dielectric layer such as a metal oxide dielectric, including but not limited to tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, or aluminum oxide. Gate dielectric layer 125 may also be formed from materials including other types of high K dielectrics, such as lead zirconium titanate (PZT).
  • In certain embodiments of the pMOS device 100, a gate structure 120 is formed on and adjacent to the gate dielectric layer 125. When formed according to an embodiment of the present invention, a gate structure 120 has a pair of laterally opposite sidewalls separated by a distance defining the gate length (Lg) of the pMOS device 100. In an embodiment of the present invention, the gate electrode may be formed of any material having an appropriate work function. A gate structure 120 in an embodiment of the pMOS device 100 of the present invention is formed from a metal gate electrode, such as tungsten, tantalum nitride, titanium silicide, nickel silicide, or cobalt silicide. Another embodiment of the present invention includes a gate structure 120 fabricated from a composite stack of thin films such as a metal/polycrystalline silicon electrode.
  • Embodiments of the pMOS device 100 include a gate structure 120 formed to couple with the top of fin 105, the sidewalls of an upper portion 115, and the sidewalls of a lower portion 110. In a tri-gate embodiment, the gate structure 120 covers the top of a fin 105 and extends between approximately 5 Å and 200 Å below the top of a lower portion 110. In another embodiment, the gate structure 120 extends 25 Å below the top of a lower portion 110. In a FinFET embodiment only the sidewall portion of a gate structure 120 is used; therefore, the top of a fin 105 is not covered by a portion of a gate structure. In a FinFET embodiment of a pMOS device 100 according to the present invention a gate structure includes sidewalls to electrically couple to an upper portion 115 and a lower portion 110. One FinFET embodiment of the pMOS device 100 includes a gate structure that extends approximately 5 Å and 200 Å below the top of the lower portion 110. In another FinFET embodiment of the pMOS device 100 a gate structure extends 25 Å below the top of a lower portion 110.
  • The embodiments illustrated in FIGS. 1 and 2 also include a source region 135 and a drain region 140 formed in the upper portion 115 on opposite sides of a gate structure 120. In an embodiment of a substrate band gap engineered pMOS device 100, a source region 135 and a drain region 140 are fully contained within an upper portion 115. Fully containing a source region 135 and a drain region 140 within an upper portion 115 also aids in minimizing the leakage current in a lower portion 110. Some embodiments of the present invention have a doping concentration of 1×1019-1×1021 atoms/cm3. An embodiment of the pMOS device 100 includes a source region 135 and a drain region 140 formed of a uniform doping concentration. In another embodiment, a source region 135 and a drain region 140 include subregions of different doping concentrations or doping profiles such as tip regions. In an embodiment including tip regions, sidewall spacers are used to create tip regions.
  • As shown in FIGS. 1 and 2, a source region 135 and a drain region 140 define a channel region in the fin 105 of the pMOS device. In an embodiment of the present invention a channel region is undoped. Another embodiment of the pMOS device 100 includes a channel region doped to a concentration as high as 1×1019 atoms/cm3. Some embodiments of the present invention include halo implants implanted below the channel region of a half order magnitude greater than the doping concentration of the channel region and the same conductivity type as the channel region. The halo implants work to further minimize the leakage of a pMOS device 100. Other embodiments of the present invention include punchthrough implants or other techniques to combat short-channel effects.
  • A method of fabricating a pMOS device 100 on a substrate in accordance with an embodiment of the present invention as shown in FIG. 1 is illustrated in FIGS. 3A-3F. In certain embodiments of the present invention, the substrate 107 of FIG. 3A can be a semiconductor layer, such as a silicon monocrystalline substrate. As shown in FIG. 3A, an upper portion layer 305 is deposited over a substrate 107. In one embodiment the upper portion layer 305 is formed from part of the substrate 107. Another embodiment of the pMOS device 100 includes an upper portion layer 305 that is an epitaxial layer formed on substrate 107. In an embodiment, the upper portion layer 305 is formed to a thickness between approximately 200 Å and 800 Å. One embodiment of the pMOS device 100 includes an upper portion layer 305 formed to a thickness of approximately 450 Å. Another embodiment of the pMOS device 100 includes the pMOS device 100 including an upper portion layer 305 formed to a thickness of approximately 600 Å. In certain embodiments of the present invention, the upper portion layer 305 is a composition of a silicon-germanium alloy having a band gap at least 0.3 eV narrower than the substrate 107. In an embodiment, the upper portion layer 305 includes an epitaxial region with p-type conductivity with an impurity concentration level between 1×1016-1×1019 atoms/cm3. In another embodiment of the present invention the upper portion layer 305 is an undoped silicon-germanium alloy layer having a band gap at least 0.4 eV narrower than the band gap of the substrate 107.
  • In embodiments of the present invention, well regions of upper portion layer 305 are doped to p-type conductivity with a concentration level between about 1×1016-1×1019 atoms/cm3. Upper portion layer 305 can be doped by, for example, ion-implantation. The doping level of the upper portion layer 305 at this point may determine the doping level of the channel region of a pMOS device 100.
  • As shown in FIG. 3B, a masking layer 310 is used to define the active regions of the pMOS device 100 on the upper portion layer 305. A masking layer 310 is used to define the active regions of an embodiment of a pMOS device 100 of the present invention. The masking layer 310 may be any material suitable for defining an upper portion layer 305 and a substrate 107. In an embodiment of the present invention, masking layer 310 is a lithographically defined photo resist. In another embodiment, masking layer 310 is formed of a dielectric material that has been lithographically defined and then etched. In an embodiment, masking layer 310 is a hard mask. In a certain embodiment, masking layer 310 may be a composite stack of materials, such as an oxide/nitride stack. Once masking layer 310 has been defined, a fin or body 105 is then defined, as shown in FIG. 3C, by an etching technique. The fin 105 having an upper portion 115 and a lower portion 110. In certain embodiments of the present invention, anisotropic plasma etch, or RIE, is used to define a fin 105. Moreover, FIG. 3C shows the upper portion layer 305 and a portion of the substrate 107 etched to form recesses or trenches 320 on the substrate 107 in alignment with the outside edges of masking portion 310. The trenches 320 are etched to a depth sufficient to isolate an adjacent transistor from the other. In an embodiment of the pMOS device 100 the trench 320 between approximately 500 Å and 2000 Å deep in the substrate 107. In one embodiment the trench 320 is etched to a depth of 1500 Å in the substrate 107.
  • As shown in FIG. 3D, the trenches 320 are filled with a dielectric to form STI regions 130 on substrate 107. In an embodiment of the present invention, a liner of oxide or nitride on the bottom and sidewalls of the trenches 320 is formed. Next, the trenches 320 are filled by blanket depositing an oxide over the liner by, for example, a high-density plasma (HDP) chemical vapor deposition process. The deposition process will also form dielectric on the top surfaces of the mask portions 310. The fill dielectric layer can then be removed from the top of mask portions 310 by chemical, mechanical, or electrochemical, polishing techniques. The polishing is continued until the mask portions 310 are revealed, forming STI regions 130. In an embodiment of the present invention, as shown in FIG. 3D, the mask portions 310 are selectively removed. In other embodiments, the mask portions 310 are retained through subsequent processes.
  • In the embodiment shown in FIG. 3E, the STI regions 130 are etched back or recessed to form the sidewalls of the fin 105. STI regions 130 are etched back with an etchant, which does not significantly etch the fin 105. In an embodiment, STI regions 130 are recessed such that the amount of the lower portion 110 that is exposed is within a range between 200 Å and 800 Å. In one embodiment, STI regions 130 are recessed using an anisotropic etch followed by an isotropic etch to remove the STI dielectric from the sidewalls of a fin 105 until 500 Å of the substrate 107 is exposed. STI regions 130 are recessed by an amount dependent on the desired channel width of the pMOS device 100 formed.
  • A gate dielectric layer 125, as shown in FIG. 3F, is formed on each upper portion 115 and lower portion 110 of fin 105 in a manner dependent on the type of device (dual-gate, tri-gate, etc.). In an embodiment of the present invention, a gate dielectric layer 125 is formed on the top surface of an upper portion 115, as well as on the laterally opposite sidewalls of a fin 105. In certain embodiments, such as dual-gate embodiments, the gate dielectric 125 is not formed on the top surface of the upper portion 115, but on the top surface of hard mask. The gate dielectric layer 125 can be a deposited dielectric or a grown dielectric. In an embodiment of the present invention, the gate dielectric layer 125 is a silicon dioxide dielectric film grown with a dry/wet oxidation process. In an embodiment of the present invention, the gate dielectric film 125 is a deposited high dielectric constant (high-K) metal oxide dielectric, such as tantalum pentaoxide, titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, or another high-K dielectric, such as barium strontium titanate (BST). A high-K film can be formed by well-known techniques, such as chemical vapor deposition (CVD) and atomic layer deposition (ALD).
  • As shown in FIG. 3F, a gate structure 120 is formed on the pMOS device 100. In an embodiment of the present invention, the gate structure 120 is formed on the gate dielectric layer 125 formed on and adjacent to the top surface of the upper portion 115 and is formed on and adjacent to the gate dielectric 125 formed on and adjacent to the sidewalls of fin 105, which includes the sidewalls of the upper portion 115 and the lower portion 110. The gate structure 120 may be formed to a thickness between 200-3000 Å. In an embodiment, the gate structure 120 has a thickness of at least three times the height of a fin 105. In an embodiment of the present invention, the gate electrode is a mid-gap metal gate electrode such as, tungsten, tantalum nitride, titanium nitride or titanium silicide, nickel silicide, or cobalt silicide. In an embodiment of the present invention, gate structure 120 is formed by techniques including but not limited to blanket depositing a gate structure 120 material over the substrate 107 and then patterning the gate electrode material through photolithography and etch. In other embodiments of the present invention, “replacement gate” methods are used to form the gate structure 120.
  • Source region 135 and drain region 140 for the transistor are formed in upper portion 115 on opposite sides of gate structure 120, as shown in FIG. 3F. In an embodiment of a pMOS device according to the present invention, a source region 135 and a drain region 140 resides on opposite sides of a channel. An embodiment of the present invention the source region 135 and drain region 140 region are completely contained in the upper portion 115. In an embodiment of the present invention, a source region 135 and a drain region 140 include tip or source/drain extension regions. For an embodiment of a pMOS device 100 of the present invention, an upper portion 115 is doped to a p-type conductivity and to a concentration between 1×1019-1×1021 atoms/cm3. At this point an embodiment of a pMOS device 100 according to the present invention is substantially complete and only device interconnection remains.
  • A method of fabricating a substrate band gap engineered pMOS device 100 on an insulating substrate in accordance with an embodiment of the present invention as shown in FIG. 2 is illustrated in FIGS. 4A-4D. Forming a pMOS device 100 on an insulating substrate according to an embodiment of the present invention may use similar techniques and materials as described for the embodiments illustrated by FIGS. 3A-3F. In an embodiment of the present invention, shown in FIG. 4A, the SOI substrate 205 includes an insulating layer 210, such as a silicon dioxide film or silicon nitride film, formed over a lower silicon carrier 215. Insulating layer 210 isolates lower portion layer 410 and upper portion layer 305 from carrier 205, and in an embodiment is formed to a thickness between 200-2000 Å. In an embodiment, insulating layer 210 is sometimes referred to as a “buried oxide” layer.
  • Although the upper portion layer 305 is ideally a silicon-germanium alloy (SiGe), other types of semiconductor films may be used so long as the band gap of the upper portion layer 305 is at least 0.3 eV narrower than that of the lower portion layer 410. Such semiconductor films may include compositions of any III-V semiconductor compounds that results in at least a 0.3 eV narrower band gap than that of the lower portion layer 410.
  • In an embodiment of the present invention, upper portion layer 305 is an intrinsic (i.e., undoped) silicon germanium alloy film having 30 atomic percent of germanium. In other embodiments, upper portion layer 305 is doped to p-type conductivity with a concentration level between 1×1016-1×1019 atoms/cm3. Upper portion layer 305 can be in-situ doped (i.e., doped while it is deposited) or doped after it is formed on substrate 107 by for example ion-implantation. The doping level of the upper body layer 305 at this point can determine the doping level of the channel region of the device. Upper body layer 305 may be formed on insulator 210 in any well-known method. In one method of forming a silicon-on-insulator substrate, known as the separation by implantation of oxygen (SIMOX) technique. Another technique currently used to form SOI substrates is an epitaxial silicon film transfer technique generally referred to as bonded SOI or SMARTCUT.
  • Similar to the process described in FIGS. 3A-3F, a masking layer 310 is used to define the active regions of a pMOS device 100. As shown in FIG. 4B, once a masking layer 310 has been defined, a fin 105 is then defined by an etching technique to expose the sidewalls of a body portion 115 and a substrate portion 110. In an embodiment of the present invention, as shown in FIG. 4C, masking layer 310 is removed from the upper portion 115. In other embodiments, such as for particular dual-gate or FinFET designs, masking layer 310 is not removed.
  • In a particular embodiment of the present invention, the upper portion 115 is a silicon-germanium layer having an atomic percent of germanium within a range of about 20 atomic percent to about 50 atomic percent. In an embodiment the amount of germanium in a silicon-germanium upper portion 115 is within a range of about 25 to 35 atomic percent. In other embodiments, the germanium concentration is about 50 percent. Ideally, the formation process for creating the silicon germanium layer is capable of producing a single crystalline upper portion 115. As in the process described in FIGS. 3A-3F, the upper portion 115 is grown to the desired thickness, some embodiments include in-situ impurity doping. In an embodiment of the present invention, a SiGe is grown to a thickness in the range of approximately 200 Å and 800 Å. One embodiment of the pMOS device 100 includes an upper portion layer 305 formed to a thickness of approximately 450 Å. In certain embodiments of the present invention, various regions over the substrate are selectively and iteratively masked and different devices such as nMOS devices, other pMOS devices, or other circuit components may be formed.
  • As shown in FIG. 4D, a gate insulator 125, gate structure 120, source regions 135, and drain regions 140 are formed following embodiments analogous to those previously described above. At this point an embodiment of a pMOS device 100 of the present invention formed on a SOI substrate is substantially complete and only device interconnection remains.
  • Although the invention has been described in language specific to structural features and/or methodological acts, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as particularly graceful implementations of the claimed invention.

Claims (30)

1. A multi-gate transistor comprising:
a fin having an upper portion and a lower portion, said upper portion having a first band gap and said lower portion having a second band gap, said first band gap and said second band gap designed to inhibit current flow from said upper portion to said lower portion;
a gate structure having sidewalls electrically coupled with said upper portion and said lower portion; and
a substrate positioned below said fin.
2. The multi-gate transistor of claim 1 wherein said first band gap is at least 0.3 electron volts narrower than said second band gap.
3. The multi-gate transistor of claim 1 wherein said gate structure includes a top portion positioned over said fin.
4. The multi-gate transistor of claim 1 wherein said lower portion is formed from said substrate.
5. The multi-gate transistor of claim 1 wherein a source region and a drain region are contained within said upper portion.
6. The multi-gate transistor of claim 1 further comprising an insulator positioned between said fin and said substrate.
7. The multi-gate transistor of claim 2 wherein said upper portion is composed of silicon-germanium having approximately 30 atomic percent of germanium.
8. The multi-gate transistor of claim 4 wherein said second band gap is 0.4 electron volts wider than said first band gap.
9. The multi-gate transistor of claim 6 wherein said insulator is formed using a bonded semiconductor-on-insulator (SOI) technique.
10. A multi-gate device comprising:
an upper portion having a first band gap, said upper portion configured to contain a source region and a drain region;
a lower portion having a second band gap wider than said first band gap and positioned below said upper portion to form a fin;
a gate structure having a first portion and a second portion, said first portion and second portion positioned on opposing sides of said fin and positioned to cover a portion of said upper portion and a portion of said lower portion; and
a substrate positioned below said lower portion.
11. The multi-gate device of claim 10 wherein said gate structure further comprises a third portion positioned over said upper portion.
12. The multi-gate device of claim 10 further comprising a channel region in said upper portion located between said source region and said drain region, said channel region doped to a concentration level of approximately 1×1019 atoms/cm3.
13. The multi-gate device of claim 10 wherein said lower portion is formed from said substrate.
14. The multi-gate device of claim 10 further comprising an insulator between said lower portion and said substrate.
15. The multi-gate device of 10 further comprising a gate insulator positioned between said gate structure and said fin.
16. The multi-gate device of claim 11 wherein said first band gap is at least 0.3 electron volts narrower than said upper portion.
17. The multi-gate device of claim 11 wherein said gate structure is formed from a metal.
18. The multi-gate device of claim 16 wherein said upper portion is formed from silicon-germanium.
19. The multi-gate device of claim 18 wherein said upper portion contains approximately 20 atomic percent of germanium.
20. The multi-gate device of claim 19 wherein said substrate is composted of silicon.
21. A method comprising:
positioning an upper portion having a first band gap over a lower portion to form a fin over a substrate, said lower portion having a second band gap wider than said first band gap;
forming a first gate and a second gate on opposite sides of said fin, said first and said second gate formed to electrically couple with said upper portion and said lower portion; and
creating a source and drain region within said upper portion on opposite sides of a channel.
22. The method of claim 21 wherein said upper portion is formed of silicon-germanium composed of 30 atomic percent of germanium.
23. The method of claim 21 further comprising forming a third gate positioned over said fin.
24. The method of claim 21 wherein the upper portion is formed using a III-V semiconductor material such that said second band gap is at least 0.3 electron volts wider than said first band gap.
25. The method of claim 21 further comprising implanting ions below said channel to form halo implants of the same conductivity type as said channel, said halo implants having a concentration of said ions of a half order greater than said channel.
26. The method of claim 21 further comprising forming an insulating layer between said lower portion and said substrate.
27. The method of claim 23 further comprising forming a gate insulator between said gates and said fin.
28. The method of claim 23 wherein said upper portion is formed to a thickness between 200 and 2000 angstroms.
29. The method of claim 23 wherein said first gate, said second gate, and said third gate are formed from titanium nitride.
30. The method of claim 28 wherein said fin is approximately 450 angstroms thick.
US11/393,168 2006-03-29 2006-03-29 Substrate band gap engineered multi-gate pMOS devices Abandoned US20070235763A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US11/393,168 US20070235763A1 (en) 2006-03-29 2006-03-29 Substrate band gap engineered multi-gate pMOS devices
US12/757,917 US8169027B2 (en) 2006-03-29 2010-04-09 Substrate band gap engineered multi-gate pMOS devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/393,168 US20070235763A1 (en) 2006-03-29 2006-03-29 Substrate band gap engineered multi-gate pMOS devices

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/757,917 Division US8169027B2 (en) 2006-03-29 2010-04-09 Substrate band gap engineered multi-gate pMOS devices

Publications (1)

Publication Number Publication Date
US20070235763A1 true US20070235763A1 (en) 2007-10-11

Family

ID=38574283

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/393,168 Abandoned US20070235763A1 (en) 2006-03-29 2006-03-29 Substrate band gap engineered multi-gate pMOS devices
US12/757,917 Expired - Fee Related US8169027B2 (en) 2006-03-29 2010-04-09 Substrate band gap engineered multi-gate pMOS devices

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/757,917 Expired - Fee Related US8169027B2 (en) 2006-03-29 2010-04-09 Substrate band gap engineered multi-gate pMOS devices

Country Status (1)

Country Link
US (2) US20070235763A1 (en)

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080054347A1 (en) * 2006-09-06 2008-03-06 Yin-Pin Wang Composite stressors in MOS devices
US20090085114A1 (en) * 2007-09-28 2009-04-02 Muhammad Nawaz Semiconductor Structure
US20100308414A1 (en) * 2009-06-04 2010-12-09 International Business Machines Corporation Cmos inverter device
JP2011505697A (en) * 2007-11-30 2011-02-24 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Heterostructure inverted T-shaped field effect transistor
CN103367162A (en) * 2012-04-08 2013-10-23 中国科学院微电子研究所 Manufacturing method of fin-shaped field effect transistor
WO2014004034A1 (en) * 2012-06-29 2014-01-03 Intel Corporation Preventing isolation leakage in iii-v devices
WO2014100010A1 (en) * 2012-12-17 2014-06-26 Synopsys, Inc. Increasing ion/ioff ratio in finfets and nano-wires
CN104282558A (en) * 2013-07-02 2015-01-14 中芯国际集成电路制造(上海)有限公司 Knot-free nanowire FinFET and manufacturing method thereof
WO2015047354A1 (en) * 2013-09-27 2015-04-02 Intel Corporation Improved cladding layer epitaxy via template engineering for heterogeneous integration on silicon
CN104934474A (en) * 2014-03-19 2015-09-23 台湾积体电路制造股份有限公司 Combination FinFET and Methods of Forming Same
US9177894B2 (en) 2012-08-31 2015-11-03 Synopsys, Inc. Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
CN105164809A (en) * 2013-06-26 2015-12-16 美商新思科技有限公司 Finfet with heterojunction and improved channel control
US20150380559A1 (en) * 2013-12-27 2015-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium-Containing FinFET and Methods for Forming the Same
US9275905B1 (en) * 2015-01-28 2016-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming semiconductor structure with anti-punch through structure
US9379018B2 (en) 2012-12-17 2016-06-28 Synopsys, Inc. Increasing Ion/Ioff ratio in FinFETs and nano-wires
WO2016190858A1 (en) * 2015-05-27 2016-12-01 Intel Corporation Apparatus and methods to create a buffer which extends into a gated region of a transistor
WO2016204737A1 (en) * 2015-06-16 2016-12-22 Intel Corporation A transistor with a subfin layer
US9817928B2 (en) 2012-08-31 2017-11-14 Synopsys, Inc. Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
US20180047847A1 (en) * 2015-09-30 2018-02-15 International Business Machines Corporation Tensile strained high percentage silicon germanium alloy finfets
TWI629716B (en) * 2015-12-04 2018-07-11 台灣積體電路製造股份有限公司 Semiconductor structure and method of forming the same
TWI643345B (en) * 2011-09-30 2018-12-01 英特爾公司 Tungsten gates for non-planar transistors
US20190122972A1 (en) * 2016-06-29 2019-04-25 Intel Corporation Wide bandgap group iv subfin to reduce leakage
US10283640B2 (en) 2011-10-01 2019-05-07 Intel Corporation Source/drain contacts for non-planar transistors
US11189729B2 (en) * 2016-09-26 2021-11-30 Tessera, Inc. Forming a sacrificial liner for dual channel devices
US11854688B2 (en) * 2020-02-19 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100598099B1 (en) * 2004-02-24 2006-07-07 삼성전자주식회사 Vertical channel fin fet having a damascene gate and method for fabricating the same
US9159626B2 (en) * 2012-03-13 2015-10-13 United Microelectronics Corp. FinFET and fabricating method thereof
US20130267073A1 (en) * 2012-04-08 2013-10-10 Huaxiang Yin Method of Manufacturing Fin Field Effect Transistor
US8866230B2 (en) * 2012-04-26 2014-10-21 United Microelectronics Corp. Semiconductor devices
US8592902B1 (en) 2012-09-21 2013-11-26 Texas Instrument Incorporated Semiconductor structure that reduces the effects of gate cross diffusion and method of forming the structure
US8815668B2 (en) 2012-12-07 2014-08-26 International Business Machines Corporation Preventing FIN erosion and limiting Epi overburden in FinFET structures by composite hardmask
US20140167162A1 (en) 2012-12-13 2014-06-19 International Business Machines Corporation Finfet with merge-free fins
US8828818B1 (en) 2013-03-13 2014-09-09 Samsung Electronics Co., Ltd. Methods of fabricating integrated circuit device with fin transistors having different threshold voltages
US9024392B2 (en) * 2013-07-03 2015-05-05 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-port SRAM manufacturing
US9525069B2 (en) 2014-04-21 2016-12-20 Globalfoundries Inc. Structure and method to form a FinFET device
CN105280496B (en) 2014-06-05 2019-06-11 联华电子股份有限公司 Semiconductor element and preparation method thereof with fin structure
US9922880B2 (en) 2014-09-26 2018-03-20 Qualcomm Incorporated Method and apparatus of multi threshold voltage CMOS
TWI629790B (en) 2015-01-26 2018-07-11 聯華電子股份有限公司 Semiconductor device and method for fabricating the same
US9583626B2 (en) 2015-04-29 2017-02-28 International Business Machines Corporation Silicon germanium alloy fins with reduced defects
EP3314666A4 (en) 2015-06-26 2019-02-13 INTEL Corporation High-mobility semiconductor source/drain spacer
WO2017052619A1 (en) * 2015-09-25 2017-03-30 Intel Corporation High mobility field effect transistors with a retrograded semiconductor source/drain
DE112015006945T5 (en) 2015-09-25 2018-06-21 Intel Corporation High electron mobility transistors with heterojunction dopant diffusion barrier
CN108028281B (en) 2015-09-25 2022-04-15 英特尔公司 High mobility field effect transistor with offset semiconductor source/drain pads
WO2017052608A1 (en) 2015-09-25 2017-03-30 Intel Corporation High-electron-mobility transistors with counter-doped dopant diffusion barrier
CN106558612B (en) * 2015-09-28 2019-07-16 中国科学院微电子研究所 A kind of p-type fin formula field effect transistor and manufacturing method
WO2017218015A1 (en) 2016-06-17 2017-12-21 Intel Corporation High-mobility field effect transistors with wide bandgap fin cladding

Citations (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5804848A (en) * 1995-01-20 1998-09-08 Sony Corporation Field effect transistor having multiple gate electrodes surrounding the channel region
US5844278A (en) * 1994-09-14 1998-12-01 Kabushiki Kaisha Toshiba Semiconductor device having a projecting element region
US6018176A (en) * 1995-05-26 2000-01-25 Samsung Electronics Co., Ltd. Vertical transistor and memory cell
US6066869A (en) * 1997-10-06 2000-05-23 Micron Technology, Inc. Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6459123B1 (en) * 1999-04-30 2002-10-01 Infineon Technologies Richmond, Lp Double gated transistor
US6472258B1 (en) * 2000-11-13 2002-10-29 International Business Machines Corporation Double gate trench transistor
US6525403B2 (en) * 2000-09-28 2003-02-25 Kabushiki Kaisha Toshiba Semiconductor device having MIS field effect transistors or three-dimensional structure
US6562665B1 (en) * 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
US6583469B1 (en) * 2002-01-28 2003-06-24 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same
US6611029B1 (en) * 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6630388B2 (en) * 2001-03-13 2003-10-07 National Institute Of Advanced Industrial Science And Technology Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
US6630386B1 (en) * 2000-07-18 2003-10-07 Advanced Micro Devices, Inc CMOS manufacturing process with self-amorphized source/drain junctions and extensions
US6635909B2 (en) * 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
US6642090B1 (en) * 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
US6657259B2 (en) * 2001-12-04 2003-12-02 International Business Machines Corporation Multiple-plane FinFET CMOS
US6689650B2 (en) * 2001-09-27 2004-02-10 International Business Machines Corporation Fin field effect transistor with self-aligned gate
US6770516B2 (en) * 2002-09-05 2004-08-03 Taiwan Semiconductor Manufacturing Company Method of forming an N channel and P channel FINFET device on the same semiconductor substrate
US6787402B1 (en) * 2001-04-27 2004-09-07 Advanced Micro Devices, Inc. Double-gate vertical MOSFET transistor and fabrication method
US6794718B2 (en) * 2002-12-19 2004-09-21 International Business Machines Corporation High mobility crystalline planes in double-gate CMOS technology
US6798000B2 (en) * 2000-07-04 2004-09-28 Infineon Technologies Ag Field effect transistor
US6800910B2 (en) * 2002-09-30 2004-10-05 Advanced Micro Devices, Inc. FinFET device incorporating strained silicon in the channel region
US6803631B2 (en) * 2003-01-23 2004-10-12 Advanced Micro Devices, Inc. Strained channel finfet
US6821834B2 (en) * 2002-12-04 2004-11-23 Yoshiyuki Ando Ion implantation methods and transistor cell layout for fin type transistors
US6833588B2 (en) * 2002-10-22 2004-12-21 Advanced Micro Devices, Inc. Semiconductor device having a U-shaped gate structure
US6835614B2 (en) * 2001-05-24 2004-12-28 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
US6869868B2 (en) * 2002-12-13 2005-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a MOSFET device with metal containing gate structures
US6885055B2 (en) * 2003-02-04 2005-04-26 Lee Jong-Ho Double-gate FinFET device and fabricating method thereof
US20050116218A1 (en) * 2003-11-24 2005-06-02 Samsung Electronics Co., Ltd. Non-planar transistor having germanium channel region and method of manufacturing the same
US20060076625A1 (en) * 2004-09-25 2006-04-13 Lee Sung-Young Field effect transistors having a strained silicon channel and methods of fabricating same
US7115945B2 (en) * 2003-06-23 2006-10-03 Sharp Laboratories Of America, Inc. Strained silicon fin structure
US20070032024A1 (en) * 2005-08-03 2007-02-08 Advanced Micro Devices, Inc. Methods for fabricating a stressed MOS device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7863674B2 (en) * 2003-09-24 2011-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-gate transistors formed on bulk substrates

Patent Citations (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5844278A (en) * 1994-09-14 1998-12-01 Kabushiki Kaisha Toshiba Semiconductor device having a projecting element region
US5804848A (en) * 1995-01-20 1998-09-08 Sony Corporation Field effect transistor having multiple gate electrodes surrounding the channel region
US5899710A (en) * 1995-01-20 1999-05-04 Sony Corporation Method for forming field effect transistor having multiple gate electrodes surrounding the channel region
US6018176A (en) * 1995-05-26 2000-01-25 Samsung Electronics Co., Ltd. Vertical transistor and memory cell
US6066869A (en) * 1997-10-06 2000-05-23 Micron Technology, Inc. Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
US6459123B1 (en) * 1999-04-30 2002-10-01 Infineon Technologies Richmond, Lp Double gated transistor
US6798000B2 (en) * 2000-07-04 2004-09-28 Infineon Technologies Ag Field effect transistor
US6630386B1 (en) * 2000-07-18 2003-10-07 Advanced Micro Devices, Inc CMOS manufacturing process with self-amorphized source/drain junctions and extensions
US6525403B2 (en) * 2000-09-28 2003-02-25 Kabushiki Kaisha Toshiba Semiconductor device having MIS field effect transistors or three-dimensional structure
US6562665B1 (en) * 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6472258B1 (en) * 2000-11-13 2002-10-29 International Business Machines Corporation Double gate trench transistor
US6630388B2 (en) * 2001-03-13 2003-10-07 National Institute Of Advanced Industrial Science And Technology Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
US6787402B1 (en) * 2001-04-27 2004-09-07 Advanced Micro Devices, Inc. Double-gate vertical MOSFET transistor and fabrication method
US6835614B2 (en) * 2001-05-24 2004-12-28 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
US6689650B2 (en) * 2001-09-27 2004-02-10 International Business Machines Corporation Fin field effect transistor with self-aligned gate
US6815277B2 (en) * 2001-12-04 2004-11-09 International Business Machines Corporation Method for fabricating multiple-plane FinFET CMOS
US6657259B2 (en) * 2001-12-04 2003-12-02 International Business Machines Corporation Multiple-plane FinFET CMOS
US6583469B1 (en) * 2002-01-28 2003-06-24 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same
US6812075B2 (en) * 2002-01-28 2004-11-02 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same
US6635909B2 (en) * 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
US6849884B2 (en) * 2002-03-19 2005-02-01 International Business Machines Corporation Strained Fin FETs structure and method
US6642090B1 (en) * 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
US6770516B2 (en) * 2002-09-05 2004-08-03 Taiwan Semiconductor Manufacturing Company Method of forming an N channel and P channel FINFET device on the same semiconductor substrate
US6800910B2 (en) * 2002-09-30 2004-10-05 Advanced Micro Devices, Inc. FinFET device incorporating strained silicon in the channel region
US6833588B2 (en) * 2002-10-22 2004-12-21 Advanced Micro Devices, Inc. Semiconductor device having a U-shaped gate structure
US6611029B1 (en) * 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6821834B2 (en) * 2002-12-04 2004-11-23 Yoshiyuki Ando Ion implantation methods and transistor cell layout for fin type transistors
US6869868B2 (en) * 2002-12-13 2005-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a MOSFET device with metal containing gate structures
US6794718B2 (en) * 2002-12-19 2004-09-21 International Business Machines Corporation High mobility crystalline planes in double-gate CMOS technology
US6803631B2 (en) * 2003-01-23 2004-10-12 Advanced Micro Devices, Inc. Strained channel finfet
US6897527B2 (en) * 2003-01-23 2005-05-24 Advanced Micro Devices, Inc. Strained channel FinFET
US6885055B2 (en) * 2003-02-04 2005-04-26 Lee Jong-Ho Double-gate FinFET device and fabricating method thereof
US7115945B2 (en) * 2003-06-23 2006-10-03 Sharp Laboratories Of America, Inc. Strained silicon fin structure
US20050116218A1 (en) * 2003-11-24 2005-06-02 Samsung Electronics Co., Ltd. Non-planar transistor having germanium channel region and method of manufacturing the same
US20060076625A1 (en) * 2004-09-25 2006-04-13 Lee Sung-Young Field effect transistors having a strained silicon channel and methods of fabricating same
US20070032024A1 (en) * 2005-08-03 2007-02-08 Advanced Micro Devices, Inc. Methods for fabricating a stressed MOS device

Cited By (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7605407B2 (en) * 2006-09-06 2009-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Composite stressors with variable element atomic concentrations in MOS devices
US20080054347A1 (en) * 2006-09-06 2008-03-06 Yin-Pin Wang Composite stressors in MOS devices
US20090085114A1 (en) * 2007-09-28 2009-04-02 Muhammad Nawaz Semiconductor Structure
US9064963B2 (en) * 2007-09-28 2015-06-23 Infineon Technologies Ag Semiconductor structure
JP2011505697A (en) * 2007-11-30 2011-02-24 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Heterostructure inverted T-shaped field effect transistor
US8815658B2 (en) 2007-11-30 2014-08-26 Advanced Micro Devices, Inc. Hetero-structured inverted-T field effect transistor
US20100308414A1 (en) * 2009-06-04 2010-12-09 International Business Machines Corporation Cmos inverter device
US8258577B2 (en) * 2009-06-04 2012-09-04 International Business Machines Corporation CMOS inverter device with fin structures
TWI643345B (en) * 2011-09-30 2018-12-01 英特爾公司 Tungsten gates for non-planar transistors
US10770591B2 (en) 2011-10-01 2020-09-08 Intel Corporation Source/drain contacts for non-planar transistors
US10283640B2 (en) 2011-10-01 2019-05-07 Intel Corporation Source/drain contacts for non-planar transistors
CN103367162A (en) * 2012-04-08 2013-10-23 中国科学院微电子研究所 Manufacturing method of fin-shaped field effect transistor
WO2014004034A1 (en) * 2012-06-29 2014-01-03 Intel Corporation Preventing isolation leakage in iii-v devices
US9748338B2 (en) 2012-06-29 2017-08-29 Intel Corporation Preventing isolation leakage in III-V devices
TWI512842B (en) * 2012-06-29 2015-12-11 Intel Corp Preventing isolation leakage in iii-v devices
US9817928B2 (en) 2012-08-31 2017-11-14 Synopsys, Inc. Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
US9177894B2 (en) 2012-08-31 2015-11-03 Synopsys, Inc. Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
US9184110B2 (en) 2012-08-31 2015-11-10 Synopsys, Inc. Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
US9190346B2 (en) 2012-08-31 2015-11-17 Synopsys, Inc. Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
US8847324B2 (en) 2012-12-17 2014-09-30 Synopsys, Inc. Increasing ION /IOFF ratio in FinFETs and nano-wires
US9379018B2 (en) 2012-12-17 2016-06-28 Synopsys, Inc. Increasing Ion/Ioff ratio in FinFETs and nano-wires
WO2014100010A1 (en) * 2012-12-17 2014-06-26 Synopsys, Inc. Increasing ion/ioff ratio in finfets and nano-wires
DE112014003027B4 (en) 2013-06-26 2020-06-04 Synopsys, Inc. Computer program product for a FinFET with heterojunction and improved channel control
US20160087099A1 (en) * 2013-06-26 2016-03-24 Synopsys, Inc. Finfet with heterojunction and improved channel control
CN108807544A (en) * 2013-06-26 2018-11-13 美商新思科技有限公司 The FinFET controlled with hetero-junctions and improved raceway groove
US10121896B2 (en) * 2013-06-26 2018-11-06 Synopsys, Inc. FinFet with heterojunction and improved channel control
CN105164809A (en) * 2013-06-26 2015-12-16 美商新思科技有限公司 Finfet with heterojunction and improved channel control
US10756212B2 (en) 2013-06-26 2020-08-25 Synopsys, Inc. FinFET with heterojunction and improved channel control
CN104282558A (en) * 2013-07-02 2015-01-14 中芯国际集成电路制造(上海)有限公司 Knot-free nanowire FinFET and manufacturing method thereof
TWI582985B (en) * 2013-09-27 2017-05-11 英特爾股份有限公司 Improved cladding layer epitaxy via template engineering for heterogeneous integration on silicon
WO2015047354A1 (en) * 2013-09-27 2015-04-02 Intel Corporation Improved cladding layer epitaxy via template engineering for heterogeneous integration on silicon
US10693008B2 (en) 2013-09-27 2020-06-23 Intel Corporation Cladding layer epitaxy via template engineering for heterogeneous integration on silicon
US20150380559A1 (en) * 2013-12-27 2015-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium-Containing FinFET and Methods for Forming the Same
US9559206B2 (en) * 2013-12-27 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with necking in the fins
US9780216B2 (en) 2014-03-19 2017-10-03 Taiwan Semiconductor Manufacturing Company, Ltd. Combination FinFET and methods of forming same
CN104934474A (en) * 2014-03-19 2015-09-23 台湾积体电路制造股份有限公司 Combination FinFET and Methods of Forming Same
US9275905B1 (en) * 2015-01-28 2016-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming semiconductor structure with anti-punch through structure
US9953836B2 (en) 2015-01-28 2018-04-24 Taiwan Semiconductor Manufacturing Co., Ltd. Barrier layer above anti-punch through (APT) implant region to improve mobility of channel region of fin field effect transistor (FinFET) device structure
US9595442B2 (en) 2015-01-28 2017-03-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming semiconductor structure with anti-punch through structure
US11158508B2 (en) 2015-01-28 2021-10-26 Taiwan Semiconductor Manufacturing Co., Ltd. Barrier layer above anti-punch through (APT) implant region to improve mobility of channel region of fin field effect transistor (finFET) device structure
KR20180012248A (en) * 2015-05-27 2018-02-05 인텔 코포레이션 Apparatus and methods for creating a buffer extending into a gate region of a transistor
WO2016190858A1 (en) * 2015-05-27 2016-12-01 Intel Corporation Apparatus and methods to create a buffer which extends into a gated region of a transistor
KR102430525B1 (en) * 2015-05-27 2022-08-09 인텔 코포레이션 Apparatus and methods for creating a buffer extending into the gate region of a transistor
EP3304601A4 (en) * 2015-05-27 2019-01-09 Intel Corporation Apparatus and methods to create a buffer which extends into a gated region of a transistor
CN107534052A (en) * 2015-05-27 2018-01-02 英特尔公司 The apparatus and method for having the buffer part in area of grid of transistor are extended to for creating
TWI720979B (en) * 2015-05-27 2021-03-11 美商英特爾股份有限公司 Apparatus and methods to create a buffer which extends into a gated region of a transistor
US20180158958A1 (en) * 2015-05-27 2018-06-07 Intel Corporation Apparatus and methods to create a buffer which extends into a gated region of a transistor
US10461193B2 (en) * 2015-05-27 2019-10-29 Intel Corporation Apparatus and methods to create a buffer which extends into a gated region of a transistor
US10347767B2 (en) 2015-06-16 2019-07-09 Intel Corporation Transistor with a subfin layer
WO2016204737A1 (en) * 2015-06-16 2016-12-22 Intel Corporation A transistor with a subfin layer
US20180047847A1 (en) * 2015-09-30 2018-02-15 International Business Machines Corporation Tensile strained high percentage silicon germanium alloy finfets
US10211341B2 (en) * 2015-09-30 2019-02-19 International Business Machines Corporation Tensile strained high percentage silicon germanium alloy FinFETS
TWI629716B (en) * 2015-12-04 2018-07-11 台灣積體電路製造股份有限公司 Semiconductor structure and method of forming the same
US10153355B2 (en) * 2015-12-04 2018-12-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor mixed gate structure
US11152290B2 (en) * 2016-06-29 2021-10-19 Intel Corporatuon Wide bandgap group IV subfin to reduce leakage
US20190122972A1 (en) * 2016-06-29 2019-04-25 Intel Corporation Wide bandgap group iv subfin to reduce leakage
US11189729B2 (en) * 2016-09-26 2021-11-30 Tessera, Inc. Forming a sacrificial liner for dual channel devices
US11894462B2 (en) 2016-09-26 2024-02-06 Adeia Semiconductor Solutions Llc Forming a sacrificial liner for dual channel devices
US11854688B2 (en) * 2020-02-19 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method

Also Published As

Publication number Publication date
US8169027B2 (en) 2012-05-01
US20100193840A1 (en) 2010-08-05

Similar Documents

Publication Publication Date Title
US8169027B2 (en) Substrate band gap engineered multi-gate pMOS devices
US7902014B2 (en) CMOS devices with a single work function gate electrode and method of fabrication
JP6371822B2 (en) Semiconductor chip
JP5041685B2 (en) Super steep retrograde well (SSRW) FET device and method of manufacturing the same
US6867433B2 (en) Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US20070069302A1 (en) Method of fabricating CMOS devices having a single work function gate electrode by band gap engineering and article made thereby
US7348225B2 (en) Structure and method of fabricating FINFET with buried channel
US7259049B2 (en) Self-aligned isolation double-gate FET
JP5695730B2 (en) Thin BOX metal back gate type ultrathin SOI device
US8871584B2 (en) Replacement source/drain finFET fabrication
US7172943B2 (en) Multiple-gate transistors formed on bulk substrates
US6432754B1 (en) Double SOI device with recess etch and epitaxy
JP5178152B2 (en) Complementary semiconductor device and manufacturing method thereof
US20110147840A1 (en) Wrap-around contacts for finfet and tri-gate devices
US20140001561A1 (en) Cmos devices having strain source/drain regions and low contact resistance
US7648880B2 (en) Nitride-encapsulated FET (NNCFET)
JP4446690B2 (en) Semiconductor device and manufacturing method thereof
US6657261B2 (en) Ground-plane device with back oxide topography
US6680504B2 (en) Method for constructing a metal oxide semiconductor field effect transistor
US20040106270A1 (en) Method for constructing a metal oxide semiconductor field effect transistor

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DOYLE, BRIAN S.;JIN, BEEN-YIH;KAVALIEROS, JACK T.;AND OTHERS;REEL/FRAME:019890/0666;SIGNING DATES FROM 20060721 TO 20060722

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION