US20070221976A1 - Trench capacitor and fabrication method thereof - Google Patents
Trench capacitor and fabrication method thereof Download PDFInfo
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- US20070221976A1 US20070221976A1 US11/388,855 US38885506A US2007221976A1 US 20070221976 A1 US20070221976 A1 US 20070221976A1 US 38885506 A US38885506 A US 38885506A US 2007221976 A1 US2007221976 A1 US 2007221976A1
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- trench capacitor
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- 239000003990 capacitor Substances 0.000 title claims abstract description 102
- 238000000034 method Methods 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 68
- 238000000059 patterning Methods 0.000 claims abstract description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 34
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 22
- 238000002955 isolation Methods 0.000 claims description 21
- 238000005229 chemical vapour deposition Methods 0.000 claims description 14
- 239000003989 dielectric material Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 13
- 229910052454 barium strontium titanate Inorganic materials 0.000 claims description 12
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 12
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 6
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 2
- 239000011810 insulating material Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
- H01L29/945—Trench capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0387—Making the trench
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
Definitions
- the present invention relates to a memory capacitor and a fabrication method thereof, and more particularly, to a trench capacitor and a fabrication method thereof.
- a trench capacitor memory device is a device with a capacitor formed in the substrate that it solves the issue of device minimization.
- FIG. 1A The prior art method of fabricating a trench capacitor is shown in FIG. 1A .
- a silicon oxide layer 102 and a silicon nitride layer 104 are sequentially formed over a substrate 100 .
- an etch process is performed to remove portions of the silicon oxide layer 102 and the silicon nitride layer 104 to form openings 106 which expose the surface of the substrate 100 .
- a portion of the substrate 100 is removed to form a plurality of trenches 108 therein by using the silicon oxide layer 102 and the silicon nitride layer 104 as an etch mask. Then, a doped region 110 is formed in the substrate 100 of the surface of the trenches 108 .
- an oxide/nitride/oxide (ONO) layer 112 is formed over the surface of the trenches 108 .
- a doped polysilicon layer 114 is deposited in the trenches 108 .
- a chemical-mechanical polish (CMP) process then is performed to remove a portion of the doped polysilicon layer 114 until the surface of the silicon nitride layer 104 is exposed.
- the silicon oxide layer 102 and the silicon nitride layer 104 are removed. Moreover, a portion of the doped polysilicon layer 114 is removed to expose the surface of the substrate 100 .
- the step shown in FIG. 1D of removing silicon oxide layer 102 , the silicon nitride layer 104 and the portion of the doped polysilicon layer 114 to expose the surface of the substrate 100 may damage the surface of the ONO layer 112 . That causes leakage currents and affects the process reliability and yields.
- the surface of the ONO layer 112 is also exposed.
- the subsequent processes such as the doping process and the etch process to define the active area and form the device, the surface of the ONO layer 112 of the trench capacitor is subject to damage as well.
- U.S. Pat. No. 6,661,050 B2 discloses a memory cell structure with a trench capacitor and a fabrication method thereof.
- U.S. Pat. No. 6,808,980 B2 discloses a trench-type one-transistor random access memory (1T-RAM) structure and a fabrication method thereof.
- the patents can be more complicated for the process, and can't effectively solve the above-mentioned question.
- the present invention is directed to a method of fabricating a trench capacitor. According to this method, the surface damage of the capacitor dielectric layer, which causes leakage currents and affects process reliability and yields, can be avoided.
- the present invention also is directed to a trench capacitor.
- the surface of the capacitor dielectric layer is protected without being subject to damage. As a result, process reliability and yields are improved.
- the present invention provides a method of fabricating a trench capacitor.
- a patterning process is performed to a substrate by using a patterned mask layer over the substrate to form a plurality of trenches.
- a bottom electrode is formed in the substrate of surfaces of the trenches.
- a portion of the patterned mask layer is removed to expose a portion of the substrate at two sides of the top of each of the trenches.
- a capacitor dielectric layer then is formed over the substrate and the surfaces of the trenches.
- a conductive layer is formed over the substrate. The conductive layer at least fills the trenches and covers the capacitor dielectric layer.
- the patterned mask layer and a portion of the conductive layer are removed; and a portion of the conductive layer, which covers the capacitor dielectric layer, is reserved to form a top electrode.
- the method of removing the portion of the patterned mask layer to expose the portion of the substrate at the two sides of the top of each of the trenches described above can be, for example, an isotropic etch method.
- the method further comprises forming an isolation structure in the conductive layer, the capacitor dielectric layer and a portion of the substrate between two neighboring trenches.
- the isolation trench structure comprises a shallow trench isolation (STI) structure.
- the capacitor dielectric layer described above can be, for example, a high-k dielectric material layer.
- the material of the high-k dielectric material layer can be, for example, silicon oxide/silicon nitride/silicon nitride (ONO), silicon nitride/silicon oxide (NO), tantalum oxide (Ta 2 O 5 ) layer, zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ) or barium strontium titanate (BST).
- the method of forming the capacitor dielectric layer can be, for example, a chemical vapor deposition (CVD) method or a sputtering method.
- the patterned mask layer described above comprises, sequentially over the substrate, a patterned pad oxide layer and a patterned silicon nitride layer.
- the material of the conductive layer can be, for example, doped polysilicon.
- the method of forming the conductive layer can be, for example, a CVD method.
- the bottom electrode described above can be, for example, a doped region.
- the method of forming the bottom electrode can be, for example, an ion implantation method or a thermal diffusion method.
- the present invention further provides a trench capacitor, which is disposed in a trench of a substrate.
- the trench capacitor comprises a bottom electrode, a capacitor dielectric layer, a top electrode and an isolation structure.
- the bottom electrode is disposed in the substrate of a surface of the trench.
- the capacitor dielectric layer is disposed over the surface of the trench and over a portion of the substrate at two sides of the top of the trench.
- the top electrode is disposed in the trench and over the substrate.
- the top electrode covers the capacitor dielectric layer.
- the isolation structure is disposed in portions of the capacitor dielectric layer, the top electrode and the substrate.
- the capacitor dielectric layer described above can be, for example, a high-k dielectric material layer.
- the material of the high-k dielectric material layer can be, for example, silicon oxide/silicon nitride/silicon nitride (ONO), silicon nitride/silicon oxide (NO), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ) or barium strontium titanate (BST).
- the method of forming the capacitor dielectric layer can be, for example, a chemical vapor deposition (CVD) method or a sputtering method.
- the top electrode described above can be, for example, a conductive layer.
- the material of the conductive layer comprises doped polysilicon.
- the bottom electrode described above can be, for example, a doped region.
- the isolation structure described above can be, for example, an STI structure.
- the subsequent top electrode is formed on the exposed substrate at two sides of the top of the trench.
- the top electrode protects the surface of the capacitor dielectric layer from damage. In other words, the prior art surface damage of the capacitor dielectric layer, which causes leakage currents and affects process reliability and yields, can be avoided.
- FIGS. 1A-1D are cross sectional views showing progress of a prior art method of fabricating a trench capacitor.
- FIGS. 2A-2H are cross sectional views showing progress of a method of fabricating a memory according to an embodiment of the present invention.
- FIGS. 2A-2H are cross sectional views showing progress of a method of fabricating a memory according to an embodiment of the present invention.
- a substrate 200 is provided.
- a mask layer 201 is formed over the substrate 200 .
- the mask layer 201 comprises, for example, a pad oxide layer 202 and a silicon nitride layer 204 , which are sequentially formed over the substrate 200 .
- the method of forming the pad oxide layer 202 can be, for example, a thermal oxidation method.
- the method of forming the silicon nitride layer 204 can be, for example, a chemical vapor deposition (CVD) method.
- CVD chemical vapor deposition
- a bottom electrode 208 is formed in the substrate 200 of the surfaces of the trenches 206 .
- a doped silicon oxide layer is first formed on the inner surfaces of the trenches 206 , for example. Then, a thermal process is performed to diffuse the dopant ions in the doped silicon oxide layer into the trenches 206 to form the bottom electrode 208 .
- the dopant ions in the doped silicon oxide layer can be, for example, arsenic ions.
- the method of forming the doped silicon oxide layer can be, for example, a low pressure CVD (LPCVD) method.
- the method of forming the bottom electrode 208 can be, for example, a multiple-angle ion implantation process so as to form the doped regions serving as the bottom electrode 208 in the substrate 200 of the surfaces of the trenches 206 .
- a portion of the mask layer 201 is removed to expose a portion of the substrate 200 at two sides of the top of each trench 206 .
- the method of removing the portion of the mask layer 201 can be, for example, an isotropic etch process.
- the isotropic etch process removes portions of the silicon nitride layer 204 and the pad oxide layer 202 .
- the step described above removes the portion of the mask layer 201 and pulls back the mask layer 201 to form the mask layer 201 a .
- the portion of the substrate 200 at two sides of the top of the trench 206 is exposed (as shown by arrow 210 ).
- a capacitor dielectric layer 212 is formed over the substrate 200 and over the surfaces of the trenches 206 .
- the capacitor dielectric layer 212 can be, for example, a high-k dielectric material layer to increase the capacitance of the capacitor.
- the material of the high-k dielectric material layer can be, for example, silicon oxide/silicon nitride/silicon nitride (ONO), silicon nitride/silicon oxide (NO), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), barium strontium titanate (BST) or other high-k dielectric material.
- the method of forming the capacitor dielectric layer 212 can be, for example, a chemical vapor deposition (CVD) method or a sputtering method.
- a conductive layer 214 is formed over the substrate 200 .
- the conductive layer 214 at least fills the trenches 206 and covers the capacitor dielectric layer 212 .
- the material of the conductive layer 214 can be, for example, doped polysilicon.
- the method of forming the conductive layer 214 can be, for example, a CVD method.
- the mask layer 201 a and the portion of the conductive layer 214 are removed; and the portion of the conductive layer 214 , which covers the capacitor dielectric layer 212 , is reserved to constitute a conductive layer 214 a .
- the conductive layer 214 a serves as a top electrode.
- the top electrode i.e., the conductive layer 214 a , the capacitor dielectric layer 212 and the bottom electrode 208 constitute a trench capacitor.
- the top electrode (the conductive layer 214 a ) of the trench capacitor of the present invention is not only the conductive material layer formed in the trenches 206 and over the substrate 200 , but also serves as the conductive material layer covering the capacitor dielectric layer 212 (arrow 215 shown in FIG. 2F ).
- the top electrode (the conductive layer 214 a ) protects the surface of the capacitor dielectric layer 212 from being damaged. In other words, the prior art surface damage of the capacitor dielectric layer 213 , which causes leakage currents and affects process reliability and yields, can be avoided.
- the portion of the top electrode (the conductive layer 214 a ) indicated by the arrow 215 shown in FIG. 2F is self-aligned formed and covers the capacitor dielectric layer 212 without performing a photolithographic process.
- an active device can further be fabricated.
- an isolation structure 216 is formed between the conductive layer 214 a , the capacitor dielectric layer 212 and the portion of the substrate 200 located between two neighboring trenches 206 .
- the area between two neighboring isolation structures 216 is called an active area (AA).
- the isolation structures 216 can be, for example, a shallow trench isolation (STI) structure.
- the method of forming the isolation structures 216 can be, for example, removing the capacitor dielectric layer 212 located between the two neighboring trenches 206 , the conductive layer 214 a and the portion of the substrate 200 .
- the conductive layer 214 a between two neighboring trenches 206 and a portion of the capacitor dielectric layer 212 are removed to form an opening.
- an insulating material layer is filled in the opening to form the isolation structure 216 .
- the material of the insulating material layer can be, for example, silicon oxide.
- the method of forming the insulating material layer can be, for example, a CVD method.
- an active device 218 is formed over the substrate 200 .
- a plurality of gate structures are formed over the substrate 200 of the active area and over the surfaces of the isolation structures 216 , for example.
- the gate structures over the substrate 200 of the active area serve as the gate 218 a of the active device 218 .
- spacers are formed on the sidewalls of the gate structures.
- An ion implantation process is performed to form source/drain regions 218 b in the substrate 200 adjacent to the two sides of the gate 218 a .
- the active device 218 electrically connects with the bottom electrode 208 of the trench capacitor through the source/drain regions 218 b .
- the active device 218 described above can be, for example, an N-type metal-oxide-semiconductor (NMOS) transistor, or a PMOS transistor.
- NMOS N-type metal-oxide-semiconductor
- the subsequent interconnect process is performed.
- the dielectric layer 220 is formed over the substrate 200 , for example.
- Contact 222 are formed in the dielectric layer 220 .
- Conductive lines (not shown) then are formed to connect with the contacts 222 .
- the top electrode (the conductive layer 214 a ) of the trench capacitor of the present invention includes the portion of the top electrode (the conductive layer 214 a , as shown by arrow 215 in FIG. 2F ) which covers the capacitor dielectric layer 212 . Accordingly, while the contacts are defined, a larger process window is obtained to improve the accuracy of process.
- the memory comprises a trench capacitor and the active device 218 .
- the trench capacitor comprises the bottom electrode 208 , the capacitor dielectric layer 212 , the top electrode (the conductive layer 214 a ) and the isolation structure 216 .
- the bottom electrode 208 is disposed in the substrate 200 of the surface of the trench 206 .
- the bottom electrode 208 can be, for example, a doped region.
- the capacitor dielectric layer 212 is disposed over the surface of the trench 206 and over the portion of the substrate 200 of two sides of the top of the trench 206 .
- the capacitor dielectric layer 212 can be, for example, a high-k dielectric material layer.
- the material of the high-k dielectric material layer can be, for example, silicon oxide/silicon nitride/silicon nitride (ONO), silicon nitride/silicon oxide (NO), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ) or barium strontium titanate (BST).
- the top electrode (the conductive layer 214 a ) is disposed in the trench 206 and over the substrate 200 , and covers the capacitor dielectric layer 212 . Its material can be, for example, doped polysilicon.
- the isolation structure 216 is disposed in the portions of the capacitor dielectric layer 212 the top electrode (the conductive layer 214 a ), and is located in the portion of the substrate 200 .
- the isolation structure 216 can be, for example, an STI structure.
- the active device 218 comprises the gate 218 a and the source/drain regions 218 b .
- the gate 218 a is disposed on the substrate 200 of the side of the trench capacitor.
- the source/drain regions 218 b are disposed in the substrate 200 adjacent to two sides of the gate 218 a and electrically connected with the bottom electrode 208 of the trench capacitor.
- the active device 218 can be, for example, an NMOS transistor, or a PMOS transistor.
- the present invention includes the following advantages:
- the surface of the capacitor dielectric layer is protected from being damaged.
- the prior art surface damage of the capacitor dielectric layer which causes leakage currents and affects process reliability and yields, can be avoided.
- the top electrode can be self-aligned formed and covers the capacitor dielectric layer without performing a photolithographic process.
- the surface damage of the capacitor dielectric layer which causes leakage currents and affects process reliability and yields, can be avoided.
- the structure of the trench capacitor of the present invention enhances defining the opening of contacts so that a larger process window can be obtained to improve the accuracy of process.
- a portion of the mask layer is removed and the mask layer is pulled back that the surface of the capacitor dielectric layer is protected. Without a complicated process, the manufacturing yields are improved and the manufacturing costs are reduced.
Abstract
A method of fabricating trench capacitors is provided. A plurality of trenches is formed in the substrate by performing a patterning process with a patterned mask layer on a substrate. A bottom electrode is formed in the substrate of the surface of the trench. A portion of the patterned mask layer is removed so as to expose a portion of the substrate at two sides of the top of the trench. A capacitor dielectric layer is formed on the substrate and the surface of the trench. A conductive layer is formed over the substrate. The conductive layer is at least filled into the trench and covers the capacitor dielectric layer. The patterned mask layer and a portion of the conductive layer are removed and the portion of the conductive layer which covers the capacitor dielectric layer is reserved as to form a top electrode.
Description
- 1. Field of the Invention
- The present invention relates to a memory capacitor and a fabrication method thereof, and more particularly, to a trench capacitor and a fabrication method thereof.
- 2. Description of the Related Art
- Due to minimization of devices, device dimensions are required shrinkage. For memory devices with capacitors, areas for fabrication of capacitors also are continuously reduced. A trench capacitor memory device is a device with a capacitor formed in the substrate that it solves the issue of device minimization.
- The prior art method of fabricating a trench capacitor is shown in
FIG. 1A . Referring toFIG. 1A , asilicon oxide layer 102 and asilicon nitride layer 104 are sequentially formed over asubstrate 100. Then, an etch process is performed to remove portions of thesilicon oxide layer 102 and thesilicon nitride layer 104 to formopenings 106 which expose the surface of thesubstrate 100. - Referring to
FIG. 1B , a portion of thesubstrate 100 is removed to form a plurality oftrenches 108 therein by using thesilicon oxide layer 102 and thesilicon nitride layer 104 as an etch mask. Then, adoped region 110 is formed in thesubstrate 100 of the surface of thetrenches 108. - Referring to
FIG. 1C , an oxide/nitride/oxide (ONO)layer 112 is formed over the surface of thetrenches 108. A dopedpolysilicon layer 114 is deposited in thetrenches 108. A chemical-mechanical polish (CMP) process then is performed to remove a portion of thedoped polysilicon layer 114 until the surface of thesilicon nitride layer 104 is exposed. - Referring to
FIG. 1D , thesilicon oxide layer 102 and thesilicon nitride layer 104 are removed. Moreover, a portion of thedoped polysilicon layer 114 is removed to expose the surface of thesubstrate 100. - In the prior art method mentioned above, the step shown in
FIG. 1D of removingsilicon oxide layer 102, thesilicon nitride layer 104 and the portion of the dopedpolysilicon layer 114 to expose the surface of thesubstrate 100 may damage the surface of theONO layer 112. That causes leakage currents and affects the process reliability and yields. After the step shown inFIG. 1D , the surface of theONO layer 112 is also exposed. In the subsequent processes, such as the doping process and the etch process to define the active area and form the device, the surface of theONO layer 112 of the trench capacitor is subject to damage as well. - U.S. Pat. No. 6,661,050 B2 discloses a memory cell structure with a trench capacitor and a fabrication method thereof. U.S. Pat. No. 6,808,980 B2 discloses a trench-type one-transistor random access memory (1T-RAM) structure and a fabrication method thereof. However, the patents can be more complicated for the process, and can't effectively solve the above-mentioned question.
- Accordingly, the present invention is directed to a method of fabricating a trench capacitor. According to this method, the surface damage of the capacitor dielectric layer, which causes leakage currents and affects process reliability and yields, can be avoided.
- The present invention also is directed to a trench capacitor. In the trench capacitor, the surface of the capacitor dielectric layer is protected without being subject to damage. As a result, process reliability and yields are improved.
- The present invention provides a method of fabricating a trench capacitor. According to this method, a patterning process is performed to a substrate by using a patterned mask layer over the substrate to form a plurality of trenches. Then, a bottom electrode is formed in the substrate of surfaces of the trenches. Later, a portion of the patterned mask layer is removed to expose a portion of the substrate at two sides of the top of each of the trenches. A capacitor dielectric layer then is formed over the substrate and the surfaces of the trenches. Next, a conductive layer is formed over the substrate. The conductive layer at least fills the trenches and covers the capacitor dielectric layer. Then, the patterned mask layer and a portion of the conductive layer are removed; and a portion of the conductive layer, which covers the capacitor dielectric layer, is reserved to form a top electrode.
- According to an embodiment of the present invention, the method of removing the portion of the patterned mask layer to expose the portion of the substrate at the two sides of the top of each of the trenches described above can be, for example, an isotropic etch method.
- According to an embodiment of the present invention, after the top electrode is formed, the method further comprises forming an isolation structure in the conductive layer, the capacitor dielectric layer and a portion of the substrate between two neighboring trenches. Wherein, the isolation trench structure comprises a shallow trench isolation (STI) structure.
- According to an embodiment of the present invention, the capacitor dielectric layer described above can be, for example, a high-k dielectric material layer. The material of the high-k dielectric material layer can be, for example, silicon oxide/silicon nitride/silicon nitride (ONO), silicon nitride/silicon oxide (NO), tantalum oxide (Ta2O5) layer, zirconium oxide (ZrO2), hafnium oxide (HfO2) or barium strontium titanate (BST). The method of forming the capacitor dielectric layer can be, for example, a chemical vapor deposition (CVD) method or a sputtering method.
- According to an embodiment of the present invention, the patterned mask layer described above comprises, sequentially over the substrate, a patterned pad oxide layer and a patterned silicon nitride layer.
- According to an embodiment of the present invention, the material of the conductive layer can be, for example, doped polysilicon. The method of forming the conductive layer can be, for example, a CVD method.
- According to an embodiment of the present invention, the bottom electrode described above can be, for example, a doped region. Wherein, the method of forming the bottom electrode can be, for example, an ion implantation method or a thermal diffusion method.
- The present invention further provides a trench capacitor, which is disposed in a trench of a substrate. The trench capacitor comprises a bottom electrode, a capacitor dielectric layer, a top electrode and an isolation structure. Wherein, the bottom electrode is disposed in the substrate of a surface of the trench. The capacitor dielectric layer is disposed over the surface of the trench and over a portion of the substrate at two sides of the top of the trench. Additionally, the top electrode is disposed in the trench and over the substrate. The top electrode covers the capacitor dielectric layer. The isolation structure is disposed in portions of the capacitor dielectric layer, the top electrode and the substrate.
- According to an embodiment of the present invention, the capacitor dielectric layer described above can be, for example, a high-k dielectric material layer. The material of the high-k dielectric material layer can be, for example, silicon oxide/silicon nitride/silicon nitride (ONO), silicon nitride/silicon oxide (NO), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), hafnium oxide (HfO2) or barium strontium titanate (BST). The method of forming the capacitor dielectric layer can be, for example, a chemical vapor deposition (CVD) method or a sputtering method.
- According to an embodiment of the present invention, the top electrode described above can be, for example, a conductive layer. The material of the conductive layer comprises doped polysilicon.
- According to an embodiment of the present invention, the bottom electrode described above can be, for example, a doped region.
- According to an embodiment of the present invention, the isolation structure described above can be, for example, an STI structure.
- According to the present invention, a portion of the mask layer is removed so that the mask layer is pulled back and a portion of the substrate at two sides of the top of the trench is exposed. Accordingly, the subsequent top electrode is formed on the exposed substrate at two sides of the top of the trench. During the subsequent doping process and etch process, the top electrode protects the surface of the capacitor dielectric layer from damage. In other words, the prior art surface damage of the capacitor dielectric layer, which causes leakage currents and affects process reliability and yields, can be avoided.
- The above and other features of the present invention will be better understood from the following detailed description of the preferred embodiments of the invention that is provided in communication with the accompanying drawings.
-
FIGS. 1A-1D are cross sectional views showing progress of a prior art method of fabricating a trench capacitor. -
FIGS. 2A-2H are cross sectional views showing progress of a method of fabricating a memory according to an embodiment of the present invention. -
FIGS. 2A-2H are cross sectional views showing progress of a method of fabricating a memory according to an embodiment of the present invention. - Referring to
FIG. 2A , asubstrate 200 is provided. Amask layer 201 is formed over thesubstrate 200. Themask layer 201 comprises, for example, apad oxide layer 202 and asilicon nitride layer 204, which are sequentially formed over thesubstrate 200. The method of forming thepad oxide layer 202 can be, for example, a thermal oxidation method. The method of forming thesilicon nitride layer 204 can be, for example, a chemical vapor deposition (CVD) method. Then, thepad oxide layer 202 and thesilicon nitride 204 are patterned, and thesubstrate 200 is etched to form a plurality oftrenches 206 in thesubstrate 200. - Referring to
FIG. 2B , abottom electrode 208 is formed in thesubstrate 200 of the surfaces of thetrenches 206. In the method of forming thebottom electrode 208, a doped silicon oxide layer is first formed on the inner surfaces of thetrenches 206, for example. Then, a thermal process is performed to diffuse the dopant ions in the doped silicon oxide layer into thetrenches 206 to form thebottom electrode 208. Wherein, the dopant ions in the doped silicon oxide layer can be, for example, arsenic ions. The method of forming the doped silicon oxide layer can be, for example, a low pressure CVD (LPCVD) method. Additionally, the method of forming thebottom electrode 208 can be, for example, a multiple-angle ion implantation process so as to form the doped regions serving as thebottom electrode 208 in thesubstrate 200 of the surfaces of thetrenches 206. - Referring to
FIG. 2C , a portion of themask layer 201 is removed to expose a portion of thesubstrate 200 at two sides of the top of eachtrench 206. The method of removing the portion of themask layer 201 can be, for example, an isotropic etch process. The isotropic etch process removes portions of thesilicon nitride layer 204 and thepad oxide layer 202. In other words, the step described above removes the portion of themask layer 201 and pulls back themask layer 201 to form themask layer 201 a. As a result, the portion of thesubstrate 200 at two sides of the top of thetrench 206 is exposed (as shown by arrow 210). - Referring to
FIG. 2D , acapacitor dielectric layer 212 is formed over thesubstrate 200 and over the surfaces of thetrenches 206. Wherein, thecapacitor dielectric layer 212 can be, for example, a high-k dielectric material layer to increase the capacitance of the capacitor. The material of the high-k dielectric material layer can be, for example, silicon oxide/silicon nitride/silicon nitride (ONO), silicon nitride/silicon oxide (NO), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), hafnium oxide (HfO2), barium strontium titanate (BST) or other high-k dielectric material. The method of forming thecapacitor dielectric layer 212 can be, for example, a chemical vapor deposition (CVD) method or a sputtering method. - Referring to
FIG. 2E , aconductive layer 214 is formed over thesubstrate 200. Theconductive layer 214 at least fills thetrenches 206 and covers thecapacitor dielectric layer 212. Wherein, the material of theconductive layer 214 can be, for example, doped polysilicon. The method of forming theconductive layer 214 can be, for example, a CVD method. - Referring to
FIG. 2F , themask layer 201 a and the portion of theconductive layer 214 are removed; and the portion of theconductive layer 214, which covers thecapacitor dielectric layer 212, is reserved to constitute aconductive layer 214 a. Theconductive layer 214 a serves as a top electrode. Wherein, the top electrode, i.e., theconductive layer 214 a, thecapacitor dielectric layer 212 and thebottom electrode 208 constitute a trench capacitor. - Particularly note that the top electrode (the
conductive layer 214 a) of the trench capacitor of the present invention is not only the conductive material layer formed in thetrenches 206 and over thesubstrate 200, but also serves as the conductive material layer covering the capacitor dielectric layer 212 (arrow 215 shown inFIG. 2F ). In the subsequent doping and etch processes, the top electrode (theconductive layer 214 a) protects the surface of thecapacitor dielectric layer 212 from being damaged. In other words, the prior art surface damage of the capacitor dielectric layer 213, which causes leakage currents and affects process reliability and yields, can be avoided. - Moreover, the portion of the top electrode (the
conductive layer 214 a) indicated by thearrow 215 shown inFIG. 2F is self-aligned formed and covers thecapacitor dielectric layer 212 without performing a photolithographic process. - After the formation of the trench capacitor, an active device can further be fabricated. Referring to
FIG. 2G , anisolation structure 216 is formed between theconductive layer 214 a, thecapacitor dielectric layer 212 and the portion of thesubstrate 200 located between two neighboringtrenches 206. The area between two neighboringisolation structures 216 is called an active area (AA). Theisolation structures 216 can be, for example, a shallow trench isolation (STI) structure. The method of forming theisolation structures 216 can be, for example, removing thecapacitor dielectric layer 212 located between the two neighboringtrenches 206, theconductive layer 214 a and the portion of thesubstrate 200. Further, a portion of theconductive layer 214 a between two neighboringtrenches 206 and a portion of thecapacitor dielectric layer 212 are removed to form an opening. Then, an insulating material layer is filled in the opening to form theisolation structure 216. Wherein, the material of the insulating material layer can be, for example, silicon oxide. The method of forming the insulating material layer can be, for example, a CVD method. - Referring to
FIG. 2H , anactive device 218 is formed over thesubstrate 200. According to the method of forming theactive device 218, a plurality of gate structures are formed over thesubstrate 200 of the active area and over the surfaces of theisolation structures 216, for example. Wherein, the gate structures over thesubstrate 200 of the active area serve as thegate 218 a of theactive device 218. Then, spacers are formed on the sidewalls of the gate structures. An ion implantation process is performed to form source/drain regions 218 b in thesubstrate 200 adjacent to the two sides of thegate 218 a. Theactive device 218 electrically connects with thebottom electrode 208 of the trench capacitor through the source/drain regions 218 b. Wherein, theactive device 218 described above can be, for example, an N-type metal-oxide-semiconductor (NMOS) transistor, or a PMOS transistor. - After the formation of the
active device 218, the subsequent interconnect process is performed. Referring toFIG. 2H , according to the interconnect process thedielectric layer 220 is formed over thesubstrate 200, for example. Contact 222 are formed in thedielectric layer 220. Conductive lines (not shown) then are formed to connect with thecontacts 222. Thus electrical connection between or among devices is established. Note that the top electrode (theconductive layer 214 a) of the trench capacitor of the present invention includes the portion of the top electrode (theconductive layer 214 a, as shown byarrow 215 inFIG. 2F ) which covers thecapacitor dielectric layer 212. Accordingly, while the contacts are defined, a larger process window is obtained to improve the accuracy of process. - Following is description of the memory structure fabricated by the method of the present invention. Referring to
FIG. 2H , the memory comprises a trench capacitor and theactive device 218. The trench capacitor comprises thebottom electrode 208, thecapacitor dielectric layer 212, the top electrode (theconductive layer 214 a) and theisolation structure 216. Wherein, thebottom electrode 208 is disposed in thesubstrate 200 of the surface of thetrench 206. Thebottom electrode 208 can be, for example, a doped region. Thecapacitor dielectric layer 212 is disposed over the surface of thetrench 206 and over the portion of thesubstrate 200 of two sides of the top of thetrench 206. Thecapacitor dielectric layer 212 can be, for example, a high-k dielectric material layer. The material of the high-k dielectric material layer can be, for example, silicon oxide/silicon nitride/silicon nitride (ONO), silicon nitride/silicon oxide (NO), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), hafnium oxide (HfO2) or barium strontium titanate (BST). Additionally, the top electrode (theconductive layer 214 a) is disposed in thetrench 206 and over thesubstrate 200, and covers thecapacitor dielectric layer 212. Its material can be, for example, doped polysilicon. Theisolation structure 216 is disposed in the portions of thecapacitor dielectric layer 212 the top electrode (theconductive layer 214 a), and is located in the portion of thesubstrate 200. Theisolation structure 216 can be, for example, an STI structure. - In addition, the
active device 218 comprises thegate 218 a and the source/drain regions 218 b. Thegate 218 a is disposed on thesubstrate 200 of the side of the trench capacitor. The source/drain regions 218 b are disposed in thesubstrate 200 adjacent to two sides of thegate 218 a and electrically connected with thebottom electrode 208 of the trench capacitor. Wherein, in this embodiment theactive device 218 can be, for example, an NMOS transistor, or a PMOS transistor. - Accordingly, the present invention includes the following advantages:
- 1. According to the present invention, the surface of the capacitor dielectric layer is protected from being damaged. In other words, the prior art surface damage of the capacitor dielectric layer, which causes leakage currents and affects process reliability and yields, can be avoided.
- 2. According to the present invention, the top electrode can be self-aligned formed and covers the capacitor dielectric layer without performing a photolithographic process. Thus, the surface damage of the capacitor dielectric layer, which causes leakage currents and affects process reliability and yields, can be avoided.
- 3. The structure of the trench capacitor of the present invention enhances defining the opening of contacts so that a larger process window can be obtained to improve the accuracy of process.
- 4. According to the present invention, a portion of the mask layer is removed and the mask layer is pulled back that the surface of the capacitor dielectric layer is protected. Without a complicated process, the manufacturing yields are improved and the manufacturing costs are reduced.
- Although the present invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be constructed broadly to include other variants and embodiments of the invention which may be made by those skilled in the field of this art without departing from the scope and range of equivalents of the invention.
Claims (19)
1. A method of fabricating a trench capacitor, comprising:
performing a patterning process to a substrate by using a patterned mask layer over the substrate to form a plurality of trenches;
forming a bottom electrode in the substrate of surfaces of the trenches;
removing a portion of the patterned mask layer to expose a portion of the substrate at two sides of a top of each of the trenches;
forming a capacitor dielectric layer over the substrate and the surfaces of the trenches;
forming a conductive layer over the substrate, the conductive layer at least filling the trenches and covering the capacitor dielectric layer; and
removing the patterned mask layer and a portion of the conductive layer; and
maintaining a portion of the conductive layer, which covers the capacitor dielectric layer to form a top electrode.
2. The method of fabricating a trench capacitor of claim 1 , wherein a method of removing the portion of the patterned mask layer to expose the portion of the substrate at the two sides of the top of each of the trenches comprises an isotropic etch method.
3. The method of fabricating a trench capacitor of claim 1 , after the top electrode is formed further comprising forming an isolation structure in the conductive layer, the capacitor dielectric layer and a portion of the substrate between two neighboring trenches.
4. The method of fabricating a trench capacitor of claim 3 , wherein the isolation structure comprises a shallow trench isolation (STI) structure.
5. The method of fabricating a trench capacitor of claim 1 , wherein the capacitor dielectric layer comprises a high-k dielectric material layer.
6. The method of fabricating a trench capacitor of claim 5 , wherein a material of the high-k dielectric material layer comprises silicon oxide/silicon nitride/silicon nitride (ONO), silicon nitride/silicon oxide (NO), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), hafnium oxide (HfO2), or barium strontium titanate (BST).
7. The method of fabricating a trench capacitor of claim 1 , wherein a method of forming the capacitor dielectric layer comprises a chemical vapor deposition (CVD) method or a sputtering method.
8. The method of fabricating a trench capacitor of claim 1 , wherein the patterned mask layer comprises, sequentially over the substrate, a patterned pad oxide layer and a patterned silicon nitride layer.
9. The method of fabricating a trench capacitor of claim 1 , wherein a material of the conductive layer comprises doped polysilicon.
10. The method of fabricating a trench capacitor of claim 1 , wherein a method of forming the conductive layer comprises a CVD method.
11. The method of fabricating a trench capacitor of claim 1 , wherein the bottom electrode comprises a doped region.
12. The method of fabricating a trench capacitor of claim 1 , wherein a method of forming the bottom electrode comprises an ion implantation method or a thermal diffusion method.
13. A trench capacitor disposed in a trench of a substrate, the trench capacitor comprising:
a bottom electrode, disposed in the substrate of a surface of the trench;
a capacitor dielectric layer, disposed over the surface of the trench and over a portion of the substrate at two sides of a top of the trench;
a top electrode, disposed in the trench and over the substrate, the top electrode covering the capacitor dielectric layer; and
an isolation structure, disposed in portions of the capacitor dielectric layer, the top electrode, and the substrate.
14. The trench capacitor of claim 13 , wherein the capacitor dielectric layer comprises a high-k dielectric material layer.
15. The trench capacitor of claim 14 , wherein a material of the high-k dielectric material layer comprises silicon oxide/silicon nitride/silicon nitride (ONO), a silicon nitride/silicon oxide (NO), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), hafnium oxide (HfO2), or barium strontium titanate (BST).
16. The trench capacitor of claim 13 , wherein the top electrode comprises a conductive layer.
17. The trench capacitor of claim 16 , wherein a material of the conductive layer comprises doped polysilicon.
18. The trench capacitor of claim 13 , wherein the bottom electrode comprises a doped region.
19. The trench capacitor of claim 13 , wherein the isolation structure comprises an STI structure.
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US11/388,855 US20070221976A1 (en) | 2006-03-23 | 2006-03-23 | Trench capacitor and fabrication method thereof |
US11/954,201 US7560356B2 (en) | 2006-03-23 | 2007-12-11 | Fabrication method of trench capacitor |
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US11/388,855 US20070221976A1 (en) | 2006-03-23 | 2006-03-23 | Trench capacitor and fabrication method thereof |
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WO2024066278A1 (en) * | 2022-09-29 | 2024-04-04 | 长鑫存储技术有限公司 | Trench capacitor packaging structure and preparation method therefor, and semiconductor structure |
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CN101986794B (en) * | 2007-11-02 | 2015-11-25 | Ipdia公司 | Sandwich construction and manufacture method thereof |
US7888723B2 (en) * | 2008-01-18 | 2011-02-15 | International Business Machines Corporation | Deep trench capacitor in a SOI substrate having a laterally protruding buried strap |
US8846470B2 (en) | 2011-06-06 | 2014-09-30 | International Business Machines Corporation | Metal trench capacitor and improved isolation and methods of manufacture |
US9012296B2 (en) * | 2012-12-11 | 2015-04-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-aligned deep trench capacitor, and method for making the same |
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US7560356B2 (en) | 2009-07-14 |
US20080090373A1 (en) | 2008-04-17 |
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