US20070152340A1 - Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry - Google Patents
Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry Download PDFInfo
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- US20070152340A1 US20070152340A1 US11/717,896 US71789607A US2007152340A1 US 20070152340 A1 US20070152340 A1 US 20070152340A1 US 71789607 A US71789607 A US 71789607A US 2007152340 A1 US2007152340 A1 US 2007152340A1
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- 238000003672 processing method Methods 0.000 title claims abstract description 38
- 239000000463 material Substances 0.000 claims abstract description 85
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 238000005530 etching Methods 0.000 claims abstract description 37
- 239000012535 impurity Substances 0.000 claims abstract description 27
- 230000000873 masking effect Effects 0.000 claims abstract description 23
- 238000009792 diffusion process Methods 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 description 4
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 239000012634 fragment Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical group CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Definitions
- This invention relates to semiconductor processing methods of forming integrated circuitry and to semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry.
- DRAM dynamic random access memory
- Processing of semiconductor devices typically involves many steps which include masking, doping, and etching. Each time one of these steps is performed, certain risks can arise which can jeopardize the integrity of a wafer being processed. For example, a mask misalignment error can cause a subsequent etch to undesirably etch into wafer or substrate structure which can cause catastrophic failure. Accordingly, it is desirable to reduce the number of processing steps utilized in the formation of integrated circuitry.
- This invention arose out of concerns associated with reducing the number of processing steps needed in the formation of integrated circuitry.
- This invention also arose out of concerns associated with improving the manner in which integrated circuitry memory devices, and in particular dynamic random access memory (DRAM) devices are fabricated.
- DRAM dynamic random access memory
- DRAM dynamic random access memory
- a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings.
- openings are contemporaneously formed in a photo masking layer over substrate areas where impurities are to be provided, and other areas where etching is to take place.
- the substrate is doped with impurities, and material of the substrate is etched through the mask openings.
- two conductive lines are formed over a substrate and a masking layer is formed over the conductive lines.
- Openings are formed in the masking layer in the same step, with one of the openings being received over one conductive line, and another of the openings being received over the other conductive line. Impurities provided through an opening into the substrate proximate one conductive line, and material from over the other conductive line is removed through the other opening to at least partially form a contact opening over the other conductive line.
- FIG. 2 is a view of the FIG. 1 wafer at a different processing step.
- FIG. 3 is a view of the FIG. 2 wafer at a different processing step.
- FIG. 4 is a view of the FIG. 3 wafer at a different processing step.
- a semiconductor wafer fragment in process is shown generally at 10 and includes a semiconductive substrate 12 .
- semiconductive substrate is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials).
- substrate refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
- substrate 12 comprises a bulk monocrystalline substrate.
- a photomasking layer 32 is formed over substrate 12 and conductive lines 18 , 20 .
- Masking layer 32 has been patterned to form masking layer openings 34 , 36 which are received over conductive lines 18 , 20 , respectively.
- the openings are preferably contemporaneously formed.
- opening 34 has a different, larger transverse cross-sectional dimension than opening 36 .
- Opening 34 is dimensioned such that insulative material 26 over conductive line 18 is entirely exposed therethrough, while insulative material 26 over conductive line 20 is only partially exposed through opening 36 .
- Opening 34 is preferably formed over a substrate area where doping impurities are primarily intended to be provided, while opening 36 is formed over a substrate area where etching is primarily intended to take place.
- the etching which is to take place through opening 36 forms a contact opening to conductive line 20 , as will become apparent below.
- memory circuitry such as dynamic random access memory (DRAM) circuitry
- DRAM dynamic random access memory
- conductive lines 38 are formed over a memory array area of substrate 12
- other conductive lines 18 , 20 are formed over a substrate area comprising a peripheral area proximate the memory array.
- the memory array is entirely masked with masking layer 32 , and remains so masked during the processing which is described just below. Accordingly, such constitutes keeping the memory array masked with masking layer 32 while forming openings, i.e., openings 34 , 36 , over the peripheral area.
- material of the substrate is etched through all of the openings, e.g., openings 34 , 36 .
- Such constitutes removing material from over the conductive lines and, in particular, from over conductive line 20 wherein a contact opening is at least partially formed thereto.
- second insulative material 30 is dry etched selectively relative to first insulative material 28 .
- Exemplary etching conditions include, in the context of a Lam 9400 etcher, a pressure of 20 mTorr, 500 Watts source power, 0 Watts bias power, 40 sccm SF 6 , and 20 sccm HBr.
- the inventive methods can reduce processing complexity by combining, in a single masking step, the doping of impurities into a substrate through openings formed in a mask layer and the etching of material of the substrate through the openings.
- the methods are employed in the formation of memory circuitry, and in particular DRAM circuitry. Accordingly, and in the preferred embodiment, processing can now take place to form capacitor constructions over the memory array ( FIG. 5 ).
Abstract
Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings. In one implementation, openings are contemporaneously formed in a photo masking layer over substrate areas where impurities are to be provided, and other areas where etching is to take place. In separate steps, the substrate is doped with impurities, and material of the substrate is etched through the mask openings. In another implementation, two conductive lines are formed over a substrate and a masking layer is formed over the conductive lines. Openings are formed in the masking layer in the same step, with one of the openings being received over one conductive line, and another of the openings being received over the other conductive line. Impurities provided through an opening into the substrate proximate one conductive line, and material from over the other conductive line is removed through the other opening to at least partially form a contact opening over the other conductive line.
Description
- This invention relates to semiconductor processing methods of forming integrated circuitry and to semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry.
- Processing of semiconductor devices typically involves many steps which include masking, doping, and etching. Each time one of these steps is performed, certain risks can arise which can jeopardize the integrity of a wafer being processed. For example, a mask misalignment error can cause a subsequent etch to undesirably etch into wafer or substrate structure which can cause catastrophic failure. Accordingly, it is desirable to reduce the number of processing steps utilized in the formation of integrated circuitry.
- This invention arose out of concerns associated with reducing the number of processing steps needed in the formation of integrated circuitry. This invention also arose out of concerns associated with improving the manner in which integrated circuitry memory devices, and in particular dynamic random access memory (DRAM) devices are fabricated.
- Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings. In one implementation, openings are contemporaneously formed in a photo masking layer over substrate areas where impurities are to be provided, and other areas where etching is to take place. In separate steps, the substrate is doped with impurities, and material of the substrate is etched through the mask openings. In another implementation, two conductive lines are formed over a substrate and a masking layer is formed over the conductive lines. Openings are formed in the masking layer in the same step, with one of the openings being received over one conductive line, and another of the openings being received over the other conductive line. Impurities provided through an opening into the substrate proximate one conductive line, and material from over the other conductive line is removed through the other opening to at least partially form a contact opening over the other conductive line.
- Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
-
FIG. 1 is a diagrammatic sectional view of a semiconductor wafer in process, in accordance with one aspect of the invention. -
FIG. 2 is a view of theFIG. 1 wafer at a different processing step. -
FIG. 3 is a view of theFIG. 2 wafer at a different processing step. -
FIG. 4 is a view of theFIG. 3 wafer at a different processing step. -
FIG. 5 is a diagrammatic sectional view of a semiconductor wafer fragment undergoing processing, in accordance with a preferred embodiment of the invention. - This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
- Referring to
FIG. 1 , a semiconductor wafer fragment in process is shown generally at 10 and includes asemiconductive substrate 12. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Preferably,substrate 12 comprises a bulk monocrystalline substrate. - In the illustrated example,
substrate 12 includes a pair offield oxide regions 14 with athin oxide layer 16, e.g., around 60 Angstroms, extending therebetween. A pair ofconductive lines substrate 12. The two illustrated conductive lines include apolysilicon layer 22 and asilicide layer 24, e.g. WSix.Insulative material 26 is provided over the conductive lines and preferably coverslayers insulative material 26 comprises a firstinsulative material 28 and a secondinsulative material 30 which is different from firstinsulative material 28. Preferably, the first and second insulative materials are selected such that one can be etched selectively relative to the other. - In this example, first
insulative material 28 comprises an oxide material and secondinsulative material 30 comprises a nitride material. The firstinsulative material 28 can be formed to a thickness of around 80 Angstroms over the sidewalls of each conductive line, and to around 300 Angstroms over top portions of the conductive lines. A suitable oxide material for firstinsulative material 28 is an oxide formed through decomposition of TEOS. Secondinsulative material 30 can be formed to a thickness over the top portions ofconductive lines insulative material 30 is silicon nitride. Of course, other materials, including other oxide and nitride materials are possible formaterials - Referring to
FIG. 2 , aphotomasking layer 32 is formed oversubstrate 12 andconductive lines Masking layer 32 has been patterned to formmasking layer openings conductive lines opening 34 has a different, larger transverse cross-sectional dimension than opening 36.Opening 34 is dimensioned such thatinsulative material 26 overconductive line 18 is entirely exposed therethrough, whileinsulative material 26 overconductive line 20 is only partially exposed throughopening 36.Opening 34 is preferably formed over a substrate area where doping impurities are primarily intended to be provided, while opening 36 is formed over a substrate area where etching is primarily intended to take place. Preferably, the etching which is to take place through opening 36 forms a contact opening toconductive line 20, as will become apparent below. - Referring to
FIGS. 2 and 5 , a preferred embodiment is set forth. There, memory circuitry, such as dynamic random access memory (DRAM) circuitry, is being formed oversubstrate 12. Accordingly,conductive lines 38 are formed over a memory array area ofsubstrate 12, and otherconductive lines masking layer 32, and remains so masked during the processing which is described just below. Accordingly, such constitutes keeping the memory array masked withmasking layer 32 while forming openings, i.e.,openings - Referring to
FIG. 3 , doping impurities are provided intosubstrate 12 proximateconductive line 18 sufficient to formdiffusion regions 40. Doping of the substrate preferably comprises providing n+ dopant to form the diffusion regions. Some doping impurities can be received through opening 36 and intoinsulative material 30, but do not meaningfully affectconductive line 20. - Referring to
FIGS. 3 and 4 , doping impurities are provided into the substrate throughopenings diffusion regions 40 are formed only relative to opening 34 and not opening 36. Of course, doping can take place after the etching of the substrate material through the openings. - Referring to
FIG. 4 , material of the substrate is etched through all of the openings, e.g.,openings conductive line 20 wherein a contact opening is at least partially formed thereto. Preferably, secondinsulative material 30 is dry etched selectively relative to firstinsulative material 28. Exemplary etching conditions include, in the context of a Lam 9400 etcher, a pressure of 20 mTorr, 500 Watts source power, 0 Watts bias power, 40 sccm SF6, and 20 sccm HBr. Such etch conditions can etch nitride at a rate of about 1200 Angstrom/minute and oxide at a rate of about 100 Angstrom/minute. Such etching can take place either anisotropically or isotropically. In the illustrated example, the etching of the second layer comprises an isotropic etch which removes insulative material from the sides of both conductive lines. - The inventive methods can reduce processing complexity by combining, in a single masking step, the doping of impurities into a substrate through openings formed in a mask layer and the etching of material of the substrate through the openings. In a preferred embodiment, the methods are employed in the formation of memory circuitry, and in particular DRAM circuitry. Accordingly, and in the preferred embodiment, processing can now take place to form capacitor constructions over the memory array (
FIG. 5 ). - In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.
Claims (32)
1. A semiconductor processing method comprising, in a single masking step, doping impurities into a substrate through openings formed in a mask layer, and etching material of the substrate through said openings.
2. The semiconductor processing method of claim 1 further comprising doping the impurities into the substrate prior to etching the substrate material.
3. The semiconductor processing method of claim 1 , wherein some of the openings have different transverse cross-sectional dimensions than other of the openings.
4. The semiconductor processing method of claim 1 , wherein the substrate comprises a bulk monocrystalline substrate and the openings are dimensioned to permit some of the impurity to be received by the substrate as diffusion regions only through some of the openings.
5. The semiconductor processing method of claim 1 , wherein two openings are received over individual conductive lines which are covered with insulative material, and the etching of the substrate material comprises etching portions of the insulative material.
6. The semiconductor processing method of claim 5 , wherein the etching comprises isotropically etching said insulative material.
7. The semiconductor processing method of claim 5 , wherein the etching comprises anisotropically etching said insulative material.
8. The semiconductor processing method of claim 5 , wherein the insulative material comprises first and second different insulative material, and the etching comprises selectively etching one relative to the other.
9. The semiconductor processing method of claim 8 , wherein the one insulative material comprises a nitride material.
10. A semiconductor processing method of forming integrated circuitry comprising:
forming a photomasking layer over a substrate;
contemporaneously forming openings in the photomasking layer over substrate areas where impurities are to be provided, and other substrate areas where etching is to take place; and
in separate steps, doping the substrate with impurities through said openings and etching the substrate through said openings.
11. The semiconductor processing method of claim 10 further comprising doping the substrate prior to etching the substrate.
12. The semiconductor processing method of claim 10 , wherein one opening is formed over a conductive line, and further comprising providing impurities into the substrate proximate the conductive line.
13. The semiconductor processing method of claim 10 , wherein the substrate comprises a *bulk substrate, and further comprising providing impurities through the openings, the openings being dimensioned to permit formation of diffusion regions within the bulk substrate proximate only some of the openings.
14. The semiconductor processing method of claim 10 further comprising etching substrate material through all of the openings.
15. The semiconductor processing method of claim 10 , wherein the forming of the openings comprises forming two spaced-apart openings over first and second different insulative materials, and further comprising selectively etching one of the insulative materials within the openings relative to the other of the insulative materials within the openings.
16. The semiconductor processing method of claim 15 , wherein the etching comprises isotropically etching said material.
17. The semiconductor processing method of claim 15 , wherein the etching comprises anisotropically etching said material.
18. A semiconductor processing method of forming integrated circuitry comprising:
forming two conductive lines over a substrate;
forming a masking layer over the two conductive lines;
forming two openings through the masking layer in the same step, one of the openings being received over one conductive line, another of the openings being received over the other conductive line;
providing impurity through the one opening and into the substrate proximate the one conductive line; and
removing material over the other conductive line through the other opening to at least partially form a contact opening over the other conductive line.
19. The semiconductor processing method of claim 18 , wherein the forming of the two openings comprises forming the one opening to have a larger transverse cross-section than the other of the openings.
20. The semiconductor processing method of claim 18 , wherein the removing comprises removing material from over both conductive lines.
21. The semiconductor processing method of claim 18 , wherein the other conductive line comprises insulative material disposed over a top portion of the conductive line, the insulative material comprising first and second different insulative materials, and wherein the removing comprises selectively etching one of the insulative materials relative to the other of the insulative material.
22. The semiconductor processing method of claim 21 , wherein the one insulative material comprises a nitride material.
23. The semiconductor processing method of claim 18 , wherein both conductive lines comprise insulative material disposed over respective top portions thereof, the insulative material comprising first and second different insulative materials, and wherein the removing comprises selectively etching one of the insulative materials relative to the other of the insulative material.
24. A semiconductor processing method of forming integrated circuitry comprising:
forming two conductive lines over a substrate, the lines comprising first and second insulative materials which are different from one another;
forming a masking layer over the two conductive lines;
forming two openings through the masking layer, one of the openings being received over one of the conductive lines, another of the openings being received over the other conductive line;
providing impurity through the one opening and into the substrate proximate the one conductive line; and
etching one of the first and second insulative materials to at least partially form a contact opening to at least one of the conductive lines.
25. The semiconductor processing method of claim 24 further comprising providing the impurity into the substrate prior to the etching of the one insulative material.
26. The semiconductor processing method of claim 24 further comprising etching the one of the first and second insulative materials prior to the providing of the impurity.
27. The semiconductor processing method of claim 24 , wherein the etching of the one of the first and second insulative materials comprising selectively etching said one material relative to the other of the first and second insulative materials.
28. The semiconductor processing method of claim 24 , wherein the forming of the two openings comprises forming said openings to have different transverse cross sections.
29. The semiconductor processing method of claim 24 , wherein insulative material of only one conductive line is entirely exposed through an opening.
30. The semiconductor processing method of claim 24 , wherein the one insulative material comprises a nitride material.
31. A semiconductor processing method of forming DRAM circuitry comprising:
forming a plurality of conductive lines over a substrate, some of the conductive lines being formed over a memory array area of the substrate, other conductive lines being formed over a substrate area comprising a peripheral area proximate the memory array;
forming a masking layer over the substrate;
in the same masking step, forming a plurality of openings through the masking layer over the peripheral area while keeping the memory array masked with the masking layer;
providing impurity through the openings; and
removing material from over the conductive lines through the openings.
32. The semiconductor processing method of claim 31 further comprising providing the impurity prior to removing the material from over the conductive lines.
Priority Applications (1)
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US11/717,896 US20070152340A1 (en) | 1998-08-27 | 2007-03-13 | Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry |
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US09/141,776 US6177339B1 (en) | 1998-08-27 | 1998-08-27 | Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry |
US09/689,237 US6337261B1 (en) | 1998-08-27 | 2000-10-11 | Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry |
US09/879,741 US6500738B2 (en) | 1998-08-27 | 2001-06-11 | Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry |
US10/243,156 US6740583B2 (en) | 1998-08-27 | 2002-09-12 | Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry |
US10/851,616 US6949430B2 (en) | 1998-08-27 | 2004-05-20 | Semiconductor processing methods |
US11/236,115 US7235480B2 (en) | 1998-08-27 | 2005-09-26 | Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry |
US11/717,896 US20070152340A1 (en) | 1998-08-27 | 2007-03-13 | Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry |
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US10/851,616 Expired - Fee Related US6949430B2 (en) | 1998-08-27 | 2004-05-20 | Semiconductor processing methods |
US11/236,115 Expired - Fee Related US7235480B2 (en) | 1998-08-27 | 2005-09-26 | Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry |
US11/717,896 Abandoned US20070152340A1 (en) | 1998-08-27 | 2007-03-13 | Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry |
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US09/141,776 Expired - Lifetime US6177339B1 (en) | 1998-08-27 | 1998-08-27 | Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry |
US09/689,237 Expired - Fee Related US6337261B1 (en) | 1998-08-27 | 2000-10-11 | Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry |
US09/879,741 Expired - Lifetime US6500738B2 (en) | 1998-08-27 | 2001-06-11 | Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry |
US10/243,156 Expired - Lifetime US6740583B2 (en) | 1998-08-27 | 2002-09-12 | Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry |
US10/851,616 Expired - Fee Related US6949430B2 (en) | 1998-08-27 | 2004-05-20 | Semiconductor processing methods |
US11/236,115 Expired - Fee Related US7235480B2 (en) | 1998-08-27 | 2005-09-26 | Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry |
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Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US6395623B1 (en) * | 1998-08-27 | 2002-05-28 | Micron Technology, Inc. | Semiconductor processing methods of forming a contact opening to a conductive line and methods of forming substrate active area source/drain regions |
US6177339B1 (en) | 1998-08-27 | 2001-01-23 | Micron Technology, Inc. | Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry |
US6887753B2 (en) * | 2001-02-28 | 2005-05-03 | Micron Technology, Inc. | Methods of forming semiconductor circuitry, and semiconductor circuit constructions |
US7800965B2 (en) | 2008-03-10 | 2010-09-21 | Micron Technology, Inc. | Digit line equilibration using access devices at the edge of sub-arrays |
US8765585B2 (en) * | 2011-04-28 | 2014-07-01 | International Business Machines Corporation | Method of forming a borderless contact structure employing dual etch stop layers |
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Also Published As
Publication number | Publication date |
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US20040214438A1 (en) | 2004-10-28 |
US20060024933A1 (en) | 2006-02-02 |
US20030027387A1 (en) | 2003-02-06 |
US6500738B2 (en) | 2002-12-31 |
US7235480B2 (en) | 2007-06-26 |
US6337261B1 (en) | 2002-01-08 |
US20010027000A1 (en) | 2001-10-04 |
US6949430B2 (en) | 2005-09-27 |
US6740583B2 (en) | 2004-05-25 |
US6177339B1 (en) | 2001-01-23 |
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