US20070145498A1 - Device with scavenging spacer layer - Google Patents
Device with scavenging spacer layer Download PDFInfo
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- US20070145498A1 US20070145498A1 US11/320,305 US32030505A US2007145498A1 US 20070145498 A1 US20070145498 A1 US 20070145498A1 US 32030505 A US32030505 A US 32030505A US 2007145498 A1 US2007145498 A1 US 2007145498A1
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- layer
- spacer layer
- metal
- gate dielectric
- dielectric layer
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- 125000006850 spacer group Chemical group 0.000 title claims abstract description 103
- 230000002000 scavenging effect Effects 0.000 title claims description 42
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 229910052751 metal Inorganic materials 0.000 claims abstract description 47
- 239000002184 metal Substances 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 40
- 239000000463 material Substances 0.000 claims description 58
- 230000007704 transition Effects 0.000 claims description 39
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 34
- 239000001301 oxygen Substances 0.000 claims description 34
- 229910052760 oxygen Inorganic materials 0.000 claims description 34
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 229910052757 nitrogen Inorganic materials 0.000 claims description 11
- 230000002950 deficient Effects 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 24
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 177
- 230000006870 function Effects 0.000 description 22
- 239000002516 radical scavenger Substances 0.000 description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 239000010936 titanium Substances 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- -1 e.g. Inorganic materials 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 229910052735 hafnium Inorganic materials 0.000 description 5
- 238000010926 purge Methods 0.000 description 5
- 229910052715 tantalum Inorganic materials 0.000 description 5
- 229910052726 zirconium Inorganic materials 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910000951 Aluminide Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910004143 HfON Inorganic materials 0.000 description 1
- 229940123973 Oxygen scavenger Drugs 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910003071 TaON Inorganic materials 0.000 description 1
- 229910010282 TiON Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 229910026551 ZrC Inorganic materials 0.000 description 1
- 229910006252 ZrON Inorganic materials 0.000 description 1
- OTCHGXYCWNXDOA-UHFFFAOYSA-N [C].[Zr] Chemical compound [C].[Zr] OTCHGXYCWNXDOA-UHFFFAOYSA-N 0.000 description 1
- XWCMFHPRATWWFO-UHFFFAOYSA-N [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] Chemical compound [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] XWCMFHPRATWWFO-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- CAVCGVPGBKGDTG-UHFFFAOYSA-N alumanylidynemethyl(alumanylidynemethylalumanylidenemethylidene)alumane Chemical compound [Al]#C[Al]=C=[Al]C#[Al] CAVCGVPGBKGDTG-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- VKJLWXGJGDEGSO-UHFFFAOYSA-N barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[Ti+4].[Ba+2] VKJLWXGJGDEGSO-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- WHJFNYXPKGDKBB-UHFFFAOYSA-N hafnium;methane Chemical compound C.[Hf] WHJFNYXPKGDKBB-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- JQJCSZOEVBFDKO-UHFFFAOYSA-N lead zinc Chemical compound [Zn].[Pb] JQJCSZOEVBFDKO-UHFFFAOYSA-N 0.000 description 1
- 150000001247 metal acetylides Chemical class 0.000 description 1
- 229910001510 metal chloride Inorganic materials 0.000 description 1
- 229910001507 metal halide Inorganic materials 0.000 description 1
- 150000005309 metal halides Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000002902 organometallic compounds Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- KJXBRHIPHIVJCS-UHFFFAOYSA-N oxo(oxoalumanyloxy)lanthanum Chemical compound O=[Al]O[La]=O KJXBRHIPHIVJCS-UHFFFAOYSA-N 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000003826 tablet Substances 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
Definitions
- MOS field-effect transistors with very thin silicon dioxide based gate dielectrics may experience unacceptable gate leakage currents.
- Forming the gate dielectric from certain high-k dielectric materials, instead of silicon dioxide, can reduce gate leakage.
- a silicon dioxide transition layer may form between the high-k dielectric and the substrate. This transition layer may grow larger during high temperature processes when available oxygen may react with the substrate to form more silicon dioxide. The presence of a thick transition layer may unfavorably contribute to the overall electrical thickness of the gate dielectric stack.
- FIG. 1 is a cross sectional side view that illustrates the semiconductor device of one embodiment of the present invention.
- FIG. 2 is a cross sectional side view that illustrates the electrode in more detail.
- FIG. 3 is a cross sectional side view that illustrates the thicknesses and sizes of various parts of the device of FIG. 1 .
- FIGS. 4 through 11 are cross sectional side views that illustrate how the device of FIG. 1 may be made in some embodiments.
- FIG. 12 is a flow chart that summarizes a method according to an embodiment of the present invention.
- FIG. 13 illustrates a system in accordance with one embodiment of the present invention.
- an apparatus and method relating to the formation of a device with a scavenging spacer layer are described.
- various embodiments will be described. However, one skilled in the relevant art will recognize that the various embodiments may be practiced without one or more of the specific details, or with other replacement and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the invention. Nevertheless, the invention may be practiced without specific details. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
- FIG. 1 is a cross sectional side view that illustrates the semiconductor device 100 of one embodiment of the present invention.
- the device 100 may include a substrate 102 .
- Substrate 102 may comprise any material that may serve as a foundation upon which a semiconductor device may be built.
- the substrate 102 may be a silicon containing substrate 102 .
- the substrate 102 may be a bulk substrate 102 , such as a wafer of single crystal silicon, a semiconductor-on-insulator (SOI) substrate 102 , such as a layer of silicon on a layer of insulating material on another layer of silicon, or another type of substrate 102 .
- SOI semiconductor-on-insulator
- the device 100 may be a transistor in some embodiments.
- the device 100 may be a planar transistor on a bulk substrate 102 , a planar transistor on an SOI substrate 102 , a FIN-FET transistor on a bulk substrate 102 , a FIN-FET transistor on an SOI substrate 102 , a tri-gate transistor on a bulk substrate 102 , a tri-gate transistor on an SOI substrate 102 , or another type of transistor or another device.
- a high-k gate dielectric layer 106 may be formed on the substrate 102 .
- the high-k gate dielectric layer 106 may comprise, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
- the high-k gate dielectric layer 106 may have a k-value higher than about 7.5 in some embodiments. In other embodiments, the high-k gate dielectric layer 106 may have a k-value higher than about 10. In other embodiments, the high-k gate dielectric layer 106 may comprise a material such as Al 2 O 3 with a k-value of about 12, or may comprise a material with a higher k-value than that. In other embodiments, the high-k gate dielectric layer 106 may have a k-value between about 15 and about 25, e.g. HfO 2 . In yet other embodiments, the high-k gate dielectric layer 106 may have a k-value even higher, such as 35, 80 or even higher.
- This transition layer 104 may be a thin layer 104 of oxide, such as a thin layer 104 of silicon dioxide in embodiments where the substrate 102 comprises silicon, in some embodiments. If, during high temperature processes (such as processes performed at about 500 degrees Celsius or higher) oxygen is available to react with the substrate at the region of the transition layer 104 , it may form an unwanted thicker oxide layer 104 beneath the high-k dielectric layer 106 and reduce the performance of the transistor.
- high temperature processes such as processes performed at about 500 degrees Celsius or higher
- An electrode 108 may be on the high-k gate dielectric layer 106 .
- the electrode 108 may include multiple layers.
- the electrode 108 may include a different number of layers, and the layers may be different.
- the polysilicon layer 118 may comprise doped polysilicon in an embodiment.
- the polysilicon layer 118 may not be a polysilicon layer 118 in some embodiments, but instead comprise other non-polysilicon materials, or it may be absent.
- the cap layer 116 may comprise silicon in some embodiments, although it may comprise other materials in other embodiments.
- the work function layer 115 may comprise a metal work function layer 115 .
- the metal work function layer 115 may be an n-type metal gate electrode.
- Materials that may be used to form n-type metal gate electrodes include: hafnium, zirconium, titanium, tantalum, aluminum, their alloys (e.g., metal carbides that include these elements, i.e., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and aluminides (e.g., an aluminide that comprises hafnium, zirconium, titanium, tantalum, or tungsten).
- the metal work function layer 115 may be a p-type metal gate electrode.
- Materials for forming p-type metal gate electrodes include: ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide.
- the metal work function layer 115 may be a mid-gap metal gate electrode.
- the work function layer 115 may comprise stoichiometric titanium nitride, tantalum nitride, or another mid-gap material.
- the device 100 may be a transistor, such as an NMOS, PMOS, or mid-gap transistor.
- metal work function layers 115 for NMOS transistor devices 100 may have a workfunction that is between about 3.9 eV and about 4.2 eV.
- metal work function layers 115 for PMOS devices 100 may have a workfunction that is between about 4.9 eV and about 5.2 eV.
- metal work function layers 115 for semiconductor on insulator (SOI) mid-gap transistor devices 100 may have a workfunction that is between the workfunctions of NMOS and PMOS gate electrode materials.
- a metal work function layer 115 may consist essentially of a homogeneous metal layer. Alternatively, relatively thin n-type, p-type, or mid-gap metal layers (like those listed above) may generate the lower part of the metal work function layer 115 , with the remainder of the metal work function layer 115 comprising another metal or metals, e.g., a metal that may be easily polished like tungsten, aluminum, titanium, or titanium nitride. Such a material may make up the remainder of the gate electrode 108 , or additional layers, such as the cap layer 116 and polysilicon layer 118 illustrated in FIG. 3 may be part of the gate electrode 108 as well. Although a few examples of materials for forming a metal work function layer 115 are identified here, such a component may be made from many other materials, as will be apparent to those skilled in the art.
- the inner spacers 110 may comprise a layer of material that can be formed at a temperature below about 500 degrees Celsius.
- the inner spacers 110 may comprise silicon nitride, aluminum nitride, silicon oxide, carbon doped silicon nitride, or another material.
- the material of the inner spacers 110 has a high etch bias relative to other materials in the device 100 . Some embodiments may lack the inner spacers 110 .
- scavenger spacers 112 may be on side walls of the high-k dielectric layer 106 and electrode 108 .
- the scavenger spacers 112 may be on side walls the inner spacers 110 .
- the scavenger spacers 112 may comprise a material that is reactive with oxygen in embodiments where the scavenger spacers 112 are oxygen scavenger spacers 112 .
- the scavenger spacers 112 may originally comprise a layer of oxidizable material such as a group III, IV or V metal (e.g., Hf, Zr, Ti, Ta), aluminum, a nitride of a group III, IV or V metal (e.g., HfN, ZrN, TiN, TaN or Ta 3 N 5 ), a nitride of a group III, IV or V metal that is deficient in nitrogen (e.g., Ti 1 N 1-x , or Ta 3 N 5-x ), a silicon nitride deficient in nitrogen (e.g., Si 3 N 4-x ), or another material.
- Deficient in nitride as used herein means the material is relatively rich in the non-nitrogen element.
- Oxygen present may react with the scavenger spacers 112 , which prevents the oxygen from reacting with other materials.
- the scavenger spacers 112 may react with oxygen and thus reduce an oxide, such as silicon dioxide, forming from the reaction of the oxygen and the substrate 102 . This may result in reduction in thickness of the transition layer 104 ; some oxygen that would react with the substrate 102 to form a thicker transition layer 104 may instead react with the scavenger spacers 112 .
- the scavenger spacers 112 may at least partially prevent oxidation of the substrate 102 , which could result in the formation of undesired oxide, such as silicon oxide, beneath the high-k dielectric layer 106 and electrode 108 .
- undesired oxide such as silicon oxide
- Such an undesired oxide could be of a thickness enough to degrade the performance of the device if its formation is not prevented.
- outer spacers 114 may be on side walls of the high-k dielectric layer 106 and electrode 108 .
- the outer spacers 114 may be on side walls of the scavenger spacers 112 .
- Outer spacers 114 may comprise a layer any material suitable for forming spacers, including materials that require high temperatures to form. Some embodiments may lack the outer spacers 114 .
- FIG. 3 is a cross sectional side view that illustrates the thicknesses and sizes of various parts of the device 100 of FIG. 1 , according to one embodiment.
- the length 202 may be the length of the gate electrode 108 , which is substantially the same as the length of the channel of the transistor.
- the electrode 108 may have a length 202 of 30-35 nm. In other embodiments, the length 202 may be different.
- the transition layer 104 may have a thickness 204 .
- This transition layer 104 may be as thin as a monolayer of oxide in some embodiments at the time of formation of the scavenger spacer layer 112 .
- the thickness 204 may be as thin as about 3 angstroms or less at the time of formation of the scavenger spacer layer 112 .
- the transition layer 104 may have more than one layer of oxide and/or may be thicker than about 3 angstroms.
- the thickness 204 may grow larger, but because of the presence of the scavenging material in the scavenger spacers 112 , the thickness 204 may not grow as big as it would absent the scavenging material.
- the thickness 204 of the transition layer 104 may remain about 3 angstroms in the completed device 100 .
- the transition layer 104 may have a thickness 204 between about 4 angstroms and about 8 angstroms in the completed device 100 .
- Other embodiments may have a transition layer 104 with a different thickness 204 in the completed device 100 .
- the inner spacer layer 110 may also have a thickness 206 .
- the inner spacer layer 110 and thus the inner spacers 110 , may have a thickness 206 between about 10 angstroms and about 100 angstroms, although the thickness 206 may be different in other embodiments.
- the scavenging spacer layer 112 may have a thickness 208 .
- the thickness 208 may be between about 30 angstroms and about 50 angstroms, although the scavenging spacer layer 112 may have a different thickness 208 in other embodiments.
- the thickness 208 may be chosen based at least in part on the fabrication of the device 100 . For example, if higher temperatures are used or there is more ambient oxygen, the thickness 208 may be greater than if lower temperatures are used, or less ambient oxygen.
- the thickness 208 may be chosen so that the metal is substantially entirely oxidized by the completion of fabrication of the device, to prevent source-to-drain short circuits.
- the outer spacers 114 may have a thickness 210 .
- This thickness 210 may be any suitable thickness 210 to result in the sum of the thicknesses 206 , 208 , 210 being a desired thickness for the device's 100 spacers.
- the high-k dielectric layer 106 may have a thickness 212 .
- the thickness 212 may be selected to provide an acceptable level of leakage current in the device 100 , and to provide a selected electrical thickness of the gate stack, in embodiments where the device 100 is a transistor.
- the high-k gate dielectric layer 106 may be less than about 40 angstroms thick 212 .
- the high-k dielectric layer 106 may have a thickness 212 less than about 25 angstroms.
- the high-k gate dielectric layer 106 may be between about 5 angstroms and about 20 angstroms thick 212 .
- the high-k dielectric layer 106 may have a different thickness 212 in other embodiments.
- the electrode 108 and a work function layer 115 may have thicknesses (not shown).
- the thickness of the work function layer 115 may be chosen to provide a desired work function and threshold voltage (V Th ) of the gate of the device 100 .
- V Th threshold voltage
- the thickness may between about 50 angstroms and about 200 angstroms. In other embodiments, the thickness may be greater than about 75 angstroms. In yet other embodiments, the thickness may be different.
- the device 100 may reduce leakage current without increasing the electrical thickness of the gate stack (including the transition layer 104 and high-k dielectric layer 106 ).
- the use of the scavenging spacer layer 112 may allow a stable amount of leakage current but allow faster performance of the device 100 , compared to a device without a scavenging spacer layer 112 .
- Other embodiments may use intermediate values, such as increasing performance somewhat and decreasing leakage current somewhat.
- FIGS. 4 through 11 are cross sectional side views that illustrate how the device 100 of FIG. 1 may be made in some embodiments.
- FIG. 4 is a cross sectional side view that illustrates a SOI substrate 102 that may be used in the device 100 .
- the SOI substrate 102 may include a semiconductor substrate layer 120 , which may also be referred to as a first semiconductor layer 120 .
- This semiconductor substrate 120 may comprise any suitable semiconductor material or materials, including silicon.
- On the semiconductor substrate 120 may be an insulating layer 122 .
- the insulating layer 122 may comprise any suitable insulating material and may function to electrically isolate various devices formed on the substrate. In embodiments where the insulating layer 122 comprises an oxide, the insulating layer may also be referred to as a buried oxide layer.
- On the insulating layer 122 may be a second semiconductor layer 124 .
- the second semiconductor layer 124 may comprise any suitable semiconductor material or materials, including silicon.
- FIG. 5 is a cross sectional side view that illustrates the SOI substrate 102 after formation of a transition layer 104 , high-k dielectric layer 106 , and electrode layer 108 on the substrate 102 , according to one embodiment of the present invention.
- the transition layer 104 may form on the surface of the substrate 102 .
- the transition layer 104 may be between about a monolayer of a material such as silicon dioxide and about three angstroms, although in other embodiments it may be thicker.
- the high-k dielectric layer 106 may be deposited on the transition layer 104 .
- high-k gate dielectric layer 106 may be formed on the substrate 102 by an atomic layer deposition (“ALD”) process.
- ALD atomic layer deposition
- a growth cycle may be repeated until a high-k gate dielectric layer 106 of a desired thickness is created.
- Such a growth cycle may comprise the following sequence in an embodiment. Steam is introduced into a CVD (“chemical vapor deposition”) reactor for a selected pulse time, followed by a purging gas. A precursor (e.g., an organometallic compound, a metal chloride or other metal halide) is then pulsed into the reactor, followed by a second purge pulse. (A carrier gas that comprises nitrogen or another inert gas may be injected into the reactor at the same time.)
- CVD chemical vapor deposition
- the pressure at which the reactor is operated, the gases' flow rates, and the temperature at which the substrate is maintained may be varied depending upon the application and the precursor that is used.
- the CVD reactor may be operated long enough to form the high-k gate dielectric layer 106 with the desired thickness 212 .
- Metal work function layer 115 may be formed on the high-k gate dielectric layer 106 .
- Metal work function layer 115 may be formed using conventional metal deposition processes, e.g. CVD or PVD processes, by using ALD, or another suitable method, and may comprise any conductive material from which metal gate electrodes may be derived.
- the other layers (if any) of the electrode 108 may then be formed on the work function layer 115 by any suitable method.
- the cap layer 116 may comprise silicon and may be formed by sputtering silicon at a relatively low temperature below about 500 degrees Celsius.
- the cap layer 116 may comprise a different material and may be formed by a different process in other embodiments.
- the polysilicon layer 118 may be deposited at a temperature of over 500 degrees Celsius. However, the cap layer 116 at this point may seal layers beneath the cap layer 116 from contact with oxygen, thus preventing or reducing growth in the thickness of the transition layer 104 in some embodiments.
- FIG. 6 is a cross sectional side view that illustrates the device 100 after the transition layer 104 , high-k dielectric layer 106 , and electrode 108 have been patterned to remove them from areas on which they are not desired, according to one embodiment of the present invention.
- Any suitable method may be used to pattern the transition layer 104 , high-k dielectric layer 106 , and electrode 108 .
- the portions of the layers 104 , 106 , 108 desired to remain in place may be protected by patterned photoresist and/or hardmask material and exposed portions of the conductive layers 104 , 106 , 108 removed by an etching procedure, such as a plasma-based dry etch.
- FIG. 7 is a cross sectional side view that illustrates the device 100 after formation of the inner spacer layer 110 , according to one embodiment.
- the inner spacer layer 110 may comprise silicon nitride, silicon nitride with carbon, or other materials in other embodiments.
- the inner spacer layer 110 may be formed by chemical vapor deposition (“CVD”), plasma-enhanced chemical vapor deposition (“PECVD”), atomic layer deposition (“ALD”), or other suitable processes.
- the inner spacer layer 110 may be formed at a temperature below about 500 degrees Celsius.
- the inner spacer layer 110 may be formed at a temperature between about 300 to about 400 degrees Celsius, although other temperatures may be used in other embodiments.
- the inner spacer layer 110 in some embodiments may not provide a good enough seal of the layers on which it is deposited to prevent oxygen from reaching those layers.
- FIG. 8 is a cross sectional side view that illustrates the device 100 after formation of the scavenger spacer layer 112 , according to one embodiment.
- the scavenger spacer layer 112 may comprise a layer of oxidizable material such as a group III, IV or V metal (e.g., Hf, Zr, Ti, Ta), aluminum, a nitride of a group III, IV or V metal (e.g., HfN, ZrN, TiN, TaN or Ta 3 N 5 ), a nitride of a group III, IV or V metal that is deficient in nitrogen (e.g., Ti 1 N 1-x , or Ta 3 N 5-x ), a silicon nitride deficient in nitrogen (e.g., Si 3 N 4-x ), or another material.
- a group III, IV or V metal e.g., Hf, Zr, Ti, Ta
- a nitride of a group III, IV or V metal
- the scavenger spacer layer 112 may be formed at a temperature below about 500 degrees Celsius. Any suitable process, depending on the material chosen for the scavenger spacer layer 112 , may be used to form the scavenger spacer layer 112 .
- FIG. 9 is a cross sectional side view that illustrates the device 100 after formation of the outer spacer layer 114 , according to one embodiment.
- the outer spacer layer 114 may comprise any suitable material and may be formed by any suitable process. As the scavenger spacer layer 112 is in place, the outer spacer layer 114 may be formed at high temperature (over 500 degrees Celsius). The scavenger spacer layer 112 material will react with oxygen to reduce or elimination growth in the thickness 204 of the transition layer 104 .
- Portions of the inner spacer layer 110 , scavenger spacer layer 112 , and outer spacer layer 114 may be removed to result in the device 100 as illustrated in FIG. 1 .
- Any suitable process such as a dry etching process, may be used to remove portions of the spacer layers 110 , 112 , 114 and result in the spacers 110 , 112 , 114 .
- FIG. 10 is a cross sectional side view that illustrates additional regions 130 added to the substrate 102 in some embodiments.
- the additional regions 130 may be omitted in some embodiments.
- the additional regions 130 may be added by epitaxy.
- the additional regions 130 may comprise the same material as the original substrate 102 .
- the additional regions 130 may be considered portions of the substrate 102 after formation of the additional regions 130 . As shown in FIG.
- the additional regions 130 may have a height above the original substrate 102 a distance away from the spacers 110 , 112 , 114 , but the thickness of the additional regions 130 may decrease closer to the spacers 110 , 112 , 114 .
- FIG. 11 is a cross sectional side view that illustrates the formation of source/drain implant regions 142 by implantation of ions 140 .
- the ions 140 are implanted into the substrate 142 to form the source/drain implanted regions 142 of the substrate 102 .
- the scavenging spacers 112 may act to react with ambient oxygen to prevent that oxygen from reaching and reacting with the substrate 102 under the gate stack 106 , 108 , which would result in a thicker transition layer 104 .
- the scavenging spacers 112 may keep the transition layer 104 thinner than it would be otherwise.
- transition layer 104 may be thinner than it would be otherwise.
- Such a thinner transition layer 104 may allow the device 100 to have faster performance than it would with a thicker transition layer 104 .
- FIG. 12 is a flow chart 300 that summarizes a method according to an embodiment of the present invention.
- a gate stack of a device such as gate stack 106 , 108 shown in FIG. 1 , may be formed 302 .
- a scavenging spacer 112 may be formed 304 . This scavenging spacer 112 may be reactive with oxygen to prevent oxygen from reaching a transition layer 104 beneath the gate stack 106 , 108 or reduce the amount of oxygen reaching a transition layer 104 beneath the gate stack 106 , 108 . Processes at high temperature or processes that involve oxygen (as part of an ambient atmosphere or part of the material of a structure) may then be performed 306 .
- These processes may include forming additional spacers, annealing processes, ion implantation, and other processes. Since the under gate region is sealed by the scavenging spacer 112 , oxygen may be mostly or entirely prevented from being transported to the under gate region during these processes. Thus, reaction of oxygen with the substrate beneath the gate and formation of a thick oxide layer 104 beneath the gate may be avoided, which may prevent degradation of the performance of the device.
- the device 100 may have one or more layers of dielectric and interconnections above the spacers 110 , 112 , 114 and electrode 108 .
- the material of the scavenging spacers 112 may have reacted with oxygen.
- the material of the scavenging spacers 112 thus may be different than it was when the scavenging spacer layer 112 was originally formed (illustrated in FIG. 8 ).
- the scavenger spacers 112 may originally comprise a layer of oxidizable material such as a group III, IV or V metal (e.g., Hf, Zr, Ti, Ta), aluminum, a nitride of a group III, IV or V metal (e.g., HfN, ZrN, TiN, TaN or Ta 3 N 5 ), a nitride of a group III, IV or V metal that is deficient in nitrogen (e.g., Ti 1 N 1-x , or Ta 3 N 5-x ), a silicon nitride deficient in nitrogen (e.g., Si 3 N 4-x ), or another material.
- a group III, IV or V metal e.g., Hf, Zr, Ti, Ta
- a nitride of a group III, IV or V metal e.g., HfN, ZrN, TiN, TaN or Ta 3 N 5
- the scavenging spacers 112 may comprise one of the above-listed materials with the addition of oxygen in varying amounts.
- the scavenging spacers 112 may comprise an oxynitride of a group III, IV or V metal.
- the scavenging spacer 112 originally comprises HfN, it may comprise HfON after completion of the device 100 .
- the scavenging spacer 112 originally comprises ZrN, it may comprise ZrON after completion of the device 100 .
- the scavenging spacer 112 originally comprises TiN it may comprise TiON after completion of the device 100 .
- the scavenging spacer 112 may comprise TaON after completion of the device 100 . In an embodiment where the scavenging spacer 112 originally comprises Si 3 N 4-x , it may comprise Si 3 N 4-x O 1.5x after completion of the device 100 . In other examples, the scavenging spacer 112 may comprise an oxidized group III, IV, or V metal, oxidized aluminum, a silicon oxynitride, or another material.
- the transition layer 104 may have a thickness 204 of around three angstroms or less in an embodiment. In another embodiment, the transition layer 104 may have a thickness 204 of around four angstroms or less after the device 100 has been completely formed, although other embodiments may have a thicker transition layer 104 . Absent the scavenging spacers 112 , the minimum size of the transition layer 104 is significantly greater. The transition layer 104 would have a larger thickness 204 had oxygen been free to reach and react with the substrate 102 , as would be the case in the absence of the scavenging spacers 112 .
- FIG. 13 illustrates a system 400 in accordance with one embodiment of the present invention.
- One or more devices 100 formed with the scavenging spacers 112 as described above may be included in the system 400 of FIG. 13 .
- system 400 includes a computing device 402 for processing data.
- Computing device 402 may include a motherboard 404 . Coupled to or part of the motherboard 404 may be in particular a processor 406 , and a networking interface 408 coupled to a bus 410 .
- a chipset may form part or all of the bus 410 .
- the processor 406 , chipset, and/or other parts of the system 400 may include one or more devices 100 with scavenging spacers 112 .
- system 400 may include other components, including but are not limited to volatile and non-volatile memory 412 , a graphics processor (integrated with the motherboard 404 or connected to the motherboard as a separate removable component such as an AGP or PCI-E graphics processor), a digital signal processor, a crypto processor, mass storage 414 (such as hard disk, compact disk (CD), digital versatile disk (DVD) and so forth), input and/or output devices 416 , and so forth.
- volatile and non-volatile memory 412 e.g., a graphics processor (integrated with the motherboard 404 or connected to the motherboard as a separate removable component such as an AGP or PCI-E graphics processor), a digital signal processor, a crypto processor, mass storage 414 (such as hard disk, compact disk (CD), digital versatile disk (DVD) and so forth), input and/or output devices 416 , and so forth.
- graphics processor integrated with the motherboard 404 or connected to the motherboard as a separate removable component such as an AGP or PCI-E graphics processor
- system 400 may be a personal digital assistant (PDA), a mobile phone, a tablet computing device, a laptop computing device, a desktop computing device, a set-top box, an entertainment control unit, a digital camera, a digital video recorder, a CD player, a DVD player, or other digital device of the like.
- PDA personal digital assistant
- any of one or more of the components 406 , 414 , etc. in FIG. 13 may include one or more devices with the scavenging spacers 112 as described herein.
- a transistor formed with the scavenging spacers 112 may be part of the CPU 406 , motherboard 404 , graphics processor, digital signal processor, or other devices.
- terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the “top” surface of that substrate; the substrate may actually be in any orientation so that a “top” side of a substrate may be lower than the “bottom” side in a standard terrestrial frame of reference and still fall within the meaning of the term “top.”
- the term “on” as used herein does not indicate that a first layer “on” a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer.
- the embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations.
Abstract
Description
- MOS field-effect transistors with very thin silicon dioxide based gate dielectrics may experience unacceptable gate leakage currents. Forming the gate dielectric from certain high-k dielectric materials, instead of silicon dioxide, can reduce gate leakage. When conventional processes are used to form such transistors, a silicon dioxide transition layer may form between the high-k dielectric and the substrate. This transition layer may grow larger during high temperature processes when available oxygen may react with the substrate to form more silicon dioxide. The presence of a thick transition layer may unfavorably contribute to the overall electrical thickness of the gate dielectric stack.
-
FIG. 1 is a cross sectional side view that illustrates the semiconductor device of one embodiment of the present invention. -
FIG. 2 is a cross sectional side view that illustrates the electrode in more detail. -
FIG. 3 is a cross sectional side view that illustrates the thicknesses and sizes of various parts of the device ofFIG. 1 . -
FIGS. 4 through 11 are cross sectional side views that illustrate how the device ofFIG. 1 may be made in some embodiments. -
FIG. 12 is a flow chart that summarizes a method according to an embodiment of the present invention. -
FIG. 13 illustrates a system in accordance with one embodiment of the present invention. - In various embodiments, an apparatus and method relating to the formation of a device with a scavenging spacer layer are described. In the following description, various embodiments will be described. However, one skilled in the relevant art will recognize that the various embodiments may be practiced without one or more of the specific details, or with other replacement and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the invention. Nevertheless, the invention may be practiced without specific details. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
- Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention, but do not denote that they are present in every embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. Various additional layers and/or structures may be included and/or described features may be omitted in other embodiments.
- Various operations will be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the invention. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
-
FIG. 1 is a cross sectional side view that illustrates thesemiconductor device 100 of one embodiment of the present invention. Thedevice 100 may include asubstrate 102.Substrate 102 may comprise any material that may serve as a foundation upon which a semiconductor device may be built. Thesubstrate 102 may be asilicon containing substrate 102. Thesubstrate 102 may be abulk substrate 102, such as a wafer of single crystal silicon, a semiconductor-on-insulator (SOI)substrate 102, such as a layer of silicon on a layer of insulating material on another layer of silicon, or another type ofsubstrate 102. - The
device 100 may be a transistor in some embodiments. Thedevice 100 may be a planar transistor on abulk substrate 102, a planar transistor on anSOI substrate 102, a FIN-FET transistor on abulk substrate 102, a FIN-FET transistor on anSOI substrate 102, a tri-gate transistor on abulk substrate 102, a tri-gate transistor on anSOI substrate 102, or another type of transistor or another device. - In that
semiconductor device 100, a high-k gatedielectric layer 106 may be formed on thesubstrate 102. The high-k gatedielectric layer 106 may comprise, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. Although a few examples of materials that may be used to form the high-k gatedielectric layer 106 are described here, the high-k gatedielectric layer 106 may be made from other materials that serve to reduce gate leakage in other embodiments. - The high-k gate
dielectric layer 106 may have a k-value higher than about 7.5 in some embodiments. In other embodiments, the high-k gatedielectric layer 106 may have a k-value higher than about 10. In other embodiments, the high-k gatedielectric layer 106 may comprise a material such as Al2O3 with a k-value of about 12, or may comprise a material with a higher k-value than that. In other embodiments, the high-k gatedielectric layer 106 may have a k-value between about 15 and about 25, e.g. HfO2. In yet other embodiments, the high-k gatedielectric layer 106 may have a k-value even higher, such as 35, 80 or even higher. - Between the high-k gate
dielectric layer 106 and thesubstrate 102 may be atransition layer 104. Thistransition layer 104 may be athin layer 104 of oxide, such as athin layer 104 of silicon dioxide in embodiments where thesubstrate 102 comprises silicon, in some embodiments. If, during high temperature processes (such as processes performed at about 500 degrees Celsius or higher) oxygen is available to react with the substrate at the region of thetransition layer 104, it may form an unwantedthicker oxide layer 104 beneath the high-kdielectric layer 106 and reduce the performance of the transistor. - An
electrode 108 may be on the high-k gatedielectric layer 106. As seen inFIG. 2 , theelectrode 108 may include multiple layers. In the embodiment illustrated inFIG. 2 , there is awork function layer 115, acap layer 116 on thework function layer 115 and apolysilicon layer 118 on thecap layer 116. In other embodiments, theelectrode 108 may include a different number of layers, and the layers may be different. Thepolysilicon layer 118 may comprise doped polysilicon in an embodiment. Thepolysilicon layer 118 may not be apolysilicon layer 118 in some embodiments, but instead comprise other non-polysilicon materials, or it may be absent. Thecap layer 116 may comprise silicon in some embodiments, although it may comprise other materials in other embodiments. Thework function layer 115 may comprise a metalwork function layer 115. - The metal
work function layer 115 may be an n-type metal gate electrode. Materials that may be used to form n-type metal gate electrodes include: hafnium, zirconium, titanium, tantalum, aluminum, their alloys (e.g., metal carbides that include these elements, i.e., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and aluminides (e.g., an aluminide that comprises hafnium, zirconium, titanium, tantalum, or tungsten). - The metal
work function layer 115 may be a p-type metal gate electrode. Materials for forming p-type metal gate electrodes include: ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. - Rather than n- or p-type, the metal
work function layer 115 may be a mid-gap metal gate electrode. In such embodiments, thework function layer 115 may comprise stoichiometric titanium nitride, tantalum nitride, or another mid-gap material. - The
device 100 may be a transistor, such as an NMOS, PMOS, or mid-gap transistor. In some embodiments, metalwork function layers 115 forNMOS transistor devices 100 may have a workfunction that is between about 3.9 eV and about 4.2 eV. In some embodiments, metalwork function layers 115 forPMOS devices 100 may have a workfunction that is between about 4.9 eV and about 5.2 eV. In some embodiments, metal work function layers 115 for semiconductor on insulator (SOI)mid-gap transistor devices 100 may have a workfunction that is between the workfunctions of NMOS and PMOS gate electrode materials. - A metal
work function layer 115 may consist essentially of a homogeneous metal layer. Alternatively, relatively thin n-type, p-type, or mid-gap metal layers (like those listed above) may generate the lower part of the metalwork function layer 115, with the remainder of the metalwork function layer 115 comprising another metal or metals, e.g., a metal that may be easily polished like tungsten, aluminum, titanium, or titanium nitride. Such a material may make up the remainder of thegate electrode 108, or additional layers, such as thecap layer 116 andpolysilicon layer 118 illustrated inFIG. 3 may be part of thegate electrode 108 as well. Although a few examples of materials for forming a metalwork function layer 115 are identified here, such a component may be made from many other materials, as will be apparent to those skilled in the art. - Returning to
FIG. 1 , there may beinner spacers 110 on side walls of the high-k dielectric layer 106 andelectrode 108. Theinner spacers 110 may comprise a layer of material that can be formed at a temperature below about 500 degrees Celsius. In various embodiments, theinner spacers 110 may comprise silicon nitride, aluminum nitride, silicon oxide, carbon doped silicon nitride, or another material. In some embodiments, the material of theinner spacers 110 has a high etch bias relative to other materials in thedevice 100. Some embodiments may lack theinner spacers 110. - There may be
scavenger spacers 112 on side walls of the high-k dielectric layer 106 andelectrode 108. In embodiments that includeinner spacers 110, thescavenger spacers 112 may be on side walls theinner spacers 110. The scavenger spacers 112 may comprise a material that is reactive with oxygen in embodiments where thescavenger spacers 112 areoxygen scavenger spacers 112. The scavenger spacers 112 may originally comprise a layer of oxidizable material such as a group III, IV or V metal (e.g., Hf, Zr, Ti, Ta), aluminum, a nitride of a group III, IV or V metal (e.g., HfN, ZrN, TiN, TaN or Ta3N5), a nitride of a group III, IV or V metal that is deficient in nitrogen (e.g., Ti1N1-x, or Ta3N5-x), a silicon nitride deficient in nitrogen (e.g., Si3N4-x), or another material. Deficient in nitride as used herein means the material is relatively rich in the non-nitrogen element. - Oxygen present may react with the
scavenger spacers 112, which prevents the oxygen from reacting with other materials. For example, in an embodiment thescavenger spacers 112 may react with oxygen and thus reduce an oxide, such as silicon dioxide, forming from the reaction of the oxygen and thesubstrate 102. This may result in reduction in thickness of thetransition layer 104; some oxygen that would react with thesubstrate 102 to form athicker transition layer 104 may instead react with thescavenger spacers 112. In other words thescavenger spacers 112 may at least partially prevent oxidation of thesubstrate 102, which could result in the formation of undesired oxide, such as silicon oxide, beneath the high-k dielectric layer 106 andelectrode 108. Such an undesired oxide could be of a thickness enough to degrade the performance of the device if its formation is not prevented. - There may be
outer spacers 114 on side walls of the high-k dielectric layer 106 andelectrode 108. Theouter spacers 114 may be on side walls of thescavenger spacers 112.Outer spacers 114 may comprise a layer any material suitable for forming spacers, including materials that require high temperatures to form. Some embodiments may lack theouter spacers 114. -
FIG. 3 is a cross sectional side view that illustrates the thicknesses and sizes of various parts of thedevice 100 ofFIG. 1 , according to one embodiment. As shown inFIG. 3 , there may be alength 202. In an embodiment where thedevice 100 is a transistor, thelength 202 may be the length of thegate electrode 108, which is substantially the same as the length of the channel of the transistor. In an embodiment, theelectrode 108 may have alength 202 of 30-35 nm. In other embodiments, thelength 202 may be different. - The
transition layer 104 may have athickness 204. Thistransition layer 104 may be as thin as a monolayer of oxide in some embodiments at the time of formation of thescavenger spacer layer 112. In some embodiments, thethickness 204 may be as thin as about 3 angstroms or less at the time of formation of thescavenger spacer layer 112. In other embodiments, thetransition layer 104 may have more than one layer of oxide and/or may be thicker than about 3 angstroms. In an embodiment, during high-temperature processes (above about 500 degrees Celsius), thethickness 204 may grow larger, but because of the presence of the scavenging material in thescavenger spacers 112, thethickness 204 may not grow as big as it would absent the scavenging material. In an embodiment, thethickness 204 of thetransition layer 104 may remain about 3 angstroms in the completeddevice 100. In another embodiment, thetransition layer 104 may have athickness 204 between about 4 angstroms and about 8 angstroms in the completeddevice 100. Other embodiments may have atransition layer 104 with adifferent thickness 204 in the completeddevice 100. - The
inner spacer layer 110 may also have athickness 206. In an embodiment, theinner spacer layer 110, and thus theinner spacers 110, may have athickness 206 between about 10 angstroms and about 100 angstroms, although thethickness 206 may be different in other embodiments. - The scavenging
spacer layer 112 may have athickness 208. In some embodiments, thethickness 208 may be between about 30 angstroms and about 50 angstroms, although the scavengingspacer layer 112 may have adifferent thickness 208 in other embodiments. In some embodiments, thethickness 208 may be chosen based at least in part on the fabrication of thedevice 100. For example, if higher temperatures are used or there is more ambient oxygen, thethickness 208 may be greater than if lower temperatures are used, or less ambient oxygen. In embodiments where the scavengingspacers 112 comprise a metal, thethickness 208 may be chosen so that the metal is substantially entirely oxidized by the completion of fabrication of the device, to prevent source-to-drain short circuits. - The
outer spacers 114 may have athickness 210. Thisthickness 210 may be anysuitable thickness 210 to result in the sum of thethicknesses - The high-
k dielectric layer 106 may have athickness 212. Thethickness 212 may be selected to provide an acceptable level of leakage current in thedevice 100, and to provide a selected electrical thickness of the gate stack, in embodiments where thedevice 100 is a transistor. In some embodiments, the high-kgate dielectric layer 106 may be less than about 40 angstroms thick 212. The high-k dielectric layer 106 may have athickness 212 less than about 25 angstroms. In other embodiments, the high-kgate dielectric layer 106 may be between about 5 angstroms and about 20 angstroms thick 212. The high-k dielectric layer 106 may have adifferent thickness 212 in other embodiments. - The
electrode 108 and awork function layer 115 may have thicknesses (not shown). The thickness of thework function layer 115 may be chosen to provide a desired work function and threshold voltage (VTh) of the gate of thedevice 100. In an embodiment, the thickness may between about 50 angstroms and about 200 angstroms. In other embodiments, the thickness may be greater than about 75 angstroms. In yet other embodiments, the thickness may be different. - By avoiding a
thick transition layer 104 through the use of a scavengingspacer layer 112, thedevice 100 may reduce leakage current without increasing the electrical thickness of the gate stack (including thetransition layer 104 and high-k dielectric layer 106). Alternatively, the use of the scavengingspacer layer 112 may allow a stable amount of leakage current but allow faster performance of thedevice 100, compared to a device without a scavengingspacer layer 112. Other embodiments may use intermediate values, such as increasing performance somewhat and decreasing leakage current somewhat. -
FIGS. 4 through 11 are cross sectional side views that illustrate how thedevice 100 ofFIG. 1 may be made in some embodiments. -
FIG. 4 is a cross sectional side view that illustrates aSOI substrate 102 that may be used in thedevice 100. Other types ofsubstrates 102 may be used in other embodiments. TheSOI substrate 102 may include asemiconductor substrate layer 120, which may also be referred to as afirst semiconductor layer 120. Thissemiconductor substrate 120 may comprise any suitable semiconductor material or materials, including silicon. On thesemiconductor substrate 120 may be an insulatinglayer 122. The insulatinglayer 122 may comprise any suitable insulating material and may function to electrically isolate various devices formed on the substrate. In embodiments where the insulatinglayer 122 comprises an oxide, the insulating layer may also be referred to as a buried oxide layer. On the insulatinglayer 122 may be asecond semiconductor layer 124. Thesecond semiconductor layer 124 may comprise any suitable semiconductor material or materials, including silicon. -
FIG. 5 is a cross sectional side view that illustrates theSOI substrate 102 after formation of atransition layer 104, high-k dielectric layer 106, andelectrode layer 108 on thesubstrate 102, according to one embodiment of the present invention. Thetransition layer 104 may form on the surface of thesubstrate 102. As stated above, thetransition layer 104 may be between about a monolayer of a material such as silicon dioxide and about three angstroms, although in other embodiments it may be thicker. - The high-
k dielectric layer 106 may be deposited on thetransition layer 104. In one embodiment of the present invention, high-kgate dielectric layer 106 may be formed on thesubstrate 102 by an atomic layer deposition (“ALD”) process. In an ALD process, a growth cycle may be repeated until a high-kgate dielectric layer 106 of a desired thickness is created. Such a growth cycle may comprise the following sequence in an embodiment. Steam is introduced into a CVD (“chemical vapor deposition”) reactor for a selected pulse time, followed by a purging gas. A precursor (e.g., an organometallic compound, a metal chloride or other metal halide) is then pulsed into the reactor, followed by a second purge pulse. (A carrier gas that comprises nitrogen or another inert gas may be injected into the reactor at the same time.) - While operating the reactor at a selected pressure and maintaining the substrate at a selected temperature, steam, the purging gas, and the precursor are, in turn, fed at selected flow rates into the reactor. By repeating this growth cycle—steam, purging gas, precursor, and purging gas—multiple times, one may create a high-k
gate dielectric layer 106 of a desiredthickness 212 on thesubstrate 102. The pressure at which the reactor is operated, the gases' flow rates, and the temperature at which the substrate is maintained may be varied depending upon the application and the precursor that is used. The CVD reactor may be operated long enough to form the high-kgate dielectric layer 106 with the desiredthickness 212. - After forming the high-k
gate dielectric layer 106 on thesubstrate 102, the metal or otherwork function layer 115 may be formed on the high-kgate dielectric layer 106. Metalwork function layer 115 may be formed using conventional metal deposition processes, e.g. CVD or PVD processes, by using ALD, or another suitable method, and may comprise any conductive material from which metal gate electrodes may be derived. - The other layers (if any) of the
electrode 108 may then be formed on thework function layer 115 by any suitable method. For example, thecap layer 116 may comprise silicon and may be formed by sputtering silicon at a relatively low temperature below about 500 degrees Celsius. Thecap layer 116 may comprise a different material and may be formed by a different process in other embodiments. Thepolysilicon layer 118 may be deposited at a temperature of over 500 degrees Celsius. However, thecap layer 116 at this point may seal layers beneath thecap layer 116 from contact with oxygen, thus preventing or reducing growth in the thickness of thetransition layer 104 in some embodiments. -
FIG. 6 is a cross sectional side view that illustrates thedevice 100 after thetransition layer 104, high-k dielectric layer 106, andelectrode 108 have been patterned to remove them from areas on which they are not desired, according to one embodiment of the present invention. Any suitable method may be used to pattern thetransition layer 104, high-k dielectric layer 106, andelectrode 108. For example, the portions of thelayers conductive layers -
FIG. 7 is a cross sectional side view that illustrates thedevice 100 after formation of theinner spacer layer 110, according to one embodiment. Theinner spacer layer 110 may comprise silicon nitride, silicon nitride with carbon, or other materials in other embodiments. In an embodiment, theinner spacer layer 110 may be formed by chemical vapor deposition (“CVD”), plasma-enhanced chemical vapor deposition (“PECVD”), atomic layer deposition (“ALD”), or other suitable processes. Theinner spacer layer 110 may be formed at a temperature below about 500 degrees Celsius. In an embodiment, theinner spacer layer 110 may be formed at a temperature between about 300 to about 400 degrees Celsius, although other temperatures may be used in other embodiments. Theinner spacer layer 110 in some embodiments may not provide a good enough seal of the layers on which it is deposited to prevent oxygen from reaching those layers. -
FIG. 8 is a cross sectional side view that illustrates thedevice 100 after formation of thescavenger spacer layer 112, according to one embodiment. Thescavenger spacer layer 112 may comprise a layer of oxidizable material such as a group III, IV or V metal (e.g., Hf, Zr, Ti, Ta), aluminum, a nitride of a group III, IV or V metal (e.g., HfN, ZrN, TiN, TaN or Ta3N5), a nitride of a group III, IV or V metal that is deficient in nitrogen (e.g., Ti1N1-x, or Ta3N5-x), a silicon nitride deficient in nitrogen (e.g., Si3N4-x), or another material. Deficient in nitride as used herein means the material is relatively rich in the non-nitrogen element. Thescavenger spacer layer 112 may be formed at a temperature below about 500 degrees Celsius. Any suitable process, depending on the material chosen for thescavenger spacer layer 112, may be used to form thescavenger spacer layer 112. -
FIG. 9 is a cross sectional side view that illustrates thedevice 100 after formation of theouter spacer layer 114, according to one embodiment. Theouter spacer layer 114 may comprise any suitable material and may be formed by any suitable process. As thescavenger spacer layer 112 is in place, theouter spacer layer 114 may be formed at high temperature (over 500 degrees Celsius). Thescavenger spacer layer 112 material will react with oxygen to reduce or elimination growth in thethickness 204 of thetransition layer 104. - Portions of the
inner spacer layer 110,scavenger spacer layer 112, andouter spacer layer 114 may be removed to result in thedevice 100 as illustrated inFIG. 1 . Any suitable process, such as a dry etching process, may be used to remove portions of the spacer layers 110, 112, 114 and result in thespacers -
FIG. 10 is a cross sectional side view that illustratesadditional regions 130 added to thesubstrate 102 in some embodiments. Theadditional regions 130 may be omitted in some embodiments. For example, when the device is a Fin-FET transistor or tri-gate transistor, there may be only a small amount of substrate on either side of thegate stack substrate 102 by forming theadditional regions 130. In some embodiments, theadditional regions 130 may be added by epitaxy. In an embodiment, theadditional regions 130 may comprise the same material as theoriginal substrate 102. Theadditional regions 130 may be considered portions of thesubstrate 102 after formation of theadditional regions 130. As shown inFIG. 10 , theadditional regions 130 may have a height above the original substrate 102 a distance away from thespacers additional regions 130 may decrease closer to thespacers -
FIG. 11 is a cross sectional side view that illustrates the formation of source/drain implant regions 142 by implantation ofions 140. In the illustrated embodiment, theions 140 are implanted into thesubstrate 142 to form the source/drain implantedregions 142 of thesubstrate 102. During ion implantation, the scavengingspacers 112 may act to react with ambient oxygen to prevent that oxygen from reaching and reacting with thesubstrate 102 under thegate stack thicker transition layer 104. Thus, the scavengingspacers 112 may keep thetransition layer 104 thinner than it would be otherwise. Other processes may also take place, such as high-temperature post-implant annealing, during which the scavengingspacers 112 may react with oxygen and keep thetransition layer 104 thinner than it would be otherwise. Such athinner transition layer 104 may allow thedevice 100 to have faster performance than it would with athicker transition layer 104. -
FIG. 12 is aflow chart 300 that summarizes a method according to an embodiment of the present invention. A gate stack of a device, such asgate stack FIG. 1 , may be formed 302. A scavengingspacer 112 may be formed 304. This scavengingspacer 112 may be reactive with oxygen to prevent oxygen from reaching atransition layer 104 beneath thegate stack transition layer 104 beneath thegate stack spacer 112, oxygen may be mostly or entirely prevented from being transported to the under gate region during these processes. Thus, reaction of oxygen with the substrate beneath the gate and formation of athick oxide layer 104 beneath the gate may be avoided, which may prevent degradation of the performance of the device. At the end of the fabrication processes, thedevice 100 may have one or more layers of dielectric and interconnections above thespacers electrode 108. - After the
device 100 has been completely formed, the material of the scavengingspacers 112 may have reacted with oxygen. The material of the scavengingspacers 112 thus may be different than it was when the scavengingspacer layer 112 was originally formed (illustrated inFIG. 8 ). As stated above, thescavenger spacers 112 may originally comprise a layer of oxidizable material such as a group III, IV or V metal (e.g., Hf, Zr, Ti, Ta), aluminum, a nitride of a group III, IV or V metal (e.g., HfN, ZrN, TiN, TaN or Ta3N5), a nitride of a group III, IV or V metal that is deficient in nitrogen (e.g., Ti1N1-x, or Ta3N5-x), a silicon nitride deficient in nitrogen (e.g., Si3N4-x), or another material. After thedevice 100 has been completely formed, the scavengingspacers 112 may comprise one of the above-listed materials with the addition of oxygen in varying amounts. For example, the scavengingspacers 112 may comprise an oxynitride of a group III, IV or V metal. In an embodiment where the scavengingspacer 112 originally comprises HfN, it may comprise HfON after completion of thedevice 100. In an embodiment where the scavengingspacer 112 originally comprises ZrN, it may comprise ZrON after completion of thedevice 100. In an embodiment where the scavengingspacer 112 originally comprises TiN, it may comprise TiON after completion of thedevice 100. In an embodiment where the scavengingspacer 112 originally comprises TaN, it may comprise TaON after completion of thedevice 100. In an embodiment where the scavengingspacer 112 originally comprises Si3N4-x, it may comprise Si3N4-xO1.5x after completion of thedevice 100. In other examples, the scavengingspacer 112 may comprise an oxidized group III, IV, or V metal, oxidized aluminum, a silicon oxynitride, or another material. - Further, after the
device 100 has been completely formed, thetransition layer 104 may have athickness 204 of around three angstroms or less in an embodiment. In another embodiment, thetransition layer 104 may have athickness 204 of around four angstroms or less after thedevice 100 has been completely formed, although other embodiments may have athicker transition layer 104. Absent the scavengingspacers 112, the minimum size of thetransition layer 104 is significantly greater. Thetransition layer 104 would have alarger thickness 204 had oxygen been free to reach and react with thesubstrate 102, as would be the case in the absence of the scavengingspacers 112. -
FIG. 13 illustrates asystem 400 in accordance with one embodiment of the present invention. One ormore devices 100 formed with the scavengingspacers 112 as described above may be included in thesystem 400 ofFIG. 13 . As illustrated, for the embodiment,system 400 includes acomputing device 402 for processing data.Computing device 402 may include amotherboard 404. Coupled to or part of themotherboard 404 may be in particular aprocessor 406, and anetworking interface 408 coupled to abus 410. A chipset may form part or all of thebus 410. Theprocessor 406, chipset, and/or other parts of thesystem 400 may include one ormore devices 100 with scavengingspacers 112. - Depending on the applications,
system 400 may include other components, including but are not limited to volatile andnon-volatile memory 412, a graphics processor (integrated with themotherboard 404 or connected to the motherboard as a separate removable component such as an AGP or PCI-E graphics processor), a digital signal processor, a crypto processor, mass storage 414 (such as hard disk, compact disk (CD), digital versatile disk (DVD) and so forth), input and/oroutput devices 416, and so forth. - In various embodiments,
system 400 may be a personal digital assistant (PDA), a mobile phone, a tablet computing device, a laptop computing device, a desktop computing device, a set-top box, an entertainment control unit, a digital camera, a digital video recorder, a CD player, a DVD player, or other digital device of the like. - Any of one or more of the
components FIG. 13 may include one or more devices with the scavengingspacers 112 as described herein. For example, a transistor formed with the scavengingspacers 112 may be part of theCPU 406,motherboard 404, graphics processor, digital signal processor, or other devices. - The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the “top” surface of that substrate; the substrate may actually be in any orientation so that a “top” side of a substrate may be lower than the “bottom” side in a standard terrestrial frame of reference and still fall within the meaning of the term “top.” The term “on” as used herein (including in the claims) does not indicate that a first layer “on” a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
Claims (9)
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