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Patent

  1. Avancerad patentsökning
PublikationsnummerUS20070090416 A1
Typ av kungörelseAnsökan
AnsökningsnummerUS 11/238,447
Publiceringsdatum26 apr 2007
Registreringsdatum28 sep 2005
Prioritetsdatum28 sep 2005
Även publicerat somUS7902014, US8294180, US20070111419, US20110180851
Publikationsnummer11238447, 238447, US 2007/0090416 A1, US 2007/090416 A1, US 20070090416 A1, US 20070090416A1, US 2007090416 A1, US 2007090416A1, US-A1-20070090416, US-A1-2007090416, US2007/0090416A1, US2007/090416A1, US20070090416 A1, US20070090416A1, US2007090416 A1, US2007090416A1
UppfinnareBrian Doyle, Been-Yih Jin, Jack Kavalieros, Suman Datta, Justin Brask, Robert Chau
Ursprunglig innehavareDoyle Brian S, Been-Yih Jin, Kavalieros Jack T, Suman Datta, Brask Justin K, Chau Robert S
Exportera citatBiBTeX, EndNote, RefMan
Externa länkar: USPTO, Överlåtelse av äganderätt till patent som har registrerats av USPTO, Espacenet
CMOS devices with a single work function gate electrode and method of fabrication
US 20070090416 A1
Sammanfattning
Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.
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1. An device comprising:
a first transistor of a first type and a second transistor of a type complementary to said first transistor on a substrate, wherein a channel region of said first transistor has a band gap that is different than that of an adjacent semiconductor region and wherein a gate electrode of said first transistor has substantially the same work function as a gate electrode of said second transistor.
2. The device of claim 1, wherein said first type is pMOS and said complementary type is nMOS.
3. The device of claim 1, wherein said channel region of said first transistor has a band gap that is smaller than that of said adjacent semiconductor region.
4. The device of claim 1, wherein said channel region of said first transistor is comprises a silicon-germanium alloy region.
5. The device of claim 4, wherein said silicon-germanium alloy region has a thickness of about 5-300 angstroms.
6. The device of claim 1, wherein said first transistor and said second transistor have a threshold voltage magnitude less than about 0.7 V.
7. The device of claim 1, wherein said gate electrode of said first transistor and said gate electrode of said second transistor have a mid-gap work function between about 4.5 and 4.9 eV.
8. The device of claim 1, wherein said first transistor and said second transistor each further comprise a non-planar semiconductor body having a top surface and a pair of opposite sidewalls.
9. The device of claim 1, wherein said substrate is a silicon-on-insulator substrate.
10. An device, comprising:
a pMOS transistor and an nMOS transistor on a substrate, wherein said pMOS transistor and said nMOS transistor each further comprise:
a non-planar silicon body having a top surface and a pair of laterally opposite sidewalls;
a channel region, wherein said channel region of said pMOS transistor comprises a silicon-germanium cladding layer adjacent to said non-planar silicon body;
a gate insulator adjacent to said channel region, wherein said gate insulator has a dielectric constant above about 8;
a gate electrode adjacent to said gate insulator, wherein said gate electrode of said pMOS transistor and said gate electrode of said nMOS transistor have the same work function; and
a source region and a drain region on opposite sides of said gate electrode.
11. The device of claim 10, wherein said channel region of said pMOS transistor comprises an n-type channel impurity concentration between about 1e17 atoms/cmˆ3 and about 1e18 atoms/cmˆ3.
12. A method, comprising:
forming a first transistor and a second transistor on a substrate, wherein forming each of said first transistor and said second transistor further comprises:
forming a channel region, wherein said channel region of said first transistor has a band gap different than that of an adjacent semiconductor region;
forming a gate insulator adjacent to said channel region;
forming a gate electrode adjacent said gate insulator, wherein said gate electrode of said first transistor and said gate electrode of said second transistor have the same mid-gap work function; and
forming a source region and a drain region on opposite sides of said gate electrode.
13. The method of claim 12, wherein forming said channel region comprises forming a non-planar body by recessing a pair of isolation regions on said substrate.
14. The method of claim 12, wherein forming said channel region comprises forming a silicon-germanium alloy region adjacent to a silicon substrate.
15. The method of claim 12, wherein forming said gate electrode comprises configuring said gate electrode into a tri-gate structure.
16. The method of claim 12, wherein forming said gate electrode comprises blanket depositing a gate electrode material over said gate insulator of said first transistor and said second transistor, wherein said gate electrode material has a mid-gap work function; and
defining said gate electrode material into said gate electrode by a subtractive etch process.
17. A method, comprising:
forming a first transistor and a second transistor on a substrate, wherein forming each of said first transistor and said second transistor further comprises:
forming a non-planar silicon body;
forming a channel region on said non-planar silicon body, wherein said channel region of said first transistor is comprised of silicon-germanium;
forming a high-k gate insulator adjacent to said channel region;
forming a gate electrode adjacent said gate insulator, wherein said gate electrode of said first transistor and said gate electrode of said second transistor have the same mid-gap work function; and
forming a source region and a drain region on opposite sides of said gate electrode.
18. The method of claim 17, wherein said non-planar semiconductor body has a top surface and a pair of opposite sidewalls.
19. The method of claim 17, wherein said first transistor is a pMOS device and said second transistor is an nMOS device.
20. The method of claim 18, wherein forming said channel region of said first transistor comprises forming a silicon-germanium region adjacent to said top surface and adjacent to said pair of opposite sidewalls.
Beskrivning
    RELATED APPLICATIONS
  • [0001]
    This application relates to the application entitled “Method of Fabricating CMOS Devices Having a Single Work Function Gate Electrode by Band Gap Engineering and Article Made Thereby,” filed on Sep. 28, 2005.
  • BACKGROUND OF THE INVENTION
  • [0002]
    1. Field of the Invention
  • [0003]
    The present invention relates to the field of semiconductor integrated circuit manufacturing, and more particularly to CMOS (complementary metal oxide semiconductor) devices having gate electrodes with a single work function.
  • [0004]
    2. Discussion of Related Art
  • [0005]
    During the past two decades, the physical dimensions of MOSFETs have been aggressively scaled for low-power, high-performance CMOS applications. In order to continue scaling future generations of CMOS, the use of metal gate electrode technology is important. For example, further gate insulator scaling will require the use of dielectric materials with a higher dielectric constant than silicon dioxide. Devices utilizing such gate insulator materials demonstrate vastly better performance when paired with metal gate electrodes rather than traditional poly-silicon gate electrodes.
  • [0006]
    Depending on the design of the transistors used in the CMOS process, the constraints placed on the metal gate material are somewhat different. For a planar, bulk or partially depleted, single-gate transistor, short-channel effects (SCE) are typically controlled through channel dopant engineering. Requirements on the transistor threshold voltages then dictate the gate work-function values must be close to the conduction and valence bands of silicon. For such devices, a “mid-gap” work function gate electrode that is located in the middle of the p and n channel work function range is inadequate. A mid-gap gate electrode typically results in a transistor having either a threshold voltage that is too high for high-performance applications, or a compromised SCE when the effective channel doping is reduced to lower the threshold voltage. For non-planar or multi-gate transistor designs, the device geometry better controls SCE and the channel may then be more lightly doped and potentially fully depleted at zero gate bias. For such devices, the threshold voltage can be determined primarily by the gate metal work function. However, even with the multi-gate transistor's improved SCE, it is typically necessary to have a gate electrode work function about 250 mV above mid-gap for an nMOS transistor and about 250 mV below mid-gap for a pMOS transistor. Therefore, a single mid-gap gate material is also incapable of achieving low threshold voltages for both pMOS (a MOSFET with a p-channel) and nMOS (a MOSFET with an n-channel) multi-gate transistors.
  • [0007]
    For these reasons, CMOS devices generally utilize two different gate electrodes, an nMOS electrode and a pMOS electrode, having two different work function values. For the traditional polysilicon gate electrode, the work function values are typically about 4.2 and 5.2 electron volts for the nMOS and pMOS electrodes respectively, and they are generally formed by doping the polysilicon material to be either n or p type. Attempts at changing the work function of metal gate materials to achieve similar threshold voltages is difficult as the metal work function must either be varied with an alloy mixture or two different metals utilized for n and p-channel devices.
  • [0008]
    One such conventional CMOS device 100 is shown in FIG. 1, where insulating substrate 102, having a carrier 101 and an insulator 103, has a pMOS transistor region 104 and an nMOS transistor region 105. The pMOS device in region 104 is comprised of a non-planar semiconductor body 106 having a source 116 and a drain 117, a gate insulator 112 and a gate electrode 113 made of a “p-metal” (a metal having a work function appropriate for a low pMOS transistor threshold voltage). The nMOS device in region 105 is comprised of a non-planar semiconductor body 107 having a source 116 and a drain 117, a gate insulator 112 and a gate electrode 114 made of an “n-metal” (a metal having a work function appropriate for a low nMOS transistor threshold voltage). While fabricating transistors having gate electrodes made of two different materials is prohibitively expensive, simpler approaches to dual-metal gate integration like work-function engineering of molybdenum, nickel and titanium through nitrogen implantation or silicidation suffer from problems such as poor reliability and insufficient work-function shift. However, as previously described, if a single mid-gap metal is used as the gate electrode for both the pMOS and nMOS transistors, the transistors have not had the low threshold voltage required for advanced CMOS.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0009]
    FIG. 1 is an illustration of a perspective view of conventional non-planar transistors on an insulating substrate and conventional gate electrodes.
  • [0010]
    FIG. 2A is an illustration of a perspective view of non-planar transistors on an insulating substrate and gate electrodes in accordance with the present invention.
  • [0011]
    FIG. 2B is an illustration of a perspective view of non-planar transistors on a bulk substrate and gate electrodes in accordance with the present invention.
  • [0012]
    FIGS. 3A-3F are illustrations of perspective views of a method of fabricating non-planar transistors on an insulating substrate with gate electrodes in accordance with the present invention.
  • [0013]
    FIGS. 4A-4F are illustrations of perspective views of a method of fabricating non-planar transistors on a bulk substrate with gate electrodes in accordance with the present invention.
  • DETAILED DESCRIPTION OF THE PRESENT INVENTION
  • [0014]
    A novel device structure and its method of fabrication are described. In the following description, numerous specific details are set forth, such as specific materials, dimensions and processes, etc. in order to provide a thorough understanding of the present invention. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the present invention.
  • [0015]
    Embodiments of the present invention include complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage. In particular embodiments, the complementary devices utilize the same material having a single work function as the gate electrode. Engineering the band gap of the semiconductor transistor channels rather than engineering the work function of the transistor gate metal for the individual pMOS and nMOS devices avoids the manufacturing difficulties associated with depositing and interconnecting two separate gate metals in a dual-metal gate process. A single metal gate stack, used for both pMOS and nMOS transistors, simplifies fabrication while engineering the band gap of the semiconductor transistor channels enables independent tuning of the pMOS and nMOS threshold voltages. In embodiments of the present invention, the threshold voltage of a device can be targeted through the use of semiconductor materials that have an appropriate valance band (pMOS) or conduction band (nMOS) offset relative to the complementary device. Therefore, embodiments of the present invention can utilize a single mid-band gap metal for both the pMOS and nMOS transistors in a CMOS device while still achieving a low threshold voltage for both the pMOS and nMOS transistors.
  • [0016]
    An example of a CMOS device 200 with a metal gate structure and an engineered band gap in accordance with an embodiment of the present invention is illustrated in FIG. 2A. Although FIG. 2A shows a tri-gate embodiment of the present invention, it should be appreciated that additional embodiments comprising single-gate or multi-gate transistors (such as dual-gate, FinFET, omega-gate) designs are also possible. CMOS device 200 comprises a transistor of a first type on a first region 204 on a first region and a transistor of a complementary type on a second region 205 of substrate 202. Embodiments of the present CMOS invention utilize a cladding 208 as a component of the device in region 204. When the cladding 208 is formed of a semiconductor having a narrower band gap than the semiconductor body 206, the effective threshold voltage of pMOS transistor in region 204 will be reduced by an amount approximately equal to the valence band offset between the semiconductor cladding 208 and the semiconductor body 206. Similarly, any conduction band offset between the cladding material the underlying semiconductor body would likewise modify the effective threshold voltage of an nMOS transistor. In a further embodiment, a semiconductor body having a larger band gap can be used to increase either a pMOS or an nMOS transistor's threshold voltage by the respective band offset relative to the unclad substrate on which the transistors are formed in order to reduce transistor leakage or increase a transistor's breakdown voltage.
  • [0017]
    In alternate embodiments of the present invention (not shown) both the pMOS transistor and nMOS transistor comprise a semiconductor cladding material having a band offset relative to the substrate semiconductor. When the cladding material has only a valence band offset (no conduction band offset) relative to the substrate, the cladding layer on the nMOS transistor will not have any effect on the nMOS threshold voltage.
  • [0018]
    In a particular embodiment of the present invention, as shown in FIG. 2A, device 200 includes non-planar monocrystalline semiconductor bodies 206 and 207 on insulating layer 203 over carrier 201. Semiconductor bodies 206 and 207 can be formed of any well-known semiconductor material, such as silicon (Si), gallium arsenide (GaAs), indium antimonide (InSb), gallium antimonide (GaSb), gallium phosphide (GaP), or indium phosphide (InP). For embodiments where monocrystalline silicon is formed on insulator 203, the structure is commonly referred to as silicon/semiconductor-on-insulator, or SOI, substrate. In an embodiment of the present invention, the semiconductor film on insulator 203 is comprised of a monocrystalline silicon semiconductor doped with either p-type or n-type conductivity with a concentration level between 1×1016-1×1019 atoms/cm3. In another embodiment of the present invention, the semiconductor film formed on insulator 203 is comprised of a silicon semiconductor substrate having an undoped, or intrinsic epitaxial silicon region. Insulator 203 can be any dielectric material and carrier 201 can be any well-known semiconductor, insulator or metallic material.
  • [0019]
    In another embodiment of the invention, as shown in device 300 of FIG. 2B, a “bulk” substrate is used and semiconductor bodies 206 and 207 are formed on an upper region of the “bulk” semiconductor substrate. In an embodiment of the present invention, the substrate 202 is comprised of a silicon semiconductor substrate having a doped epitaxial silicon region with either p-type or n-type conductivity with a concentration level between 1×1016-1×1019 atoms/cm3. In another embodiment of the present invention, the substrate 202 is comprised of a silicon semiconductor substrate having an undoped, or intrinsic epitaxial silicon region. In bulk substrate embodiments of the present invention, isolation regions 210 are formed on the bulk, monocrystalline, semiconductor and border the semiconductor bodies 206 and 207, as shown in FIG. 2B. In some embodiments, at least a portion of the sidewalls of the bodies 206 and 207 extend above the bordering isolation regions 210. In other embodiments, such as for planar single-gate designs, the semiconductor bodies 206 and 207 have only a top surface exposed.
  • [0020]
    In embodiments shown in both FIGS. 2A and 2B, semiconductor bodies 206 and 207 have a pair of opposite sidewalls separated by a distance defining an individual semiconductor body width. Additionally, semiconductor bodies 206 and 207 have a top surface opposite a bottom surface formed over substrate 202. In embodiments with an insulating substrate, semiconductor bodies 206 and 207 are in contact with the insulating layer shown in FIG. 2A. In embodiments with a bulk substrate, semiconductor bodies 206 and 207 are in contact with the bulk semiconductor substrate and the bottom surface of the body is considered to be planar with the bottom surface of the isolation region 210 bordering the body, as shown in FIG. 2B. The distance between the top surface and the bottom surface defines an individual semiconductor body height. In an embodiment of the present invention, the individual body height is substantially equal to the individual semiconductor body width. In a particular embodiment of the present invention, the semiconductor bodies 206 and 207 have a width and height less than 30 nanometers, and more particularly, less than 20 nanometers. In another embodiment of the present invention, the individual semiconductor body height is between half the individual semiconductor body width and twice the individual semiconductor body width. In still other embodiments of the present invention, a planar or single-gate transistor design (not shown) is formed on the substrate so that a gate dielectric and a gate electrode are formed only on a top surface of the semiconductor regions.
  • [0021]
    The semiconductor cladding 208 is ideally capable of remaining single crystalline with the semiconductor body 206 to ensure sufficient carrier lifetime and mobility, as the cladding 208 comprises the channel region of pMOS transistor 204. Semiconductor cladding 208 can be formed of any well-known semiconductor material, such as silicon germanium (SiGe), indium gallium arsenide (InxGa1-xAsy), indium antimonide (InxSby), indium gallium phosphide (InxGa1-xPy), or carbon nanotubes (CNT). In certain embodiments of the present invention where the semiconductor of bodies 206 and 207 are silicon, the semiconductor material used for the cladding 208 is SiGe. In certain other embodiments, one semiconductor body is silicon and the cladding layer is an alloy of silicon and carbon (SiC). In other embodiments of the present invention having a planar or single-gate transistor design (not shown), the cladding layer is formed directly on and adjacent to a top surface of the active semiconductor region over the substrate. In certain embodiments of the present invention having a multi-gate transistor design, as shown in FIGS. 2A and 2B, the cladding region 208 surrounds the semiconductor body 206, on and adjacent to all free semiconductor surfaces. In an embodiment of the present invention the cladding region 208 has a thickness between about 5 and about 300 angstroms, and more particularly, between about 30 and about 200 angstroms.
  • [0022]
    In certain embodiments of the present invention, the cladding 208, as shown in FIGS. 2A and 2B, extends beyond the channel region and substantially covers the portions of the semiconductor body 206 that will become the source 216 and drain 217 regions of the pMOS transistor 204. In this manner it is possible to form germanicide source and drain contact region having a low conductivity and a low thermal activation temperature. In other embodiments of the present invention, the cladding 208 does not extend beyond the channel region under the gate insulator 212 and instead, the surfaces of the semiconductor body 206 are directly formed into source and drain regions.
  • [0023]
    Embodiments of the present invention include increasing the valence band energy of a pMOS transistor having a SiGe cladding region by increasing the concentration of the germanium. In this manner, it is possible to fabricate both a pMOS and nMOS multi-gate transistor having gate electrodes of the same material and threshold voltage magnitudes less than 0.7 V over a range of transistor channel doping levels. As the valence band energy increases, the threshold voltage is lowered by an amount approximately equal to the valance band voltage offset. In an embodiment of the present invention, the germanium concentration is between 5 and 50 percent, and more particularly, between 15 and 30 percent. For embodiments having about 25 percent germanium, the valence band energy is increased by about 300 mV above the valence band of silicon. Thus, a pMOS device having a SiGe channel region comprised of about 25 percent germanium will have a threshold voltage magnitude approximately 300 mV less than that of a pure silicon channel.
  • [0024]
    In embodiments of the present invention, nMOS multi-gate devices have a work function difference (the difference between the gate metal work function an the semiconductor work function or (φmetal−φsemiconductor) of about 0.4 eV while the work function difference for a pMOS multi-gate device is about 0.7 eV. In a particular embodiment of the present invention, the 0.4 eV nMOS work function difference is achieved through Fermi-level pinning a mid-gap titanium nitride metal gate material (having a work function of about 4.7 eV). In a further embodiment of the present invention, a 0.7 eV pMOS work function difference is achieved with a band-engineered SiGe channel region comprised of about 25 percent germanium. The 25 percent germanium-cladding region increases the semiconductor valance band energy and, in effect, shifts the work function difference of the mid-gap titanium nitride metal gate material by about 300 mV, from the pinned Fermi-level of 0.4 eV to the desired 0.7 eV.
  • [0025]
    Embodiments of the present invention include adjusting the germanium concentration of a pMOS SiGe cladding region to adjust the threshold voltage, enabling multiple threshold voltages on the same chip, which is a different challenge from setting a single threshold voltage to match an nMOS device. For ULSI systems, it is typically necessary to provide a menu of devices with different threshold voltages to allow for the optimization of performance and power consumption. The ability to tune the threshold voltage by about 150 mV is often required. For devices with geometries in the sub-50-nm gate-length regime, it is very difficult to achieve such a range by merely doping the transistor channel. Disadvantageous channel doping can by avoided by embodiments of the present invention where a first pMOS device has a cladding layer comprised of a first germanium concentration targeting a first threshold voltage while a second pMOS device has a cladding layer comprised of a second germanium concentration targeting a second threshold voltage.
  • [0026]
    In the embodiments depicted in FIGS. 2A and 2B, CMOS devices 200 and 300, respectively, have a gate insulator layer 212. In the depicted embodiments, gate insulator 212 surrounds the cladding 208 of pMOS device 204 and the semiconductor body 207 of the nMOS device. In such tri-gate embodiments, gate dielectric layer 212 is formed on the sidewalls as well as on the top surfaces of the cladding 208 and semiconductor body 207, as shown in FIGS. 2A and 2B. In other embodiments, such as in FinFET or dual-gate designs, gate dielectric layer 212 is only formed on the sidewalls of the cladding 208 and sidewalls of semiconductor body 207. Gate insulator 212 can be of any commonly known dielectric material compatible with the cladding 208, semiconductor body 207 and the gate electrode 213. In an embodiment of the present invention, the gate dielectric layer is a silicon dioxide (SiO2), silicon oxynitride (SiOxNy) or a silicon nitride (Si3N4) dielectric layer. In one particular embodiment of the present invention, the gate dielectric layer 212 is a silicon oxynitride film formed to a thickness of between 5-20 Å. In another embodiment of the present invention, gate dielectric layer 212 is a high K gate dielectric layer, such as a metal oxide dielectric, such as to tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, or aluminum oxide. Gate dielectric layer 212 can be other types of high K dielectric, such as lead zirconium titanate (PZT).
  • [0027]
    CMOS device embodiments 200 and 300 have a gate electrode 213, as shown in FIGS. 2A and 2B, respectively. In certain embodiments, gate electrode 213 is formed on and adjacent to gate dielectric layer 212, adjacent to gate insulator 212 formed on and adjacent to sidewalls of each of the semiconductor bodies 206 and 207. Gate electrode 213 has a pair of laterally opposite sidewalls separated by a distance, defining the gate length (Lg) of pMOS transistor in region 204 and nMOS transistor in region 205. In certain embodiments of the present invention, where the transistors in regions 204 and 205 are planar or single-gate devices (not shown), the gate electrode is merely on and adjacent to a top surface of the gate insulator over the semiconductor substrate. In the embodiments of the present invention, as shown in FIGS. 2A and 2B, the same material is used to form the gate electrode 213 for pMOS device in region 204 and nMOS device in region 205. In this manner, CMOS device fabrication can be greatly simplified because there is no need for the pMOS device to have a gate metal with a different work function than that of the nMOS device. In further embodiments of the present invention, the same gate electrode structure physically connects a pMOS device 204 to an nMOS device 205. Gate electrode 213 of FIGS. 2A and 2B can be formed of any suitable gate electrode material having the appropriate work function. In an embodiment of the present invention, the gate electrode is a metal gate electrode, such as tungsten, tantalum nitride, titanium nitride or titanium silicide, nickel silicide, or cobalt silicide. In an embodiment of the present invention, the gate electrode 213 of both the pMOS device and then nMOS device is formed from a material having a mid-gap work function between 4.5 and 4.9 eV. In a specific embodiment of the present invention, gate electrode 213 comprises titanium nitride having a work function equal to about 4.7 eV. It should also be appreciated that the gate electrode 213 need not necessarily be a single material, but rather can also be a composite stack of thin films such as a metal/polycrystalline silicon electrode.
  • [0028]
    As shown in FIGS. 2A and 2B, a pair of source 216 drain 217 regions are formed in body 206 and 207 on opposite sides of gate electrode 213. The source region 216 and the drain region 217 are formed of the same conductivity type such as n-type or p-type conductivity, depending on if the transistor is an nMOS device or a pMOS device. In an embodiment of the present invention, source region 216 and drain region 217 have a doping concentration of 1×1019-1'31021 atoms/cm3. Source region 216 and drain region 217 can be formed of uniform concentration or can include subregions of different concentrations or doping profiles such as tip regions (e.g., source/drain extensions).
  • [0029]
    As shown in FIGS. 2A and 2B, the portion of semiconductor cladding 208 and semiconductor body 207 located between source regions 216 and drain regions 217 define the channel region of the pMOS device in region 204 and nMOS device in 205. In certain embodiments of the present invention, the channel region of the cladding 208 on the pMOS device in region 204 is undoped SiGe. In other embodiments the channel region of the cladding 208 is doped SiGe. In an embodiment of the present invention, the channel region of semiconductor body 207 is intrinsic or undoped monocrystalline silicon. In an embodiment of the present invention, channel region of semiconductor body 207 is doped monocrystalline silicon. When the channel region is doped, it is typically doped to the opposite conductivity type of the source region 216 and the drain region 217. For example, the nMOS device in region 205 has source and drain regions which are n-type conductivity while the channel region is doped to p-type conductivity. When channel region is doped, it can be doped to a conductivity level of between 1×1016 to 1×1019 atoms/cm3. In certain multi-gate transistor embodiments of the present invention, the pMOS channel regions have an impurity concentration of 1017 to 10 e18 atoms/cm3.
  • [0030]
    A method of fabricating a CMOS device on an insulating substrate in accordance with an embodiment of the present invention as shown in FIG. 2A is illustrated in FIGS. 3A-3F. Insulating substrate can be formed in any commonly known fashion. In an embodiment of the present invention, shown in FIG. 3A, the insulating substrate includes a lower monocrystalline silicon carrier 201 formed on an insulating layer 203, such as a silicon dioxide film or silicon nitride film. Insulating layer 203 isolates semiconductor film 315 from carrier 201, and in an embodiment is formed to a thickness between 200-2000 Å. Insulating layer 203 is sometimes referred to as a “buried oxide” layer and the substrate comprised of 201, 203 and 315 is referred to as a silicon or semiconductor on insulating (SOI) substrate.
  • [0031]
    Although the semiconductor film 315 is ideally a silicon film, in other embodiments it can be other types of semiconductor films, such as germanium (Ge), a silicon germanium alloy (SiGe), gallium arsenide (GaAs), InSb, GaP, GaSb, or InP. In an embodiment of the present invention, semiconductor film 315 is an intrinsic (i.e., undoped) silicon film. In other embodiments, semiconductor film 315 is doped to p-type or n-type conductivity with a concentration level between 1×1016-1×1019 atoms/cm3. Semiconductor film 315 can be in-situ doped (i.e., doped while it is deposited) or doped after it is formed on substrate 202 by for example ion-implantation. Doping after formation enables complementary devices 204 and 205 to be fabricated easily on the same substrate. The doping level of the semiconductor substrate film 315 at this point can determine the doping level of the channel region of the device.
  • [0032]
    In certain embodiments of the present invention, semiconductor substrate film 315 is formed to a thickness approximately equal to the height desired for the subsequently formed semiconductor body or bodies of the fabricated transistor. In an embodiment of the present invention, semiconductor substrate film 315 has a thickness or height of less than 30 nanometers and ideally less than 20 nanometers. In certain embodiments of the present invention, semiconductor substrate region 315 is formed to a thickness enabling the fabricated transistor to be operated in a fully depleted manner for its designed gate length (Lg).
  • [0033]
    Semiconductor substrate region 315 can be formed on insulator 203 in any well-known method. In one method of forming a silicon-on-insulator substrate, known as the separation by implantation of oxygen (SIMOX) technique. Another technique currently used to form SOI substrates is an epitaxial silicon film transfer technique generally referred to as bonded SOI.
  • [0034]
    A masking layer 310 is used to define the active regions of the devices in regions 204 and 205. The masking layer can be any well-known material suitable for defining the semiconductor film 315. In an embodiment of the present invention, masking layer 310 is a lithographically defined photo resist. In another embodiment, 310 is formed of a dielectric material that has been lithographically defined and then etched. In a certain embodiment, masking layer can be a composite stack of materials, such as an oxide/nitride stack. As shown in FIG. 3B, once masking layer 310 has been defined, semiconductor 315 is then defined by commonly any known etching technique to form semiconductor bodies 206 and 207. In certain embodiments of the present invention anisotropic plasma etch, or RIE, is used to define semiconductor bodies 206 and 207. For planar, or single-gate embodiments, non-planar bodies 206 and 207 are not formed, rather the planar device is merely formed on the film 315 and mask 310 is used to define isolation regions. In an embodiment of the present invention, as shown in FIG. 3C, masking layer 310 is removed from the semiconductor bodies 206 and 207 using commonly known techniques that depend on the material selected for masking layer 310. In other embodiments, such as for particular dual-gate or FinFET designs, masking layer 310 is not removed.
  • [0035]
    If desired, a masking can be formed over any regions of the substrate where there is to be no semiconductor cladding layer. As shown, in FIG. 3D, mask layer 320 is formed over the nMOS device region 205. Mask layer 320 can be of any commonly known material capable of surviving the subsequent process of forming the semiconductor cladding layer. In an embodiment of the present invention, mask layer 320 is a dielectric material capable of serving as a good diffusion barrier, such as silicon nitride. Hard mask 320 ideally has good conformality so that semiconductor body 207 is completely encapsulated by the protective mask 20. Commonly known techniques, such as CVD, LPCVD, or PECVD may be used to deposit the mask material. Mask 320 is then selectively defined by commonly known lithographic and etch techniques, so that the mask 320 is substantially removed from the pMOS region leaving no spacer material or stringers along the semiconductor body 206. In certain embodiments of the present invention, when the semiconductor cladding layer is to be formed on all transistors, no mask layer 320 is formed.
  • [0036]
    In certain embodiments, semiconductor cladding layer 208 is selectively formed on the semiconductor body 206 of the pMOS device 204, as shown in FIG. 3E. Any commonly known epitaxial processes suitable for the particular semiconductor materials can be used to form the semiconductor cladding layer on the semiconductor body 206. In a particular embodiment, an LPCVD process using germane and a silane as precursors forms a SiGe cladding on a silicon semiconductor body. In still another embodiment, a silicon cladding layer is formed on a SiGe body to form an nMOS device. The cladding layer can be grown to have a particular composition determined by the amount of band offset desired. In a particular embodiment of the present invention a silicon germanium cladding layer having about 25 percent to about 30 percent germanium is formed. In other embodiments, the germanium concentration is about 50 percent. Ideally, the formation process is capable of producing a single crystalline cladding 208 from the semiconductor body 206 seed layer. In an embodiment of the present invention the cladding layer is epitaxially grown on both the top surface and the sidewalls of the semiconductor body 206. In another embodiment where the top surface of semiconductor body 206 is protected by a dielectric, the cladding layer is only grown on and adjacent to the sidewalls. In still other embodiments, when the transistor is a planar design, the cladding layer is grown only on the top surface. The semiconductor cladding layer is grown to the desired thickness, some embodiments including in-situ impurity doping. In certain embodiments where the semiconductor cladding 208 is not lattice matched to the semiconductor body 206, the maximum cladding thickness is the critical thickness. In an embodiment of the present invention, a SiGe cladding is grown to a thickness of 5-300 Å. Once the cladding 208 is formed, the mask layer 320 protecting the nMOS region 205 is removed by commonly known techniques, as shown in FIG. 3E. In certain embodiments of the present invention, various regions over the substrate are selectively and iteratively masked and different pMOS devices clad with semiconductor layers having different band offsets thereby providing pMOS devices with various voltage threshold characteristics. In still other embodiments of the present invention, semiconductor cladding 208 is formed on both the pMOS device 204 and the nMOS device 205.
  • [0037]
    A gate dielectric layer 212, as shown in FIG. 3F, is formed on each of the cladding 208 and semiconductor body 207 in a manner dependent on the type of device (single-gate, dual-gate, tri-gate, etc.). In an embodiment of the present invention, a gate dielectric layer 212 is formed on the top surface of each of the semiconductor bodies 206 and 207, as well as on the laterally opposite sidewalls of each of the semiconductor bodies. In certain embodiments, such as dual-gate embodiments, the gate dielectric is not formed on the top surface of the cladding 208 or semiconductor body 207. The gate dielectric can be a deposited dielectric or a grown dielectric. In an embodiment of the present invention, the gate dielectric layer 212 is a silicon dioxide dielectric film grown with a dry/wet oxidation process. In an embodiment of the present invention, the gate dielectric film 212 is a deposited high dielectric constant (high-K) metal oxide dielectric, such as tantalum pentaoxide, titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, or another high-K dielectric, such as barium strontium titanate (BST). A high-K film can be formed by well-known techniques, such as chemical vapor deposition (CVD) and atomic layer deposition (ALD).
  • [0038]
    As shown in FIG. 3F, a gate electrode 213 is formed on both the pMOS and nMOS devices. In certain embodiments, the same gate electrode material is used for both the pMOS device in region 204 and nMOS device in region 205, but it is not necessarily so as other advantages of the present invention have been described. In an embodiment of the present invention, the gate electrode 213 is formed on the gate dielectric layer 212 formed on and adjacent to the top surface of each of the cladding 208 or semiconductor body 207 and is formed on and adjacent to the gate dielectric 212 formed on and adjacent to the sidewalls of each of the cladding 208 or semiconductor body 207. The gate electrode can be formed to a thickness between 200-3000 Å. In an embodiment, the gate electrode has a thickness of at least three times the height of the semiconductor bodies 206 and 207. In an embodiment of the present invention, the gate electrode is a mid-gap metal gate electrode such as, tungsten, tantalum nitride, titanium nitride or titanium silicide, nickel silicide, or cobalt silicide. In an embodiment of the present invention gate electrode 213 is simultaneously formed for both the pMOS device in region 204 and nMOS device in region 205 by well-known techniques, such as blanket depositing a gate electrode material over the substrate of and then patterning the gate electrode material for both the pMOS and nMOS devices through photolithography and etch. In other embodiments of the present invention, “replacement gate” methods are used to form both the pMOS and nMOS gate electrodes 213, concurrently or otherwise.
  • [0039]
    Source regions 216 and drain regions 217 for the transistor are formed in semiconductor bodies 206 and 207 on opposite sides of gate electrode 213, as shown in FIG. 3F. In an embodiment of the present invention, the source and drain regions include tip or source/drain extension regions. For a pMOS transistor, the semiconductor fin or body 206 is doped to p-type conductivity and to a concentration between 1×1019-1×1021 atoms/cm3. For an nMOS transistor, the semiconductor fin or body 207 is doped with n-type conductivity ions to a concentration between 1×1019-1×1021 atoms/cm3. At this point the CMOS device of the present invention is substantially complete and only device interconnection remains.
  • [0040]
    A method of fabricating a CMOS device on a bulk substrate in accordance with an embodiment of the present invention as shown in FIG. 2B is illustrated in FIGS. 4A-4F. In certain embodiments of the present invention, the substrate 202 of FIG. 4A can be a “bulk” semiconductor substrate, such as a silicon monocrystalline substrate or gallium arsenide substrate. The method of fabrication on a bulk substrate in accordance with an embodiment of the present invention is similar to the method of fabrication previously described for an SOI structure in reference to FIG. 3A-3F. In certain embodiments of the present invention, the substrate 202 is a silicon semiconductor substrate, upon which there is a doped epitaxial region with either p-type or n-type conductivity with an impurity concentration level between 1×1016-1×1019 atoms/cm3. In another embodiment of the present invention the substrate 202 is a silicon semiconductor substrate upon which there is an undoped, or intrinsic epitaxial silicon region.
  • [0041]
    In embodiments of the present invention, well regions of semiconductor substrate 202 are doped to p-type or n-type conductivity with a concentration level between about 1×1016-1×1019 atoms/cm3. Semiconductor substrate 202 can be doped by, for example, ion-implantation enabling both pMOS and nMOS well regions to be fabricated easily on the same substrate. The doping level of the semiconductor substrate 202 at this point can determine the doping level of the channel region of the device.
  • [0042]
    As shown in FIG. 4A, a masking layer 410, like masking layer 310 in FIG. 3A, is used to define the active regions of the pMOS device 204 and the nMOS device 205 on the bulk semiconductor substrate. The method of forming masking layer 410 can be essentially the same as those described for masking layer 310 of FIG. 3A.
  • [0043]
    As shown in FIG. 4B, the bulk semiconductor is etched using commonly known methods, very similar to those previously described for layer 315 of to SOI substrate shown FIG. 3B, to form recesses or trenches 420 on the substrate in alignment with the outside edges of masking portion 410. The trenches 420 are etched to a depth sufficient to isolate adjacent transistor from one another. As shown in FIG. 4C, the trenches 420 are filled with a dielectric to form shallow trench isolation (STI) regions 210 on substrate 202. In an embodiment of the present invention, a liner of oxide or nitride on the bottom and sidewalls of the trenches 420 is formed by commonly known methods. Next, the trenches 420 are filled by blanket depositing an oxide over the liner by, for example, a high-density plasma (HDP) chemical vapor deposition process. The deposition process will also form dielectric on the top surfaces of the mask portions 410. The fill dielectric layer can then be removed from the top of mask portions 410 by chemical, mechanical, or electrochemical, polishing techniques. The polishing is continued until the mask portions 410 are revealed, forming STI regions 210. In an embodiment of the present invention, as shown in FIG. 4C, the mask portions 410 are selectively removed at this time. In other embodiments, the mask portions 410 are retained through subsequent processes.
  • [0044]
    In certain embodiments, as shown in FIG. 4D, the STI regions 210 are etched back or recessed to form the sidewalls of the semiconductor bodies 206 and 207. STI regions 210 are etched back with an etchant, which does not significantly etch the semiconductor bodies 206 and 207. In embodiments where semiconductor bodies are silicon, isolation regions 210 can be recessed with an etchant comprising a fluorine ion, such as HF. In other embodiments, STI regions 210 are recessed using a commonly known anisotropic etch followed by an isotropic etch to completely remove the STI dielectric from the sidewalls of the semiconductor bodies 206 and 207. STI regions 210 are recessed by an amount dependent on the desired channel width of the transistors formed in regions 204 205. In an embodiment of the present invention STI regions 210 are recessed by approximately the same amount as the smaller, or width, dimension of the top surface of the semiconductor bodies 206 and 207. In other embodiments the STI regions 210 are recessed by a significantly larger amount than the width dimension of the top surface of the semiconductor bodies 206 and 207. In still other embodiments, the STI regions 210 are not recessed so that planar, or single-gate, devices can be formed.
  • [0045]
    In certain embodiments, once the non-planar semiconductor bodies 206 and 207 are formed on the bulk substrate, the remaining fabrication operations are analogous to those previously described for the embodiments describing a non-planar transistors on an SOI substrate. FIG. 4E depicts the selective formation of the semiconductor cladding 208 on the semiconductor body 206 using the various techniques described previously in the context of FIGS. 3D and 3E for the SOI embodiments of the present invention. As described for the SOI embodiments, semiconductor cladding 208 may also be formed on semiconductor body 207, if desired. As shown in FIG. 4F, a gate insulator 212, gate electrode 213, source regions 216, and drain regions 217 are formed on both the device in region 204 and complementary device in region 205 following embodiments analogous to those previously described in the context of an SOI substrate. At this point the transistors of the present invention formed on a bulk substrate is substantially complete and only device interconnection remains.
  • [0046]
    Although the invention has been described in language specific to structural features and/or methodological acts, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as particularly graceful implementations of the claimed invention.
Citat från patent
citerade patent Registreringsdatum Publiceringsdatum Sökande Titel
US4906589 *6 feb 19896 mar 1990Industrial Technology Research InstituteInverse-T LDDFET with self-aligned silicide
US5124777 *3 jan 199123 jun 1992Samsung Electronics Co., Ltd.Dielectric medium for capacitor of semiconductor device
US5338959 *30 mar 199316 aug 1994Samsung Electronics Co., Ltd.Thin film transistor with three dimensional multichannel structure
US5346839 *8 jan 199313 sep 1994Texas Instruments IncorporatedSidewall doping technique for SOI transistors
US5466621 *25 okt 199314 nov 1995Hitachi, Ltd.Method of manufacturing a semiconductor device having silicon islands
US5479033 *27 maj 199426 dec 1995Sandia CorporationComplementary junction heterostructure field-effect transistor
US5545586 *13 maj 199413 aug 1996Nec CorporationMethod of making a transistor having easily controllable impurity profile
US5563077 *20 jun 19958 okt 1996Hyundai Electronics Industries Co., Ltd.Method of fabricating a thin film transistor having vertical channel
US5578513 *20 apr 199526 nov 1996Mitsubishi Denki Kabushiki KaishaMethod of making a semiconductor device having a gate all around type of thin film transistor
US5652454 *3 jul 199629 jul 1997Iwamatsu; ToshiakiSemiconductor device on an SOI substrate
US5658806 *26 okt 199519 aug 1997National Science CouncilMethod for fabricating thin-film transistor with bottom-gate or dual-gate configuration
US5701016 *24 nov 199523 dec 1997Kabushiki Kaisha ToshibaSemiconductor device and method for its manufacture
US5716879 *13 jan 199710 feb 1998Goldstar Electron Company, Ltd.Method of making a thin film transistor
US5827769 *20 nov 199627 okt 1998Intel CorporationMethod for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode
US5888309 *29 dec 199730 mar 1999Taiwan Semiconductor Manufacturing Company, Ltd.Lateral etch inhibited multiple for forming a via through a microelectronics layer susceptible to etching within a fluorine containing plasma followed by an oxygen containing plasma
US5905285 *26 feb 199818 maj 1999Advanced Micro Devices, Inc.Ultra short trench transistors and process for making same
US6031249 *8 jul 199729 feb 2000Semiconductor Energy Laboratory Co., Ltd.CMOS semiconductor device having boron doped channel
US6163053 *5 nov 199719 dec 2000Ricoh Company, Ltd.Semiconductor device having opposite-polarity region under channel
US6252284 *9 dec 199926 jun 2001International Business Machines CorporationPlanarized silicon fin device
US6310367 *22 feb 200030 okt 2001Kabushiki Kaisha ToshibaMOS transistor having a tensile-strained SI layer and a compressive-strained SI-GE layer
US6376317 *28 jun 200023 apr 2002Micron Technology, Inc.Methods for dual-gated transistors
US6396108 *13 nov 200028 maj 2002Advanced Micro Devices, Inc.Self-aligned double gate silicon-on-insulator (SOI) device
US6399970 *16 sep 19974 jun 2002Matsushita Electric Industrial Co., Ltd.FET having a Si/SiGeC heterojunction channel
US6403434 *9 feb 200111 jun 2002Advanced Micro Devices, Inc.Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric
US6407442 *26 okt 199518 jun 2002Canon Kabushiki KaishaSemiconductor device, and operating device, signal converter, and signal processing system using the same semiconductor device
US6413802 *23 okt 20002 jul 2002The Regents Of The University Of CaliforniaFinfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6413877 *22 dec 20002 jul 2002Lam Research CorporationMethod of preventing damage to organo-silicate-glass materials during resist stripping
US6458662 *4 apr 20011 okt 2002Advanced Micro Devices, Inc.Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed
US6475869 *26 feb 20015 nov 2002Advanced Micro Devices, Inc.Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
US6475890 *12 feb 20015 nov 2002Advanced Micro Devices, Inc.Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
US6483156 *16 mar 200019 nov 2002International Business Machines CorporationDouble planar gated SOI MOSFET structure
US6525403 *24 sep 200125 feb 2003Kabushiki Kaisha ToshibaSemiconductor device having MIS field effect transistors or three-dimensional structure
US6562665 *16 okt 200013 maj 2003Advanced Micro Devices, Inc.Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
US6611029 *8 nov 200226 aug 2003Advanced Micro Devices, Inc.Double gate semiconductor device having separate gates
US6635909 *19 mar 200221 okt 2003International Business Machines CorporationStrained fin FETs structure and method
US6645797 *6 dec 200211 nov 2003Advanced Micro Devices, Inc.Method for forming fins in a FinFET device using sacrificial carbon layer
US6680240 *25 jun 200220 jan 2004Advanced Micro Devices, Inc.Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
US6706571 *22 okt 200216 mar 2004Advanced Micro Devices, Inc.Method for forming multiple structures in a semiconductor device
US6709982 *26 nov 200223 mar 2004Advanced Micro Devices, Inc.Double spacer FinFET formation
US6713396 *29 apr 200230 mar 2004Hewlett-Packard Development Company, L.P.Method of fabricating high density sub-lithographic features on a substrate
US6716684 *13 nov 20006 apr 2004Advanced Micro Devices, Inc.Method of making a self-aligned triple gate silicon-on-insulator device
US6716690 *12 mar 20036 apr 2004Advanced Micro Devices, Inc.Uniformly doped source/drain junction in a double-gate MOSFET
US6730964 *1 okt 20024 maj 2004Hitachi, Ltd.Semiconductor device and method of producing the same
US6756657 *28 jan 199929 jun 2004Semiconductor Energy Laboratory Co., Ltd.Method of preparing a semiconductor having controlled crystal orientation
US6764884 *3 apr 200320 jul 2004Advanced Micro Devices, Inc.Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
US6790733 *28 mar 200314 sep 2004International Business Machines CorporationPreserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer
US6794313 *20 sep 200221 sep 2004Taiwan Semiconductor Manufacturing Company, Ltd.Oxidation process to improve polysilicon sidewall roughness
US6835618 *5 aug 200328 dec 2004Advanced Micro Devices, Inc.Epitaxially grown fin for FinFET
US6858478 *14 feb 200322 feb 2005Intel CorporationTri-gate devices and methods of fabrication
US6884154 *21 feb 200126 apr 2005Shin-Etsu Handotai Co., Ltd.Method for apparatus for polishing outer peripheral chamfered part of wafer
US6921982 *21 jul 200326 jul 2005International Business Machines CorporationFET channel having a strained lattice structure along multiple surfaces
US20020011612 *30 jul 200131 jan 2002Kabushiki Kaisha ToshibaSemiconductor device and method for manufacturing the same
US20020036290 *24 sep 200128 mar 2002Kabushiki Kaisha ToshibaSemiconductor device having MIS field effect transistors or three-dimensional structure
US20020081794 *26 dec 200127 jun 2002Nec CorporationEnhanced deposition control in fabricating devices in a semiconductor wafer
US20020096724 *2 mar 200025 jul 2002Chunlin LiangComplementary metal gate electrode technology
US20020160553 *14 feb 200231 okt 2002Hideo YamanakaMethod and apparatus for forming a thin semiconductor film, method and apparatus for producing a semiconductor device, and electro-opitcal apparatus
US20020166838 *6 jul 200114 nov 2002Institute Of MicroelectronicsSloped trench etching process
US20020167007 *7 mar 200214 nov 2002Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method of fabricating the same
US20030057486 *27 sep 200127 mar 2003International Business Machines CorporationFin field effect transistor with self-aligned gate
US20030085194 *7 nov 20018 maj 2003Hopkins Dean A.Method for fabricating close spaced mirror arrays
US20030098488 *27 nov 200129 maj 2003O'keeffe JamesBand-structure modulation of nano-structures in an electric field
US20030102497 *4 dec 20015 jun 2003International Business Machines CorporationMultiple-plane finFET CMOS
US20030111686 *13 dec 200119 jun 2003Nowak Edward J.Method for forming asymmetric dual gate transistor
US20030122186 *23 dec 20023 jul 2003Nat'l. Inst. Of Advanced Indust'l Sci. And Tech.Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
US20030143791 *12 nov 200231 jul 2003Samsung Electronics Co., Ltd.Methods for fabricating MOS transistors with notched gate electrodes
US20030151077 *13 feb 200214 aug 2003Leo MathewMethod of forming a vertical double gate semiconductor device and structure thereof
US20030201458 *16 maj 200330 okt 2003Clark William F.Strained fin fets structure and method
US20030227036 *21 feb 200311 dec 2003Naoharu SugiyamaSemiconductor device
US20040031979 *6 jun 200319 feb 2004Amberwave Systems CorporationStrained-semiconductor-on-insulator device structures
US20040036118 *26 aug 200226 feb 2004International Business Machines CorporationConcurrent Fin-FET and thick-body device fabrication
US20040036127 *14 feb 200326 feb 2004Chau Robert S.Tri-gate devices and methods of fabrication
US20040075149 *23 jul 200322 apr 2004Amberwave Systems CorporationCMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US20040092062 *8 nov 200213 maj 2004Ahmed Shibly S.Planarizing gate material to improve gate critical dimension in semiconductor devices
US20040092067 *30 jun 200313 maj 2004International Business Machines CorporationDamascene double-gate MOSFET with vertical channel regions
US20040094807 *7 nov 200320 maj 2004Chau Robert S.Tri-gate devices and methods of fabrication
US20040110097 *25 nov 200310 jun 2004Ahmed Shibly S.Double gate semiconductor device having a metal gate
US20040119100 *19 dec 200224 jun 2004International Business Machines CorporationDense dual-plane devices
US20040126975 *24 jun 20031 jul 2004Ahmed Shibly S.Double gate semiconductor device having separate gates
US20040166642 *20 feb 200326 aug 2004Hao-Yu ChenSemiconductor nano-rod devices
US20040180491 *11 mar 200416 sep 2004Nobutoshi AraiMemory function body, particle forming method therefor and, memory device, semiconductor device, and electronic equipment having the memory function body
US20040191980 *27 mar 200330 sep 2004Rafael RiosMulti-corner FET for better immunity from short channel effects
US20040195624 *24 feb 20047 okt 2004National Taiwan UniversityStrained silicon fin field effect transistor
US20040198003 *26 mar 20037 okt 2004Taiwan Semiconductor Manufacturing Co., Ltd.Multiple-gate transistors with improved gate control
US20040219780 *29 apr 20044 nov 2004Elpida Memory, IncManufacturing method of semiconductor device
US20040227187 *13 feb 200418 nov 2004Zhiyuan ChengIntegrated semiconductor device and method to make same
US20040238887 *25 jun 20022 dec 2004Fumiyuki NiheyField-effect transistor constituting channel by carbon nano tubes
US20040256647 *23 jun 200323 dec 2004Sharp Laboratories Of America Inc.Strained silicon finFET device
US20040262683 *27 jun 200330 dec 2004Bohr Mark T.PMOS transistor strain optimization with raised junction regions
US20040262699 *30 jun 200330 dec 2004Rafael RiosN-gate transistor
US20050035415 *24 sep 200317 feb 2005Yee-Chia YeoMultiple-gate transistors formed on bulk substrates
US20050118790 *1 dec 20032 jun 2005Taiwan Semiconductor Manufacturing Company, Ltd.Method for dicing semiconductor wafers
US20050127362 *10 dec 200316 jun 2005Ying ZhangSectional field effect devices and method of fabrication
US20050145941 *7 jan 20047 jul 2005International Business Machines CorporationHigh performance strained silicon FinFETs device and method for forming same
US20050224797 *1 apr 200413 okt 2005Taiwan Semiconductor Manufacturing Company, Ltd.CMOS fabricated on different crystallographic orientation substrates
US20050224800 *31 mar 200413 okt 2005Nick LindertBulk non-planar transistor having strained enhanced mobility and methods of fabrication
US20060172480 *3 feb 20053 aug 2006Taiwan Semiconductor Manufacturing Company, Ltd.Single metal gate CMOS device design
US20070001219 *30 jun 20054 jan 2007Marko RadosavljevicBlock contact architectures for nanoscale channel transistors
Hänvisningar finns i följande patent
citeras i Registreringsdatum Publiceringsdatum Sökande Titel
US77283923 jan 20081 jun 2010International Business Machines CorporationSRAM device structure including same band gap transistors having gate stacks with high-K dielectrics and same work function
US794346020 apr 200917 maj 2011International Business Machines CorporationHigh-K metal gate CMOS
US798928018 dec 20082 aug 2011Intel CorporationDielectric interface for group III-V semiconductor device
US81436462 aug 200627 mar 2012Intel CorporationStacking fault and twin blocking barrier for integrating III-V on Si
US818355615 dec 200522 maj 2012Intel CorporationExtreme high mobility CMOS logic
US8203148 *30 jun 201119 jun 2012Monolithic 3D Inc.Semiconductor device and structure
US823722827 sep 20117 aug 2012Monolithic 3D Inc.System comprising a semiconductor device and structure
US827361014 okt 201125 sep 2012Monolithic 3D Inc.Method of constructing a semiconductor device and structure
US829415928 mar 201123 okt 2012Monolithic 3D Inc.Method for fabrication of a semiconductor device and structure
US82941801 mar 201123 okt 2012Intel CorporationCMOS devices with a single work function gate electrode and method of fabrication
US836248228 jan 201129 jan 2013Monolithic 3D Inc.Semiconductor device and structure
US836256623 jun 200829 jan 2013Intel CorporationStress in trigate devices using complimentary gate fill materials
US836280013 okt 201029 jan 2013Monolithic 3D Inc.3D semiconductor device including field repairable logics
US837323013 okt 201012 feb 2013Monolithic 3D Inc.Method for fabrication of a semiconductor device and structure
US83734397 nov 201012 feb 2013Monolithic 3D Inc.3D semiconductor device
US837849416 jun 201119 feb 2013Monolithic 3D Inc.Method for fabrication of a semiconductor device and structure
US837871524 aug 201219 feb 2013Monolithic 3D Inc.Method to construct systems
US837945813 okt 201019 feb 2013Monolithic 3D Inc.Semiconductor device and structure
US838442614 apr 200926 feb 2013Monolithic 3D Inc.Semiconductor device and structure
US83951917 okt 201012 mar 2013Monolithic 3D Inc.Semiconductor device and structure
US840542019 aug 201026 mar 2013Monolithic 3D Inc.System comprising a semiconductor device and structure
US84272007 nov 201023 apr 2013Monolithic 3D Inc.3D semiconductor device
US844054226 aug 201114 maj 2013Monolithic 3D Inc.Semiconductor device and structure
US84405479 feb 200914 maj 2013International Business Machines CorporationMethod and structure for PMOS devices with high K metal gate integration and SiGe channel engineering
US845080410 aug 201228 maj 2013Monolithic 3D Inc.Semiconductor device and structure for heat removal
US846103530 sep 201011 jun 2013Monolithic 3D Inc.Method for fabrication of a semiconductor device and structure
US847614513 okt 20102 jul 2013Monolithic 3D Inc.Method of fabricating a semiconductor device and structure
US849288622 nov 201023 jul 2013Monolithic 3D Inc3D integrated circuit with logic
US850235123 sep 20116 aug 2013Intel CorporationNonplanar device with thinned lower body portion and method of fabrication
US850799215 mar 201113 aug 2013International Business Machines CorporationHigh-K metal gate CMOS
US851876818 apr 201227 aug 2013Intel CorporationExtreme high mobility CMOS logic
US853602322 nov 201017 sep 2013Monolithic 3D Inc.Method of manufacturing a semiconductor device and structure
US85418199 dec 201024 sep 2013Monolithic 3D Inc.Semiconductor device and structure
US85576329 apr 201215 okt 2013Monolithic 3D Inc.Method for fabrication of a semiconductor device and structure
US857492916 nov 20125 nov 2013Monolithic 3D Inc.Method to form a 3D semiconductor device and structure
US857565527 mar 20125 nov 2013International Business Machines CorporationMethod and structure for PMOS devices with high K metal gate integration and SiGe channel engineering
US858125820 okt 201112 nov 2013Intel CorporationSemiconductor device structures and methods of forming semiconductor structures
US85813492 maj 201112 nov 2013Monolithic 3D Inc.3D memory semiconductor device and structure
US86179453 feb 201231 dec 2013Intel CorporationStacking fault and twin blocking barrier for integrating III-V on Si
US8629478 *10 jun 201014 jan 2014Taiwan Semiconductor Manufacturing Company, Ltd.Fin structure for high mobility multiple-gate transistor
US864241628 jun 20114 feb 2014Monolithic 3D Inc.Method of forming three dimensional integrated circuit devices using layer transfer technique
US866404214 maj 20124 mar 2014Monolithic 3D Inc.Method for fabrication of configurable systems
US866469428 jan 20134 mar 2014Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US86697782 maj 201111 mar 2014Monolithic 3D Inc.Method for design and manufacturing of a 3D semiconductor device
US867447022 dec 201218 mar 2014Monolithic 3D Inc.Semiconductor device and structure
US868642816 nov 20121 apr 2014Monolithic 3D Inc.Semiconductor device and structure
US86873992 okt 20111 apr 2014Monolithic 3D Inc.Semiconductor device and structure
US870359725 apr 201322 apr 2014Monolithic 3D Inc.Method for fabrication of a semiconductor device and structure
US87098808 dec 201129 apr 2014Monolithic 3D IncMethod for fabrication of a semiconductor device and structure
US8723223 *4 maj 201213 maj 2014Taiwan Semiconductor Manufacturing Company, Ltd.Hybrid Fin field-effect transistors
US874173325 jan 20133 jun 2014Intel CorporationStress in trigate devices using complimentary gate fill materials
US874247627 nov 20123 jun 2014Monolithic 3D Inc.Semiconductor device and structure
US87490263 jun 201310 jun 2014Intel CorporationNonplanar device with thinned lower body portion and method of fabrication
US875391316 mar 201217 jun 2014Monolithic 3D Inc.Method for fabricating novel semiconductor and optoelectronic devices
US875453318 nov 201017 jun 2014Monolithic 3D Inc.Monolithic three-dimensional semiconductor device and structure
US88025178 aug 201312 aug 2014Intel CorporationExtreme high mobility CMOS logic
US8802531 *13 nov 201312 aug 2014Taiwan Semiconductor Manufacturing Company, Ltd.Split-channel transistor and methods for forming the same
US88032063 apr 201312 aug 2014Monolithic 3D Inc.3D semiconductor device and structure
US881639420 dec 201326 aug 2014Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US882312216 mar 20122 sep 2014Monolithic 3D Inc.Semiconductor and optoelectronic devices
US88360736 aug 201316 sep 2014Monolithic 3D Inc.Semiconductor device and structure
US884646324 maj 201330 sep 2014Monolithic 3D Inc.Method to construct a 3D semiconductor device
US89016136 mar 20112 dec 2014Monolithic 3D Inc.Semiconductor device and structure for heat removal
US89016642 jun 20112 dec 2014International Business Machines CorporationHigh-K/metal gate CMOS finFET with improved pFET threshold voltage
US890266311 mar 20132 dec 2014Monolithic 3D Inc.Method of maintaining a memory state
US89074428 jun 20129 dec 2014Monolthic 3D Inc.System comprising a semiconductor device and structure
US891205220 jan 201216 dec 2014Monolithic 3D Inc.Semiconductor device and structure
US89219705 mar 201430 dec 2014Monolithic 3D IncSemiconductor device and structure
US89334588 okt 201313 jan 2015Intel CorporationSemiconductor device structures and methods of forming semiconductor structures
US8946811 *10 jul 20063 feb 2015Taiwan Semiconductor Manufacturing Company, Ltd.Body-tied, strained-channel multi-gate device and methods of manufacturing same
US895695927 sep 201117 feb 2015Monolithic 3D Inc.Method of manufacturing a semiconductor device with two monocrystalline layers
US897567022 jul 201210 mar 2015Monolithic 3D Inc.Semiconductor device and structure for heat removal
US898707921 nov 201224 mar 2015Monolithic 3D Inc.Method for developing a custom device
US899440412 mar 201331 mar 2015Monolithic 3D Inc.Semiconductor device and structure
US900055717 mar 20127 apr 2015Zvi Or-BachSemiconductor device and structure
US902917318 okt 201112 maj 2015Monolithic 3D Inc.Method for fabrication of a semiconductor device and structure
US903085823 sep 201212 maj 2015Monolithic 3D Inc.Semiconductor device and structure
US904831421 aug 20142 jun 2015Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US909942424 apr 20134 aug 2015Monolithic 3D Inc.Semiconductor system, device and structure with heat removal
US90995262 okt 20114 aug 2015Monolithic 3D Inc.Integrated circuit device and structure
US9105745 *28 sep 201211 aug 2015International Business Machines CorporationFabrication of low threshold voltage and inversion oxide thickness scaling for a high-k metal gate p-type MOSFET
US911774915 mar 201325 aug 2015Monolithic 3D Inc.Semiconductor device and structure
US9123567 *19 dec 20111 sep 2015Intel CorporationCMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
US91361538 jun 201215 sep 2015Monolithic 3D Inc.3D semiconductor device and structure with back-bias
US91905188 maj 201417 nov 2015Intel CorporationNonplanar device with thinned lower body portion and method of fabrication
US919780414 okt 201124 nov 2015Monolithic 3D Inc.Semiconductor and optoelectronic devices
US921455428 jan 201515 dec 2015Taiwan Semiconductor Manufacturing Company, Ltd.Body-tied, strained-channel multi-gate device and methods of manufacturing same
US921900520 sep 201222 dec 2015Monolithic 3D Inc.Semiconductor system and device
US921907818 apr 201322 dec 2015International Business Machines CorporationSimplified multi-threshold voltage scheme for fully depleted SOI MOSFETs
US92247548 maj 201429 dec 2015Intel CorporationStress in trigate devices using complimentary gate fill materials
US9230992 *30 apr 20145 jan 2016International Business Machines CorporationSemiconductor device including gate channel having adjusted threshold voltage
US9245805 *7 jul 201026 jan 2016Taiwan Semiconductor Manufacturing Company, Ltd.Germanium FinFETs with metal gates and stressors
US925213414 nov 20142 feb 2016Monolithic 3D Inc.Semiconductor device and structure
US92759083 jun 20151 mar 2016International Business Machines CorporationSemiconductor device including gate channel having adjusted threshold voltage
US9299840 *8 mar 201329 mar 2016Taiwan Semiconductor Manufacturing Company, Ltd.FinFETs and methods for forming the same
US930586728 aug 20145 apr 2016Monolithic 3D Inc.Semiconductor devices and structures
US93685831 maj 201514 jun 2016Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US938505814 mar 20135 jul 2016Monolithic 3D Inc.Semiconductor device and structure
US938518018 dec 20145 jul 2016Intel CorporationSemiconductor device structures and methods of forming semiconductor structures
US940667015 okt 20142 aug 2016Monolithic 3D Inc.System comprising a semiconductor device and structure
US940680015 dec 20152 aug 2016Taiwan Semiconductor Manufacturing Company, Ltd.Body-tied, strained-channel multi-gate device and methods of manufacturing same
US94126457 mar 20149 aug 2016Monolithic 3D Inc.Semiconductor devices and structures
US9418903 *21 maj 201416 aug 2016Globalfoundries Inc.Structure and method for effective device width adjustment in finFET devices using gate workfunction shift
US941903118 aug 201416 aug 2016Monolithic 3D Inc.Semiconductor and optoelectronic devices
US942070717 dec 200916 aug 2016Intel CorporationSubstrate for integrated circuit devices including multi-layer glass core and methods of making the same
US945009211 nov 201520 sep 2016Intel CorporationStress in trigate devices using complimentary gate fill materials
US946097817 apr 20134 okt 2016Monolithic 3D Inc.Semiconductor device and structure
US946099117 apr 20134 okt 2016Monolithic 3D Inc.Semiconductor device and structure
US94962713 okt 201415 nov 2016Monolithic 3D Inc.3DIC system with a two stable state memory and back-bias region
US95093136 mar 201129 nov 2016Monolithic 3D Inc.3D semiconductor device
US954836311 jun 201417 jan 2017Intel CorporationExtreme high mobility CMOS logic
US95483677 dec 201517 jan 2017Taiwan Semiconductor Manufacturing Company, Ltd.Method of reducing the heights of source-drain sidewall spacers of FinFETs through etching and the FinFETs thereof
US95644328 okt 20147 feb 2017Monolithic 3D Inc.3D semiconductor device and structure
US95776427 nov 201021 feb 2017Monolithic 3D Inc.Method to form a 3D semiconductor device
US963391125 mar 201525 apr 2017International Business Machines CorporationSimplified multi-threshold voltage scheme for fully depleted SOI MOSFETs
US964224810 feb 20152 maj 2017Intel CorporationMicroelectronic structures having laminated or embedded glass routing structures for high density packaging
US965355128 dec 201516 maj 2017Samsung Electronics Co., Ltd.Field effect transistors including fin structures with different doped regions and semiconductor devices including the same
US96535528 jul 201616 maj 2017Taiwan Semiconductor Manufacturing Company, Ltd.Body-tied, strained-channel multi-gate device and methods
US966649213 jul 201530 maj 2017Intel CorporationCMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
US96868612 jun 201620 jun 2017Intel CorporationGlass core substrate for integrated circuit devices and methods of making the same
US969185621 dec 201527 jun 2017Intel CorporationExtreme high mobility CMOS logic
US969806025 jan 20164 jul 2017Taiwan Semiconductor Manufacturing Company, Ltd.Germanium FinFETs with metal gates and stressors
US971140716 dec 201018 jul 2017Monolithic 3D Inc.Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer
US974180916 sep 201522 aug 2017Intel CorporationNonplanar device with thinned lower body portion and method of fabrication
US974838713 nov 201529 aug 2017Globalfoundries Inc.Methods of forming PMOS FinFET devices and multiple NMOS FinFET devices with different performance characteristics
US97615148 jul 201612 sep 2017Intel CorporationSubstrate for integrated circuit devices including multi-layer glass core and methods of making the same
US9761666 *16 jun 201112 sep 2017Taiwan Semiconductor Manufacturing Company, Ltd.Strained channel field effect transistor
US976172414 jun 201612 sep 2017Intel CorporationSemiconductor device structures and methods of forming semiconductor structures
US97932014 aug 201617 okt 2017Intel CorporationGlass clad microelectronic substrate
US9799767 *13 nov 201524 okt 2017Globalfoundries Inc.Methods of forming PMOS and NMOS FinFET devices on CMOS based integrated circuit products
US98061772 mar 201631 okt 2017Taiwan Semiconductor Manufacturing Company, Ltd.FinFETs and methods for forming the same
US980619329 aug 201631 okt 2017Intel CorporationStress in trigate devices using complimentary gate fill materials
US981880026 nov 201414 nov 2017Monolithic 3D Inc.Self aligned semiconductor device and structure
US20070138565 *15 dec 200521 jun 2007Intel CorporationExtreme high mobility CMOS logic
US20080006908 *10 jul 200610 jan 2008Taiwan Semiconductor Manufacturing Company, Ltd.Body-tied, strained-channel multi-gate device and methods of manufacturing same
US20080032478 *2 aug 20067 feb 2008Hudait Mantu KStacking fault and twin blocking barrier for integrating III-V on Si
US20090001438 *29 jun 20071 jan 2009Doyle Brian SIsolation of MIM FIN DRAM capacitor
US20090004868 *29 jun 20071 jan 2009Doyle Brian SAmorphous silicon oxidation patterning
US20090174010 *3 jan 20089 jul 2009International Business Machines CorporationSram device structure including same band gap transistors having gate stacks with high-k dielectrics and same work function
US20090315114 *23 jun 200824 dec 2009Intel CorporationStress in trigate devices using complimentary gate fill materials
US20100200937 *9 feb 200912 aug 2010International Business Machines CorporationMETHOD AND STRUCTURE FOR PMOS DEVICES WITH HIGH K METAL GATE INTEGRATION AND SiGe CHANNEL ENGINEERING
US20100258908 *24 jun 201014 okt 2010Doyle Brian SIsolation of mim fin dram capacitor
US20110024794 *10 jun 20103 feb 2011Taiwan Semiconductor Manufacturing Company, Ltd.Fin structure for high mobility multiple-gate transistor
US20110037497 *14 apr 200917 feb 2011Or-Ment LlcMethod for Fabrication of a Semiconductor Device and Structure
US20110068407 *7 jul 201024 mar 2011Taiwan Semiconductor Manufacturing Company, Ltd.Germanium FinFETs with Metal Gates and Stressors
US20110227165 *2 jun 201122 sep 2011International Business Machines CorporationHigh-k/metal gate cmos finfet with improved pfet threshold voltage
US20120192413 *9 apr 20122 aug 2012Qing MaGlass core substrate for integrated circuit devices and methods of making the same
US20120319211 *16 jun 201120 dec 2012Taiwan Semiconductor Manufacturing Company, Ltd.Strained channel field effect transistor
US20130034940 *28 sep 20127 feb 2013International Business Machines CorporationLow Threshold Voltage And Inversion Oxide thickness Scaling For A High-K Metal Gate P-Type MOSFET
US20130134522 *4 maj 201230 maj 2013Taiwan Semiconductor Manufacturing Company, Ltd.Hybrid Fin Field-Effect Transistors
US20130270512 *19 dec 201117 okt 2013Marko RadosavljevicCmos implementation of germanium and iii-v nanowires and nanoribbons in gate-all-around architecture
US20140252475 *8 mar 201311 sep 2014Taiwan Semiconductor Manufacturing Company, Ltd.FinFETs and Methods for Forming the Same
US20140374807 *19 jun 201325 dec 2014International Business Machines CorporationMETHOD OF DEVICE ISOLATION IN CLADDING Si THROUGH IN SITU DOPING
US20150340294 *21 maj 201426 nov 2015International Business Machines CorporationStructure and method for effective device width adjustment in finfet devices using gate workfunction shift
US20160181250 *23 dec 201423 jun 2016International Business Machines CorporationFinfet based zram with convex channel region
US20160329331 *18 jul 201610 nov 2016Taiwan Semiconductor Manufacturing Company, Ltd.Mechanism for FinFET Well Doping
CN103137696A *4 jun 20125 jun 2013台湾积体电路制造股份有限公司Split-channel transistor and methods for forming the same
CN103325736A *19 mar 201325 sep 2013三星电子株式会社Method for fabricating fin type field effect transistor with fins of different widths
CN104282692A *10 sep 201314 jan 2015台湾积体电路制造股份有限公司Multi-port sram manufacturing
CN105097513A *24 apr 201425 nov 2015中芯国际集成电路制造(北京)有限公司Semiconductor device, manufacture method thereof and electronic device
EP2901470A4 *11 jun 20131 jun 2016Intel CorpNon-planar semiconductor device having channel region with low band-gap cladding layer
WO2011054776A1 *1 nov 201012 maj 2011International Business Machines CorporationHigh-k/metal gate cmos finfet with improved pfet threshold voltage
WO2014051731A111 jun 20133 apr 2014Intel CorporationNon-planar semiconductor device having channel region with low band-gap cladding layer
Klassificeringar
USA-klassificering257/288, 257/E21.703, 257/E27.112, 257/E21.642, 257/E21.633
Internationell klassificeringH01L29/76
Kooperativ klassningH01L29/1054, H01L29/785, H01L29/66795, H01L27/1211, H01L21/845, H01L21/823878, H01L21/823821, H01L21/823807, H01L29/068, H01L29/0673, H01L29/66439, H01L29/775
Europeisk klassificeringH01L21/84F, H01L27/12B4, H01L21/8238F, H01L29/66M6T6F16F, H01L21/8238U, H01L21/8238C, H01L29/78S
Juridiska händelser
DatumKodHändelseBeskrivning
27 dec 2005ASAssignment
Owner name: INTEL, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DOYLE, BRYAN S.;JIN, BEEN-YIH;KAVALIEROS, JACK T.;AND OTHERS;REEL/FRAME:017396/0581;SIGNING DATES FROM 20051210 TO 20051212