US20070032016A1 - Protective layer in memory device and method therefor - Google Patents
Protective layer in memory device and method therefor Download PDFInfo
- Publication number
- US20070032016A1 US20070032016A1 US11/490,483 US49048306A US2007032016A1 US 20070032016 A1 US20070032016 A1 US 20070032016A1 US 49048306 A US49048306 A US 49048306A US 2007032016 A1 US2007032016 A1 US 2007032016A1
- Authority
- US
- United States
- Prior art keywords
- layer
- forming
- protective layer
- nitride
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000011241 protective layer Substances 0.000 title claims abstract description 51
- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000010410 layer Substances 0.000 claims abstract description 104
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 47
- 229920005591 polysilicon Polymers 0.000 claims description 44
- 150000004767 nitrides Chemical class 0.000 claims description 34
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 229910021332 silicide Inorganic materials 0.000 claims description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 229910045601 alloy Inorganic materials 0.000 claims description 11
- 239000000956 alloy Substances 0.000 claims description 11
- 239000011521 glass Substances 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 238000001020 plasma etching Methods 0.000 claims description 6
- 239000006097 ultraviolet radiation absorber Substances 0.000 claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 3
- 150000003376 silicon Chemical class 0.000 claims description 3
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 3
- 229910001203 Alloy 20 Inorganic materials 0.000 claims 1
- 230000000694 effects Effects 0.000 description 12
- 238000005530 etching Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 7
- 230000005641 tunneling Effects 0.000 description 6
- 238000007667 floating Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000006096 absorbing agent Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005289 physical deposition Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/954—Making oxide-nitride-oxide device
Definitions
- the present invention relates to the manufacture of semiconductor products in general, and particularly to protection against damage to semiconductor circuits from effects of electromagnetic wave energy generated during an etch process.
- the chip contains a memory array, it typically has a plurality of memory transistors that may be programmed or erased.
- the memory transistors may be floating gate transistors, nitride read only memory (NROM) transistors, silicon oxide-nitride oxide-silicon (SONOS) transistors, and any other non-volatile memory metal oxide semiconductor (MOS) devices capable of storing charge.
- NROM nitride read only memory
- SONOS silicon oxide-nitride oxide-silicon
- MOS non-volatile memory metal oxide semiconductor
- the manufacturing process may have some undesirable side effects. For example, in MOS technology, the charging of active elements during the manufacturing process may alter die device's characteristics or even damage them.
- FIG. 1 illustrates a typical cross-section of an MOS or complementary MOS (CMOS) transistor wafer It is typically formed of a gate oxide 10 over which is a polysilicon element 12 On either side of tile gate oxide 10 are field oxides 14 which are much thicker than the gate oxide 10 Typically, tie polysilicon element 12 also spreads over the field oxides 14 A more advanced process may have trench isolation instead of field oxides but the effects discussed hereinbelow are the same in such a case.
- CMOS complementary MOS
- die field oxides 14 are first produced on a substrate 8 , after which the gate oxides 10 are grown.
- a layer of polysilicon is laid over the oxides 10 and 14 , and then etched to the desired shapes, such as by employing a shaped photoresist layer 15 .
- the etching process typically involves placing a plasma 16 , as is now explained.
- the etching process may be carried out by many methods, however, plasma based processes such as plasma enhanced chemical vapor deposition (CVD) and reactive ion etching (RIE) are very common.
- energy for etching is generated by coupling radio frequency (RF) electromagnetic energy to a plasma 16 .
- the RF energy may be supplied by an RF generator coupled to a power supply
- the etching process involves placing plasma 16 between die transistor and a electrified plate 18 connected to a high voltage source, and electrically connecting a second electrified plate 20 to the substrate 8
- Plasma may generate ultraviolet (UV) photons
- UV photons may also be generated during deposition of metal layers, such as in sputtering techniques.
- High energy electrons associated with the UV photons may charge the transistor. More specifically, since polysilicon is a conductive material, the polysilicon element 12 may become charged by the high energy photons. This is known as the “charging effect”
- the charging effect is not generally a problem in conventional floating gate transistors because the excess charge may be erased. However, it may degrade tile gate oxide as is now explained.
- the extent of the F-N tunneling is a function of the size of the polysilicon element 12 , the area of the gate oxide 10 and its thickness. As long as the area of polysilicon over the field oxides 14 is no larger than K times die area over the the gate oxides 10 (where K, called the “antenna ratio”, varies according to tie specific manufacturing process), the F-N tunneling will not occur Alternatively, the total charge passing through the oxide will be small enough not to cause breakdown of the oxide. Accordingly, the account of F-N tunneling may be reduced by reducing the area of die field oxide relative to the area of the gate.
- the abovementioned charging effect may be reduced by various techniques, such as tie reduction of the antenna ratio K and adding discharge devices along the poly lines.
- various techniques such as tie reduction of the antenna ratio K and adding discharge devices along the poly lines.
- Such techniques are discussed in applicant/assignee's U.S. patent application Ser. No. 09/336,666, filed Jun. 18, 1999 and entitled “Method and Circuit for Minimizing the Charging Effect During Manufacture of Semiconductor Devices”.
- NROM devices yet another problem may occur, wherein excess charge may accumulate along the edges of word lines.
- the excess charge is not uniform, and increases the threshold voltage V 1 of the cell.
- the increase in threshold voltage being non-uniformly across the device width, may degrade the reliability and endurance of tie cell
- programmed bits in the charge-trapping nitride layer are generally erased by hot hole injection.
- hot hole injection may only erase charge next to the source/drain junctions
- the charge along the word line edge, far from the source/drain junctions may not generally be erased. It would therefore be desirable to prevent UV photon-induced charge effect in die word-line edges of NROM devices
- the present invention seeks to provide methods and apparatus for protecting against plasma-induced damage to semiconductor circuits
- the invention may be used in any non-volatile memory device, particularly a memory device with a non-conducting charge layer
- the invention will be described with reference to an NROM device, although it is understood that the invention is not limited to NROM devices.
- a protective layer is formed in the NROM device over a polycide structure (e.g., a word line).
- the protective layer may comprise an ultraviolet absorber, e.g, a nitride layer
- Nitride is a good absorber of UV energy, and accordingly may prevent UV photons from the plasma etching from inducing stress in the polysilicon layer or gate stress in al oxide-nitride-oxide (ONO) layer.
- One preferred nitride comprises a thick silicon-rich silicon nitride alloy.
- the protective layer may comprise a layer of highly resistive undoped polysilicon.
- a method for protecting a non-volatile memory device die method including forming a non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and forming a protective layer over at least a portion of the polycide structure, the protective layer being adapted to absorb electromagnetic wave energy having a wavelength shorter than visible light
- non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and a protective layer formed over at least a portion of the polycide structure, the protective layer being adapted to absorb electromagnetic wave energy having a wavelength shorter than visible light.
- the protective layer includes an ultraviolet absorber.
- the protective layer includes a nitride layer.
- the nitride layer includes a silicon-rich silicon nitride alloy.
- tile nitride layer includes Si 3+x N 4 , wherein x>0.
- the nitride layer includes a hydrogenated silicon-rich silicon nitride alloy.
- the nitride layer includes an amorphous silicon-rich silicon nitride alloy.
- the protective layer includes a nitride layer with a thickness of 50-1000 ⁇ .
- the protective layer includes a layer of resistive undoped polysilicon.
- the protective layer of undoped polysilicon includes a resistivity of at least 1 G ⁇ .
- the protective layer of undoped polysilicon includes a thickness of 30-600 ⁇ .
- At least one additional layer is formed over the protective layer.
- the at least one additional layer includes at least one of a layer of undoped glass, a layer of doped glass, and a metal layer
- the polycide structure includes a polysilicon layer and a metal silicide film.
- die polysilicon layer includes a polycrystalline silicon (polysilicon).
- the polysilicon layer may or may not be doped with a dopant.
- the metal silicide film includes at least one of a tungsten silicide film and a titanium silicide film.
- the non-volatile memory device includes a nitride, read only memory (NROM) device, and die non-conducting charge trapping layer includes a nitride charge trapping layer.
- FIG. 1 is a schematic illustration of a prior art metal oxide semiconductor (MOS) transistor in a semiconductor chip during an etching operation;
- MOS metal oxide semiconductor
- FIG. 2 is a simplified illustration of a charging effect in an NROM non-volatile memory device
- FIGS. 3 and 4 are simplified cross-sectional illustrations of application of a protective layer over portions of the NROM device of FIG. 2 , in accordance with a preferred embodiment of the present invention, wherein FIG. 3 is a cross-section along poly lines and FIG. 4 is a cross-section of word lines between bit lines.
- FIG. 2 illustrates a charging effect in an NROM non-volatile memory device 43 , which includes one or more word lines (WL) 40 and bit lines (BL) 42 Bit lines 42 may be separated from each other by a distance L D .
- portions of device 43 such as but not limited to, edges 50 of word line 40 , may accumulate charge (indicated by dots along edges 50 in FIG. 2 ) due to the deleterious charge effect mentioned hereinabove.
- WL 40 may comprise a polycide structure, comprising for example, a lower polysilicon layer 44 and an upper layer formed of a metal silicide film 48
- Polysilicon layer 44 may comprise without limitation a polycrystalline silicon (polysilicon), which may or may not be doped with a dopant such as phosphorus, for example.
- Metal silicide film 48 may comprise without limitation a tungsten silicide film or a titanium silicide film, for example.
- bit line 42 may include a BL oxide layer 54 and a BL junction 56
- Additional layers may be formed over polysilicon layer 44 and metal silicide film 48 .
- Such layers may include, without limitation, a layer of undoped glass 60 (silicon dioxide), a layer of doped glass 62 , and a metal layer 64
- the doped glass layer 62 may comprise borophosphosilicate glass (BPSG), and phosphosilicate glass (PSG), for example.
- the additional layers may be grown, or deposited by physical deposition (e g, sputtering) or formed by any other suitable technique, and are generally etched to their final dimensions and form by plasma etching. As mentioned hereinabove, high energy electrons from UV light photons generated by the sputtering and etching may cause charge to be accumulated in the edges 50 .
- a protective layer 52 is applied over at least a portion of the polycide structure of polysilicon layer 44 and metal silicide film 48
- the protective layer 52 may be applied prior to the formation of the additional layers 60 and 62 .
- the protective layer 52 may be applied over additional layers 60 and 62 , and prior to tile formation of the metal layer 64 , as seen in FIG. 3 .
- the protective layer 52 has the property of absorbing electromagnetic wave energy, such as but not limited to UV light, and serves as a protective mask that may prevent high energy photons from reaching the polycide structure of polysilicon layer 44 and metal silicide film 48 while sputtering aid etching the additional layers 60 and 62 , or metal layer 64 .
- protective layer 52 may absorb electromagnetic wave energy having a wavelength shorter than visible light.
- the protective layer 52 comprises an ultraviolet absorber, e g., a nitride layer Nitride is a good absorber of UV energy, and accordingly may prevent UV photons from the sputtering or plasma etching from inducing stress in the polycide structure of polysilicon layer 44 and/or metal silicide film 48 , or gate stress in the ONO layer 46 .
- a nitride layer Nitride is a good absorber of UV energy, and accordingly may prevent UV photons from the sputtering or plasma etching from inducing stress in the polycide structure of polysilicon layer 44 and/or metal silicide film 48 , or gate stress in the ONO layer 46 .
- One preferred nitride comprises a silicon-rich silicon nitride alloy, such as Si 3+x N 4 , wherein x>0.
- the silicon-rich silicon nitride alloy may be hydrogenated and/or amorphous.
- Tile nitride layer is preferably relatively very thick, such as without limitation, in the range of 50-1000 ⁇ .
- the nitride layer may be formed using any suitable technique, such as but not limited to, a low pressure chemical vapor deposition technique (LPCVD).
- LPCVD low pressure chemical vapor deposition technique
- the protective layer 52 may comprise a layer of highly resistive undoped polysilicon
- the layer of undoped polysilicon may be deposited using any suitable technique, such as but not limited to, CVD methods.
- the undoped polysilicon layer is preferably relatively very thin, such as without limitation, in the range of 30-600 ⁇ .
- the undoped polysilicon layer preferably has a high resistance, such as without limitation, at least 1 G ⁇ .
- the additional layers 60 and 62 may be formed over protective layer 52 , such as but not limited to, by sputtering and etching If the protective layer 52 has been formed over the additional layers 60 and 62 , the metal layer 64 may be deposited or etched over protective layer 52 , for example.
- the protective layer 52 may have a high electrical resistivity so as to prevent leakage from one contact to another contact (or from one via to another via) formed in the device 43 . The protective layer 52 may thus prevent electrical stress and gate stress problems, as well as prevent leakage between contacts in device 43 .
Abstract
A method protecting a non-volatile memory device, the method including forming a non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and forming a protective layer over at least a portion of the polycide structure, die protective layer being adapted to absorb electromagnetic wave energy having a wavelength shorter than visible light. A device constructed in accordance with the method is also disclosed.
Description
- The present invention relates to the manufacture of semiconductor products in general, and particularly to protection against damage to semiconductor circuits from effects of electromagnetic wave energy generated during an etch process.
- During the manufacture of semiconductor products, layers of material are laid down or grown. Some layers are then etched, to produce die desired shapes of transistors, metal lines, and other microelectronics devices. When the processing has finished, a functioning chip is produced. If the chip contains a memory array, it typically has a plurality of memory transistors that may be programmed or erased. For example, the memory transistors may be floating gate transistors, nitride read only memory (NROM) transistors, silicon oxide-nitride oxide-silicon (SONOS) transistors, and any other non-volatile memory metal oxide semiconductor (MOS) devices capable of storing charge. Unfortunately, the manufacturing process may have some undesirable side effects. For example, in MOS technology, the charging of active elements during the manufacturing process may alter die device's characteristics or even damage them.
- Reference is now made to
FIG. 1 , which illustrates a typical cross-section of an MOS or complementary MOS (CMOS) transistor wafer It is typically formed of agate oxide 10 over which is apolysilicon element 12 On either side oftile gate oxide 10 arefield oxides 14 which are much thicker than thegate oxide 10 Typically,tie polysilicon element 12 also spreads over the field oxides 14 A more advanced process may have trench isolation instead of field oxides but the effects discussed hereinbelow are the same in such a case. - During manufacture, die
field oxides 14 are first produced on asubstrate 8, after which thegate oxides 10 are grown. A layer of polysilicon is laid over theoxides photoresist layer 15. The etching process typically involves placing aplasma 16, as is now explained. - The etching process may be carried out by many methods, however, plasma based processes such as plasma enhanced chemical vapor deposition (CVD) and reactive ion etching (RIE) are very common. Typically, energy for etching is generated by coupling radio frequency (RF) electromagnetic energy to a
plasma 16. The RF energy may be supplied by an RF generator coupled to a power supply InFIG. 1 , the etching process involves placingplasma 16 between die transistor and aelectrified plate 18 connected to a high voltage source, and electrically connecting a secondelectrified plate 20 to thesubstrate 8 - Plasma may generate ultraviolet (UV) photons, UV photons may also be generated during deposition of metal layers, such as in sputtering techniques. High energy electrons associated with the UV photons may charge the transistor. More specifically, since polysilicon is a conductive material, the
polysilicon element 12 may become charged by the high energy photons. This is known as the “charging effect” The charging effect is not generally a problem in conventional floating gate transistors because the excess charge may be erased. However, it may degrade tile gate oxide as is now explained. - The more charge the
polysilicon element 12 attracts, the greater the voltage drop between diepolysilicon element 12 and thesubstrate 8 If the voltage drop is high enough, it induces Fowler-Nordheim (F-N) tunneling of charge from thesubstrate 8 to thepolysilicon element 12, via thegate oxide 10, as indicated byarrows 24 Since thefield oxides 14 are quite thick, no F-N tunneling generally occurs through them Unfortunately, F-N tunneling may cause breakdown oftile gate oxide 10, especially if thegate oxide 10 is quite thin. It is appreciated that, once thegate oxide 10 has broken down, the transistor will not function. - Solutions are known for handling the gate oxide degradation problem of CMOS and floating gate transistors. The extent of the F-N tunneling is a function of the size of the
polysilicon element 12, the area of thegate oxide 10 and its thickness. As long as the area of polysilicon over thefield oxides 14 is no larger than K times die area over the the gate oxides 10 (where K, called the “antenna ratio”, varies according to tie specific manufacturing process), the F-N tunneling will not occur Alternatively, the total charge passing through the oxide will be small enough not to cause breakdown of the oxide. Accordingly, the account of F-N tunneling may be reduced by reducing the area of die field oxide relative to the area of the gate. - In NROM devices, similar to the CMOS and floating gate memory devices, the abovementioned charging effect may be reduced by various techniques, such as tie reduction of the antenna ratio K and adding discharge devices along the poly lines. Such techniques are discussed in applicant/assignee's U.S. patent application Ser. No. 09/336,666, filed Jun. 18, 1999 and entitled “Method and Circuit for Minimizing the Charging Effect During Manufacture of Semiconductor Devices”.
- However, in NROM devices, yet another problem may occur, wherein excess charge may accumulate along the edges of word lines. The excess charge is not uniform, and increases the threshold voltage V1 of the cell. The increase in threshold voltage being non-uniformly across the device width, may degrade the reliability and endurance of tie cell In N-ROM cells, programmed bits in the charge-trapping nitride layer are generally erased by hot hole injection. However, hot hole injection may only erase charge next to the source/drain junctions The charge along the word line edge, far from the source/drain junctions, may not generally be erased. It would therefore be desirable to prevent UV photon-induced charge effect in die word-line edges of NROM devices
- The present invention seeks to provide methods and apparatus for protecting against plasma-induced damage to semiconductor circuits The invention may be used in any non-volatile memory device, particularly a memory device with a non-conducting charge layer The invention will be described with reference to an NROM device, although it is understood that the invention is not limited to NROM devices.
- In accordance with a preferred embodiment of the present invention, a protective layer is formed in the NROM device over a polycide structure (e.g., a word line). The protective layer may comprise an ultraviolet absorber, e.g, a nitride layer Nitride is a good absorber of UV energy, and accordingly may prevent UV photons from the plasma etching from inducing stress in the polysilicon layer or gate stress in al oxide-nitride-oxide (ONO) layer. One preferred nitride comprises a thick silicon-rich silicon nitride alloy. Additionally or alternatively, the protective layer may comprise a layer of highly resistive undoped polysilicon.
- There is thus provided in accordance with a preferred embodiment of the present invention a method for protecting a non-volatile memory device, die method including forming a non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and forming a protective layer over at least a portion of the polycide structure, the protective layer being adapted to absorb electromagnetic wave energy having a wavelength shorter than visible light
- There is also provided in accordance with a preferred embodiment of the present invention a non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and a protective layer formed over at least a portion of the polycide structure, the protective layer being adapted to absorb electromagnetic wave energy having a wavelength shorter than visible light.
- In accordance with a preferred embodiment of the present invention the protective layer includes an ultraviolet absorber.
- Further in accordance with a preferred embodiment of the present invention the protective layer includes a nitride layer.
- 5 Still further in accordance with a preferred embodiment of the present invention the nitride layer includes a silicon-rich silicon nitride alloy.
- In accordance with a preferred embodiment of the present invention tile nitride layer includes Si3+xN4, wherein x>0.
- Further in accordance with a preferred embodiment of die present invention the nitride layer includes a hydrogenated silicon-rich silicon nitride alloy.
- Still further in accordance with a preferred embodiment of tile present invention the nitride layer includes an amorphous silicon-rich silicon nitride alloy.
- In accordance with a preferred embodiment of the present invention the protective layer includes a nitride layer with a thickness of 50-1000 Å.
- Further in accordance with a preferred embodiment of the present invention the protective layer includes a layer of resistive undoped polysilicon.
- Still further in accordance with a preferred embodiment of the present invention the protective layer of undoped polysilicon includes a resistivity of at least 1 GΩ.
- In accordance with a preferred embodiment of the present invention the protective layer of undoped polysilicon includes a thickness of 30-600 Å.
- Further in accordance with a preferred embodiment of the present invention at least one additional layer is formed over the protective layer.
- Still further in accordance with a preferred embodiment of the present invention the at least one additional layer includes at least one of a layer of undoped glass, a layer of doped glass, and a metal layer
- In accordance with a preferred embodiment of the present invention the polycide structure includes a polysilicon layer and a metal silicide film.
- Further in accordance with a preferred embodiment of die present invention die polysilicon layer includes a polycrystalline silicon (polysilicon). The polysilicon layer may or may not be doped with a dopant.
- Still further in accordance with a preferred embodiment of the present invention the metal silicide film includes at least one of a tungsten silicide film and a titanium silicide film.
- In accordance with a preferred embodiment of the present invention the non-volatile memory device includes a nitride, read only memory (NROM) device, and die non-conducting charge trapping layer includes a nitride charge trapping layer.
- The present invention will be understood and appreciated more fully from the following detailed description taken in conjuction with the appended drawings in which:
-
FIG. 1 is a schematic illustration of a prior art metal oxide semiconductor (MOS) transistor in a semiconductor chip during an etching operation; -
FIG. 2 is a simplified illustration of a charging effect in an NROM non-volatile memory device; and -
FIGS. 3 and 4 are simplified cross-sectional illustrations of application of a protective layer over portions of the NROM device ofFIG. 2 , in accordance with a preferred embodiment of the present invention, whereinFIG. 3 is a cross-section along poly lines andFIG. 4 is a cross-section of word lines between bit lines. - Reference is now made to
FIG. 2 , which illustrates a charging effect in an NROMnon-volatile memory device 43, which includes one or more word lines (WL) 40 and bit lines (BL) 42Bit lines 42 may be separated from each other by a distance LD. During etching and/or sputtering processes, portions ofdevice 43, such as but not limited to, edges 50 ofword line 40, may accumulate charge (indicated by dots alongedges 50 inFIG. 2 ) due to the deleterious charge effect mentioned hereinabove. - Reference is now made to
FIGS. 3 and 4 , which illustrate cross-sections of the NROMnon-volatile memory device 43.WL 40 may comprise a polycide structure, comprising for example, alower polysilicon layer 44 and an upper layer formed of ametal silicide film 48Polysilicon layer 44 may comprise without limitation a polycrystalline silicon (polysilicon), which may or may not be doped with a dopant such as phosphorus, for example.Metal silicide film 48 may comprise without limitation a tungsten silicide film or a titanium silicide film, for example. - The polycide structure of
polysilicon layer 44 andmetal silicide film 48 may be formed over anONO layer 46ONO layer 46 is also referred to as a nitride charge trapping layer. As seen inFIG. 3 ,bit line 42 may include aBL oxide layer 54 and aBL junction 56 - Additional layers may be formed over
polysilicon layer 44 andmetal silicide film 48. Such layers may include, without limitation, a layer of undoped glass 60 (silicon dioxide), a layer of dopedglass 62, and ametal layer 64 The dopedglass layer 62 may comprise borophosphosilicate glass (BPSG), and phosphosilicate glass (PSG), for example. The additional layers may be grown, or deposited by physical deposition (e g, sputtering) or formed by any other suitable technique, and are generally etched to their final dimensions and form by plasma etching. As mentioned hereinabove, high energy electrons from UV light photons generated by the sputtering and etching may cause charge to be accumulated in theedges 50. - In accordance with a preferred embodiment of the present invention, in order to prevent the change effect, a
protective layer 52 is applied over at least a portion of the polycide structure ofpolysilicon layer 44 andmetal silicide film 48 Theprotective layer 52 may be applied prior to the formation of theadditional layers protective layer 52 may be applied overadditional layers metal layer 64, as seen inFIG. 3 . Theprotective layer 52 has the property of absorbing electromagnetic wave energy, such as but not limited to UV light, and serves as a protective mask that may prevent high energy photons from reaching the polycide structure ofpolysilicon layer 44 andmetal silicide film 48 while sputtering aid etching theadditional layers metal layer 64. In general,protective layer 52 may absorb electromagnetic wave energy having a wavelength shorter than visible light. - In accordance with a preferred embodiment of die present invention, the
protective layer 52 comprises an ultraviolet absorber, e g., a nitride layer Nitride is a good absorber of UV energy, and accordingly may prevent UV photons from the sputtering or plasma etching from inducing stress in the polycide structure ofpolysilicon layer 44 and/ormetal silicide film 48, or gate stress in theONO layer 46. One preferred nitride comprises a silicon-rich silicon nitride alloy, such as Si3+xN4, wherein x>0. The silicon-rich silicon nitride alloy may be hydrogenated and/or amorphous. Tile nitride layer is preferably relatively very thick, such as without limitation, in the range of 50-1000 Å. The nitride layer may be formed using any suitable technique, such as but not limited to, a low pressure chemical vapor deposition technique (LPCVD). - Additionally or alternatively, the
protective layer 52 may comprise a layer of highly resistive undoped polysilicon The layer of undoped polysilicon may be deposited using any suitable technique, such as but not limited to, CVD methods. The undoped polysilicon layer is preferably relatively very thin, such as without limitation, in the range of 30-600 Å. The undoped polysilicon layer preferably has a high resistance, such as without limitation, at least 1 GΩ. - As seen in
FIG. 4 , if needed, there may be aspacer 49 betweenprotective layer 52 and portions ofpolysilicon layer 44 - If the
protective layer 52 has been formed overmetal silicide film 48, theadditional layers protective layer 52, such as but not limited to, by sputtering and etching If theprotective layer 52 has been formed over theadditional layers metal layer 64 may be deposited or etched overprotective layer 52, for example. Theprotective layer 52 may have a high electrical resistivity so as to prevent leakage from one contact to another contact (or from one via to another via) formed in thedevice 43. Theprotective layer 52 may thus prevent electrical stress and gate stress problems, as well as prevent leakage between contacts indevice 43. - It will be appreciated by persons skilled in die art that tile present invention is not limited by what has been particularly shown and described herein above Rather the scope of the invention is defined by the claims that follow:
Claims (34)
1. A method for protecting a non-volatile memory device, the method comprising:
forming a non-volatile memory device comprising a polycide structure formed over a non-conducting charge trapping layer; and
forming a protective layer over at least a portion of said polycide structure, said protective layer being adapted to absorb electromagnetic wave energy having a wavelength shorter than visible light
2. The method according to claim 1 wherein said forming said protective layer comprises forming an ultraviolet absorber
3. The method according to claim 1 wherein said forming said protective layer comprises forming a nitride layer
4. The method according to claim 3 wherein said forming said nitride layer comprises forming a silicon-rich silicon nitride alloy.
5. The method according to claim 4 wherein said forming said nitride layer comprises forming a nitride layer comprising Si3+xN4, wherein x>0.
6. The method according to claim 3 wherein said forming said nitride layer comprises forming a hydrogenated silicon-rich silicon nitride alloy
7. The method according to claim 3 wherein said forming said nitride layer comprises forming an amorphous silicon-rich silicon nitride alloy
8. The method according to claim 1 wherein said forming said protective layer comprises forming a nitride layer with a thickness of 50-1000 Å.
9. The method according to claim 1 wherein said forming said protective layer comprises forming a layer of resistive undoped polysilicon.
10. The method according to claim 9 wherein said forming said protective layer of undoped polysilicon comprises forming a layer with a resistivity of at least 1 GΩ.
11. The method according to claim 9 wherein said forming said protective layer of undoped polysilicon comprises forming a layer with a thickness of 30-600 Å.
12. The method according to claim 1 and further comprising forming at least one additional layer over said protective layer.
13. The method according to claim 12 wherein said forming said at least one additional layer comprises forming at least one of a layer of undoped glass, a layer of doped glass and a metal layer
14. The method according to claim 12 and further comprising plasma etching said at least one additional layer with said protective layer making at least a portion of said polycide structure.
15. The method according to claim 1 wherein said forming said non-volatile memory device comprises forming said non-volatile memory device with a polycide structure comprising is a polysilicon layer and a metal silicide film.
16. A non-volatile memory device comprising:
a polycide structure formed over a nonconducting charge trapping layer; and
a protective layer formed over at least a portion of said polycide structure, said protective layer being adapted to absorb electromagnetic wave energy leaving a wavelength shorter than visible light.
17. The device according to claim 16 wherein said protective layer comprises an ultraviolet absorber.
18. The device according to claim 16 wherein said protective layer comprises a nitride layer.
19. The device according to claim 18 wherein said nitride layer comprises a silicon-rich silicon nitride alloy
20. The device according to claim 19 wherein said nitride layer comprises Si3+xN4, wherein x>0.
21. The device according to claim 18 wherein said nitride layer comprises a hydrogenated silicon-rich silicon nitride alloy
22. The device according to claim 18 wherein said nitride layer comprises an amorphous silicon-rich silicon nitride alloy.
23. The device according to claim 16 wherein said protective layer comprises a nitride layer with a thickness of 50-1000 Å.
24. The device according to claim 16 wherein said protective layer comprises a layer of resistive undoped polysilicon.
25. The device according to claim 24 wherein said protective layer of undoped polysilicon comprises a resistivity of at least 1 GΩ.
26. The device according to claim 24 wherein said protective layer of undoped polysilicon comprises a thickness of 30-600 Å.
27. The device according to claim 16 and further comprising at least one additional layer formed over said protective layer
28. The device according to claim 27 wherein said at least one additional layer comprises at least one of a layer of undoped glass, a layer of doped glass, and a metal layer
29. The device according to claim 16 wherein said polycide structure comprises a polysilicon layer and a metal silicide film.
30. The device according to claim 29 wherein said polysilicon layer comprises a polycrystalline silicon (polysilicon).
31. The device according to claim 29 wherein said polysilicon layer is doped with a dopant.
32. The device according to claim 29 wherein said polysilicon layer is undoped.
33. The device according to claim 29 wherein said metal silicide film comprises at least one of a tungsten silicide film and a titanium silicide film.
34. The device according to claim 16 wherein said non-volatile memory device comprises a nitride, read only memory (NROM) device, and said non-conducting charge trapping layer comprises a nitride charge trapping layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/490,483 US20070032016A1 (en) | 2001-11-19 | 2006-07-20 | Protective layer in memory device and method therefor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/988,122 US7098107B2 (en) | 2001-11-19 | 2001-11-19 | Protective layer in memory device and method therefor |
US11/490,483 US20070032016A1 (en) | 2001-11-19 | 2006-07-20 | Protective layer in memory device and method therefor |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/988,122 Continuation US7098107B2 (en) | 2001-11-19 | 2001-11-19 | Protective layer in memory device and method therefor |
Publications (1)
Publication Number | Publication Date |
---|---|
US20070032016A1 true US20070032016A1 (en) | 2007-02-08 |
Family
ID=25533873
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/988,122 Expired - Lifetime US7098107B2 (en) | 2001-11-19 | 2001-11-19 | Protective layer in memory device and method therefor |
US10/189,533 Expired - Lifetime US6828625B2 (en) | 2001-11-19 | 2002-07-08 | Protective layer in memory device and method therefor |
US11/490,483 Abandoned US20070032016A1 (en) | 2001-11-19 | 2006-07-20 | Protective layer in memory device and method therefor |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/988,122 Expired - Lifetime US7098107B2 (en) | 2001-11-19 | 2001-11-19 | Protective layer in memory device and method therefor |
US10/189,533 Expired - Lifetime US6828625B2 (en) | 2001-11-19 | 2002-07-08 | Protective layer in memory device and method therefor |
Country Status (6)
Country | Link |
---|---|
US (3) | US7098107B2 (en) |
EP (1) | EP1313138A3 (en) |
JP (1) | JP2003243545A (en) |
AU (1) | AU2002353459A1 (en) |
IL (1) | IL152913A0 (en) |
WO (1) | WO2003044856A1 (en) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004193585A (en) * | 2002-11-29 | 2004-07-08 | Fujitsu Ltd | Method for manufacturing semiconductor device and semiconductor device |
US6774432B1 (en) * | 2003-02-05 | 2004-08-10 | Advanced Micro Devices, Inc. | UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL |
US7060554B2 (en) * | 2003-07-11 | 2006-06-13 | Advanced Micro Devices, Inc. | PECVD silicon-rich oxide layer for reduced UV charging |
US6869844B1 (en) * | 2003-11-05 | 2005-03-22 | Advanced Micro Device, Inc. | Method and structure for protecting NROM devices from induced charge damage during device fabrication |
US6989563B1 (en) | 2004-02-02 | 2006-01-24 | Advanced Micro Devices, Inc. | Flash memory cell with UV protective layer |
US7157331B2 (en) * | 2004-06-01 | 2007-01-02 | Macronix International Co., Ltd. | Ultraviolet blocking layer |
US7091088B1 (en) | 2004-06-03 | 2006-08-15 | Spansion Llc | UV-blocking etch stop layer for reducing UV-induced charging of charge storage layer in memory devices in BEOL processing |
JP2005347589A (en) | 2004-06-04 | 2005-12-15 | Matsushita Electric Ind Co Ltd | Nonvolatile semiconductor memory device and method for manufacturing the same |
JP4813778B2 (en) * | 2004-06-30 | 2011-11-09 | 富士通セミコンダクター株式会社 | Semiconductor device |
JP2006032797A (en) | 2004-07-20 | 2006-02-02 | Matsushita Electric Ind Co Ltd | Nonvolatile semiconductor storage device and its manufacturing method |
US7335610B2 (en) * | 2004-07-23 | 2008-02-26 | Macronix International Co., Ltd. | Ultraviolet blocking layer |
US20060141804A1 (en) * | 2004-12-28 | 2006-06-29 | Goodman Cathryn E | Method and apparatus to facilitate electrostatic discharge resiliency |
US8022468B1 (en) * | 2005-03-29 | 2011-09-20 | Spansion Llc | Ultraviolet radiation blocking interlayer dielectric |
JP2007158289A (en) * | 2005-11-11 | 2007-06-21 | Matsushita Electric Ind Co Ltd | Semiconductor storage device and manufacturing method of the same |
US7662712B2 (en) * | 2006-02-10 | 2010-02-16 | Macronix International Co., Ltd. | UV blocking and crack protecting passivation layer fabricating method |
US7755197B2 (en) * | 2006-02-10 | 2010-07-13 | Macronix International Co., Ltd. | UV blocking and crack protecting passivation layer |
US7498228B2 (en) * | 2007-07-09 | 2009-03-03 | United Microelectronics Corp. | Method for fabricating SONOS a memory |
JP2009021319A (en) * | 2007-07-11 | 2009-01-29 | Panasonic Corp | Nonvolatile semiconductor storage device and manufacturing method thereof |
JP2010212454A (en) * | 2009-03-10 | 2010-09-24 | Panasonic Corp | Nonvolatile semiconductor memory device |
JP2011003600A (en) * | 2009-06-16 | 2011-01-06 | Panasonic Corp | Method of fabricating semiconductor memory device |
US8866213B2 (en) | 2013-01-30 | 2014-10-21 | Spansion Llc | Non-Volatile memory with silicided bit line contacts |
TWI708373B (en) * | 2016-10-11 | 2020-10-21 | 聯華電子股份有限公司 | Flash memory structure |
CN109659275B (en) * | 2017-10-10 | 2020-11-03 | 联华电子股份有限公司 | Method for manufacturing dynamic random access memory |
Citations (99)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2004A (en) * | 1841-03-12 | Improvement in the manner of constructing and propelling steam-vessels | ||
US596929A (en) * | 1898-01-04 | James godfrey wilson | ||
US4145703A (en) * | 1977-04-15 | 1979-03-20 | Supertex, Inc. | High power MOS device and fabrication method therefor |
US4247861A (en) * | 1979-03-09 | 1981-01-27 | Rca Corporation | High performance electrically alterable read-only memory (EAROM) |
US4257832A (en) * | 1978-07-24 | 1981-03-24 | Siemens Aktiengesellschaft | Process for producing an integrated multi-layer insulator memory cell |
US4373248A (en) * | 1978-07-12 | 1983-02-15 | Texas Instruments Incorporated | Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like |
US4435786A (en) * | 1981-11-23 | 1984-03-06 | Fairchild Camera And Instrument Corporation | Self-refreshing memory cell |
US4494016A (en) * | 1982-07-26 | 1985-01-15 | Sperry Corporation | High performance MESFET transistor for VLSI implementation |
US4507673A (en) * | 1979-10-13 | 1985-03-26 | Tokyo Shibaura Denki Kabushiki Kaisha | Semiconductor memory device |
US4725984A (en) * | 1984-02-21 | 1988-02-16 | Seeq Technology, Inc. | CMOS eprom sense amplifier |
US4733105A (en) * | 1985-09-04 | 1988-03-22 | Oki Electric Industry Co., Ltd. | CMOS output circuit |
US4992391A (en) * | 1989-11-29 | 1991-02-12 | Advanced Micro Devices, Inc. | Process for fabricating a control gate for a floating gate FET |
US5081371A (en) * | 1990-11-07 | 1992-01-14 | U.S. Philips Corp. | Integrated charge pump circuit with back bias voltage reduction |
US5086325A (en) * | 1990-11-21 | 1992-02-04 | Atmel Corporation | Narrow width EEPROM with single diffusion electrode formation |
US5095968A (en) * | 1990-04-09 | 1992-03-17 | Didion Manufacturing Co. | Rotary media drum with cooling component |
US5276646A (en) * | 1990-09-25 | 1994-01-04 | Samsung Electronics Co., Ltd. | High voltage generating circuit for a semiconductor memory circuit |
US5280420A (en) * | 1992-10-02 | 1994-01-18 | National Semiconductor Corporation | Charge pump which operates on a low voltage power supply |
US5289412A (en) * | 1992-06-19 | 1994-02-22 | Intel Corporation | High-speed bias-stabilized current-mirror referencing circuit for non-volatile memories |
US5293563A (en) * | 1988-12-29 | 1994-03-08 | Sharp Kabushiki Kaisha | Multi-level memory cell with increased read-out margin |
US5295108A (en) * | 1992-04-08 | 1994-03-15 | Nec Corporation | Electrically erasable and programmable read only memory device with simple controller for selecting operational sequences after confirmation |
US5295092A (en) * | 1992-01-21 | 1994-03-15 | Sharp Kabushiki Kaisha | Semiconductor read only memory |
US5381374A (en) * | 1992-01-09 | 1995-01-10 | Kabushiki Kaisha Toshiba | Memory cell data output circuit having improved access time |
US5393701A (en) * | 1993-04-08 | 1995-02-28 | United Microelectronics Corporation | Layout design to eliminate process antenna effect |
US5394355A (en) * | 1990-08-28 | 1995-02-28 | Mitsubishi Denki Kabushiki Kaisha | Read only memory for storing multi-data |
US5399891A (en) * | 1992-01-22 | 1995-03-21 | Macronix International Co., Ltd. | Floating gate or flash EPROM transistor array having contactless source and drain diffusions |
US5495440A (en) * | 1993-01-19 | 1996-02-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having hierarchical bit line structure |
US5592417A (en) * | 1994-01-31 | 1997-01-07 | Sgs-Thomson Microelectronics S.A. | Non-volatile programmable bistable multivibrator, programmable by the source, for memory redundancy circuit |
US5596527A (en) * | 1992-12-07 | 1997-01-21 | Nippon Steel Corporation | Electrically alterable n-bit per cell non-volatile memory with reference cells |
US5600586A (en) * | 1994-05-26 | 1997-02-04 | Aplus Integrated Circuits, Inc. | Flat-cell ROM and decoder |
US5599727A (en) * | 1994-12-15 | 1997-02-04 | Sharp Kabushiki Kaisha | Method for producing a floating gate memory device including implanting ions through an oxidized portion of the silicon film from which the floating gate is formed |
US5604804A (en) * | 1996-04-23 | 1997-02-18 | Micali; Silvio | Method for certifying public keys in a digital signature scheme |
US5606523A (en) * | 1994-01-31 | 1997-02-25 | Sgs-Thomson Microelectronics S.A. | Non-volatile programmable bistable multivibrator in predefined initial state for memory redundancy circuit |
US5708608A (en) * | 1995-12-28 | 1998-01-13 | Hyundai Electronics Industries Cp., Ltd. | High-speed and low-noise output buffer |
US5712814A (en) * | 1994-07-18 | 1998-01-27 | Sgs-Thomson Microelectronics S.R.L. | Nonvolatile memory cell and a method for forming the same |
US5712815A (en) * | 1996-04-22 | 1998-01-27 | Advanced Micro Devices, Inc. | Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells |
US5715193A (en) * | 1996-05-23 | 1998-02-03 | Micron Quantum Devices, Inc. | Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks |
US5717581A (en) * | 1994-06-30 | 1998-02-10 | Sgs-Thomson Microelectronics, Inc. | Charge pump circuit with feedback control |
US5717635A (en) * | 1996-08-27 | 1998-02-10 | International Business Machines Corporation | High density EEPROM for solid state file |
US5717632A (en) * | 1996-11-27 | 1998-02-10 | Advanced Micro Devices, Inc. | Apparatus and method for multiple-level storage in non-volatile memories |
US5721781A (en) * | 1995-09-13 | 1998-02-24 | Microsoft Corporation | Authentication system and method for smart card transactions |
US5862076A (en) * | 1990-11-13 | 1999-01-19 | Waferscale Integration, Inc. | Fast EPROM array |
US5861771A (en) * | 1996-10-28 | 1999-01-19 | Fujitsu Limited | Regulator circuit and semiconductor integrated circuit device having the same |
US5864164A (en) * | 1996-12-09 | 1999-01-26 | United Microelectronics Corp. | Multi-stage ROM structure and method for fabricating the same |
US5867429A (en) * | 1997-11-19 | 1999-02-02 | Sandisk Corporation | High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates |
US5870334A (en) * | 1994-09-17 | 1999-02-09 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US5870335A (en) * | 1997-03-06 | 1999-02-09 | Agate Semiconductor, Inc. | Precision programming of nonvolatile memory cells |
US5872848A (en) * | 1997-02-18 | 1999-02-16 | Arcanvs | Method and apparatus for witnessed authentication of electronic documents |
US5875128A (en) * | 1996-06-28 | 1999-02-23 | Nec Corporation | Semiconductor memory |
US6011725A (en) * | 1997-08-01 | 2000-01-04 | Saifun Semiconductors, Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US6018186A (en) * | 1997-04-15 | 2000-01-25 | United Microelectronics Corp. | Three-dimensional, deep-trench, high-density read-only memory (ROM) and its manufacturing method |
US6020241A (en) * | 1997-12-22 | 2000-02-01 | Taiwan Semiconductor Manufacturing Company | Post metal code engineering for a ROM |
US6028324A (en) * | 1997-03-07 | 2000-02-22 | Taiwan Semiconductor Manufacturing Company | Test structures for monitoring gate oxide defect densities and the plasma antenna effect |
US6030871A (en) * | 1998-05-05 | 2000-02-29 | Saifun Semiconductors Ltd. | Process for producing two bit ROM cell utilizing angled implant |
US6169691B1 (en) * | 1998-09-15 | 2001-01-02 | Stmicroelectronics S.R.L. | Method for maintaining the memory content of non-volatile memory cells |
US6175523B1 (en) * | 1999-10-25 | 2001-01-16 | Advanced Micro Devices, Inc | Precharging mechanism and method for NAND-based flash memory devices |
US6175519B1 (en) * | 1999-07-22 | 2001-01-16 | Macronix International Co., Ltd. | Virtual ground EPROM structure |
US6181605B1 (en) * | 1999-10-06 | 2001-01-30 | Advanced Micro Devices, Inc. | Global erase/program verification apparatus and method |
US6181597B1 (en) * | 1999-02-04 | 2001-01-30 | Tower Semiconductor Ltd. | EEPROM array using 2-bit non-volatile memory cells with serial read operations |
US6185143B1 (en) * | 2000-02-04 | 2001-02-06 | Hewlett-Packard Company | Magnetic random access memory (MRAM) device including differential sense amplifiers |
US6188211B1 (en) * | 1998-05-13 | 2001-02-13 | Texas Instruments Incorporated | Current-efficient low-drop-out voltage regulator with improved load regulation and frequency response |
US6190966B1 (en) * | 1997-03-25 | 2001-02-20 | Vantis Corporation | Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration |
US6192445B1 (en) * | 1996-09-24 | 2001-02-20 | Altera Corporation | System and method for programming EPROM cells using shorter duration pulse(s) in repeating the programming process of a particular cell |
US6195196B1 (en) * | 1998-03-13 | 2001-02-27 | Fuji Photo Film Co., Ltd. | Array-type exposing device and flat type display incorporating light modulator and driving method thereof |
US6335990B1 (en) * | 1997-07-03 | 2002-01-01 | Cisco Technology, Inc. | System and method for spatial temporal-filtering for improving compressed digital video |
US6335874B1 (en) * | 1997-12-12 | 2002-01-01 | Saifun Semiconductors Ltd. | Symmetric segmented memory array architecture |
US6337502B1 (en) * | 1999-06-18 | 2002-01-08 | Saifun Semicinductors Ltd. | Method and circuit for minimizing the charging effect during manufacture of semiconductor devices |
US20020004878A1 (en) * | 1996-08-08 | 2002-01-10 | Robert Norman | System and method which compares data preread from memory cells to data to be written to the cells |
US20020004921A1 (en) * | 2000-07-10 | 2002-01-10 | Hitachi, Ltd. | Method of deciding error rate and semiconductor integrated circuit device |
US6339556B1 (en) * | 1999-11-15 | 2002-01-15 | Nec Corporation | Semiconductor memory device |
US6343033B1 (en) * | 2000-02-25 | 2002-01-29 | Advanced Micro Devices, Inc. | Variable pulse width memory programming |
US6344959B1 (en) * | 1998-05-01 | 2002-02-05 | Unitrode Corporation | Method for sensing the output voltage of a charge pump circuit without applying a load to the output stage |
US6346442B1 (en) * | 1999-02-04 | 2002-02-12 | Tower Semiconductor Ltd. | Methods for fabricating a semiconductor chip having CMOS devices and a fieldless array |
US6348380B1 (en) * | 2000-08-25 | 2002-02-19 | Micron Technology, Inc. | Use of dilute steam ambient for improvement of flash devices |
US6348381B1 (en) * | 2001-02-21 | 2002-02-19 | Macronix International Co., Ltd. | Method for forming a nonvolatile memory with optimum bias condition |
US6348711B1 (en) * | 1998-05-20 | 2002-02-19 | Saifun Semiconductors Ltd. | NROM cell with self-aligned programming and erasure areas |
US6351415B1 (en) * | 2001-03-28 | 2002-02-26 | Tower Semiconductor Ltd. | Symmetrical non-volatile memory array architecture without neighbor effect |
US20030001213A1 (en) * | 2001-06-29 | 2003-01-02 | Chinatech Corporation | High density read only memory and fabrication method thereof |
US6504755B1 (en) * | 1999-05-14 | 2003-01-07 | Hitachi, Ltd. | Semiconductor memory device |
US6510082B1 (en) * | 2001-10-23 | 2003-01-21 | Advanced Micro Devices, Inc. | Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold |
US6512701B1 (en) * | 2001-06-21 | 2003-01-28 | Advanced Micro Devices, Inc. | Erase method for dual bit virtual ground flash |
US20030021155A1 (en) * | 2001-04-09 | 2003-01-30 | Yachareni Santosh K. | Soft program and soft program verify of the core cells in flash memory array |
US6519182B1 (en) * | 2000-07-10 | 2003-02-11 | Advanced Micro Devices, Inc. | Using hot carrier injection to control over-programming in a non-volatile memory cell having an oxide-nitride-oxide (ONO) structure |
US6519180B2 (en) * | 1999-01-14 | 2003-02-11 | Silicon Storage Technology, Inc. | Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system |
US6522585B2 (en) * | 2001-05-25 | 2003-02-18 | Sandisk Corporation | Dual-cell soft programming for virtual-ground memory arrays |
US6525969B1 (en) * | 2001-08-10 | 2003-02-25 | Advanced Micro Devices, Inc. | Decoder apparatus and methods for pre-charging bit lines |
US6674138B1 (en) * | 2001-12-31 | 2004-01-06 | Advanced Micro Devices, Inc. | Use of high-k dielectric materials in modified ONO structure for semiconductor devices |
US6677805B2 (en) * | 2001-04-05 | 2004-01-13 | Saifun Semiconductors Ltd. | Charge pump stage with body effect minimization |
US6680509B1 (en) * | 2001-09-28 | 2004-01-20 | Advanced Micro Devices, Inc. | Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory |
US20040014280A1 (en) * | 2002-07-22 | 2004-01-22 | Josef Willer | Non-Volatile memory cell and fabrication method |
US20040012993A1 (en) * | 2002-07-16 | 2004-01-22 | Kazuhiro Kurihara | System for using a dynamic reference in a double-bit cell memory |
US20040013000A1 (en) * | 2002-07-16 | 2004-01-22 | Fujitsu Limited | Nonvolatile semiconductor memory and method of operating the same |
US20040014290A1 (en) * | 2002-03-14 | 2004-01-22 | Yang Jean Y. | Hard mask process for memory device without bitline shorts |
US6686242B2 (en) * | 2001-03-02 | 2004-02-03 | Infineon Technologies Ag | Method for producing metallic bit lines for memory cell arrays, method for producing memory cell arrays and memory cell array |
US20040021172A1 (en) * | 2001-12-20 | 2004-02-05 | Advanced Micro Devices, Inc. | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same |
US6690602B1 (en) * | 2002-04-08 | 2004-02-10 | Advanced Micro Devices, Inc. | Algorithm dynamic reference programming |
US20040027858A1 (en) * | 2002-08-12 | 2004-02-12 | Fujitsu Limited | Nonvolatile memory having a trap layer |
US6693483B2 (en) * | 2000-04-11 | 2004-02-17 | Infineon Technologies Ag | Charge pump configuration having closed-loop control |
US6859028B2 (en) * | 2002-11-26 | 2005-02-22 | Sige Semiconductor Inc. | Design-for-test modes for a phase locked loop |
US6996692B2 (en) * | 2002-04-17 | 2006-02-07 | Matsushita Electric Industrial Co., Ltd. | Nonvolatile semiconductor memory device and method for providing security for the same |
Family Cites Families (92)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1297899A (en) | 1970-10-02 | 1972-11-29 | ||
US3895360A (en) | 1974-01-29 | 1975-07-15 | Westinghouse Electric Corp | Block oriented random access memory |
US4016588A (en) | 1974-12-27 | 1977-04-05 | Nippon Electric Company, Ltd. | Non-volatile semiconductor memory device |
US4016688A (en) * | 1975-05-27 | 1977-04-12 | Fmc Corporation | Extensible crane boom structure |
US4017888A (en) | 1975-12-31 | 1977-04-12 | International Business Machines Corporation | Non-volatile metal nitride oxide semiconductor device |
US4151021A (en) | 1977-01-26 | 1979-04-24 | Texas Instruments Incorporated | Method of making a high density floating gate electrically programmable ROM |
US4173791A (en) | 1977-09-16 | 1979-11-06 | Fairchild Camera And Instrument Corporation | Insulated gate field-effect transistor read-only memory array |
US4173766A (en) | 1977-09-16 | 1979-11-06 | Fairchild Camera And Instrument Corporation | Insulated gate field-effect transistor read-only memory cell |
US4360900A (en) | 1978-11-27 | 1982-11-23 | Texas Instruments Incorporated | Non-volatile semiconductor memory elements |
DE2923995C2 (en) | 1979-06-13 | 1985-11-07 | Siemens AG, 1000 Berlin und 8000 München | Process for the production of integrated MOS circuits with MOS transistors and MNOS memory transistors in silicon gate technology |
JPS56501146A (en) | 1979-09-13 | 1981-08-13 | ||
DE2947350A1 (en) | 1979-11-23 | 1981-05-27 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING MNOS STORAGE TRANSISTORS WITH A VERY SHORT CHANNEL LENGTH IN SILICON GATE TECHNOLOGY |
JPS56120166A (en) | 1980-02-27 | 1981-09-21 | Hitachi Ltd | Semiconductor ic device and manufacture thereof |
US4380057A (en) | 1980-10-27 | 1983-04-12 | International Business Machines Corporation | Electrically alterable double dense memory |
US4521796A (en) | 1980-12-11 | 1985-06-04 | General Instrument Corporation | Memory implant profile for improved channel shielding in electrically alterable read only memory semiconductor device |
US4527257A (en) | 1982-08-25 | 1985-07-02 | Westinghouse Electric Corp. | Common memory gate non-volatile transistor memory |
JPS6021531A (en) * | 1983-07-15 | 1985-02-02 | Hitachi Micro Comput Eng Ltd | Nonvolatile semiconductor memory |
US4769340A (en) | 1983-11-28 | 1988-09-06 | Exel Microelectronics, Inc. | Method for making electrically programmable memory device by doping the floating gate by implant |
JPS60182174A (en) | 1984-02-28 | 1985-09-17 | Nec Corp | Non-volatile semiconductor memory |
GB2157489A (en) | 1984-03-23 | 1985-10-23 | Hitachi Ltd | A semiconductor integrated circuit memory device |
US4665426A (en) * | 1985-02-01 | 1987-05-12 | Advanced Micro Devices, Inc. | EPROM with ultraviolet radiation transparent silicon nitride passivation layer |
US4667217A (en) | 1985-04-19 | 1987-05-19 | Ncr Corporation | Two bit vertically/horizontally integrated memory cell |
US4742491A (en) | 1985-09-26 | 1988-05-03 | Advanced Micro Devices, Inc. | Memory cell having hot-hole injection erase mode |
JPH0828431B2 (en) | 1986-04-22 | 1996-03-21 | 日本電気株式会社 | Semiconductor memory device |
US4758869A (en) * | 1986-08-29 | 1988-07-19 | Waferscale Integration, Inc. | Nonvolatile floating gate transistor structure |
US5168334A (en) | 1987-07-31 | 1992-12-01 | Texas Instruments, Incorporated | Non-volatile semiconductor memory |
US4780424A (en) | 1987-09-28 | 1988-10-25 | Intel Corporation | Process for fabricating electrically alterable floating gate memory devices |
US4870470A (en) | 1987-10-16 | 1989-09-26 | International Business Machines Corporation | Non-volatile memory cell having Si rich silicon nitride charge trapping layer |
JPH07120720B2 (en) | 1987-12-17 | 1995-12-20 | 三菱電機株式会社 | Nonvolatile semiconductor memory device |
US5159570A (en) | 1987-12-22 | 1992-10-27 | Texas Instruments Incorporated | Four memory state EEPROM |
US5268870A (en) | 1988-06-08 | 1993-12-07 | Eliyahou Harari | Flash EEPROM system and intelligent programming and erasing methods therefor |
US4941028A (en) | 1988-08-10 | 1990-07-10 | Actel Corporation | Structure for protecting thin dielectrics during processing |
US5120672A (en) * | 1989-02-22 | 1992-06-09 | Texas Instruments Incorporated | Fabricating a single level merged EEPROM cell having an ONO memory stack substantially spaced from the source region |
US5104819A (en) | 1989-08-07 | 1992-04-14 | Intel Corporation | Fabrication of interpoly dielctric for EPROM-related technologies |
US5075245A (en) | 1990-08-03 | 1991-12-24 | Intel Corporation | Method for improving erase characteristics of buried bit line flash EPROM devices without using sacrificial oxide growth and removal steps |
JPH0725489Y2 (en) * | 1990-11-24 | 1995-06-07 | 株式会社堀場製作所 | Pinch valve |
JP2612969B2 (en) | 1991-02-08 | 1997-05-21 | シャープ株式会社 | Method for manufacturing semiconductor device |
US5424567A (en) | 1991-05-15 | 1995-06-13 | North American Philips Corporation | Protected programmable transistor with reduced parasitic capacitances and method of fabrication |
GB9111947D0 (en) * | 1991-06-04 | 1991-07-24 | Telsis Limited | Apparatus for voice services equipment |
JP3109537B2 (en) | 1991-07-12 | 2000-11-20 | 日本電気株式会社 | Read-only semiconductor memory device |
JP2965415B2 (en) | 1991-08-27 | 1999-10-18 | 松下電器産業株式会社 | Semiconductor storage device |
EP0740854B1 (en) | 1991-08-29 | 2003-04-23 | Hyundai Electronics Industries Co., Ltd. | A self-aligned dual-bit split gate (dsg) flash eeprom cell |
US5305262A (en) | 1991-09-11 | 1994-04-19 | Kawasaki Steel Corporation | Semiconductor integrated circuit |
US5175120A (en) | 1991-10-11 | 1992-12-29 | Micron Technology, Inc. | Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors |
JPH05110114A (en) | 1991-10-17 | 1993-04-30 | Rohm Co Ltd | Nonvolatile semiconductor memory device |
JP3358663B2 (en) | 1991-10-25 | 2002-12-24 | ローム株式会社 | Semiconductor storage device and storage information reading method thereof |
US5338954A (en) | 1991-10-31 | 1994-08-16 | Rohm Co., Ltd. | Semiconductor memory device having an insulating film and a trap film joined in a channel region |
JPH05129284A (en) * | 1991-11-06 | 1993-05-25 | Sony Corp | Method of setting condition of plasma sin forming film and manufacture of semiconductor device |
US5293328A (en) | 1992-01-15 | 1994-03-08 | National Semiconductor Corporation | Electrically reprogrammable EPROM cell with merged transistor and optiumum area |
US5654568A (en) | 1992-01-17 | 1997-08-05 | Rohm Co., Ltd. | Semiconductor device including nonvolatile memories |
US5324675A (en) | 1992-03-31 | 1994-06-28 | Kawasaki Steel Corporation | Method of producing semiconductor devices of a MONOS type |
US5496753A (en) | 1992-05-29 | 1996-03-05 | Citizen Watch, Co., Ltd. | Method of fabricating a semiconductor nonvolatile storage device |
GB9217743D0 (en) | 1992-08-19 | 1992-09-30 | Philips Electronics Uk Ltd | A semiconductor memory device |
US5412238A (en) | 1992-09-08 | 1995-05-02 | National Semiconductor Corporation | Source-coupling, split-gate, virtual ground flash EEPROM array |
US5319593A (en) | 1992-12-21 | 1994-06-07 | National Semiconductor Corp. | Memory array with field oxide islands eliminated and method |
US5436481A (en) | 1993-01-21 | 1995-07-25 | Nippon Steel Corporation | MOS-type semiconductor device and method of making the same |
US5350710A (en) | 1993-06-24 | 1994-09-27 | United Microelectronics Corporation | Device for preventing antenna effect on circuit |
US5477499A (en) | 1993-10-13 | 1995-12-19 | Advanced Micro Devices, Inc. | Memory architecture for a three volt flash EEPROM |
US5983412A (en) * | 1993-11-29 | 1999-11-16 | Lordahl; Var E. | Toilet tank ball flapper and plastic chain assembly formed as a unitary structures |
JPH07193151A (en) | 1993-12-27 | 1995-07-28 | Toshiba Corp | Non-volatile semiconductor storage and its storage method |
US5418176A (en) | 1994-02-17 | 1995-05-23 | United Microelectronics Corporation | Process for producing memory devices having narrow buried N+ lines |
US5467308A (en) | 1994-04-05 | 1995-11-14 | Motorola Inc. | Cross-point eeprom memory array |
US5553081A (en) * | 1994-04-08 | 1996-09-03 | Echelon Corporation | Apparatus and method for detecting a signal in a communications system |
JP3725911B2 (en) | 1994-06-02 | 2005-12-14 | 株式会社ルネサステクノロジ | Semiconductor device |
JPH08181284A (en) | 1994-09-13 | 1996-07-12 | Hewlett Packard Co <Hp> | Protective element and manufacture thereof |
DE4434725C1 (en) | 1994-09-28 | 1996-05-30 | Siemens Ag | Fixed value memory cell arrangement and method for the production thereof |
US5619052A (en) | 1994-09-29 | 1997-04-08 | Macronix International Co., Ltd. | Interpoly dielectric structure in EEPROM device |
US5523251A (en) | 1994-10-05 | 1996-06-04 | United Microelectronics Corp. | Method for fabricating a self aligned mask ROM |
JP3670321B2 (en) * | 1994-10-18 | 2005-07-13 | 住友化学株式会社 | Crosshead die and method for producing long fiber reinforced resin structure |
DE19504398A1 (en) * | 1995-02-10 | 1996-08-14 | Beiersdorf Ag | Tocopherylglycoside, their preparation and their use as surfactants, as antioxidants and as a cell aging preventive agent in cosmetic or pharmaceutical preparations |
DE19505293A1 (en) | 1995-02-16 | 1996-08-22 | Siemens Ag | Multi-value read-only memory cell with improved signal-to-noise ratio |
US5801076A (en) | 1995-02-21 | 1998-09-01 | Advanced Micro Devices, Inc. | Method of making non-volatile memory device having a floating gate with enhanced charge retention |
US5518942A (en) | 1995-02-22 | 1996-05-21 | Alliance Semiconductor Corporation | Method of making flash EPROM cell having improved erase characteristics by using a tilt angle implant |
KR100187656B1 (en) | 1995-05-16 | 1999-06-01 | 김주용 | Method for manufacturing a flash eeprom and the programming method |
US5656513A (en) | 1995-06-07 | 1997-08-12 | Advanced Micro Devices, Inc. | Nonvolatile memory cell formed using self aligned source implant |
DE69528971D1 (en) | 1995-06-30 | 2003-01-09 | St Microelectronics Srl | Method of manufacturing a circuit containing non-volatile memory cells and edge transistors of at least two different types, and corresponding IC |
US6034896A (en) | 1995-07-03 | 2000-03-07 | The University Of Toronto, Innovations Foundation | Method of fabricating a fast programmable flash E2 PROM cell |
KR970008496A (en) | 1995-07-04 | 1997-02-24 | 모리시다 요이치 | MIS semiconductor device, manufacturing method thereof, and diagnostic method thereof |
JP2982670B2 (en) | 1995-12-12 | 1999-11-29 | 日本電気株式会社 | Nonvolatile semiconductor storage device and storage method |
US5847441A (en) | 1996-05-10 | 1998-12-08 | Micron Technology, Inc. | Semiconductor junction antifuse circuit |
US6156149A (en) * | 1997-05-07 | 2000-12-05 | Applied Materials, Inc. | In situ deposition of a dielectric oxide layer and anti-reflective coating |
US5793079A (en) | 1996-07-22 | 1998-08-11 | Catalyst Semiconductor, Inc. | Single transistor non-volatile electrically alterable semiconductor memory device |
US5768192A (en) | 1996-07-23 | 1998-06-16 | Saifun Semiconductors, Ltd. | Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping |
KR100232678B1 (en) * | 1996-12-18 | 1999-12-01 | 구본준 | A structure and a method of ridged bump |
TW347581B (en) | 1997-02-05 | 1998-12-11 | United Microelectronics Corp | Process for fabricating read-only memory cells |
US6103572A (en) * | 1997-02-07 | 2000-08-15 | Citizen Watch Co., Ltd. | Method of fabricating a semiconductor nonvolatile storage device |
US6297096B1 (en) | 1997-06-11 | 2001-10-02 | Saifun Semiconductors Ltd. | NROM fabrication method |
US5963412A (en) | 1997-11-13 | 1999-10-05 | Advanced Micro Devices, Inc. | Process induced charging damage control device |
US6063666A (en) | 1998-06-16 | 2000-05-16 | Advanced Micro Devices, Inc. | RTCVD oxide and N2 O anneal for top oxide of ONO film |
US6034403A (en) | 1998-06-25 | 2000-03-07 | Acer Semiconductor Manufacturing, Inc. | High density flat cell mask ROM |
US5991202A (en) | 1998-09-24 | 1999-11-23 | Advanced Micro Devices, Inc. | Method for reducing program disturb during self-boosting in a NAND flash memory |
JP2000332241A (en) * | 1999-05-20 | 2000-11-30 | Nec Corp | Manufacture of semiconductor device |
-
2001
- 2001-11-19 US US09/988,122 patent/US7098107B2/en not_active Expired - Lifetime
-
2002
- 2002-07-08 US US10/189,533 patent/US6828625B2/en not_active Expired - Lifetime
- 2002-11-18 IL IL15291302A patent/IL152913A0/en not_active IP Right Cessation
- 2002-11-19 AU AU2002353459A patent/AU2002353459A1/en not_active Abandoned
- 2002-11-19 WO PCT/IL2002/000922 patent/WO2003044856A1/en not_active Application Discontinuation
- 2002-11-19 EP EP02257954A patent/EP1313138A3/en not_active Withdrawn
- 2002-11-19 JP JP2002334684A patent/JP2003243545A/en active Pending
-
2006
- 2006-07-20 US US11/490,483 patent/US20070032016A1/en not_active Abandoned
Patent Citations (99)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2004A (en) * | 1841-03-12 | Improvement in the manner of constructing and propelling steam-vessels | ||
US596929A (en) * | 1898-01-04 | James godfrey wilson | ||
US4145703A (en) * | 1977-04-15 | 1979-03-20 | Supertex, Inc. | High power MOS device and fabrication method therefor |
US4373248A (en) * | 1978-07-12 | 1983-02-15 | Texas Instruments Incorporated | Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like |
US4257832A (en) * | 1978-07-24 | 1981-03-24 | Siemens Aktiengesellschaft | Process for producing an integrated multi-layer insulator memory cell |
US4247861A (en) * | 1979-03-09 | 1981-01-27 | Rca Corporation | High performance electrically alterable read-only memory (EAROM) |
US4507673A (en) * | 1979-10-13 | 1985-03-26 | Tokyo Shibaura Denki Kabushiki Kaisha | Semiconductor memory device |
US4435786A (en) * | 1981-11-23 | 1984-03-06 | Fairchild Camera And Instrument Corporation | Self-refreshing memory cell |
US4494016A (en) * | 1982-07-26 | 1985-01-15 | Sperry Corporation | High performance MESFET transistor for VLSI implementation |
US4725984A (en) * | 1984-02-21 | 1988-02-16 | Seeq Technology, Inc. | CMOS eprom sense amplifier |
US4733105A (en) * | 1985-09-04 | 1988-03-22 | Oki Electric Industry Co., Ltd. | CMOS output circuit |
US5293563A (en) * | 1988-12-29 | 1994-03-08 | Sharp Kabushiki Kaisha | Multi-level memory cell with increased read-out margin |
US4992391A (en) * | 1989-11-29 | 1991-02-12 | Advanced Micro Devices, Inc. | Process for fabricating a control gate for a floating gate FET |
US5095968A (en) * | 1990-04-09 | 1992-03-17 | Didion Manufacturing Co. | Rotary media drum with cooling component |
US5394355A (en) * | 1990-08-28 | 1995-02-28 | Mitsubishi Denki Kabushiki Kaisha | Read only memory for storing multi-data |
US5276646A (en) * | 1990-09-25 | 1994-01-04 | Samsung Electronics Co., Ltd. | High voltage generating circuit for a semiconductor memory circuit |
US5081371A (en) * | 1990-11-07 | 1992-01-14 | U.S. Philips Corp. | Integrated charge pump circuit with back bias voltage reduction |
US5862076A (en) * | 1990-11-13 | 1999-01-19 | Waferscale Integration, Inc. | Fast EPROM array |
US5086325A (en) * | 1990-11-21 | 1992-02-04 | Atmel Corporation | Narrow width EEPROM with single diffusion electrode formation |
US5381374A (en) * | 1992-01-09 | 1995-01-10 | Kabushiki Kaisha Toshiba | Memory cell data output circuit having improved access time |
US5295092A (en) * | 1992-01-21 | 1994-03-15 | Sharp Kabushiki Kaisha | Semiconductor read only memory |
US5399891A (en) * | 1992-01-22 | 1995-03-21 | Macronix International Co., Ltd. | Floating gate or flash EPROM transistor array having contactless source and drain diffusions |
US5295108A (en) * | 1992-04-08 | 1994-03-15 | Nec Corporation | Electrically erasable and programmable read only memory device with simple controller for selecting operational sequences after confirmation |
US5289412A (en) * | 1992-06-19 | 1994-02-22 | Intel Corporation | High-speed bias-stabilized current-mirror referencing circuit for non-volatile memories |
US5280420A (en) * | 1992-10-02 | 1994-01-18 | National Semiconductor Corporation | Charge pump which operates on a low voltage power supply |
US5596527A (en) * | 1992-12-07 | 1997-01-21 | Nippon Steel Corporation | Electrically alterable n-bit per cell non-volatile memory with reference cells |
US5495440A (en) * | 1993-01-19 | 1996-02-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having hierarchical bit line structure |
US5393701A (en) * | 1993-04-08 | 1995-02-28 | United Microelectronics Corporation | Layout design to eliminate process antenna effect |
US5592417A (en) * | 1994-01-31 | 1997-01-07 | Sgs-Thomson Microelectronics S.A. | Non-volatile programmable bistable multivibrator, programmable by the source, for memory redundancy circuit |
US5606523A (en) * | 1994-01-31 | 1997-02-25 | Sgs-Thomson Microelectronics S.A. | Non-volatile programmable bistable multivibrator in predefined initial state for memory redundancy circuit |
US5600586A (en) * | 1994-05-26 | 1997-02-04 | Aplus Integrated Circuits, Inc. | Flat-cell ROM and decoder |
US5717581A (en) * | 1994-06-30 | 1998-02-10 | Sgs-Thomson Microelectronics, Inc. | Charge pump circuit with feedback control |
US5712814A (en) * | 1994-07-18 | 1998-01-27 | Sgs-Thomson Microelectronics S.R.L. | Nonvolatile memory cell and a method for forming the same |
US5870334A (en) * | 1994-09-17 | 1999-02-09 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US5599727A (en) * | 1994-12-15 | 1997-02-04 | Sharp Kabushiki Kaisha | Method for producing a floating gate memory device including implanting ions through an oxidized portion of the silicon film from which the floating gate is formed |
US5721781A (en) * | 1995-09-13 | 1998-02-24 | Microsoft Corporation | Authentication system and method for smart card transactions |
US5708608A (en) * | 1995-12-28 | 1998-01-13 | Hyundai Electronics Industries Cp., Ltd. | High-speed and low-noise output buffer |
US5712815A (en) * | 1996-04-22 | 1998-01-27 | Advanced Micro Devices, Inc. | Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells |
US5604804A (en) * | 1996-04-23 | 1997-02-18 | Micali; Silvio | Method for certifying public keys in a digital signature scheme |
US5715193A (en) * | 1996-05-23 | 1998-02-03 | Micron Quantum Devices, Inc. | Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks |
US5875128A (en) * | 1996-06-28 | 1999-02-23 | Nec Corporation | Semiconductor memory |
US20020004878A1 (en) * | 1996-08-08 | 2002-01-10 | Robert Norman | System and method which compares data preread from memory cells to data to be written to the cells |
US5717635A (en) * | 1996-08-27 | 1998-02-10 | International Business Machines Corporation | High density EEPROM for solid state file |
US6192445B1 (en) * | 1996-09-24 | 2001-02-20 | Altera Corporation | System and method for programming EPROM cells using shorter duration pulse(s) in repeating the programming process of a particular cell |
US5861771A (en) * | 1996-10-28 | 1999-01-19 | Fujitsu Limited | Regulator circuit and semiconductor integrated circuit device having the same |
US5717632A (en) * | 1996-11-27 | 1998-02-10 | Advanced Micro Devices, Inc. | Apparatus and method for multiple-level storage in non-volatile memories |
US5864164A (en) * | 1996-12-09 | 1999-01-26 | United Microelectronics Corp. | Multi-stage ROM structure and method for fabricating the same |
US5872848A (en) * | 1997-02-18 | 1999-02-16 | Arcanvs | Method and apparatus for witnessed authentication of electronic documents |
US5870335A (en) * | 1997-03-06 | 1999-02-09 | Agate Semiconductor, Inc. | Precision programming of nonvolatile memory cells |
US6028324A (en) * | 1997-03-07 | 2000-02-22 | Taiwan Semiconductor Manufacturing Company | Test structures for monitoring gate oxide defect densities and the plasma antenna effect |
US6190966B1 (en) * | 1997-03-25 | 2001-02-20 | Vantis Corporation | Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration |
US6018186A (en) * | 1997-04-15 | 2000-01-25 | United Microelectronics Corp. | Three-dimensional, deep-trench, high-density read-only memory (ROM) and its manufacturing method |
US6335990B1 (en) * | 1997-07-03 | 2002-01-01 | Cisco Technology, Inc. | System and method for spatial temporal-filtering for improving compressed digital video |
US6011725A (en) * | 1997-08-01 | 2000-01-04 | Saifun Semiconductors, Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US5867429A (en) * | 1997-11-19 | 1999-02-02 | Sandisk Corporation | High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates |
US6335874B1 (en) * | 1997-12-12 | 2002-01-01 | Saifun Semiconductors Ltd. | Symmetric segmented memory array architecture |
US6020241A (en) * | 1997-12-22 | 2000-02-01 | Taiwan Semiconductor Manufacturing Company | Post metal code engineering for a ROM |
US6195196B1 (en) * | 1998-03-13 | 2001-02-27 | Fuji Photo Film Co., Ltd. | Array-type exposing device and flat type display incorporating light modulator and driving method thereof |
US6344959B1 (en) * | 1998-05-01 | 2002-02-05 | Unitrode Corporation | Method for sensing the output voltage of a charge pump circuit without applying a load to the output stage |
US6030871A (en) * | 1998-05-05 | 2000-02-29 | Saifun Semiconductors Ltd. | Process for producing two bit ROM cell utilizing angled implant |
US6188211B1 (en) * | 1998-05-13 | 2001-02-13 | Texas Instruments Incorporated | Current-efficient low-drop-out voltage regulator with improved load regulation and frequency response |
US6348711B1 (en) * | 1998-05-20 | 2002-02-19 | Saifun Semiconductors Ltd. | NROM cell with self-aligned programming and erasure areas |
US6169691B1 (en) * | 1998-09-15 | 2001-01-02 | Stmicroelectronics S.R.L. | Method for maintaining the memory content of non-volatile memory cells |
US6519180B2 (en) * | 1999-01-14 | 2003-02-11 | Silicon Storage Technology, Inc. | Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system |
US6181597B1 (en) * | 1999-02-04 | 2001-01-30 | Tower Semiconductor Ltd. | EEPROM array using 2-bit non-volatile memory cells with serial read operations |
US6346442B1 (en) * | 1999-02-04 | 2002-02-12 | Tower Semiconductor Ltd. | Methods for fabricating a semiconductor chip having CMOS devices and a fieldless array |
US6504755B1 (en) * | 1999-05-14 | 2003-01-07 | Hitachi, Ltd. | Semiconductor memory device |
US6337502B1 (en) * | 1999-06-18 | 2002-01-08 | Saifun Semicinductors Ltd. | Method and circuit for minimizing the charging effect during manufacture of semiconductor devices |
US6175519B1 (en) * | 1999-07-22 | 2001-01-16 | Macronix International Co., Ltd. | Virtual ground EPROM structure |
US6181605B1 (en) * | 1999-10-06 | 2001-01-30 | Advanced Micro Devices, Inc. | Global erase/program verification apparatus and method |
US6175523B1 (en) * | 1999-10-25 | 2001-01-16 | Advanced Micro Devices, Inc | Precharging mechanism and method for NAND-based flash memory devices |
US6339556B1 (en) * | 1999-11-15 | 2002-01-15 | Nec Corporation | Semiconductor memory device |
US6185143B1 (en) * | 2000-02-04 | 2001-02-06 | Hewlett-Packard Company | Magnetic random access memory (MRAM) device including differential sense amplifiers |
US6343033B1 (en) * | 2000-02-25 | 2002-01-29 | Advanced Micro Devices, Inc. | Variable pulse width memory programming |
US6693483B2 (en) * | 2000-04-11 | 2004-02-17 | Infineon Technologies Ag | Charge pump configuration having closed-loop control |
US20020004921A1 (en) * | 2000-07-10 | 2002-01-10 | Hitachi, Ltd. | Method of deciding error rate and semiconductor integrated circuit device |
US6519182B1 (en) * | 2000-07-10 | 2003-02-11 | Advanced Micro Devices, Inc. | Using hot carrier injection to control over-programming in a non-volatile memory cell having an oxide-nitride-oxide (ONO) structure |
US6348380B1 (en) * | 2000-08-25 | 2002-02-19 | Micron Technology, Inc. | Use of dilute steam ambient for improvement of flash devices |
US6348381B1 (en) * | 2001-02-21 | 2002-02-19 | Macronix International Co., Ltd. | Method for forming a nonvolatile memory with optimum bias condition |
US6686242B2 (en) * | 2001-03-02 | 2004-02-03 | Infineon Technologies Ag | Method for producing metallic bit lines for memory cell arrays, method for producing memory cell arrays and memory cell array |
US6351415B1 (en) * | 2001-03-28 | 2002-02-26 | Tower Semiconductor Ltd. | Symmetrical non-volatile memory array architecture without neighbor effect |
US6677805B2 (en) * | 2001-04-05 | 2004-01-13 | Saifun Semiconductors Ltd. | Charge pump stage with body effect minimization |
US20030021155A1 (en) * | 2001-04-09 | 2003-01-30 | Yachareni Santosh K. | Soft program and soft program verify of the core cells in flash memory array |
US6522585B2 (en) * | 2001-05-25 | 2003-02-18 | Sandisk Corporation | Dual-cell soft programming for virtual-ground memory arrays |
US6512701B1 (en) * | 2001-06-21 | 2003-01-28 | Advanced Micro Devices, Inc. | Erase method for dual bit virtual ground flash |
US20030001213A1 (en) * | 2001-06-29 | 2003-01-02 | Chinatech Corporation | High density read only memory and fabrication method thereof |
US6525969B1 (en) * | 2001-08-10 | 2003-02-25 | Advanced Micro Devices, Inc. | Decoder apparatus and methods for pre-charging bit lines |
US6680509B1 (en) * | 2001-09-28 | 2004-01-20 | Advanced Micro Devices, Inc. | Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory |
US6510082B1 (en) * | 2001-10-23 | 2003-01-21 | Advanced Micro Devices, Inc. | Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold |
US20040021172A1 (en) * | 2001-12-20 | 2004-02-05 | Advanced Micro Devices, Inc. | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same |
US6674138B1 (en) * | 2001-12-31 | 2004-01-06 | Advanced Micro Devices, Inc. | Use of high-k dielectric materials in modified ONO structure for semiconductor devices |
US20040014290A1 (en) * | 2002-03-14 | 2004-01-22 | Yang Jean Y. | Hard mask process for memory device without bitline shorts |
US6690602B1 (en) * | 2002-04-08 | 2004-02-10 | Advanced Micro Devices, Inc. | Algorithm dynamic reference programming |
US6996692B2 (en) * | 2002-04-17 | 2006-02-07 | Matsushita Electric Industrial Co., Ltd. | Nonvolatile semiconductor memory device and method for providing security for the same |
US20040013000A1 (en) * | 2002-07-16 | 2004-01-22 | Fujitsu Limited | Nonvolatile semiconductor memory and method of operating the same |
US20040012993A1 (en) * | 2002-07-16 | 2004-01-22 | Kazuhiro Kurihara | System for using a dynamic reference in a double-bit cell memory |
US20040014280A1 (en) * | 2002-07-22 | 2004-01-22 | Josef Willer | Non-Volatile memory cell and fabrication method |
US20040027858A1 (en) * | 2002-08-12 | 2004-02-12 | Fujitsu Limited | Nonvolatile memory having a trap layer |
US6859028B2 (en) * | 2002-11-26 | 2005-02-22 | Sige Semiconductor Inc. | Design-for-test modes for a phase locked loop |
Also Published As
Publication number | Publication date |
---|---|
JP2003243545A (en) | 2003-08-29 |
IL152913A0 (en) | 2003-06-24 |
WO2003044856A1 (en) | 2003-05-30 |
US20030096476A1 (en) | 2003-05-22 |
EP1313138A2 (en) | 2003-05-21 |
AU2002353459A1 (en) | 2003-06-10 |
US6828625B2 (en) | 2004-12-07 |
US7098107B2 (en) | 2006-08-29 |
EP1313138A3 (en) | 2007-12-05 |
US20030096475A1 (en) | 2003-05-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20070032016A1 (en) | Protective layer in memory device and method therefor | |
KR101071965B1 (en) | - uv-blocking layer for reducing uv-induced charging of sonos dual-bit flash memory devices in beol processing | |
US8541277B2 (en) | Non-volatile memory device and method for fabricating the same | |
US4833514A (en) | Planar FAMOS transistor with sealed floating gate and DCS+N2 O oxide | |
US7015098B2 (en) | Methods and structure for an improved floating gate memory cell | |
US5953254A (en) | Serial flash memory | |
EP0780902B1 (en) | Nonvolatile semiconductor memory and method for fabricating the same | |
US6380033B1 (en) | Process to improve read disturb for NAND flash memory devices | |
KR100418091B1 (en) | Method of manufacturing semiconductor device | |
US7439575B2 (en) | Protection against in-process charging in silicon-oxide-nitride-oxide-silicon (SONOS) memories | |
US6818511B2 (en) | Non-volatile memory device to protect floating gate from charge loss and method for fabricating the same | |
US5933729A (en) | Reduction of ONO fence during self-aligned etch to eliminate poly stringers | |
US6448126B1 (en) | Method of forming an embedded memory | |
US6465303B1 (en) | Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory | |
US20070008782A1 (en) | Method for programming a memory device | |
KR100643468B1 (en) | Nonvolatile memory devices having insulating spacer and manufacturing method thereof | |
US6894342B1 (en) | Structure and method for preventing UV radiation damage in a memory cell and improving contact CD control | |
US6833581B1 (en) | Structure and method for preventing process-induced UV radiation damage in a memory cell | |
US6794701B2 (en) | Non-volatile memory | |
US6284602B1 (en) | Process to reduce post cycling program VT dispersion for NAND flash memory devices | |
JP3947041B2 (en) | Semiconductor device and manufacturing method thereof | |
US20090065841A1 (en) | SILICON OXY-NITRIDE (SiON) LINER, SUCH AS OPTIONALLY FOR NON-VOLATILE MEMORY CELLS | |
US6458659B1 (en) | Method of fabricating non-volatile memory devices integrated in a semiconductor substrate and organized into memory matrices | |
KR20010045232A (en) | Method for manufacturing flash memory cell and the same | |
US6429093B1 (en) | Sidewall process for forming a low resistance source line |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SAIFUN SEMICONDUCTORS LTD, ISRAEL Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BLOOM, ILAN;EITAN, BOAZ;REEL/FRAME:018163/0401 Effective date: 20060713 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |