US20060261397A1 - Lanthanide oxide/hafnium oxide dielectric layers - Google Patents
Lanthanide oxide/hafnium oxide dielectric layers Download PDFInfo
- Publication number
- US20060261397A1 US20060261397A1 US11/493,074 US49307406A US2006261397A1 US 20060261397 A1 US20060261397 A1 US 20060261397A1 US 49307406 A US49307406 A US 49307406A US 2006261397 A1 US2006261397 A1 US 2006261397A1
- Authority
- US
- United States
- Prior art keywords
- layer
- hafnium oxide
- lanthanide
- oxide
- lanthanide oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 229910000311 lanthanide oxide Inorganic materials 0.000 title claims abstract description 192
- 229910000449 hafnium oxide Inorganic materials 0.000 title claims abstract description 187
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims abstract description 181
- 239000000758 substrate Substances 0.000 claims description 110
- 238000010894 electron beam technology Methods 0.000 claims description 52
- 230000015654 memory Effects 0.000 claims description 20
- 239000003990 capacitor Substances 0.000 claims description 18
- 210000000746 body region Anatomy 0.000 claims description 16
- NLQFUUYNQFMIJW-UHFFFAOYSA-N dysprosium(III) oxide Inorganic materials O=[Dy]O[Dy]=O NLQFUUYNQFMIJW-UHFFFAOYSA-N 0.000 claims description 15
- CMIHHWBVHJVIGI-UHFFFAOYSA-N gadolinium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Gd+3].[Gd+3] CMIHHWBVHJVIGI-UHFFFAOYSA-N 0.000 claims description 15
- PLDDOISOJJCEMH-UHFFFAOYSA-N neodymium oxide Inorganic materials [O-2].[O-2].[O-2].[Nd+3].[Nd+3] PLDDOISOJJCEMH-UHFFFAOYSA-N 0.000 claims description 15
- FKTOIHSPIPYAPE-UHFFFAOYSA-N samarium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Sm+3].[Sm+3] FKTOIHSPIPYAPE-UHFFFAOYSA-N 0.000 claims description 15
- 229910052747 lanthanoid Inorganic materials 0.000 claims description 4
- 150000002602 lanthanoids Chemical class 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 425
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 102
- 239000002243 precursor Substances 0.000 description 97
- 239000007789 gas Substances 0.000 description 76
- 238000000231 atomic layer deposition Methods 0.000 description 69
- 238000000034 method Methods 0.000 description 59
- 238000006243 chemical reaction Methods 0.000 description 50
- 239000000377 silicon dioxide Substances 0.000 description 48
- 229910052681 coesite Inorganic materials 0.000 description 40
- 229910052906 cristobalite Inorganic materials 0.000 description 40
- 229910052682 stishovite Inorganic materials 0.000 description 40
- 229910052905 tridymite Inorganic materials 0.000 description 40
- 238000010926 purge Methods 0.000 description 35
- 239000000463 material Substances 0.000 description 33
- 230000008569 process Effects 0.000 description 31
- 238000012545 processing Methods 0.000 description 27
- 229910052751 metal Inorganic materials 0.000 description 22
- 239000002184 metal Substances 0.000 description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 20
- 229910052710 silicon Inorganic materials 0.000 description 20
- 239000010703 silicon Substances 0.000 description 20
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 19
- 238000001704 evaporation Methods 0.000 description 18
- 239000001301 oxygen Substances 0.000 description 18
- 229910052760 oxygen Inorganic materials 0.000 description 18
- 239000004065 semiconductor Substances 0.000 description 18
- 238000009826 distribution Methods 0.000 description 17
- 230000008020 evaporation Effects 0.000 description 17
- 230000015572 biosynthetic process Effects 0.000 description 15
- 239000003989 dielectric material Substances 0.000 description 14
- 238000005566 electron beam evaporation Methods 0.000 description 14
- 235000021251 pulses Nutrition 0.000 description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 11
- 239000010408 film Substances 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 11
- 239000000376 reactant Substances 0.000 description 9
- 235000012239 silicon dioxide Nutrition 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 235000012431 wafers Nutrition 0.000 description 8
- 239000006227 byproduct Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 7
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 7
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 7
- 239000000203 mixture Substances 0.000 description 6
- 239000007787 solid Substances 0.000 description 6
- 239000013077 target material Substances 0.000 description 6
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 229910001882 dioxygen Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 229910052735 hafnium Inorganic materials 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 239000002245 particle Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 238000004377 microelectronic Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000002829 reductive effect Effects 0.000 description 4
- 238000012163 sequencing technique Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000005476 size effect Effects 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- -1 A2O3 Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 3
- 230000007613 environmental effect Effects 0.000 description 3
- 238000007667 floating Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000000670 limiting effect Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical group [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 229910021486 amorphous silicon dioxide Inorganic materials 0.000 description 2
- 238000003877 atomic layer epitaxy Methods 0.000 description 2
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000012705 liquid precursor Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910003865 HfCl4 Inorganic materials 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical group [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 235000010627 Phaseolus vulgaris Nutrition 0.000 description 1
- 244000046052 Phaseolus vulgaris Species 0.000 description 1
- 229910002637 Pr6O11 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910004481 Ta2O3 Inorganic materials 0.000 description 1
- 239000005083 Zinc sulfide Substances 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910052784 alkaline earth metal Inorganic materials 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000012612 commercial material Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000010574 gas phase reaction Methods 0.000 description 1
- PDPJQWYGJJBYLF-UHFFFAOYSA-J hafnium tetrachloride Chemical compound Cl[Hf](Cl)(Cl)Cl PDPJQWYGJJBYLF-UHFFFAOYSA-J 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000011344 liquid material Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 229910021426 porous silicon Inorganic materials 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000012713 reactive precursor Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000011343 solid material Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000000153 supplemental effect Effects 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 229910052984 zinc sulfide Inorganic materials 0.000 description 1
- DRDVZXDWVBGGMH-UHFFFAOYSA-N zinc;sulfide Chemical compound [S-2].[Zn+2] DRDVZXDWVBGGMH-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/08—Oxides
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/405—Oxides of refractory metals or yttrium
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02192—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02269—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by thermal evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3141—Deposition using atomic layer deposition techniques [ALD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3141—Deposition using atomic layer deposition techniques [ALD]
- H01L21/3142—Deposition using atomic layer deposition techniques [ALD] of nano-laminates, e.g. alternating layers of Al203-Hf02
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31645—Deposition of Hafnium oxides, e.g. HfO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
- H01L29/78657—SOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
Definitions
- This application relates generally to semiconductor devices and device fabrication and, more particularly, to dielectric layers and their method of fabrication.
- the semiconductor device industry has a market driven need to improve speed performance, improve its low static (off-state) power requirements, and adapt to a wide range of power supply and output voltage requirements for its silicon based microelectronic products.
- the ultimate goal is to fabricate increasingly smaller and more reliable integrated circuits (ICs) for use in products such as processor chips, mobile telephones, and memory devices such as dynamic random access memories (DRAMs).
- ICs integrated circuits
- DRAMs dynamic random access memories
- FIG. 1 A common configuration of such a transistor is shown in FIG. 1 . While the following discussion uses FIG. 1 to illustrate a transistor from the prior art, one skilled in the art will recognize that the present invention could be incorporated into the transistor shown in FIG. 1 to form a transistor according to the present invention.
- a transistor 100 is fabricated in a substrate 110 that is typically silicon.
- Transistor 100 has a source region 120 and a drain region 130 .
- a body region 132 is located between source region 120 and drain region 130 , where body region 132 defines a channel of the transistor with a channel length 134 .
- a gate dielectric 140 is located on body region 132 with a gate 150 located over gate dielectric 140 .
- Gate dielectric 140 is typically an oxide, and is commonly referred to as a gate oxide.
- Gate 150 may be fabricated from polycrystalline silicon (polysilicon), or other conducting materials such as metal may be used.
- gate dielectric 140 In fabricating transistors to be smaller in size and reliably operate on lower power supplies, one design criteria is gate dielectric 140 .
- the mainstay for forming the gate dielectric has been silicon dioxide, SiO 2 .
- a thermally grown amorphous SiO 2 layer provides an electrically and thermodynamically stable material, where the interface of the SiO 2 layer with underlying Si provides a high quality interface as well as superior electrical isolation properties.
- increased scaling and other requirements in microelectronic devices have created the need to use other dielectric materials as gate dielectrics.
- FIG. 1 shows a configuration of a transistor having a gate dielectric containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to various embodiments of the present invention.
- FIG. 2A depicts an atomic layer deposition system for processing a layer of hafnium oxide for a dielectric layer containing a hafnium oxide and a lanthanide oxide, according to various embodiments of the present invention.
- FIG. 2B depicts a gas-distribution fixture of an atomic layer deposition system for processing a layer of hafnium oxide for a dielectric layer containing a hafnium oxide and a lanthanide oxide, according to various embodiments of the present invention.
- FIG. 3 depicts an electron beam evaporation system for processing a layer of lanthanide oxide for a dielectric layer containing a hafnium oxide and a lanthanide oxide, according to various embodiments of the present invention.
- FIG. 4 illustrates a flow diagram of elements for an embodiment of a method to process a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to the present invention.
- FIG. 5 illustrates a flow diagram of elements for an embodiment of a method to process a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to the present invention.
- FIG. 6 depicts an embodiment of a dielectric layer including a nanolaminate of a hafnium oxide layer and a lanthanide oxide layer, according to the present invention.
- FIG. 7 shows an embodiment of a configuration of a transistor having a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to the present invention.
- FIG. 8 shows an embodiment of a configuration of a capacitor having a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to the present invention.
- FIG. 9 is a simplified block diagram for an embodiment of a memory device with a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to the present invention.
- FIG. 10 illustrates a block diagram for an embodiment of an electronic system having devices with a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to the present invention.
- wafer and substrate used in the following description include any structure having an exposed surface with which to form an integrated circuit (IC).
- substrate is understood to include semiconductor wafers.
- substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art.
- horizontal as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate.
- vertical refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate.
- a dielectric layer includes a hafnium oxide layer and a lanthanide oxide layer, where the hafnium oxide layer is formed by atomic layer deposition (ALD) and the lanthanide oxide layer is formed by electron beam evaporation.
- the lanthanide oxide can be selected from Pr 2 O 3 , Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .
- a dielectric layer includes a hafnium oxide/lanthanide oxide nanolaminate.
- nanolaminate means a composite film of ultra thin layers of two or more materials in a layered stack, where the layers are alternating layers of materials of the composite film.
- each layer in a nanolaminate has a thickness of an order of magnitude in the nanometer range.
- each individual material layer of the nanolaminate can have a thickness as low as a monolayer of the material.
- a nanolaminate of hafnium oxide and a lanthanide oxide includes at least one thin layer of hafnium oxide, and one thin layer of the lanthanide oxide, which can be written as a nanolaminate of hafnium oxide/lanthanide oxide.
- a hafnium oxide/lanthanide oxide nanolaminate is not limited to alternating one lanthanide layer after a hafnium oxide layer, but can include multiple thin layers of a lanthanide oxide alternating with multiple thin layers of hafnium oxide. Further, the number of thin layers of lanthanide oxide and the number of thin layers of hafnium oxide can vary independently within a nanolaminate structure. Additionally, a hafnium oxide/lanthanide oxide nanolaminate can include layers of different lanthanide oxides, where each layer is independently selected from Pr 2 O 3 , Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .
- a dielectric layer containing alternating layers of a lanthanide oxide and a hafnium oxide has an effective dielectric constant related to the series combination of the layers of lanthanide oxide and hafnium oxide, which depends on the relative thicknesses of the lanthanide oxide layers and the hafnium oxide layers.
- a dielectric containing a hafnium oxide/lanthanide oxide nanolaminate can be engineered to effectively provide a selected dielectric constant.
- a gate dielectric 140 of FIG. 1 when operating in a transistor, has both a physical gate dielectric thickness and an equivalent oxide thickness (t eq ).
- the equivalent oxide thickness quantifies the electrical properties, such as capacitance, of a gate dielectric 140 in terms of a representative physical thickness.
- the equivalent oxide thickness, t eq is defined as the thickness of a theoretical SiO 2 layer that would have the same capacitance density as a given dielectric, ignoring leakage current and reliability considerations.
- a SiO 2 layer of thickness, t, deposited on a Si surface as a gate dielectric will have a t eq larger than its thickness, t.
- This t eq results from the capacitance in the surface channel on which the SiO 2 is deposited due to the formation of a depletion/inversion region.
- This depletion/inversion region may result in t eq being from 3 to 6 Angstroms ( ⁇ ) larger than the SiO 2 thickness, t.
- the physical thickness for a SiO 2 layer used for a gate dielectric would be need to be approximately 4 to 7 ⁇ .
- SiO 2 layer Additional characteristics depend on the gate electrode used in conjunction with the SiO 2 gate dielectric. Using a conventional polysilicon gate results in an additional increase in t eq for the SiO 2 layer. This additional thickness could be eliminated by using a metal gate electrode, though metal gates are not currently used in typical complementary metal-oxide-semiconductor field effect transistor (CMOS) technology. Thus, future devices would be designed towards a physical SiO 2 gate dielectric layer of about 5 ⁇ or less. Such a small thickness for a SiO 2 oxide layer creates additional problems.
- CMOS complementary metal-oxide-semiconductor field effect transistor
- Silicon dioxide is used as a gate dielectric, in part, due to its electrical isolation properties in a SiO 2 —Si based structure. This electrical isolation is due to the relatively large bandgap of SiO 2 (8.9 eV) making it a good insulator from electrical conduction. Signification reductions in its bandgap would eliminate it as a material for a gate dielectric. As the thickness of a SiO 2 layer decreases, the number of atomic layers, or monolayers of the SiO 2 decreases. At a certain thickness, the number of monolayers will be sufficiently small that the SiO 2 layer will not have a complete arrangement of atoms as in a larger or bulk layer.
- a thin SiO 2 layer of only one or two monolayers will not form a full bandgap.
- the lack of a full bandgap in a SiO 2 gate dielectric could cause an effective short between an underlying Si channel and an overlying polysilicon gate.
- This undesirable property sets a limit on the physical thickness to which a SiO 2 layer may be scaled.
- the minimum thickness due to this monolayer effect is thought to be about 7-8 ⁇ . Therefore, for future devices to have a t eq less than about 10 ⁇ , dielectrics other than SiO 2 need to be considered for use as a gate dielectric.
- materials with a dielectric constant greater than that of SiO 2 , 3.9 will have a physical thickness that may be considerably larger than a desired t eq , while providing the desired equivalent oxide thickness.
- an alternate dielectric material with a dielectric constant of 10 could have a thickness of about 25.6 ⁇ to provide a t eq of 10 ⁇ , not including any depletion/inversion layer effects.
- a reduced t eq for transistors may be realized by using dielectric materials with higher dielectric constants than SiO 2 .
- the thinner t eq for lower transistor operating voltages and smaller transistor dimensions may be realized by a significant number of materials, but additional fabricating characteristics makes determining a suitable replacement for SiO 2 difficult.
- the gate dielectric employed will grow on a silicon substrate or silicon layer, which places significant restraints on the substitute dielectric material.
- the dielectric on the silicon layer there exists the possibility that a small layer of SiO 2 could be formed in addition to the desired dielectric.
- the result would effectively be a dielectric layer consisting of two sublayers in parallel with each other and the silicon layer on which the dielectric is formed. In such a case, the resulting capacitance would be that of two dielectrics in series.
- t eq t SiO 2 +( ⁇ ox / ⁇ ) t.
- One of the advantages for using SiO 2 as a gate dielectric has been that the formation of the SiO 2 layer results in an amorphous gate dielectric. Having an amorphous structure for a gate dielectric is advantageous because grain boundaries in polycrystalline gate dielectrics provide high leakage paths. Additionally, grain size and orientation changes throughout a polycrystalline gate dielectric may cause variations in the layer's dielectric constant. Many materials having a high dielectric constant relative to SiO 2 also have a disadvantage of a crystalline form, at least in a bulk configuration. Thus, the best candidates for replacing SiO 2 as a gate dielectric are those with high dielectric constant, a relatively large bandgap, and are able to be fabricated as a thin layer with an amorphous form.
- Materials such as Ta 2 O 3 , TiO 2 , A 2 O 3 , HfO 2 , HfSi x O y , HfSi x O y , and barium strontium titanate (BST) have been proposed as replacements for SiO 2 as gate dielectric materials. Additional materials have been proposed to not only provide a material layer with a dielectric constant greater than silicon dioxide, but also to provide adjustment to the insulating properties of the material. Such materials can be provided as nanolaminates, for example, Ta 2 O 5 /HfO 2 , ZrO 2 /HfO 2 , Ta 2 O 5 /HfO 2 nanolaminates. Providing dielectric layers configured as nanolaminates can provide a dielectric layer with relatively low leakage current properties.
- An embodiment for a method for forming a dielectric layer containing a hafnium oxide and a lanthanide oxide includes forming a layer of the hafnium oxide by atomic layer deposition and forming a layer of the lanthanide oxide by electron beam evaporation. The layer of hafnium oxide is adjacent to and in contact with the layer of lanthanide oxide.
- a dielectric layer includes a hafnium oxide/lanthanide oxide nanolaminate having an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer.
- Dielectric layers containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer have a larger dielectric constant than silicon dioxide. Such dielectric layers provide a significantly thinner equivalent oxide thickness compared with a silicon oxide layer having the same physical thickness. Alternately, such dielectric layers provide a significantly thicker physical thickness than a silicon oxide layer having the same equivalent oxide thickness.
- Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, and methods for forming such structures.
- a dielectric film having an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide allows for the engineering of a dielectric layer with a dielectric constant significantly higher than that of silicon dioxide and a relatively low leakage current characteristic.
- layers of atomic layer deposited HfO 2 in various embodiments provides layers, as compared to ZrO 2 , that have a stronger tendency to form a single phase structure, a higher refractive index when deposited at low temperatures, a larger band gap, higher band offsets on silicon, and better thermal stability against silicide formation.
- amorphous lanthanide oxides provide high oxide capacitance, low leakage current, and high thermal stability.
- particles of the material to be deposited bombard the surface at a high energy. When a particle hits the surface, some particles adhere, and other particles cause damage. High-energy impacts remove body region particles creating pits.
- the surface of such a deposited layer may have a rough contour due to the rough interface at the body region.
- a hafnium oxide layer having a substantially smooth surface relative to other processing techniques is formed on a substrate using atomic layer deposition. Further, the ALD deposited hafnium oxide layer provides a conformal coverage on the substrate surface on which it is deposited. A lanthanide oxide layer is then formed on the hafnium oxide layer, where the lanthanide oxide layer is formed by electron beam evaporation.
- ALD also known as atomic layer epitaxy (ALE)
- ALE atomic layer epitaxy
- CVD chemical vapor deposition
- ALD gaseous precursors are introduced one at a time to the substrate surface mounted within a reaction chamber (or reactor). This introduction of the gaseous precursors takes the form of pulses of each gaseous precursor. Between the pulses, the reaction chamber is purged with a gas, which in many cases is an inert gas, and/or evacuated.
- CS-ALD chemisorption-saturated ALD
- the second pulsing phase introduces another precursor on the substrate where the growth reaction of the desired layer takes place. Subsequent to the layer growth reaction, reaction by-products and precursor excess are purged from the reaction chamber.
- one ALD cycle may be performed in less than one second in properly designed flow type reaction chambers. Typically, precursor pulse times range from about 0.5 sec to about 2 to 3 seconds.
- ALD In ALD, the saturation of all the reaction and purging phases makes the growth self-limiting. This self-limiting growth results in large area uniformity and conformality, which has important applications for such cases as planar substrates, deep trenches, and in the processing of porous silicon and high surface area silica and alumina powders.
- ALD provides for controlling layer thickness in a straightforward manner by controlling the number of growth cycles.
- ALD was originally developed to manufacture luminescent and dielectric layers needed in electroluminescent displays. Significant efforts have been made to apply ALD to the growth of doped zinc sulfide and alkaline earth metal sulfide layers. Additionally, ALD has been studied for the growth of different epitaxial II-V and II-VI layers, nonepitaxial crystalline or amorphous oxide and nitride layers and multilayer structures of these. There also has been considerable interest towards the ALD growth of silicon and germanium layers, but due to the difficult precursor chemistry, this has not been very successful.
- the precursors used in an ALD process may be gaseous, liquid or solid. However, liquid or solid precursors must be volatile. The vapor pressure must be high enough for effective mass transportation. Also, solid and some liquid precursors need to be heated inside the reaction chamber and introduced through heated tubes to the substrates. The necessary vapor pressure must be reached at a temperature below the substrate temperature to avoid the condensation of the precursors on the substrate. Due to the self-limiting growth mechanisms of ALD, relatively low vapor pressure solid precursors may be used though evaporation rates may somewhat vary during the process because of changes in their surface area.
- precursors used in ALD there are several other characteristics for precursors used in ALD.
- the precursors must be thermally stable at the substrate temperature because their decomposition would destroy the surface control and accordingly the advantages of the ALD method that relies on the reaction of the precursor at the substrate surface.
- the precursors have to chemisorb on or react with the surface, though the interaction between the precursor and the surface as well as the mechanism for the adsorption is different for different precursors.
- the molecules at the substrate surface must react aggressively with the second precursor to form the desired solid layer. Additionally, precursors should not react with the layer to cause etching, and precursors should not dissolve in the layer. Using highly reactive precursors in ALD contrasts with the selection of precursors for conventional CVD.
- the by-products in the reaction must be gaseous in order to allow their easy removal from the reaction chamber. Further, the by-products should not react or adsorb on the surface.
- RS-ALD reaction sequence ALD
- the self-limiting process sequence involves sequential surface chemical reactions.
- RS-ALD relies on chemistry between a reactive surface and a reactive molecular precursor.
- molecular precursors are pulsed into the ALD reaction chamber separately.
- the metal precursor reaction at the substrate is typically followed by an inert gas pulse to remove excess precursor and by-products from the reaction chamber prior to pulsing the next precursor of the fabrication sequence.
- RS-ALD layers can be layered in equal metered sequences that are all identical in chemical kinetics, deposition per cycle, composition, and thickness.
- RS-ALD sequences generally deposit less than a full layer per cycle.
- a deposition or growth rate of about 0.25 to about 2.00 ⁇ per RS-ALD cycle may be realized.
- RS-ALD The characteristics of RS-ALD include continuity at an interface, conformality over a substrate, use of low temperature and mildly oxidizing processes, freedom from first wafer effects and chamber dependence, growth thickness dependent solely on the number of cycles performed, and ability to engineer multilayer laminate layers with resolution of one to two monolayers.
- RS-ALD allows for deposition control on the order on monolayers and the ability to deposit monolayers of amorphous layers.
- a sequence refers to the ALD material formation based on an ALD reaction of a precursor or a precursor with its reactant precursor. For example, forming a metal layer from a precursor containing the metal forms an embodiment of a metal sequence. Additionally, forming a layer of metal oxide from a precursor containing the metal and from an oxygen containing precursor as its reactant precursor forms an embodiment of a metal/oxygen sequence, which may be referred to as the metal oxide sequence.
- a cycle of a metal sequence includes pulsing a precursor containing the metal and pulsing a purging gas for the precursor.
- a cycle of a metal oxide sequence includes pulsing a precursor containing the metal, pulsing a purging gas for the precursor, pulsing a reactant precursor, and pulsing a purging gas for the reactant precursor.
- a cycle for a compound metal oxide includes pulsing a precursor containing a first metal, pulsing a purging gas for this precursor, pulsing a reactant precursor for the first metal precursor, pulsing a purging gas for the reactant precursor, pulsing a precursor containing a second metal, pulsing a purging gas for this precursor, pulsing a reactant precursor for the second metal precursor, and pulsing a purging gas for this reactant precursor.
- the order of the metal precursors can depend on the tendency of the metals to allow diffusion of atoms through the metal to the underlying substrate. The order employed can limit the amount of unwanted atomic diffusion to the substrate surface.
- a hafnium oxide layer is formed on a substrate mounted in a reaction chamber by ALD using precursor gases individually pulsed into the reaction chamber.
- precursor gases individually pulsed into the reaction chamber.
- solid or liquid precursors may be used in an appropriately designed reaction chamber.
- FIG. 2A depicts an embodiment of an atomic layer deposition system 200 for processing a layer of hafnium oxide for a dielectric layer containing a hafnium oxide and a lanthanide oxide.
- the elements depicted are those elements necessary for discussion of embodiments of the present invention such that those skilled in the art may practice various embodiments of the present invention without undue experimentation.
- a further discussion of the ALD reaction chamber can be found in co-pending, commonly assigned U.S. patent application: entitled “Methods, Systems, and Apparatus for Uniform Chemical-Vapor Depositions,” Ser. No. 09/797,324, filed 1 Mar. 2001, incorporated herein by reference.
- a substrate 210 is located inside a reaction chamber 220 of ALD system 200 . Also located within reaction chamber 220 is a heating element 230 , which is thermally coupled to substrate 210 to control the substrate temperature.
- a gas-distribution fixture 240 introduces precursor gases to the substrate 210 .
- Each precursor gas originates from individual gas sources 251 - 254 whose flow is controlled by mass-flow controllers 256 - 259 , respectively.
- Each gas source, 251 - 254 provides a precursor gas either by storing the precursor as a gas or by providing a location and apparatus for evaporating a solid or liquid material to form the selected precursor gas.
- additional gas sources may be included, one for each metal precursor employed and one for each reactant precursor associated with each metal precursor.
- purging gas sources 261 , 262 are also included in the ALD system.
- additional purging gas sources may be constructed in ALD system 200 , one purging gas source for each precursor gas. For a process that uses the same purging gas for multiple precursor gases less purging gas sources are used in ALD system 200 .
- Gas sources 251 - 254 and purging gas sources 261 - 262 are coupled by their associated mass-flow controllers to a common gas line or conduit 270 , which is coupled to the gas-distribution fixture 240 inside reaction chamber 220 .
- Gas conduit 270 is also coupled to vacuum pump, or exhaust pump, 281 by mass-flow controller 286 to remove excess precursor gases, purging gases, and by-product gases at the end of a purging sequence from gas conduit 270 .
- Vacuum pump, or exhaust pump, 282 is coupled by mass-flow controller 287 to remove excess precursor gases, purging gases, and by-product gases at the end of a purging sequence from reaction chamber 220 .
- mass-flow controller 287 to remove excess precursor gases, purging gases, and by-product gases at the end of a purging sequence from reaction chamber 220 .
- control displays, mounting apparatus, temperature sensing devices, substrate maneuvering apparatus, and necessary electrical connections as are known to those skilled in the art are not shown in FIG. 2A .
- FIG. 2B depicts an embodiment of a gas-distribution fixture 240 of atomic layer deposition system 200 for processing a layer of hafnium oxide for a dielectric layer containing a hafnium oxide and a lanthanide oxide.
- Gas-distribution fixture 240 includes a gas-distribution member 242 , and a gas inlet 244 .
- Gas inlet 244 couples gas-distribution member 242 to gas conduit 270 of FIG. 2A .
- Gas-distribution member 242 includes gas-distribution holes, or orifices, 246 and gas-distribution channels 248 .
- holes 246 are substantially circular with a common diameter in the range of 15-20 microns
- gas-distribution channels 248 have a common width in the range of 20-45 microns.
- the surface 249 of gas distribution member 242 having gas-distribution holes 246 is substantially planar and parallel to substrate 210 of FIG. 2A .
- other embodiments use other surface forms as well as shapes and sizes of holes and channels.
- the distribution and size of holes may also affect deposition thickness and thus might be used to assist thickness control.
- Holes 246 are coupled through gas-distribution channels 248 to gas inlet 244 .
- ALD system 200 is well suited for practicing embodiments of the present invention, other ALD systems commercially available may be used.
- ALD system 200 may be controlled by a computer. To focus on the use of ALD system 200 in the various embodiments of the present invention, the computer is not shown. Those skilled in the art can appreciate that the individual elements such as pressure control, temperature control, and gas flow within ALD system 200 may be under computer control.
- a computer executes instructions stored in a computer readable medium to accurately control the integrated functioning of the elements of ALD system 200 to form a hafnium oxide layer for a dielectric layer containing a hafnium oxide layer and a lanthanide oxide layer.
- a layer of a lanthanide oxide is formed by electron beam evaporation.
- FIG. 3 depicts an electron beam evaporation system 300 for processing a layer of lanthanide oxide for a dielectric layer containing a hafnium oxide and a lanthanide oxide.
- Evaporation system 300 includes a reaction chamber 305 in which is located a substrate 310 having a surface 312 that is to be processed. Substrate 310 rests on substrate holder 315 and its temperature can be raised above room temperature using a heater 320 with its associated reflector 325 .
- Evaporation system 300 also includes an electron gun device 330 regulated by electron gun controller 335 for depositing material on substrate surface 312 .
- Ionizer ring 345 provides supplemental oxygen for processes that require additional oxygen due to lost of oxygen in the evaporation of target materials.
- ionizer ring 345 provides initial oxygen to a film deposited on substrate surface 312 that is to undergo a subsequent oxidation process.
- Shutter 350 is used in conjunction with the control of electron gun device 330 to control the growth rate of a film on substrate 310 .
- the growth rate is determined using quartz crystal monitors 355 , 360 .
- the quartz crystal monitors 355 , 360 are coupled to a thickness/rate control 365 , typically located outside reaction chamber 305 .
- an oxygen gas source 370 including a mass-flow controller 375 .
- the oxygen gas source is ozone gas.
- Mass-flow controller 375 controls the flow of the oxygen source into reaction chamber 305 .
- a vacuum pump 380 with mass flow controller 385 maintains the overall atmosphere of evaporation system 300 at desired levels prior to, during, and after evaporation.
- Electron gun device 330 can include an electron gun and receptacle for a target material that is to be evaporated.
- Target material placed in the target receptacle of electron gun device 330 is heated by impact from an electron beam from its associated electron gun.
- the electron beam is generated with an intensity and duration with which to evaporate the material in the target receptacle of electron gun device 330 .
- the evaporated material then distributes throughout the reaction chamber 305 .
- the evaporated material and pre-evaporation contaminants are prevented from depositing on substrate surface 312 in an unwanted manner by shutter 350 .
- electron gun device can be realized using commercially available devices as are known to those skilled in the art.
- Ionizer ring 345 provides oxygen necessary to compensate for loss of oxygen in the evaporated target material, or to add initial oxygen for subsequent oxidation processing.
- it includes a ring with a center axis.
- the ring has a plurality of openings adapted to direct oxygen flowing to ionizer ring 345 from oxygen gas source 370 towards substrate surface 312 .
- Oxygen is uniformly distributed to substrate surface 312 by ionizer ring 345 positioned generally parallel to substrate 310 .
- the evaporation chamber 300 can be included as part of an overall processing system including ALD system 200 of FIG. 2A, 2B . To avoid contamination of the surface of a layer formed by atomic layer deposition, evaporation chamber 300 can be connected to ALD system 200 using sealable connections to maintain the substrate, which is substrate 210 in FIG. 2 and substrate 310 of FIG. 3 , in an appropriate environment between ALD processing of a hafnium oxide layer and electron beam evaporation of a lanthanide oxide layer. Other means as are known to those skilled in the art can be employed for maintaining an appropriate environment between different processing procedures.
- FIG. 4 illustrates a flow diagram of elements for an embodiment of a method to process a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer.
- This embodiment includes forming a layer of hafnium oxide by atomic layer deposition, at block 410 , and forming a layer of a lanthanide oxide by electron beam evaporation, at block 420 , where the layer of hafnium oxide is adjacent to and in contact with the lanthanide oxide layer.
- the lanthanide oxide can be selected from Pr 2 O 3 , Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .
- the method includes forming the layer of hafnium oxide on a substrate and forming the layer of lanthanide oxide on the layer of hafnium oxide. Alternately, a layer of lanthanide oxide is formed on a substrate and a layer of hafnium oxide is formed on the layer of lanthanide oxide. In an embodiment, the method includes controlling the forming of the layer of hafnium oxide and the layer of the lanthanide oxide to form a lanthanide oxide/hafnium oxide nanolaminate.
- the nanolaminate may have multiple layers of different lanthanide oxides selected from Pr 2 O 3 , Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .
- the combined thickness of lanthanide oxide layers can be limited to a total thickness between about 2 nanometers and about 10 nanometers. Also, for a dielectric layer having a lanthanide oxide layer and one or more layers of hafnium oxide, the combined thickness of hafnium oxide layers can be limited to a total thickness between about 2 nanometers and about 10 nanometers. In an embodiment, hafnium oxide layers are limited to between 2 nanometers and 5 nanometers. In an embodiment, a dielectric layer includes a hafnium oxide layer and multiple layers of lanthanide oxide, where each layer of lanthanide oxide is limited to a thickness between about 2 nanometers and about 10 nanometers.
- Performing each atomic layer deposition includes pulsing one or more precursors into a reaction chamber for a predetermined period.
- the predetermined period is individually controlled for each precursor pulsed into the reaction chamber.
- the substrate is maintained at a selected temperature for each pulsing of a precursor, where the selected temperature is set independently for pulsing each precursor.
- each precursor may be pulsed into the reaction under separate environmental conditions. Appropriate temperatures and pressures are maintained dependent on the nature of the precursor, whether the precursor is a single precursor or a mixture of precursors.
- the pulsing of the precursor gases is separated by purging the reaction chamber with a purging gas following each pulsing of a precursor.
- nitrogen gas is used as the purging gas following the pulsing of each precursor used in a cycle to form a hafnium oxide layer.
- the reaction chamber may also be purged by evacuating the reaction chamber.
- FIG. 5 illustrates a flow diagram of elements for an embodiment of a method to process a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer.
- the method depicted in FIG. 5 can be used to form a gate dielectric layer for a transistor.
- This embodiment may be implemented with the atomic layer deposition system 200 of FIG. 2A , B, and the electron beam evaporation system of FIG. 3 .
- substrate 210 is prepared.
- Substrate 210 used for forming a transistor is typically a silicon or silicon containing material. In other embodiments, germanium, gallium arsenide, silicon-on-sapphire substrates, or other suitable substrates may be used. This preparation process may include cleaning of substrate 210 and forming layers and regions of the substrate, such as drains and sources of a metal oxide semiconductor (MOS) transistor, prior to forming a gate dielectric.
- MOS metal oxide semiconductor
- the substrate is cleaned to provide an initial substrate depleted of its native oxide.
- the initial substrate is cleaned to provide a hydrogen-terminated surface.
- a silicon substrate undergoes a final hydrofluoric acid, HF, rinse prior to ALD processing to provide the silicon substrate with a hydrogen-terminated surface without a native silicon oxide layer.
- substrate 210 is prepared as a chemical oxide-terminated silicon surface prior to forming a hafnium oxide by atomic layer deposition. This preparation allows for forming an interface layer to provide a structure that may further aid in reducing the leakage current through the dielectric layer.
- the sequencing of the formation of the regions of the transistor being processed follows typical sequencing that is generally performed in the fabrication of a MOS transistor as is well known to those skilled in the art. Included in the processing is the masking of substrate regions to be protected during the gate dielectric formation, as is typically performed in MOS fabrication. In this embodiment, the unmasked region may include a body region of a transistor; however one skilled in the art will recognize that other semiconductor device structures may utilize this process. Additionally, substrate 210 in its ready for processing form is conveyed into a position in reaction chamber 220 for ALD processing.
- a hafnium-containing precursor is pulsed into reaction chamber 220 .
- HfI 4 is used as a precursor.
- a hafnium-containing precursor includes but is not limited to HfCl 4 , and Hf(NO 3 ) 4 .
- the HfI 4 precursor is pulsed into reaction chamber 220 through the gas-distribution fixture 240 to substrate 210 .
- Mass-flow controller 256 regulates the flow of the HfI 4 from gas source 251 , where the HfI 4 gas is held at a temperature ranging from about 185° C. to about 195° C. In an embodiment, the substrate temperature is maintained between about 500° C. and about 750° C.
- the substrate temperature is maintained at about 300° C. In other embodiments, the substrate may be held at lower temperatures lower than 300° C.
- the HfI 4 reacts with the surface of the substrate 210 in the desired region defined by the unmasked areas of the substrate 210 .
- a first purging gas is pulsed into reaction chamber 220 .
- nitrogen with a purity of about 99.999% is used as a purging gas.
- Mass-flow controller 266 regulates the nitrogen flow from the purging gas source 261 into the gas conduit 270 . Using the pure nitrogen purge avoids overlap of the precursor pulses and possible gas phase reactions.
- a first oxygen-containing precursor is pulsed onto substrate 210 , at block 520 .
- molecular oxygen is used as a precursor.
- an oxygen-containing precursor for a hafnium/oxygen sequence includes but is not limited to H 2 O, H 2 O 2 , an H 2 O—H 2 O 2 mixture, alcohol (ROH), N 2 O, or O 3 .
- the molecular oxygen precursor is pulsed into reaction chamber 220 through the gas-distribution fixture 240 on substrate 210 .
- Mass-flow controller 257 regulates the flow of the water vapor from gas source 252 .
- the substrate temperature is maintained between about 100° C. and about 150° C.
- the water vapor reacts with at the surface of substrate 210 in the desired region defined by the unmasked areas of the substrate 210 .
- a second purging gas is pulsed, at block, 525 .
- nitrogen is used as the second purging gas.
- Excess precursor gas and reaction by-products are removed from the system by the purge gas in conjunction with the exhausting of reaction chamber 220 using vacuum pump 282 through mass-flow controller 287 , and exhausting of the gas conduit 270 by the vacuum pump 281 through mass-flow controller 286 .
- the substrate may be held between about 500° C. and about 750° C. by the heating element 230 . In an embodiment, the substrate may be held at 300° C. In other embodiments, the substrate may be held at lower temperatures lower than 300° C.
- the HfI 4 precursor can be pulsed for about 2.0 s. After the HfI 4 pulse, the hafnium/O 2 sequence continues with a purge pulse followed by a O 2 pulse followed by a purge pulse. In an embodiment, the O 2 pulse time is about 2.0 sec, and the two nitrogen purging pulse times are each at about 2.0 sec.
- the predetermined number corresponds to a predetermined thickness for the ALD hafnium oxide layer.
- the thickness of the hafnium oxide layer is determined by a fixed growth rate for the pulsing periods and precursors used, set at a value such as N nm/cycle.
- a hafnium oxide layer may be grown at a rate ranging from about 0.07 nm/cycle to about 0.12 nm/cycle for an oxygen pressure ranging from about 0.1 Torr to about 0.3 Torr.
- the ALD process is repeated for t/N total cycles. Once the t/N cycles have completed, no further ALD processing for the current hafnium oxide layer is performed.
- the hafnium-containing precursor is pulsed into reaction chamber 220 , at block 510 , and the process continues. If the total number of cycles to form the desired thickness for the hafnium oxide layer has been completed, a determination is made as to whether the dielectric layer being formed contains the desired number of layers of a lanthanide oxide, at block 535 . If the desired number of layers of a lanthanide oxide have been made, a determination is made as to whether the desired number of layers of hafnium oxide have been processed, at block 545 . Such a case may occur in embodiments for a dielectric layer having hafnium oxide formed as consecutive layers on a lanthanide oxide layer. If more layers of hafnium oxide are required for the given application, the overall process continues as an atomic layer deposition with the pulsing of a hafnium-containing precursor, at block 510 .
- a layer of lanthanide oxide is formed on substrate 210 , at block 540 , which may include hafnium oxide layers and other lanthanide oxide layers.
- substrate 210 in the ALD system is moved into the evaporation system depicted in FIG. 3 , where the substrate 210 , with its formed layers, becomes substrate 310 of FIG. 3 .
- evaporation chamber 300 can be connected to ALD system 200 using sealable connections to maintain the substrate in an appropriate environment between ALD processing of a hafnium oxide layer and electron beam evaporation of a lanthanide oxide layer.
- sealable connections to maintain the substrate in an appropriate environment between ALD processing of a hafnium oxide layer and electron beam evaporation of a lanthanide oxide layer.
- Other means as are known to those skilled in the art can be employed for maintaining an appropriate environment between different processing procedures.
- Electron gun 330 contains a receptacle for a source target on which an electron beam is directed. Electron gun controller 335 regulates the rate of evaporation of material from the target source.
- evaporation chamber 305 can include multiple electron guns, where each electron gun is directed to different targets containing sources to form selected lanthanide oxides to be used at different times in the process.
- the target source of electron gun 330 contains a ceramic Pr 6 O 11 source, which is evaporated due to the impact of the electron beam. The evaporated material is then distributed throughout the chamber 305 .
- a dielectric layer of Pr 2 O 3 is grown on surface 312 of substrate 310 , which is maintained at a temperature ranging from about 100° C. to about 150° C. The growth rate can vary with a typical rate of 0.1 ⁇ /s.
- a Pr 2 O 3 layer may include a thin amorphous interfacial layer separating a crystalline layer of Pr 2 O 3 from the substrate on which it is grown. This thin amorphous layer may be beneficial in reducing the number of interface charges and eliminating any grain boundary paths for conductance from the substrate.
- Other source materials can be used for forming a Pr 2 O 3 layer, as are known to those skilled in the art.
- the lanthanide oxide layer formed by electron beam evaporation for a dielectric layer containing an atomic layer deposited hafnium oxide and a lanthanide oxide can be an oxide selected from Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , or Dy 2 O 3 .
- a dielectric layer may include a number of hafnium oxide layers and a number of lanthanide oxide layers, where the lanthanide oxide layers are different lanthanide oxides.
- the different lanthanide oxides can be selected from Pr 2 O 3 , Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .
- the source material for the particular lanthanide oxide is chosen from commercial materials for forming the lanthanide oxide by electron bean evaporation, as is known by those skilled in the art.
- a layer of lanthanide oxide is formed by electron beam evaporation, at block 540 , and the process continues. If is determined that the desired number of lanthanide oxide layers have been formed, at block 550 , and if the desired number of hafnium oxide layers have been formed, then the substrate is further processed to complete device processing, at block 555 .
- the growth of the dielectric layer is complete.
- the dielectric layer may be annealed. To avoid the diffusion of oxygen during annealing to the semiconductor substrate surface, annealing may be performed in an oxygen-free environment for short periods of time.
- An embodiment of an annealing environment may include a nitrogen atmosphere.
- the relatively low processing temperatures employed by atomic layer deposition of the hafnium oxide layers and by electron beam evaporation of the lanthanide layers allows for the formation of an amorphous dielectric layer.
- processing the device having this dielectric layer is completed.
- completing the device includes completing the formation of a transistor.
- completing the device includes completing the formation of a capacitor.
- completing the process includes completing the construction of a memory device having an array with access transistors formed with gate dielectrics containing atomic layer deposited hafnium oxide and electron beam deposited lanthanide oxide.
- completing the process includes the formation of an electronic system including an information handling device that uses electronic devices with transistors formed with dielectric layers having an atomic layer deposited hafnium oxide and an electron beam deposited lanthanide oxide.
- the elements of a method for forming a dielectric layer containing atomic layer deposited hafnium oxide and electron beam deposited lanthanide oxide in the embodiment of FIG. 5 may be performed under various environmental conditions, including various pressures and temperatures, and pulse periods depending on the dielectric layer to be formed for a given application and the systems used to fabricate such a dielectric layer. Determination of the environmental conditions, precursors used, purging gases employed, pulse periods for the precursors and purging gases, and electron beam target materials may be made without undue experimentation.
- the elements for a method for forming a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam deposited lanthanide oxide as illustrated in FIG. 5 can vary and include numerous permutations.
- an atomic layer deposited hafnium oxide layer is formed on a substrate and an electron beam evaporated lanthanide oxide layer is formed on the hafnium oxide layer.
- an electron beam evaporated lanthanide oxide layer is formed on a substrate and an atomic layer deposited hafnium oxide layer is deposited on the lanthanide oxide layer.
- a hafnium oxide layer may be formed as multiple layers of atomic layer deposited hafnium oxide.
- a lanthanide oxide layer may be formed as multiple layers of an electron beam evaporated lanthanide oxide.
- a dielectric layer may contain multiple layers of lanthanide oxide, where two or more layers contain different lanthanide oxides selected from Pr 2 O 3 , Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .
- a dielectric containing hafnium oxide and lanthanide oxide is formed as a nanolaminate.
- the nanolaminate may have multiple layers of different lanthanide oxides selected from Pr 2 O 3 , Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .
- the combined thickness of lanthanide oxide layers can be limited to a total thickness between about 2 nanometers and about 10 nanometers.
- the combined thickness of hafnium oxide layers can be limited to a total thickness between about 2 nanometers and about 10 nanometers. In an embodiment, hafnium oxide layers are limited to between 2 nanometers and 5 nanometers. In an embodiment, a dielectric layer includes a hafnium oxide layer and multiple layers of lanthanide oxide, where each layer of lanthanide oxide is limited to a thickness between about 2 nanometers and about 10 nanometers.
- a dielectric layer includes a lanthanide oxide layer and multiple layers of hafnium oxide, where each layer of hafnium oxide is limited to a thickness between about 2 nanometers and about 10 nanometers.
- a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electron beam evaporated lanthanide oxide layer has a thickness ranging from about 2 nanometers to about 20 nanometers.
- a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam deposited lanthanide oxide may be processed in an atomic layer deposition system such as ALD system 200 and evaporation system 300 under computer control to perform various embodiments, and operated under computer-executable instructions to perform these embodiments.
- Instructions stored in a computer readable medium are executed by a computer to accurately control the integrated functioning of the elements of atomic layer deposition system 200 and evaporation system 300 to form a dielectric layer containing hafnium oxide and a lanthanide oxide, according to various embodiments.
- the computer-executable instructions may be provided in any computer-readable medium.
- Such computer-readable medium may include, but is not limited to, floppy disks, diskettes, hard disks, CD-ROMS, flash ROMS, nonvolatile ROM, and RAM.
- Dielectric layers containing hafnium oxide layers and lanthanide oxide layers can have a wide range of dielectric constants determined by the series configuration and relative thickness of the hafnium oxide layers and the lanthanide oxide layers.
- HfO 2 has a dielectric constant of about 25.
- Bulk Pr 2 O 3 has a dielectric constant of about 31, while the dielectric constants for Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 , in bulk form, are generally also in the range of 25-30. Consequently, a dielectric layer containing bulk layers of hafnium oxide and lanthanide oxide could be expected to have a dielectric constant engineered in the range from about 25 to about 31.
- Such a dielectric layer would have a t eq that is about one-sixth to one-eight smaller than a silicon oxide layer of the same thickness.
- a thin dielectric layer with an interfacial layer formed between the surface of the substrate and the first layer of a hafnium oxide or a lanthanide oxide will have a t eq that is based on an interfacial layer physically in parallel with the dielectric layer equivalently forming a series configuration of electrical structures.
- the dielectric layer formed having an interfacial layer between it and the substrate on which it is grown can have an effective dielectric constant considerably less than a dielectric constant associated with the combination of hafnium oxide and lanthanide oxide layers.
- the effective dielectric constants for thin dielectric layers containing any of these materials and/or combinations of these materials may be reduced from their bulk value depending on the thickness and material composition of any interfacial layer that may be formed.
- the dielectric layer may be subject to a thin film effect related to the abrupt termination of the film.
- a planar bulk or thick film can be considered as a bulk region with two surface regions. Due to the termination of the thick film, the properties of the two surface regions can vary from that of the bulk region. In a thick film, the effective properties of the film are dominated by the bulk region. In a thin film, including nanolaminates, the properties of the thin film are effectively controlled by two surface regions. See K. Natori et al., Applied Physics Letters, vol. 73: no. 5, pp. 632-634 (1998).
- thin films of hafnium oxide and lanthanide oxide may have effective dielectric constants reduced from their bulk values without being formed in a structure with interfacial regions.
- dielectric layers containing hafnium oxide and lanthanide oxide may have a dielectric constant in the range of about 25 to about 31.
- dielectric layers containing hafnium oxide and lanthanide oxide may have dielectric constants in the range from about 11 to about 16.
- the embodiments described herein provide a process for growing a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide having a wide range of useful equivalent oxide thickness, t eq .
- the relatively large dielectric constant for such a dielectric layer ranges from about 11 to about 31, depending on the presence of an interfacial layer and/or on a size effect.
- Forming a dielectric layer according to various embodiments with a thickness ranging from 2 nanometers to 20 nanometers allows for the engineering of dielectric layers achieving a t eq in the range of about 0.7 nanometers to about 7 nanometers.
- the t eq for such a dielectric layer may range from about 0.25 nanometers to about 2.5 nanometers.
- a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide may be formed for applications with a t eq between 10 ⁇ and 20 ⁇ , or less than 10 ⁇ .
- Dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide using embodiments of the present invention may be engineered with various structures and compositions including an amorphous structure.
- Embodiments using low processing temperatures tend to provide an amorphous structure, which is better suited for reducing leakage current than structures exhibiting a polycrystalline structure or a partial polycrystalline structure.
- FIG. 6 depicts a nanolaminate structure 600 for an embodiment of a dielectric structure including atomic layer deposited hafnium oxide and electron beam evaporated lanthanide oxide.
- Nanolaminate structure 600 includes a plurality of layers 605 - 1 to 605 -N, where each layer contains atomic layer deposited hafnium oxide or electron beam evaporated lanthanide oxide. The sequencing of the layers depends on the application.
- the effective dielectric constant associated with nanolaminate structure 600 is that attributable to N capacitors in series, where each capacitor has a thickness defined by the thickness of the corresponding electron beam evaporated lanthanide oxide or atomic layer deposited hafnium oxide layer. By selecting each thickness and the composition of each layer, electron beam evaporated lanthanide oxide or atomic layer deposited hafnium oxide layer, a nanolaminate structure can be engineered to have a predetermined dielectric constant.
- Embodiments for forming a dielectric layer including ALD processing of a hafnium oxide and processing of an lanthanide oxide by electron beam evaporation may be implemented to form transistors, capacitors, memory devices, and other electronic systems including electro-optic devices, microwave devices, and information handling devices. With careful preparation and engineering of the dielectric layer limiting the size of interfacial regions, a t eq less than about 10 ⁇ for these devices is anticipated.
- a transistor 100 as depicted in FIG. 1 may be constructed by forming a source region 120 and a drain region 130 in a silicon based substrate 110 where source and drain regions 120 , 130 are separated by a body region 132 .
- Body region 132 defines a channel having a channel length 134 .
- a dielectric layer is disposed on substrate 110 formed as a layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide. The resulting dielectric layer forms gate dielectric 140 .
- a gate 150 is formed over gate dielectric 140 .
- forming gate 150 may include forming a polysilicon layer, though a metal gate may be formed in an alternative process.
- An interfacial layer 133 may form between body region 132 and gate dielectric 140 .
- Interfacial layer 133 may be limited to a thickness less than 1 nanometer, or to a thickness significantly less than 1 nanometer as to be effectively eliminated.
- Forming the substrate, the source and drain regions, and the gate is performed using standard processes known to those skilled in the art. Additionally, the sequencing of the various elements of the process for forming a transistor is conducted with standard fabrication processes, also as known to those skilled in the art.
- FIG. 7 shows an embodiment of a configuration of a transistor 700 having a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide.
- Transistor 700 includes a silicon based substrate 710 with a source 720 and a drain 730 separated by a body region 732 .
- Body region 732 between source 720 and drain 730 defines a channel region having a channel length 734 .
- Gate dielectric 740 includes a dielectric containing an atomic layer deposited hafnium oxide layer and an electron beam evaporated lanthanide oxide layer as described herein with the remaining elements of the transistor 700 formed using processes known to those skilled in the art.
- both gate dielectric 740 and floating gate dielectric 742 may be formed as dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide in various embodiments as described herein.
- An interfacial layer 733 may form between body region 732 and gate dielectric 740 . Interfacial layer 733 may be limited to a thickness less than 1 nanometer, or to a thickness significantly less than 1 nanometer as to be effectively eliminated.
- a method includes forming a first conductive layer 810 , forming a dielectric layer 820 containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide on first conductive layer 810 , and forming a second conductive layer 830 on dielectric layer 820 .
- An interfacial layer 815 may form between first conductive layer 810 and dielectric layer 820 .
- Interfacial layer 815 may be limited to a thickness less than 1 nanometer, or to a thickness significantly less than 1 nanometer as to be effectively eliminated.
- Transistors, capacitors, and other devices dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide using methods described herein may be implemented into memory devices and electronic systems including information handling devices.
- Such information devices may include wireless systems, telecommunication systems, and computers. It will be recognized by one skilled in the art that several types of memory devices and electronic systems including information handling devices utilize embodiments of the present invention.
- FIG. 9 is a simplified block diagram of a memory device 900 using an embodiment of a dielectric containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide.
- Memory device 900 includes an array of memory cells 902 , address decoder 904 , row access circuitry 906 , column access circuitry 908 , control circuitry 910 , and Input/Output (I/O) circuit 912 .
- the memory is operably coupled to an external microprocessor 914 , or memory controller for memory accessing.
- Memory device 900 receives control signals from processor 914 , such as WE*, RAS* and CAS* signals, which can be supplied on a system bus.
- Memory device 900 stores data that is accessed via I/O lines.
- Each memory cell in a row of memory cell array 902 is coupled to a common word line.
- the word line is coupled to gates of individual transistors, where at least one transistor has a gate coupled to a gate dielectric containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide in accordance with the methods and structure previously described herein.
- each memory cell in a column is coupled to a common bit line.
- Each cell in memory array 902 may include a storage capacitor and an access transistor as is conventional in the art. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device of FIG. 9 has been simplified to focus on embodiments of the present invention.
- DRAM Dynamic Random Access Memory
- embodiments are equally applicable to any size and type of memory circuit and are not intended to be limited to the DRAM described above.
- Other alternative types of devices include SRAM (Static Random Access Memory) or Flash memories.
- the DRAM could be a synchronous DRAM commonly referred to as SGRAM (Synchronous Graphics Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), SDRAM II, and DDR SDRAM (Double Data Rate SDRAM), as well as Synchlink or Rambus DRAMs and other emerging DRAM technologies.
- FIG. 10 illustrates a block diagram for an electronic system 1000 having devices with an embodiment for a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide.
- Electronic system 1000 includes a controller 1005 , a bus 1015 , and an electronic device 1025 , where bus 1015 provides electrical conductivity between controller 1005 and electronic device 1025 .
- controller 1005 and/or electronic device 1025 include an embodiment for a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide as previously discussed herein.
- electronic system 1000 includes a plurality of electronic devices using an embodiment for a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide according to the present invention.
- Electronic system 1000 may include, but is not limited to, information handling devices, wireless systems, telecommunication systems, fiber optic systems, electro-optic systems, and computers.
- a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide provides a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO 2 .
- Forming dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide in relatively low processing temperatures may allow for dielectric layers that are amorphous and conformally layered on a substrate surface. Further, the formation of these dielectric layers provides for enhanced dielectric and electrical properties relative to those attained with an amorphous SiO 2 layer.
- Capacitors, transistors, electro-optic devices, higher level ICs or devices, and electronic systems are constructed utilizing various embodiments for forming a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide structured to provide an ultra thin equivalent oxide thickness, t eq .
- Dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide are formed having a dielectric constant substantially higher than that of silicon dioxide, where such dielectric layers are capable of a t eq thinner than 10 ⁇ , thinner than the expected limit for SiO 2 gate dielectrics.
- the thinner t eq of these dielectric layers allows for a higher capacitance than SiO 2 gate dielectrics, which provides further effective scaling for microelectronic devices and systems.
- the physical thickness of the dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide is much larger than the SiO 2 thickness associated with the t eq limit of SiO 2 . Forming the larger thickness aids in the manufacturing process for gate dielectrics and other dielectric layers.
Abstract
Dielectric layers are provided configured with a layer of lanthanide oxide and a layer of hafnium oxide, where the layer of hafnium oxide is structured as one of more monolayers of hafnium oxide. In an embodiment, a dielectric layer may be arranged as a nanolaminate of hafnium oxide and a lanthanide oxide, with the layer of hafnium oxide structured as one of more monolayers of hafnium oxide.
Description
- This application is a divisional of U.S. application Ser. No. 10/931,343, filed 31 Aug. 2004, which is a divisional of U.S. application Ser. No. 10/602,323, filed 24 Jun. 2003, which applications are incorporated herein by reference in their entirety.
- This application is related to the following commonly assigned U.S. patent applications, which are herein incorporated by reference in their entirety:
- U.S. application Ser. No. 10/602,315, entitled “Lanthanide Oxide/Hafnium Oxide Dielectrics,” filed 24 Jun. 2003, now issued as U.S. Pat. No. 7,049,192;
- U.S. application Ser. No. 10/137,058, entitled: “Atomic Layer Deposition and Conversion,” filed 2 May 2002;
- U.S. application Ser. No. 10/137,168, entitled: “Methods, Systems, and Apparatus for Atomic-Layer Deposition of Aluminum Oxides in Integrated Circuits,” filed 2 May 2002; and
- U.S. application Ser. No. 09/797,324, entitled: “Methods, Systems, and Apparatus for Uniform Chemical-Vapor Depositions,” filed 1 Mar. 2001, now issued as U.S. Pat. No. 6,852,167.
- This application relates generally to semiconductor devices and device fabrication and, more particularly, to dielectric layers and their method of fabrication.
- The semiconductor device industry has a market driven need to improve speed performance, improve its low static (off-state) power requirements, and adapt to a wide range of power supply and output voltage requirements for its silicon based microelectronic products. In particular, there is continuous pressure to reduce the size of devices such as transistors. The ultimate goal is to fabricate increasingly smaller and more reliable integrated circuits (ICs) for use in products such as processor chips, mobile telephones, and memory devices such as dynamic random access memories (DRAMs).
- Currently, the semiconductor industry relies on the ability to reduce or scale the dimensions of its basic devices, primarily, the silicon based metal-oxide-semiconductor field effect transistor (MOSFET). A common configuration of such a transistor is shown in
FIG. 1 . While the following discussion usesFIG. 1 to illustrate a transistor from the prior art, one skilled in the art will recognize that the present invention could be incorporated into the transistor shown inFIG. 1 to form a transistor according to the present invention. Atransistor 100 is fabricated in asubstrate 110 that is typically silicon.Transistor 100 has asource region 120 and adrain region 130. Abody region 132 is located betweensource region 120 anddrain region 130, wherebody region 132 defines a channel of the transistor with achannel length 134. A gate dielectric 140 is located onbody region 132 with agate 150 located over gate dielectric 140. Gate dielectric 140 is typically an oxide, and is commonly referred to as a gate oxide. Gate 150 may be fabricated from polycrystalline silicon (polysilicon), or other conducting materials such as metal may be used. - In fabricating transistors to be smaller in size and reliably operate on lower power supplies, one design criteria is gate dielectric 140. The mainstay for forming the gate dielectric has been silicon dioxide, SiO2. A thermally grown amorphous SiO2 layer provides an electrically and thermodynamically stable material, where the interface of the SiO2 layer with underlying Si provides a high quality interface as well as superior electrical isolation properties. However, increased scaling and other requirements in microelectronic devices have created the need to use other dielectric materials as gate dielectrics.
-
FIG. 1 shows a configuration of a transistor having a gate dielectric containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to various embodiments of the present invention. -
FIG. 2A depicts an atomic layer deposition system for processing a layer of hafnium oxide for a dielectric layer containing a hafnium oxide and a lanthanide oxide, according to various embodiments of the present invention. -
FIG. 2B depicts a gas-distribution fixture of an atomic layer deposition system for processing a layer of hafnium oxide for a dielectric layer containing a hafnium oxide and a lanthanide oxide, according to various embodiments of the present invention. -
FIG. 3 depicts an electron beam evaporation system for processing a layer of lanthanide oxide for a dielectric layer containing a hafnium oxide and a lanthanide oxide, according to various embodiments of the present invention. -
FIG. 4 illustrates a flow diagram of elements for an embodiment of a method to process a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to the present invention. -
FIG. 5 illustrates a flow diagram of elements for an embodiment of a method to process a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to the present invention. -
FIG. 6 depicts an embodiment of a dielectric layer including a nanolaminate of a hafnium oxide layer and a lanthanide oxide layer, according to the present invention. -
FIG. 7 shows an embodiment of a configuration of a transistor having a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to the present invention. -
FIG. 8 shows an embodiment of a configuration of a capacitor having a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to the present invention. -
FIG. 9 is a simplified block diagram for an embodiment of a memory device with a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to the present invention. -
FIG. 10 illustrates a block diagram for an embodiment of an electronic system having devices with a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, according to the present invention. - The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.
- The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form an integrated circuit (IC). The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art.
- The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
- In various embodiments, a dielectric layer includes a hafnium oxide layer and a lanthanide oxide layer, where the hafnium oxide layer is formed by atomic layer deposition (ALD) and the lanthanide oxide layer is formed by electron beam evaporation. The lanthanide oxide can be selected from Pr2O3, Nd2O3, Sm2O3, Gd2O3, and Dy2O3. In an embodiment, a dielectric layer includes a hafnium oxide/lanthanide oxide nanolaminate.
- The term “nanolaminate” means a composite film of ultra thin layers of two or more materials in a layered stack, where the layers are alternating layers of materials of the composite film. Typically, each layer in a nanolaminate has a thickness of an order of magnitude in the nanometer range. Further, each individual material layer of the nanolaminate can have a thickness as low as a monolayer of the material. A nanolaminate of hafnium oxide and a lanthanide oxide includes at least one thin layer of hafnium oxide, and one thin layer of the lanthanide oxide, which can be written as a nanolaminate of hafnium oxide/lanthanide oxide. Further, a hafnium oxide/lanthanide oxide nanolaminate is not limited to alternating one lanthanide layer after a hafnium oxide layer, but can include multiple thin layers of a lanthanide oxide alternating with multiple thin layers of hafnium oxide. Further, the number of thin layers of lanthanide oxide and the number of thin layers of hafnium oxide can vary independently within a nanolaminate structure. Additionally, a hafnium oxide/lanthanide oxide nanolaminate can include layers of different lanthanide oxides, where each layer is independently selected from Pr2O3, Nd2O3, Sm2O3, Gd2O3, and Dy2O3. A dielectric layer containing alternating layers of a lanthanide oxide and a hafnium oxide has an effective dielectric constant related to the series combination of the layers of lanthanide oxide and hafnium oxide, which depends on the relative thicknesses of the lanthanide oxide layers and the hafnium oxide layers. Thus, a dielectric containing a hafnium oxide/lanthanide oxide nanolaminate can be engineered to effectively provide a selected dielectric constant.
- A
gate dielectric 140 ofFIG. 1 , when operating in a transistor, has both a physical gate dielectric thickness and an equivalent oxide thickness (teq). The equivalent oxide thickness quantifies the electrical properties, such as capacitance, of agate dielectric 140 in terms of a representative physical thickness. The equivalent oxide thickness, teq, is defined as the thickness of a theoretical SiO2 layer that would have the same capacitance density as a given dielectric, ignoring leakage current and reliability considerations. - A SiO2 layer of thickness, t, deposited on a Si surface as a gate dielectric will have a teq larger than its thickness, t. This teq results from the capacitance in the surface channel on which the SiO2 is deposited due to the formation of a depletion/inversion region. This depletion/inversion region may result in teq being from 3 to 6 Angstroms (Å) larger than the SiO2 thickness, t. Thus, with the semiconductor industry driving to scale the gate dielectric equivalent oxide thickness to under 10 Å, the physical thickness for a SiO2 layer used for a gate dielectric would be need to be approximately 4 to 7 Å.
- Additional characteristics for a SiO2 layer depend on the gate electrode used in conjunction with the SiO2 gate dielectric. Using a conventional polysilicon gate results in an additional increase in teq for the SiO2 layer. This additional thickness could be eliminated by using a metal gate electrode, though metal gates are not currently used in typical complementary metal-oxide-semiconductor field effect transistor (CMOS) technology. Thus, future devices would be designed towards a physical SiO2 gate dielectric layer of about 5 Å or less. Such a small thickness for a SiO2 oxide layer creates additional problems.
- Silicon dioxide is used as a gate dielectric, in part, due to its electrical isolation properties in a SiO2—Si based structure. This electrical isolation is due to the relatively large bandgap of SiO2 (8.9 eV) making it a good insulator from electrical conduction. Signification reductions in its bandgap would eliminate it as a material for a gate dielectric. As the thickness of a SiO2 layer decreases, the number of atomic layers, or monolayers of the SiO2 decreases. At a certain thickness, the number of monolayers will be sufficiently small that the SiO2 layer will not have a complete arrangement of atoms as in a larger or bulk layer. As a result of incomplete formation relative to a bulk structure, a thin SiO2 layer of only one or two monolayers will not form a full bandgap. The lack of a full bandgap in a SiO2 gate dielectric could cause an effective short between an underlying Si channel and an overlying polysilicon gate. This undesirable property sets a limit on the physical thickness to which a SiO2 layer may be scaled. The minimum thickness due to this monolayer effect is thought to be about 7-8 Å. Therefore, for future devices to have a teq less than about 10 Å, dielectrics other than SiO2 need to be considered for use as a gate dielectric.
- For a typical dielectric layer used as a gate dielectric, the capacitance is determined as one for a parallel plate capacitance: C=κε0A/t, where κ is the dielectric constant, ε0 is the permittivity of free space, A is the area of the capacitor, and t is the thickness of the dielectric. The thickness, t, of a material is related to its teq for a given capacitance, with SiO2 having a dielectric constant κ0=3.9, as
t=(κ/κox) t eq=(κ/3.9)t eq.
Thus, materials with a dielectric constant greater than that of SiO2, 3.9, will have a physical thickness that may be considerably larger than a desired teq, while providing the desired equivalent oxide thickness. For example, an alternate dielectric material with a dielectric constant of 10 could have a thickness of about 25.6 Å to provide a teq of 10 Å, not including any depletion/inversion layer effects. Thus, a reduced teq for transistors may be realized by using dielectric materials with higher dielectric constants than SiO2. The thinner teq for lower transistor operating voltages and smaller transistor dimensions may be realized by a significant number of materials, but additional fabricating characteristics makes determining a suitable replacement for SiO2 difficult. - The current view for the microelectronics industry is still for Si based devices. Thus, the gate dielectric employed will grow on a silicon substrate or silicon layer, which places significant restraints on the substitute dielectric material. During the formation of the dielectric on the silicon layer, there exists the possibility that a small layer of SiO2 could be formed in addition to the desired dielectric. The result would effectively be a dielectric layer consisting of two sublayers in parallel with each other and the silicon layer on which the dielectric is formed. In such a case, the resulting capacitance would be that of two dielectrics in series. As a result, the teq of the dielectric layer would be the sum of the SiO2 thickness and a multiplicative factor of the thickness of the dielectric being formed, written as
t eq =t SiO2 +(κox/κ)t.
Thus, if a SiO2 layer is formed in the process, the teq is again limited by a SiO2 layer. Thus, use of an ultra-thin silicon dioxide interface layer should be limited to significantly less than ten angstroms. In the event that a barrier layer is formed between the silicon layer and the desired dielectric in which the barrier layer prevents the formation of a SiO2 layer, the teq would be limited by the layer with the lowest dielectric constant. However, whether a single dielectric layer with a high dielectric constant or a barrier layer with a higher dielectric constant than SiO2 is employed, the layer interfacing with the silicon layer must provide a high quality interface to maintain a high channel carrier mobility. - One of the advantages for using SiO2 as a gate dielectric has been that the formation of the SiO2 layer results in an amorphous gate dielectric. Having an amorphous structure for a gate dielectric is advantageous because grain boundaries in polycrystalline gate dielectrics provide high leakage paths. Additionally, grain size and orientation changes throughout a polycrystalline gate dielectric may cause variations in the layer's dielectric constant. Many materials having a high dielectric constant relative to SiO2 also have a disadvantage of a crystalline form, at least in a bulk configuration. Thus, the best candidates for replacing SiO2 as a gate dielectric are those with high dielectric constant, a relatively large bandgap, and are able to be fabricated as a thin layer with an amorphous form.
- Materials such as Ta2O3, TiO2, A2O3, HfO2, HfSixOy, HfSixOy, and barium strontium titanate (BST) have been proposed as replacements for SiO2 as gate dielectric materials. Additional materials have been proposed to not only provide a material layer with a dielectric constant greater than silicon dioxide, but also to provide adjustment to the insulating properties of the material. Such materials can be provided as nanolaminates, for example, Ta2O5/HfO2, ZrO2/HfO2, Ta2O5/HfO2 nanolaminates. Providing dielectric layers configured as nanolaminates can provide a dielectric layer with relatively low leakage current properties.
- An embodiment for a method for forming a dielectric layer containing a hafnium oxide and a lanthanide oxide includes forming a layer of the hafnium oxide by atomic layer deposition and forming a layer of the lanthanide oxide by electron beam evaporation. The layer of hafnium oxide is adjacent to and in contact with the layer of lanthanide oxide. In an embodiment, a dielectric layer includes a hafnium oxide/lanthanide oxide nanolaminate having an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer.
- Dielectric layers containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer have a larger dielectric constant than silicon dioxide. Such dielectric layers provide a significantly thinner equivalent oxide thickness compared with a silicon oxide layer having the same physical thickness. Alternately, such dielectric layers provide a significantly thicker physical thickness than a silicon oxide layer having the same equivalent oxide thickness. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer, and methods for forming such structures.
- In an embodiment of the present invention, a dielectric film having an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide allows for the engineering of a dielectric layer with a dielectric constant significantly higher than that of silicon dioxide and a relatively low leakage current characteristic. Using layers of atomic layer deposited HfO2 in various embodiments, provides layers, as compared to ZrO2, that have a stronger tendency to form a single phase structure, a higher refractive index when deposited at low temperatures, a larger band gap, higher band offsets on silicon, and better thermal stability against silicide formation. Additionally, amorphous lanthanide oxides provide high oxide capacitance, low leakage current, and high thermal stability. Other considerations for selecting the material and method for forming a dielectric layer for use in electronic devices and systems concern the suitability of the material for applications requiring a dielectric layer to have an ultra-thin equivalent oxide thickness, form conformally on a substrate, and/or be engineered to specific thickness and elemental concentrations.
- Another consideration concerns the roughness of the dielectric layer on a substrate. Surface roughness of the dielectric layer has a significant effect on the electrical properties of the gate oxide, and the resulting operating characteristics of the transistor. Leakage current through a physical 1.0 nanometer gate oxide has been found to be increased by a factor of 10 for every 0.1 increase in the root-mean-square (RMS) roughness.
- During a conventional sputtering deposition process stage, particles of the material to be deposited bombard the surface at a high energy. When a particle hits the surface, some particles adhere, and other particles cause damage. High-energy impacts remove body region particles creating pits. The surface of such a deposited layer may have a rough contour due to the rough interface at the body region.
- In an embodiment, a hafnium oxide layer having a substantially smooth surface relative to other processing techniques is formed on a substrate using atomic layer deposition. Further, the ALD deposited hafnium oxide layer provides a conformal coverage on the substrate surface on which it is deposited. A lanthanide oxide layer is then formed on the hafnium oxide layer, where the lanthanide oxide layer is formed by electron beam evaporation.
- ALD, also known as atomic layer epitaxy (ALE), was developed in the early 1970's as a modification of chemical vapor deposition (CVD) and is also called “alternatively pulsed-CVD.” In ALD, gaseous precursors are introduced one at a time to the substrate surface mounted within a reaction chamber (or reactor). This introduction of the gaseous precursors takes the form of pulses of each gaseous precursor. Between the pulses, the reaction chamber is purged with a gas, which in many cases is an inert gas, and/or evacuated.
- In a chemisorption-saturated ALD (CS-ALD) process, during the first pulsing phase, reaction with the substrate occurs with the precursor saturatively chemisorbed at the substrate surface. Subsequent pulsing with a purging gas removes precursor excess from the reaction chamber.
- The second pulsing phase introduces another precursor on the substrate where the growth reaction of the desired layer takes place. Subsequent to the layer growth reaction, reaction by-products and precursor excess are purged from the reaction chamber. With favourable precursor chemistry where the precursors adsorb and react with each other on the substrate aggressively, one ALD cycle may be performed in less than one second in properly designed flow type reaction chambers. Typically, precursor pulse times range from about 0.5 sec to about 2 to 3 seconds.
- In ALD, the saturation of all the reaction and purging phases makes the growth self-limiting. This self-limiting growth results in large area uniformity and conformality, which has important applications for such cases as planar substrates, deep trenches, and in the processing of porous silicon and high surface area silica and alumina powders. Thus, ALD provides for controlling layer thickness in a straightforward manner by controlling the number of growth cycles.
- ALD was originally developed to manufacture luminescent and dielectric layers needed in electroluminescent displays. Significant efforts have been made to apply ALD to the growth of doped zinc sulfide and alkaline earth metal sulfide layers. Additionally, ALD has been studied for the growth of different epitaxial II-V and II-VI layers, nonepitaxial crystalline or amorphous oxide and nitride layers and multilayer structures of these. There also has been considerable interest towards the ALD growth of silicon and germanium layers, but due to the difficult precursor chemistry, this has not been very successful.
- The precursors used in an ALD process may be gaseous, liquid or solid. However, liquid or solid precursors must be volatile. The vapor pressure must be high enough for effective mass transportation. Also, solid and some liquid precursors need to be heated inside the reaction chamber and introduced through heated tubes to the substrates. The necessary vapor pressure must be reached at a temperature below the substrate temperature to avoid the condensation of the precursors on the substrate. Due to the self-limiting growth mechanisms of ALD, relatively low vapor pressure solid precursors may be used though evaporation rates may somewhat vary during the process because of changes in their surface area.
- There are several other characteristics for precursors used in ALD. The precursors must be thermally stable at the substrate temperature because their decomposition would destroy the surface control and accordingly the advantages of the ALD method that relies on the reaction of the precursor at the substrate surface. A slight decomposition, if slow compared to the ALD growth, may be tolerated.
- The precursors have to chemisorb on or react with the surface, though the interaction between the precursor and the surface as well as the mechanism for the adsorption is different for different precursors. The molecules at the substrate surface must react aggressively with the second precursor to form the desired solid layer. Additionally, precursors should not react with the layer to cause etching, and precursors should not dissolve in the layer. Using highly reactive precursors in ALD contrasts with the selection of precursors for conventional CVD.
- The by-products in the reaction must be gaseous in order to allow their easy removal from the reaction chamber. Further, the by-products should not react or adsorb on the surface.
- In a reaction sequence ALD (RS-ALD) process, the self-limiting process sequence involves sequential surface chemical reactions. RS-ALD relies on chemistry between a reactive surface and a reactive molecular precursor. In an RS-ALD process, molecular precursors are pulsed into the ALD reaction chamber separately. The metal precursor reaction at the substrate is typically followed by an inert gas pulse to remove excess precursor and by-products from the reaction chamber prior to pulsing the next precursor of the fabrication sequence.
- By RS-ALD, layers can be layered in equal metered sequences that are all identical in chemical kinetics, deposition per cycle, composition, and thickness. RS-ALD sequences generally deposit less than a full layer per cycle. Typically, a deposition or growth rate of about 0.25 to about 2.00 Å per RS-ALD cycle may be realized.
- The characteristics of RS-ALD include continuity at an interface, conformality over a substrate, use of low temperature and mildly oxidizing processes, freedom from first wafer effects and chamber dependence, growth thickness dependent solely on the number of cycles performed, and ability to engineer multilayer laminate layers with resolution of one to two monolayers. RS-ALD allows for deposition control on the order on monolayers and the ability to deposit monolayers of amorphous layers.
- Herein, a sequence refers to the ALD material formation based on an ALD reaction of a precursor or a precursor with its reactant precursor. For example, forming a metal layer from a precursor containing the metal forms an embodiment of a metal sequence. Additionally, forming a layer of metal oxide from a precursor containing the metal and from an oxygen containing precursor as its reactant precursor forms an embodiment of a metal/oxygen sequence, which may be referred to as the metal oxide sequence. A cycle of a metal sequence includes pulsing a precursor containing the metal and pulsing a purging gas for the precursor. Further, a cycle of a metal oxide sequence includes pulsing a precursor containing the metal, pulsing a purging gas for the precursor, pulsing a reactant precursor, and pulsing a purging gas for the reactant precursor. Additionally, a cycle for a compound metal oxide includes pulsing a precursor containing a first metal, pulsing a purging gas for this precursor, pulsing a reactant precursor for the first metal precursor, pulsing a purging gas for the reactant precursor, pulsing a precursor containing a second metal, pulsing a purging gas for this precursor, pulsing a reactant precursor for the second metal precursor, and pulsing a purging gas for this reactant precursor. The order of the metal precursors can depend on the tendency of the metals to allow diffusion of atoms through the metal to the underlying substrate. The order employed can limit the amount of unwanted atomic diffusion to the substrate surface.
- In an embodiment, a hafnium oxide layer is formed on a substrate mounted in a reaction chamber by ALD using precursor gases individually pulsed into the reaction chamber. Alternately, solid or liquid precursors may be used in an appropriately designed reaction chamber.
-
FIG. 2A depicts an embodiment of an atomiclayer deposition system 200 for processing a layer of hafnium oxide for a dielectric layer containing a hafnium oxide and a lanthanide oxide. The elements depicted are those elements necessary for discussion of embodiments of the present invention such that those skilled in the art may practice various embodiments of the present invention without undue experimentation. A further discussion of the ALD reaction chamber can be found in co-pending, commonly assigned U.S. patent application: entitled “Methods, Systems, and Apparatus for Uniform Chemical-Vapor Depositions,” Ser. No. 09/797,324, filed 1 Mar. 2001, incorporated herein by reference. - In
FIG. 2A , asubstrate 210 is located inside areaction chamber 220 ofALD system 200. Also located withinreaction chamber 220 is aheating element 230, which is thermally coupled tosubstrate 210 to control the substrate temperature. A gas-distribution fixture 240 introduces precursor gases to thesubstrate 210. Each precursor gas originates from individual gas sources 251-254 whose flow is controlled by mass-flow controllers 256-259, respectively. Each gas source, 251-254, provides a precursor gas either by storing the precursor as a gas or by providing a location and apparatus for evaporating a solid or liquid material to form the selected precursor gas. Furthermore, additional gas sources may be included, one for each metal precursor employed and one for each reactant precursor associated with each metal precursor. - Also included in the ALD system are purging
gas sources flow controllers ALD system 200, one purging gas source for each precursor gas. For a process that uses the same purging gas for multiple precursor gases less purging gas sources are used inALD system 200. - Gas sources 251-254 and purging gas sources 261-262 are coupled by their associated mass-flow controllers to a common gas line or
conduit 270, which is coupled to the gas-distribution fixture 240 insidereaction chamber 220.Gas conduit 270 is also coupled to vacuum pump, or exhaust pump, 281 by mass-flow controller 286 to remove excess precursor gases, purging gases, and by-product gases at the end of a purging sequence fromgas conduit 270. - Vacuum pump, or exhaust pump, 282 is coupled by mass-
flow controller 287 to remove excess precursor gases, purging gases, and by-product gases at the end of a purging sequence fromreaction chamber 220. For convenience, control displays, mounting apparatus, temperature sensing devices, substrate maneuvering apparatus, and necessary electrical connections as are known to those skilled in the art are not shown inFIG. 2A . -
FIG. 2B depicts an embodiment of a gas-distribution fixture 240 of atomiclayer deposition system 200 for processing a layer of hafnium oxide for a dielectric layer containing a hafnium oxide and a lanthanide oxide. Gas-distribution fixture 240 includes a gas-distribution member 242, and agas inlet 244.Gas inlet 244 couples gas-distribution member 242 togas conduit 270 ofFIG. 2A . Gas-distribution member 242 includes gas-distribution holes, or orifices, 246 and gas-distribution channels 248. In the illustrated embodiment, holes 246 are substantially circular with a common diameter in the range of 15-20 microns, gas-distribution channels 248 have a common width in the range of 20-45 microns. Thesurface 249 ofgas distribution member 242 having gas-distribution holes 246 is substantially planar and parallel tosubstrate 210 ofFIG. 2A . However, other embodiments use other surface forms as well as shapes and sizes of holes and channels. The distribution and size of holes may also affect deposition thickness and thus might be used to assist thickness control.Holes 246 are coupled through gas-distribution channels 248 togas inlet 244. ThoughALD system 200 is well suited for practicing embodiments of the present invention, other ALD systems commercially available may be used. - Those of ordinary skill in the art of semiconductor fabrication understand the use, construction and fundamental operation of reaction chambers for deposition of material layers. Embodiments of the present invention may be practiced on a variety of such reaction chambers without undue experimentation. Furthermore, one of ordinary skill in the art will comprehend the necessary detection, measurement, and control techniques in the art of semiconductor fabrication upon reading and studying this disclosure.
- The elements of
ALD system 200 may be controlled by a computer. To focus on the use ofALD system 200 in the various embodiments of the present invention, the computer is not shown. Those skilled in the art can appreciate that the individual elements such as pressure control, temperature control, and gas flow withinALD system 200 may be under computer control. In an embodiment, a computer executes instructions stored in a computer readable medium to accurately control the integrated functioning of the elements ofALD system 200 to form a hafnium oxide layer for a dielectric layer containing a hafnium oxide layer and a lanthanide oxide layer. In an embodiment, following the ALD formation of a hafnium oxide layer, a layer of a lanthanide oxide is formed by electron beam evaporation. -
FIG. 3 depicts an electronbeam evaporation system 300 for processing a layer of lanthanide oxide for a dielectric layer containing a hafnium oxide and a lanthanide oxide.Evaporation system 300 includes areaction chamber 305 in which is located asubstrate 310 having asurface 312 that is to be processed.Substrate 310 rests onsubstrate holder 315 and its temperature can be raised above room temperature using aheater 320 with its associatedreflector 325.Evaporation system 300 also includes anelectron gun device 330 regulated byelectron gun controller 335 for depositing material onsubstrate surface 312. - Material evaporated using
electron gun device 330 travels tosubstrate 310 through anionizer ring 345 andshutter 350.Ionizer ring 345 provides supplemental oxygen for processes that require additional oxygen due to lost of oxygen in the evaporation of target materials. For target materials substantially void of oxygen,ionizer ring 345 provides initial oxygen to a film deposited onsubstrate surface 312 that is to undergo a subsequent oxidation process.Shutter 350 is used in conjunction with the control ofelectron gun device 330 to control the growth rate of a film onsubstrate 310. The growth rate is determined using quartz crystal monitors 355, 360. The quartz crystal monitors 355, 360 are coupled to a thickness/rate control 365, typically located outsidereaction chamber 305. - Also located outside
reaction chamber 305 is anoxygen gas source 370 including a mass-flow controller 375. In an embodiment, the oxygen gas source is ozone gas. Mass-flow controller 375 controls the flow of the oxygen source intoreaction chamber 305. Further, avacuum pump 380 withmass flow controller 385 maintains the overall atmosphere ofevaporation system 300 at desired levels prior to, during, and after evaporation. -
Electron gun device 330 can include an electron gun and receptacle for a target material that is to be evaporated. Target material placed in the target receptacle ofelectron gun device 330 is heated by impact from an electron beam from its associated electron gun. The electron beam is generated with an intensity and duration with which to evaporate the material in the target receptacle ofelectron gun device 330. The evaporated material then distributes throughout thereaction chamber 305. The evaporated material and pre-evaporation contaminants are prevented from depositing onsubstrate surface 312 in an unwanted manner byshutter 350. Further, electron gun device can be realized using commercially available devices as are known to those skilled in the art. -
Ionizer ring 345 provides oxygen necessary to compensate for loss of oxygen in the evaporated target material, or to add initial oxygen for subsequent oxidation processing. In one embodiment, it includes a ring with a center axis. The ring has a plurality of openings adapted to direct oxygen flowing toionizer ring 345 fromoxygen gas source 370 towardssubstrate surface 312. Oxygen is uniformly distributed tosubstrate surface 312 byionizer ring 345 positioned generally parallel tosubstrate 310. - The
evaporation chamber 300 can be included as part of an overall processing system includingALD system 200 ofFIG. 2A, 2B . To avoid contamination of the surface of a layer formed by atomic layer deposition,evaporation chamber 300 can be connected toALD system 200 using sealable connections to maintain the substrate, which issubstrate 210 inFIG. 2 andsubstrate 310 ofFIG. 3 , in an appropriate environment between ALD processing of a hafnium oxide layer and electron beam evaporation of a lanthanide oxide layer. Other means as are known to those skilled in the art can be employed for maintaining an appropriate environment between different processing procedures. -
FIG. 4 illustrates a flow diagram of elements for an embodiment of a method to process a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer. This embodiment includes forming a layer of hafnium oxide by atomic layer deposition, atblock 410, and forming a layer of a lanthanide oxide by electron beam evaporation, atblock 420, where the layer of hafnium oxide is adjacent to and in contact with the lanthanide oxide layer. The lanthanide oxide can be selected from Pr2O3, Nd2O3, Sm2O3, Gd2O3, and Dy2O3. In an embodiment the method includes forming the layer of hafnium oxide on a substrate and forming the layer of lanthanide oxide on the layer of hafnium oxide. Alternately, a layer of lanthanide oxide is formed on a substrate and a layer of hafnium oxide is formed on the layer of lanthanide oxide. In an embodiment, the method includes controlling the forming of the layer of hafnium oxide and the layer of the lanthanide oxide to form a lanthanide oxide/hafnium oxide nanolaminate. The nanolaminate may have multiple layers of different lanthanide oxides selected from Pr2O3, Nd2O3, Sm2O3, Gd2O3, and Dy2O3. For a dielectric layer having a hafnium oxide layer and one or more layers of a lanthanide oxide, the combined thickness of lanthanide oxide layers can be limited to a total thickness between about 2 nanometers and about 10 nanometers. Also, for a dielectric layer having a lanthanide oxide layer and one or more layers of hafnium oxide, the combined thickness of hafnium oxide layers can be limited to a total thickness between about 2 nanometers and about 10 nanometers. In an embodiment, hafnium oxide layers are limited to between 2 nanometers and 5 nanometers. In an embodiment, a dielectric layer includes a hafnium oxide layer and multiple layers of lanthanide oxide, where each layer of lanthanide oxide is limited to a thickness between about 2 nanometers and about 10 nanometers. - Performing each atomic layer deposition includes pulsing one or more precursors into a reaction chamber for a predetermined period. The predetermined period is individually controlled for each precursor pulsed into the reaction chamber. Further the substrate is maintained at a selected temperature for each pulsing of a precursor, where the selected temperature is set independently for pulsing each precursor. Additionally, each precursor may be pulsed into the reaction under separate environmental conditions. Appropriate temperatures and pressures are maintained dependent on the nature of the precursor, whether the precursor is a single precursor or a mixture of precursors.
- Using atomic layer deposition, the pulsing of the precursor gases is separated by purging the reaction chamber with a purging gas following each pulsing of a precursor. In an embodiment, nitrogen gas is used as the purging gas following the pulsing of each precursor used in a cycle to form a hafnium oxide layer. Additionally, the reaction chamber may also be purged by evacuating the reaction chamber.
-
FIG. 5 illustrates a flow diagram of elements for an embodiment of a method to process a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electronic beam evaporated lanthanide oxide layer. In an embodiment, the method depicted inFIG. 5 can be used to form a gate dielectric layer for a transistor. This embodiment may be implemented with the atomiclayer deposition system 200 ofFIG. 2A , B, and the electron beam evaporation system ofFIG. 3 . - At
block 505,substrate 210 is prepared.Substrate 210 used for forming a transistor is typically a silicon or silicon containing material. In other embodiments, germanium, gallium arsenide, silicon-on-sapphire substrates, or other suitable substrates may be used. This preparation process may include cleaning ofsubstrate 210 and forming layers and regions of the substrate, such as drains and sources of a metal oxide semiconductor (MOS) transistor, prior to forming a gate dielectric. In an embodiment, the substrate is cleaned to provide an initial substrate depleted of its native oxide. In an embodiment, the initial substrate is cleaned to provide a hydrogen-terminated surface. In an embodiment, a silicon substrate undergoes a final hydrofluoric acid, HF, rinse prior to ALD processing to provide the silicon substrate with a hydrogen-terminated surface without a native silicon oxide layer. - In an embodiment,
substrate 210 is prepared as a chemical oxide-terminated silicon surface prior to forming a hafnium oxide by atomic layer deposition. This preparation allows for forming an interface layer to provide a structure that may further aid in reducing the leakage current through the dielectric layer. - The sequencing of the formation of the regions of the transistor being processed follows typical sequencing that is generally performed in the fabrication of a MOS transistor as is well known to those skilled in the art. Included in the processing is the masking of substrate regions to be protected during the gate dielectric formation, as is typically performed in MOS fabrication. In this embodiment, the unmasked region may include a body region of a transistor; however one skilled in the art will recognize that other semiconductor device structures may utilize this process. Additionally,
substrate 210 in its ready for processing form is conveyed into a position inreaction chamber 220 for ALD processing. - At
block 510, a hafnium-containing precursor is pulsed intoreaction chamber 220. In an embodiment, HfI4 is used as a precursor. In other embodiments, a hafnium-containing precursor includes but is not limited to HfCl4, and Hf(NO3)4. The HfI4 precursor is pulsed intoreaction chamber 220 through the gas-distribution fixture 240 tosubstrate 210. Mass-flow controller 256 regulates the flow of the HfI4 fromgas source 251, where the HfI4 gas is held at a temperature ranging from about 185° C. to about 195° C. In an embodiment, the substrate temperature is maintained between about 500° C. and about 750° C. In an embodiment, the substrate temperature is maintained at about 300° C. In other embodiments, the substrate may be held at lower temperatures lower than 300° C. The HfI4 reacts with the surface of thesubstrate 210 in the desired region defined by the unmasked areas of thesubstrate 210. - At
block 515, a first purging gas is pulsed intoreaction chamber 220. In an embodiment, nitrogen with a purity of about 99.999% is used as a purging gas. Mass-flow controller 266 regulates the nitrogen flow from the purginggas source 261 into thegas conduit 270. Using the pure nitrogen purge avoids overlap of the precursor pulses and possible gas phase reactions. - A first oxygen-containing precursor is pulsed onto
substrate 210, atblock 520. In an embodiment, molecular oxygen is used as a precursor. In other embodiments, an oxygen-containing precursor for a hafnium/oxygen sequence includes but is not limited to H2O, H2O2, an H2O—H2O2 mixture, alcohol (ROH), N2O, or O3. The molecular oxygen precursor is pulsed intoreaction chamber 220 through the gas-distribution fixture 240 onsubstrate 210. Mass-flow controller 257 regulates the flow of the water vapor fromgas source 252. In an embodiment, the substrate temperature is maintained between about 100° C. and about 150° C. The water vapor reacts with at the surface ofsubstrate 210 in the desired region defined by the unmasked areas of thesubstrate 210. - After pulsing the first oxygen-containing precursor, a second purging gas is pulsed, at block, 525. In an embodiment, nitrogen is used as the second purging gas. Excess precursor gas and reaction by-products are removed from the system by the purge gas in conjunction with the exhausting of
reaction chamber 220 usingvacuum pump 282 through mass-flow controller 287, and exhausting of thegas conduit 270 by thevacuum pump 281 through mass-flow controller 286. With the conclusion of the second purging gas pulse, a cycle. for forming an atomic layer deposited hafnium oxide is completed. - In an embodiment using a HfI4/O2 sequence, the substrate may be held between about 500° C. and about 750° C. by the
heating element 230. In an embodiment, the substrate may be held at 300° C. In other embodiments, the substrate may be held at lower temperatures lower than 300° C. The HfI4 precursor can be pulsed for about 2.0 s. After the HfI4 pulse, the hafnium/O2 sequence continues with a purge pulse followed by a O2 pulse followed by a purge pulse. In an embodiment, the O2 pulse time is about 2.0 sec, and the two nitrogen purging pulse times are each at about 2.0 sec. - At
block 530, a determination is made as to whether a desired number of cycles has been performed, that is, whether the number of completed cycles is equal to a predetermined number. The predetermined number corresponds to a predetermined thickness for the ALD hafnium oxide layer. The thickness of the hafnium oxide layer is determined by a fixed growth rate for the pulsing periods and precursors used, set at a value such as N nm/cycle. In an embodiment, a hafnium oxide layer may be grown at a rate ranging from about 0.07 nm/cycle to about 0.12 nm/cycle for an oxygen pressure ranging from about 0.1 Torr to about 0.3 Torr. For a desired dielectric layer thickness, t, the ALD process is repeated for t/N total cycles. Once the t/N cycles have completed, no further ALD processing for the current hafnium oxide layer is performed. - If the number of completed cycles is less than the predetermined number, the hafnium-containing precursor is pulsed into
reaction chamber 220, atblock 510, and the process continues. If the total number of cycles to form the desired thickness for the hafnium oxide layer has been completed, a determination is made as to whether the dielectric layer being formed contains the desired number of layers of a lanthanide oxide, atblock 535. If the desired number of layers of a lanthanide oxide have been made, a determination is made as to whether the desired number of layers of hafnium oxide have been processed, atblock 545. Such a case may occur in embodiments for a dielectric layer having hafnium oxide formed as consecutive layers on a lanthanide oxide layer. If more layers of hafnium oxide are required for the given application, the overall process continues as an atomic layer deposition with the pulsing of a hafnium-containing precursor, atblock 510. - If it is determined, at
block 535, that the desired number of layers of a lanthanide oxide have not been formed, then a layer of lanthanide oxide is formed onsubstrate 210, atblock 540, which may include hafnium oxide layers and other lanthanide oxide layers.Substrate 210 in the ALD system, as illustrated inFIG. 2 , is moved into the evaporation system depicted inFIG. 3 , where thesubstrate 210, with its formed layers, becomessubstrate 310 ofFIG. 3 . To avoid contamination of the surface of a layer formed by atomic layer deposition,evaporation chamber 300 can be connected toALD system 200 using sealable connections to maintain the substrate in an appropriate environment between ALD processing of a hafnium oxide layer and electron beam evaporation of a lanthanide oxide layer. Other means as are known to those skilled in the art can be employed for maintaining an appropriate environment between different processing procedures. -
Substrate 310, suitably masked for the given application and process procedures, is moved intoevaporation chamber 305.Electron gun 330 contains a receptacle for a source target on which an electron beam is directed.Electron gun controller 335 regulates the rate of evaporation of material from the target source. Alternatively,evaporation chamber 305 can include multiple electron guns, where each electron gun is directed to different targets containing sources to form selected lanthanide oxides to be used at different times in the process. - In an embodiment, the target source of
electron gun 330 contains a ceramic Pr6O11 source, which is evaporated due to the impact of the electron beam. The evaporated material is then distributed throughout thechamber 305. A dielectric layer of Pr2O3 is grown onsurface 312 ofsubstrate 310, which is maintained at a temperature ranging from about 100° C. to about 150° C. The growth rate can vary with a typical rate of 0.1 Å/s. In an embodiment in which a lanthanide is first formed on a substrate prior to forming a hafnium oxide layer, a Pr2O3 layer may include a thin amorphous interfacial layer separating a crystalline layer of Pr2O3 from the substrate on which it is grown. This thin amorphous layer may be beneficial in reducing the number of interface charges and eliminating any grain boundary paths for conductance from the substrate. Other source materials can be used for forming a Pr2O3 layer, as are known to those skilled in the art. - Alternately, the lanthanide oxide layer formed by electron beam evaporation for a dielectric layer containing an atomic layer deposited hafnium oxide and a lanthanide oxide can be an oxide selected from Nd2O3, Sm2O3, Gd2O3, or Dy2O3. Further, a dielectric layer may include a number of hafnium oxide layers and a number of lanthanide oxide layers, where the lanthanide oxide layers are different lanthanide oxides. The different lanthanide oxides can be selected from Pr2O3, Nd2O3, Sm2O3, Gd2O3, and Dy2O3. The source material for the particular lanthanide oxide is chosen from commercial materials for forming the lanthanide oxide by electron bean evaporation, as is known by those skilled in the art.
- After forming the layer of lanthanide oxide, at
block 540, a determination is made as to whether the desired number of hafnium oxide layers has been formed, atblock 545. If the desired number of hafnium oxide layers has not been formed,substrate 310 is moved back into atomiclayer deposition system 200 and a hafnium-containing precursor is pulsed, atblock 510 and the process continues. If it is determined that the desired number of hafnium oxide layers have been formed, atblock 545, it is then determined whether the desired number of layers of a lanthanide oxide have been formed, atblock 550. If the desired number of lanthanide oxide layers has not been formed, a layer of lanthanide oxide is formed by electron beam evaporation, atblock 540, and the process continues. If is determined that the desired number of lanthanide oxide layers have been formed, atblock 550, and if the desired number of hafnium oxide layers have been formed, then the substrate is further processed to complete device processing, atblock 555. - If the dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide has been formed to have the desired thickness, the growth of the dielectric layer is complete. The dielectric layer may be annealed. To avoid the diffusion of oxygen during annealing to the semiconductor substrate surface, annealing may be performed in an oxygen-free environment for short periods of time. An embodiment of an annealing environment may include a nitrogen atmosphere. In addition to limiting or avoiding oxygen diffusion to the semiconductor substrate, the relatively low processing temperatures employed by atomic layer deposition of the hafnium oxide layers and by electron beam evaporation of the lanthanide layers allows for the formation of an amorphous dielectric layer.
- At
block 555, after forming the dielectric film containing atomic layer deposited hafnium oxide and electron beam deposited lanthanide oxide, processing the device having this dielectric layer is completed. In an embodiment, completing the device includes completing the formation of a transistor. In an embodiment, completing the device includes completing the formation of a capacitor. In an embodiment, completing the process includes completing the construction of a memory device having an array with access transistors formed with gate dielectrics containing atomic layer deposited hafnium oxide and electron beam deposited lanthanide oxide. In an embodiment, completing the process includes the formation of an electronic system including an information handling device that uses electronic devices with transistors formed with dielectric layers having an atomic layer deposited hafnium oxide and an electron beam deposited lanthanide oxide. - Upon reading and comprehending this disclosure, it can be appreciated by those skilled in the art that the elements of a method for forming a dielectric layer containing atomic layer deposited hafnium oxide and electron beam deposited lanthanide oxide in the embodiment of
FIG. 5 may be performed under various environmental conditions, including various pressures and temperatures, and pulse periods depending on the dielectric layer to be formed for a given application and the systems used to fabricate such a dielectric layer. Determination of the environmental conditions, precursors used, purging gases employed, pulse periods for the precursors and purging gases, and electron beam target materials may be made without undue experimentation. - The elements for a method for forming a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam deposited lanthanide oxide as illustrated in
FIG. 5 can vary and include numerous permutations. In an embodiment, an atomic layer deposited hafnium oxide layer is formed on a substrate and an electron beam evaporated lanthanide oxide layer is formed on the hafnium oxide layer. Alternately, an electron beam evaporated lanthanide oxide layer is formed on a substrate and an atomic layer deposited hafnium oxide layer is deposited on the lanthanide oxide layer. A hafnium oxide layer may be formed as multiple layers of atomic layer deposited hafnium oxide. Similarly, a lanthanide oxide layer may be formed as multiple layers of an electron beam evaporated lanthanide oxide. Additionally, a dielectric layer may contain multiple layers of lanthanide oxide, where two or more layers contain different lanthanide oxides selected from Pr2O3, Nd2O3, Sm2O3, Gd2O3, and Dy2O3. - In an embodiment, a dielectric containing hafnium oxide and lanthanide oxide is formed as a nanolaminate. The nanolaminate may have multiple layers of different lanthanide oxides selected from Pr2O3, Nd2O3, Sm2O3, Gd2O3, and Dy2O3. For a dielectric layer having a hafnium oxide layer and one or more layers of a lanthanide oxide, the combined thickness of lanthanide oxide layers can be limited to a total thickness between about 2 nanometers and about 10 nanometers. Also, for a dielectric layer having a lanthanide oxide layer and one or more layers of hafnium oxide, the combined thickness of hafnium oxide layers can be limited to a total thickness between about 2 nanometers and about 10 nanometers. In an embodiment, hafnium oxide layers are limited to between 2 nanometers and 5 nanometers. In an embodiment, a dielectric layer includes a hafnium oxide layer and multiple layers of lanthanide oxide, where each layer of lanthanide oxide is limited to a thickness between about 2 nanometers and about 10 nanometers. In an embodiment, a dielectric layer includes a lanthanide oxide layer and multiple layers of hafnium oxide, where each layer of hafnium oxide is limited to a thickness between about 2 nanometers and about 10 nanometers. In an embodiment, a dielectric layer containing an atomic layer deposited hafnium oxide layer and an electron beam evaporated lanthanide oxide layer has a thickness ranging from about 2 nanometers to about 20 nanometers.
- A dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam deposited lanthanide oxide may be processed in an atomic layer deposition system such as
ALD system 200 andevaporation system 300 under computer control to perform various embodiments, and operated under computer-executable instructions to perform these embodiments. Instructions stored in a computer readable medium are executed by a computer to accurately control the integrated functioning of the elements of atomiclayer deposition system 200 andevaporation system 300 to form a dielectric layer containing hafnium oxide and a lanthanide oxide, according to various embodiments. The computer-executable instructions may be provided in any computer-readable medium. Such computer-readable medium may include, but is not limited to, floppy disks, diskettes, hard disks, CD-ROMS, flash ROMS, nonvolatile ROM, and RAM. - Dielectric layers containing hafnium oxide layers and lanthanide oxide layers can have a wide range of dielectric constants determined by the series configuration and relative thickness of the hafnium oxide layers and the lanthanide oxide layers. In bulk form, HfO2 has a dielectric constant of about 25. Bulk Pr2O3 has a dielectric constant of about 31, while the dielectric constants for Nd2O3, Sm2O3, Gd2O3, and Dy2O3, in bulk form, are generally also in the range of 25-30. Consequently, a dielectric layer containing bulk layers of hafnium oxide and lanthanide oxide could be expected to have a dielectric constant engineered in the range from about 25 to about 31. Such a dielectric layer would have a teq that is about one-sixth to one-eight smaller than a silicon oxide layer of the same thickness.
- However, a thin dielectric layer with an interfacial layer formed between the surface of the substrate and the first layer of a hafnium oxide or a lanthanide oxide will have a teq that is based on an interfacial layer physically in parallel with the dielectric layer equivalently forming a series configuration of electrical structures. Thus, the dielectric layer formed having an interfacial layer between it and the substrate on which it is grown can have an effective dielectric constant considerably less than a dielectric constant associated with the combination of hafnium oxide and lanthanide oxide layers.
- Effective dielectric constants associated with thin layers of Pr2O3, Nd2O3, Sm2O3, Gd2O3, and Dy2O3 oxides on silicon have been reported to have dielectric constants in the range of 11 to 15 with interfacial regions having a thickness in the of about 0.5 nm to about 1.1 nm. See J. Sanghun et al., Technical Digest of International Electron Devices Meetings 2001, pp. 471-474 (2001). Similarly, HfO2 also has been reported to have an effective dielectric constant reduced from its bulk value to a value in the range of 12 to 16 when formed as a thin layer on a silicon substrate with an interfacial layer. See K. Kukli et al., Journal of Applied Physics, vol. 92: no. 10, pp. 5698-5703 (2002). The effective dielectric constants for thin dielectric layers containing any of these materials and/or combinations of these materials may be reduced from their bulk value depending on the thickness and material composition of any interfacial layer that may be formed.
- Further, for those cases in which a dielectric layer containing hafnium oxide and lanthanide oxide is formed with little or no interfacial layer, the dielectric layer may be subject to a thin film effect related to the abrupt termination of the film. A planar bulk or thick film can be considered as a bulk region with two surface regions. Due to the termination of the thick film, the properties of the two surface regions can vary from that of the bulk region. In a thick film, the effective properties of the film are dominated by the bulk region. In a thin film, including nanolaminates, the properties of the thin film are effectively controlled by two surface regions. See K. Natori et al., Applied Physics Letters, vol. 73: no. 5, pp. 632-634 (1998). Thus, thin films of hafnium oxide and lanthanide oxide may have effective dielectric constants reduced from their bulk values without being formed in a structure with interfacial regions. Without a size effect, dielectric layers containing hafnium oxide and lanthanide oxide may have a dielectric constant in the range of about 25 to about 31. With a size effect, dielectric layers containing hafnium oxide and lanthanide oxide may have dielectric constants in the range from about 11 to about 16.
- The embodiments described herein provide a process for growing a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide having a wide range of useful equivalent oxide thickness, teq. The relatively large dielectric constant for such a dielectric layer ranges from about 11 to about 31, depending on the presence of an interfacial layer and/or on a size effect. Forming a dielectric layer according to various embodiments with a thickness ranging from 2 nanometers to 20 nanometers allows for the engineering of dielectric layers achieving a teq in the range of about 0.7 nanometers to about 7 nanometers. Without an interfacial layer and without a size effect, the teq for such a dielectric layer may range from about 0.25 nanometers to about 2.5 nanometers. A dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide may be formed for applications with a teq between 10 Å and 20 Å, or less than 10 Å.
- Dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide using embodiments of the present invention may be engineered with various structures and compositions including an amorphous structure. Embodiments using low processing temperatures tend to provide an amorphous structure, which is better suited for reducing leakage current than structures exhibiting a polycrystalline structure or a partial polycrystalline structure.
-
FIG. 6 depicts ananolaminate structure 600 for an embodiment of a dielectric structure including atomic layer deposited hafnium oxide and electron beam evaporated lanthanide oxide.Nanolaminate structure 600 includes a plurality of layers 605-1 to 605-N, where each layer contains atomic layer deposited hafnium oxide or electron beam evaporated lanthanide oxide. The sequencing of the layers depends on the application. The effective dielectric constant associated withnanolaminate structure 600 is that attributable to N capacitors in series, where each capacitor has a thickness defined by the thickness of the corresponding electron beam evaporated lanthanide oxide or atomic layer deposited hafnium oxide layer. By selecting each thickness and the composition of each layer, electron beam evaporated lanthanide oxide or atomic layer deposited hafnium oxide layer, a nanolaminate structure can be engineered to have a predetermined dielectric constant. - Embodiments for forming a dielectric layer including ALD processing of a hafnium oxide and processing of an lanthanide oxide by electron beam evaporation may be implemented to form transistors, capacitors, memory devices, and other electronic systems including electro-optic devices, microwave devices, and information handling devices. With careful preparation and engineering of the dielectric layer limiting the size of interfacial regions, a teq less than about 10 Å for these devices is anticipated.
- A
transistor 100 as depicted inFIG. 1 may be constructed by forming asource region 120 and adrain region 130 in a silicon basedsubstrate 110 where source and drainregions body region 132.Body region 132 defines a channel having achannel length 134. A dielectric layer is disposed onsubstrate 110 formed as a layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide. The resulting dielectric layer formsgate dielectric 140. - A
gate 150 is formed overgate dielectric 140. Typically, forminggate 150 may include forming a polysilicon layer, though a metal gate may be formed in an alternative process. Aninterfacial layer 133 may form betweenbody region 132 andgate dielectric 140.Interfacial layer 133 may be limited to a thickness less than 1 nanometer, or to a thickness significantly less than 1 nanometer as to be effectively eliminated. Forming the substrate, the source and drain regions, and the gate is performed using standard processes known to those skilled in the art. Additionally, the sequencing of the various elements of the process for forming a transistor is conducted with standard fabrication processes, also as known to those skilled in the art. - The method for forming a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide in various embodiments may be applied to other transistor structures having dielectric layers.
FIG. 7 shows an embodiment of a configuration of atransistor 700 having a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide.Transistor 700 includes a silicon basedsubstrate 710 with asource 720 and adrain 730 separated by abody region 732.Body region 732 betweensource 720 and drain 730 defines a channel region having achannel length 734. Located abovebody region 732 is astack 755 including agate dielectric 740, a floatinggate 752, a floatinggate dielectric 742, and acontrol gate 750.Gate dielectric 740 includes a dielectric containing an atomic layer deposited hafnium oxide layer and an electron beam evaporated lanthanide oxide layer as described herein with the remaining elements of thetransistor 700 formed using processes known to those skilled in the art. Alternately, bothgate dielectric 740 and floatinggate dielectric 742 may be formed as dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide in various embodiments as described herein. Aninterfacial layer 733 may form betweenbody region 732 andgate dielectric 740.Interfacial layer 733 may be limited to a thickness less than 1 nanometer, or to a thickness significantly less than 1 nanometer as to be effectively eliminated. - The embodiments of methods for forming dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide may also be applied to forming capacitors in various integrated circuits, memory devices, and electronic systems. In an embodiment for forming a
capacitor 800 illustrated inFIG. 8 , a method includes forming a first conductive layer 810, forming adielectric layer 820 containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide on first conductive layer 810, and forming a secondconductive layer 830 ondielectric layer 820. Aninterfacial layer 815 may form between first conductive layer 810 anddielectric layer 820.Interfacial layer 815 may be limited to a thickness less than 1 nanometer, or to a thickness significantly less than 1 nanometer as to be effectively eliminated. - Transistors, capacitors, and other devices dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide using methods described herein may be implemented into memory devices and electronic systems including information handling devices. Such information devices may include wireless systems, telecommunication systems, and computers. It will be recognized by one skilled in the art that several types of memory devices and electronic systems including information handling devices utilize embodiments of the present invention.
-
FIG. 9 is a simplified block diagram of amemory device 900 using an embodiment of a dielectric containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide.Memory device 900 includes an array ofmemory cells 902,address decoder 904,row access circuitry 906,column access circuitry 908,control circuitry 910, and Input/Output (I/O)circuit 912. The memory is operably coupled to anexternal microprocessor 914, or memory controller for memory accessing.Memory device 900 receives control signals fromprocessor 914, such as WE*, RAS* and CAS* signals, which can be supplied on a system bus.Memory device 900 stores data that is accessed via I/O lines. Each memory cell in a row ofmemory cell array 902 is coupled to a common word line. The word line is coupled to gates of individual transistors, where at least one transistor has a gate coupled to a gate dielectric containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide in accordance with the methods and structure previously described herein. Additionally, each memory cell in a column is coupled to a common bit line. Each cell inmemory array 902 may include a storage capacitor and an access transistor as is conventional in the art. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device ofFIG. 9 has been simplified to focus on embodiments of the present invention. - It will be understood that the above description of a memory device is intended to provide a general understanding of the memory and is not a complete description of all the elements and features of a specific type of memory, such as DRAM (Dynamic Random Access Memory). Further, embodiments are equally applicable to any size and type of memory circuit and are not intended to be limited to the DRAM described above. Other alternative types of devices include SRAM (Static Random Access Memory) or Flash memories. Additionally, the DRAM could be a synchronous DRAM commonly referred to as SGRAM (Synchronous Graphics Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), SDRAM II, and DDR SDRAM (Double Data Rate SDRAM), as well as Synchlink or Rambus DRAMs and other emerging DRAM technologies.
-
FIG. 10 illustrates a block diagram for anelectronic system 1000 having devices with an embodiment for a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide.Electronic system 1000 includes acontroller 1005, abus 1015, and anelectronic device 1025, wherebus 1015 provides electrical conductivity betweencontroller 1005 andelectronic device 1025. In various embodiments,controller 1005 and/orelectronic device 1025 include an embodiment for a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide as previously discussed herein. In an embodiment,electronic system 1000 includes a plurality of electronic devices using an embodiment for a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide according to the present invention.Electronic system 1000 may include, but is not limited to, information handling devices, wireless systems, telecommunication systems, fiber optic systems, electro-optic systems, and computers. - A dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide, using methods described herein, provides a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Forming dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide in relatively low processing temperatures may allow for dielectric layers that are amorphous and conformally layered on a substrate surface. Further, the formation of these dielectric layers provides for enhanced dielectric and electrical properties relative to those attained with an amorphous SiO2 layer. These properties of dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide allow for application as dielectric layers in numerous devices and systems.
- Capacitors, transistors, electro-optic devices, higher level ICs or devices, and electronic systems are constructed utilizing various embodiments for forming a dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide structured to provide an ultra thin equivalent oxide thickness, teq. Dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide are formed having a dielectric constant substantially higher than that of silicon dioxide, where such dielectric layers are capable of a teq thinner than 10 Å, thinner than the expected limit for SiO2 gate dielectrics. The thinner teq of these dielectric layers allows for a higher capacitance than SiO2 gate dielectrics, which provides further effective scaling for microelectronic devices and systems. At the same time, the physical thickness of the dielectric layer containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide is much larger than the SiO2 thickness associated with the teq limit of SiO2. Forming the larger thickness aids in the manufacturing process for gate dielectrics and other dielectric layers.
- Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover any adaptations or variations of the present invention. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments, and other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the present invention includes any other applications in which the above structures and fabrication methods are used. The scope of the present invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Claims (37)
1. An electronic device comprising:
a first conductive region disposed on a substrate;
a dielectric layer disposed on the first conductive region, the dielectric layer including a hafnium oxide layer in contact with a lanthanide oxide layer, the hafnium oxide layer structured as one or more monolayers of hafnium oxide; and
a first conductive region disposed on the dielectric layer, wherein the first conductive region, the dielectric layer, and the second conductive region are structured in a capacitor or in a transistor.
2. The electronic device of claim 1 , wherein the lanthanide oxide layer is disposed as an electron beam evaporated lanthanide oxide layer.
3. The electronic device of claim 1 , wherein the hafnium oxide layer and the lanthanide oxide layer are arranged as a hafnium oxide/lanthanide oxide nanolaminate.
4. The electronic device of claim 1 , wherein the lanthanide oxide layer has a thickness essentially between 2 nanometers and 10 nanometers.
5. The electronic device of claim 1 , wherein the lanthanide oxide layer includes Pr2O3.
6. The electronic device of claim 1 , wherein the dielectric layer includes Nd2O3.
7. The electronic device of claim 1 , wherein the dielectric layer includes Sm2O3.
8. The electronic device of claim 1 , wherein the dielectric layer includes Gd2O3.
9. The electronic device of claim 1 , wherein the dielectric layer includes Dy2O3.
10. A capacitor, comprising:
a first conductive layer disposed on a substrate;
a dielectric layer disposed on the first conductive layer, the dielectric layer including a hafnium oxide layer in contact with a lanthanide oxide layer, the hafnium oxide layer structured as one or more monolayers of hafnium oxide, the hafnium oxide layer and lanthanide oxide layer disposed in a hafnium oxide/lanthanide oxide nanolaminate, the nanolaminate having one or more lanthanide oxide layers; and
a second conductive layer disposed on the dielectric layer, wherein the lanthanide layers of the nanolaminate have a combined thickness ranging from about 2 nanometers to about 10 nanometers.
11. The capacitor of claim 10 , wherein the lanthanide oxide layer includes an electronic beam evaporated lanthanide oxide layer.
12. The capacitor of claim 10 , wherein the hafnium oxide layer is disposed in contact with the first conductive layer.
13. The capacitor of claim 10 , wherein hafnium oxide/lanthanide oxide nanolaminate includes an electron beam evaporated lanthanide oxide layer disposed in contact with the first conductive layer.
14. The capacitor of claim 10 , wherein the lanthanide oxide layer includes one or more of Pr2O3, Nd2O3, Sm2O3, Gd2O3, or Dy2O3.
15. A transistor comprising:
a body region in a substrate between a source region and a drain region;
a dielectric layer disposed on the body region, the dielectric layer including a hafnium oxide layer in contact with a lanthanide oxide layer, the hafnium oxide layer structured as one or more monolayers of hafnium oxide; and
a gate coupled to the dielectric layer.
16. The transistor of claim 15 , wherein the lanthanide oxide layer dielectric layer includes an electron beam evaporated lanthanide oxide layer.
17. The transistor of claim 15 , wherein the hafnium oxide layer and the lanthanide oxide layer are layers in a lanthanide oxide/hafnium oxide nanolaminate.
18. The transistor of claim 15 , wherein the dielectric layer contains multiple electron beam evaporated lanthanide oxide layers with a combined thickness of the multiple electron beam evaporated lanthanide oxide layers ranging from about 2 nanometers and about 10 nanometers.
19. The transistor of claim 15 , wherein the dielectric layer contains multiple hafnium oxide layers, the hafnium oxide layers structured as one or more monolayers of hafnium oxide, the multiple hafnium oxide layers having a combined thickness of the multiple hafnium oxide layers ranging from about 2 nanometers and about 10 nanometers.
20. The transistor of claim 15 , wherein the hafnium oxide layer and the lanthanide oxide layer are layers in a lanthanide oxide/hafnium oxide nanolaminate having multiple layers of lanthanide oxide, each layer of lanthanide oxide limited to a thickness of between about 2 nanometers and about 10 nanometers.
21. The transistor of claim 15 , wherein the lanthanide oxide layer includes a combination of lanthanide oxides, the oxides selected from the group of Pr2O3, Nd2O3, Sm2O3, Gd2O3, and Dy2O3.
22. A memory comprising:
a number of transistors, each transistor including a gate coupled to a dielectric layer, the dielectric layer disposed on a body region in a substrate between a source region and a drain region, the dielectric layer including a hafnium oxide layer in contact with a lanthanide oxide layer, the hafnium oxide layer structured as one or more monolayers of hafnium oxide; and
a number of bit lines, each bit line coupled to one of the number of transistors.
23. The memory of claim 22 , wherein the dielectric layer includes a hafnium oxide/lanthanide oxide nanolaminate such that a combined thickness of the lanthanide oxide layers in the nanolaminate ranges from a thickness of 2 nanometers to 10 nanometers.
24. The memory of claim 22 , wherein the transistor is a transistor in a flash memory and the dielectric layer is an inter-gate dielectric of the transistor.
25. The memory of claim 22 , wherein the dielectric layer is structured as a nanolaminate.
26. The memory of claim 22 , wherein the dielectric layer includes a hafnium oxide/lanthanide oxide nanolaminate having a combined thickness of hafnium oxide layers ranging from about 2 nanometers to about 10 nanometers.
27. The memory of claim 22 , wherein the lanthanide oxide layer includes an electron beam evaporated lanthanide oxide layer having one or more Pr2O3, Nd2O3, Sm2O3, Gd2O3, or Dy2O3.
28. An electronic system comprising:
a controller; and
an electronic device coupled to the controller, wherein at least one of the controller and the electronic device includes a dielectric layer, the dielectric layer including a hafnium oxide layer in contact with a lanthanide oxide layer, the hafnium oxide layer structured as one or more monolayers of hafnium oxide.
29. The electronic system of claim 28 , where the lanthanide oxide layer includes an electron beam evaporated lanthanide oxide layer.
30. The electronic system of claim 28 , wherein the hafnium oxide layer and the lanthanide oxide layer are layers in a lanthanide oxide/hafnium oxide nanolaminate.
31. The electronic system of claim 28 , wherein the dielectric layer contains multiple electron beam evaporated lanthanide oxide layers with a combined thickness of the multiple electron beam evaporated lanthanide oxide layers ranging from about 2 nanometers and about 10 nanometers.
32. The electronic system of claim 28 , wherein the dielectric layer contains multiple hafnium oxide layers with a combined thickness of the multiple hafnium oxide layers ranging from about 2 nanometers and about 10 nanometers.
33. The electronic system of claim 28 , wherein the lanthanide oxide layer includes Pr2O3.
34. The electronic system of claim 28 , wherein the lanthanide oxide layer includes one or more of Nd2O3 or Sm2O3.
35. The electronic system of claim 28 , wherein the lanthanide oxide layer includes one or more of Gd2O3 or Dy2O3.
36. The electronic system of claim 28 , wherein the electronic system includes an information handling device.
37. The electronic system of claim 28 , wherein the electronic system includes a wireless system.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/493,074 US20060261397A1 (en) | 2003-06-24 | 2006-07-26 | Lanthanide oxide/hafnium oxide dielectric layers |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/602,323 US7192824B2 (en) | 2003-06-24 | 2003-06-24 | Lanthanide oxide / hafnium oxide dielectric layers |
US10/931,343 US7312494B2 (en) | 2003-06-24 | 2004-08-31 | Lanthanide oxide / hafnium oxide dielectric layers |
US11/493,074 US20060261397A1 (en) | 2003-06-24 | 2006-07-26 | Lanthanide oxide/hafnium oxide dielectric layers |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/931,343 Division US7312494B2 (en) | 2003-06-24 | 2004-08-31 | Lanthanide oxide / hafnium oxide dielectric layers |
Publications (1)
Publication Number | Publication Date |
---|---|
US20060261397A1 true US20060261397A1 (en) | 2006-11-23 |
Family
ID=34079543
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/602,323 Expired - Lifetime US7192824B2 (en) | 2003-06-24 | 2003-06-24 | Lanthanide oxide / hafnium oxide dielectric layers |
US10/931,343 Expired - Lifetime US7312494B2 (en) | 2003-06-24 | 2004-08-31 | Lanthanide oxide / hafnium oxide dielectric layers |
US11/493,074 Abandoned US20060261397A1 (en) | 2003-06-24 | 2006-07-26 | Lanthanide oxide/hafnium oxide dielectric layers |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/602,323 Expired - Lifetime US7192824B2 (en) | 2003-06-24 | 2003-06-24 | Lanthanide oxide / hafnium oxide dielectric layers |
US10/931,343 Expired - Lifetime US7312494B2 (en) | 2003-06-24 | 2004-08-31 | Lanthanide oxide / hafnium oxide dielectric layers |
Country Status (1)
Country | Link |
---|---|
US (3) | US7192824B2 (en) |
Cited By (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090162551A1 (en) * | 2007-12-21 | 2009-06-25 | Thomas Zilbauer | Hafnium oxide ald process |
US7635634B2 (en) * | 2007-04-16 | 2009-12-22 | Infineon Technologies Ag | Dielectric apparatus and associated methods |
US7662729B2 (en) | 2005-04-28 | 2010-02-16 | Micron Technology, Inc. | Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer |
US7670646B2 (en) | 2002-05-02 | 2010-03-02 | Micron Technology, Inc. | Methods for atomic-layer deposition |
US7687409B2 (en) | 2005-03-29 | 2010-03-30 | Micron Technology, Inc. | Atomic layer deposited titanium silicon oxide films |
US7709402B2 (en) | 2006-02-16 | 2010-05-04 | Micron Technology, Inc. | Conductive layers for hafnium silicon oxynitride films |
US7719065B2 (en) | 2004-08-26 | 2010-05-18 | Micron Technology, Inc. | Ruthenium layer for a dielectric layer containing a lanthanide oxide |
US7727905B2 (en) | 2004-08-02 | 2010-06-01 | Micron Technology, Inc. | Zirconium-doped tantalum oxide films |
US7754618B2 (en) | 2005-02-10 | 2010-07-13 | Micron Technology, Inc. | Method of forming an apparatus having a dielectric containing cerium oxide and aluminum oxide |
US7867919B2 (en) | 2004-08-31 | 2011-01-11 | Micron Technology, Inc. | Method of fabricating an apparatus having a lanthanum-metal oxide dielectric layer |
US7923381B2 (en) | 2002-12-04 | 2011-04-12 | Micron Technology, Inc. | Methods of forming electronic devices containing Zr-Sn-Ti-O films |
US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
US7989290B2 (en) | 2005-08-04 | 2011-08-02 | Micron Technology, Inc. | Methods for forming rhodium-based charge traps and apparatus including rhodium-based charge traps |
US8084808B2 (en) | 2005-04-28 | 2011-12-27 | Micron Technology, Inc. | Zirconium silicon oxide films |
US8084370B2 (en) | 2006-08-31 | 2011-12-27 | Micron Technology, Inc. | Hafnium tantalum oxynitride dielectric |
US8102013B2 (en) | 2005-03-29 | 2012-01-24 | Micron Technology, Inc. | Lanthanide doped TiOx films |
US8110469B2 (en) | 2005-08-30 | 2012-02-07 | Micron Technology, Inc. | Graded dielectric layers |
US8154066B2 (en) | 2004-08-31 | 2012-04-10 | Micron Technology, Inc. | Titanium aluminum oxide films |
US8278225B2 (en) | 2005-01-05 | 2012-10-02 | Micron Technology, Inc. | Hafnium tantalum oxide dielectrics |
US8445952B2 (en) | 2002-12-04 | 2013-05-21 | Micron Technology, Inc. | Zr-Sn-Ti-O films |
US9496355B2 (en) | 2005-08-04 | 2016-11-15 | Micron Technology, Inc. | Conductive nanoparticles |
Families Citing this family (401)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6969539B2 (en) | 2000-09-28 | 2005-11-29 | President And Fellows Of Harvard College | Vapor deposition of metal oxides, silicates and phosphates, and silicon dioxide |
US6852167B2 (en) * | 2001-03-01 | 2005-02-08 | Micron Technology, Inc. | Methods, systems, and apparatus for uniform chemical-vapor depositions |
US7476925B2 (en) * | 2001-08-30 | 2009-01-13 | Micron Technology, Inc. | Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators |
US8026161B2 (en) * | 2001-08-30 | 2011-09-27 | Micron Technology, Inc. | Highly reliable amorphous high-K gate oxide ZrO2 |
US7068544B2 (en) * | 2001-08-30 | 2006-06-27 | Micron Technology, Inc. | Flash memory with low tunnel barrier interpoly insulators |
US6900122B2 (en) * | 2001-12-20 | 2005-05-31 | Micron Technology, Inc. | Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics |
US6953730B2 (en) | 2001-12-20 | 2005-10-11 | Micron Technology, Inc. | Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics |
US7045430B2 (en) * | 2002-05-02 | 2006-05-16 | Micron Technology Inc. | Atomic layer-deposited LaAlO3 films for gate dielectrics |
US7589029B2 (en) * | 2002-05-02 | 2009-09-15 | Micron Technology, Inc. | Atomic layer deposition and conversion |
US7205218B2 (en) * | 2002-06-05 | 2007-04-17 | Micron Technology, Inc. | Method including forming gate dielectrics having multiple lanthanide oxide layers |
US7135421B2 (en) * | 2002-06-05 | 2006-11-14 | Micron Technology, Inc. | Atomic layer-deposited hafnium aluminum oxide |
US7221586B2 (en) | 2002-07-08 | 2007-05-22 | Micron Technology, Inc. | Memory utilizing oxide nanolaminates |
US6921702B2 (en) * | 2002-07-30 | 2005-07-26 | Micron Technology Inc. | Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics |
US6790791B2 (en) * | 2002-08-15 | 2004-09-14 | Micron Technology, Inc. | Lanthanide doped TiOx dielectric films |
US6884739B2 (en) * | 2002-08-15 | 2005-04-26 | Micron Technology Inc. | Lanthanide doped TiOx dielectric films by plasma oxidation |
US7199023B2 (en) * | 2002-08-28 | 2007-04-03 | Micron Technology, Inc. | Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed |
US7084078B2 (en) * | 2002-08-29 | 2006-08-01 | Micron Technology, Inc. | Atomic layer deposited lanthanide doped TiOx dielectric films |
US7037863B2 (en) * | 2002-09-10 | 2006-05-02 | Samsung Electronics Co., Ltd. | Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices |
US7192892B2 (en) * | 2003-03-04 | 2007-03-20 | Micron Technology, Inc. | Atomic layer deposited dielectric layers |
US7135369B2 (en) * | 2003-03-31 | 2006-11-14 | Micron Technology, Inc. | Atomic layer deposited ZrAlxOy dielectric layers including Zr4AlO9 |
US7183186B2 (en) * | 2003-04-22 | 2007-02-27 | Micro Technology, Inc. | Atomic layer deposited ZrTiO4 films |
US7192824B2 (en) * | 2003-06-24 | 2007-03-20 | Micron Technology, Inc. | Lanthanide oxide / hafnium oxide dielectric layers |
US7049192B2 (en) * | 2003-06-24 | 2006-05-23 | Micron Technology, Inc. | Lanthanide oxide / hafnium oxide dielectrics |
US20060125030A1 (en) * | 2004-12-13 | 2006-06-15 | Micron Technology, Inc. | Hybrid ALD-CVD of PrxOy/ZrO2 films as gate dielectrics |
US7235501B2 (en) * | 2004-12-13 | 2007-06-26 | Micron Technology, Inc. | Lanthanum hafnium oxide dielectrics |
US7508648B2 (en) * | 2005-02-08 | 2009-03-24 | Micron Technology, Inc. | Atomic layer deposition of Dy doped HfO2 films as gate dielectrics |
US7399666B2 (en) * | 2005-02-15 | 2008-07-15 | Micron Technology, Inc. | Atomic layer deposition of Zr3N4/ZrO2 films as gate dielectrics |
US7498247B2 (en) | 2005-02-23 | 2009-03-03 | Micron Technology, Inc. | Atomic layer deposition of Hf3N4/HfO2 films as gate dielectrics |
US7572695B2 (en) * | 2005-05-27 | 2009-08-11 | Micron Technology, Inc. | Hafnium titanium oxide films |
US7510983B2 (en) * | 2005-06-14 | 2009-03-31 | Micron Technology, Inc. | Iridium/zirconium oxide structure |
US7195999B2 (en) | 2005-07-07 | 2007-03-27 | Micron Technology, Inc. | Metal-substituted transistor gates |
US7393736B2 (en) * | 2005-08-29 | 2008-07-01 | Micron Technology, Inc. | Atomic layer deposition of Zrx Hfy Sn1-x-y O2 films as high k gate dielectrics |
US20070049023A1 (en) * | 2005-08-29 | 2007-03-01 | Micron Technology, Inc. | Zirconium-doped gadolinium oxide films |
US7544596B2 (en) | 2005-08-30 | 2009-06-09 | Micron Technology, Inc. | Atomic layer deposition of GdScO3 films as gate dielectrics |
US7410910B2 (en) * | 2005-08-31 | 2008-08-12 | Micron Technology, Inc. | Lanthanum aluminum oxynitride dielectric films |
US8071476B2 (en) | 2005-08-31 | 2011-12-06 | Micron Technology, Inc. | Cobalt titanium oxide dielectric films |
US20070045752A1 (en) * | 2005-08-31 | 2007-03-01 | Leonard Forbes | Self aligned metal gates on high-K dielectrics |
KR100809685B1 (en) * | 2005-09-13 | 2008-03-06 | 삼성전자주식회사 | Dielectric film, Method of manufacturing the dielectric film and method of manufacturing capacitor using the same |
US20070093004A1 (en) * | 2005-10-25 | 2007-04-26 | Park Sang H | Method of manufacturing thin film transistor including ZnO thin layer |
TW200720499A (en) * | 2005-11-24 | 2007-06-01 | Univ Nat Tsing Hua | Manufacturing method of substrate used for forming MOSFET device and products thereof |
US7972974B2 (en) * | 2006-01-10 | 2011-07-05 | Micron Technology, Inc. | Gallium lanthanide oxide films |
US7700438B2 (en) * | 2006-01-30 | 2010-04-20 | Freescale Semiconductor, Inc. | MOS device with nano-crystal gate structure |
JP2007266438A (en) * | 2006-03-29 | 2007-10-11 | Hitachi Ltd | Semiconductor memory device |
US7582161B2 (en) | 2006-04-07 | 2009-09-01 | Micron Technology, Inc. | Atomic layer deposited titanium-doped indium oxide films |
US7956168B2 (en) * | 2006-07-06 | 2011-06-07 | Praxair Technology, Inc. | Organometallic compounds having sterically hindered amides |
US7985995B2 (en) | 2006-08-03 | 2011-07-26 | Micron Technology, Inc. | Zr-substituted BaTiO3 films |
US7749879B2 (en) * | 2006-08-03 | 2010-07-06 | Micron Technology, Inc. | ALD of silicon films on germanium |
US7727908B2 (en) | 2006-08-03 | 2010-06-01 | Micron Technology, Inc. | Deposition of ZrA1ON films |
US7582549B2 (en) * | 2006-08-25 | 2009-09-01 | Micron Technology, Inc. | Atomic layer deposited barium strontium titanium oxide films |
US7563730B2 (en) | 2006-08-31 | 2009-07-21 | Micron Technology, Inc. | Hafnium lanthanide oxynitride films |
US7776765B2 (en) | 2006-08-31 | 2010-08-17 | Micron Technology, Inc. | Tantalum silicon oxynitride high-k dielectrics and metal gates |
US7544604B2 (en) * | 2006-08-31 | 2009-06-09 | Micron Technology, Inc. | Tantalum lanthanide oxynitride films |
US20080057659A1 (en) * | 2006-08-31 | 2008-03-06 | Micron Technology, Inc. | Hafnium aluminium oxynitride high-K dielectric and metal gates |
US7759747B2 (en) * | 2006-08-31 | 2010-07-20 | Micron Technology, Inc. | Tantalum aluminum oxynitride high-κ dielectric |
US7432548B2 (en) * | 2006-08-31 | 2008-10-07 | Micron Technology, Inc. | Silicon lanthanide oxynitride films |
US8986456B2 (en) | 2006-10-10 | 2015-03-24 | Asm America, Inc. | Precursor delivery system |
US20080087890A1 (en) * | 2006-10-16 | 2008-04-17 | Micron Technology, Inc. | Methods to form dielectric structures in semiconductor devices and resulting devices |
US8287647B2 (en) * | 2007-04-17 | 2012-10-16 | Lam Research Corporation | Apparatus and method for atomic layer deposition |
US8367506B2 (en) * | 2007-06-04 | 2013-02-05 | Micron Technology, Inc. | High-k dielectrics with gold nano-particles |
JP4863296B2 (en) * | 2007-06-22 | 2012-01-25 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
US7662693B2 (en) | 2007-09-26 | 2010-02-16 | Micron Technology, Inc. | Lanthanide dielectric with controlled interfaces |
US8076237B2 (en) * | 2008-05-09 | 2011-12-13 | Asm America, Inc. | Method and apparatus for 3D interconnect |
US10378106B2 (en) | 2008-11-14 | 2019-08-13 | Asm Ip Holding B.V. | Method of forming insulation film by modified PEALD |
US9394608B2 (en) | 2009-04-06 | 2016-07-19 | Asm America, Inc. | Semiconductor processing reactor and components thereof |
US8071452B2 (en) * | 2009-04-27 | 2011-12-06 | Asm America, Inc. | Atomic layer deposition of hafnium lanthanum oxides |
US8877655B2 (en) | 2010-05-07 | 2014-11-04 | Asm America, Inc. | Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species |
US8802201B2 (en) | 2009-08-14 | 2014-08-12 | Asm America, Inc. | Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species |
US8883270B2 (en) | 2009-08-14 | 2014-11-11 | Asm America, Inc. | Systems and methods for thin-film deposition of metal oxides using excited nitrogen—oxygen species |
US8030725B1 (en) * | 2010-10-05 | 2011-10-04 | Skyworks Solutions, Inc. | Apparatus and methods for detecting evaporation conditions |
US9312155B2 (en) | 2011-06-06 | 2016-04-12 | Asm Japan K.K. | High-throughput semiconductor-processing apparatus equipped with multiple dual-chamber modules |
US9793148B2 (en) | 2011-06-22 | 2017-10-17 | Asm Japan K.K. | Method for positioning wafers in multiple wafer transport |
US10364496B2 (en) | 2011-06-27 | 2019-07-30 | Asm Ip Holding B.V. | Dual section module having shared and unshared mass flow controllers |
US10854498B2 (en) | 2011-07-15 | 2020-12-01 | Asm Ip Holding B.V. | Wafer-supporting device and method for producing same |
US20130023129A1 (en) | 2011-07-20 | 2013-01-24 | Asm America, Inc. | Pressure transmitter for a semiconductor processing environment |
US9096931B2 (en) | 2011-10-27 | 2015-08-04 | Asm America, Inc | Deposition valve assembly and method of heating the same |
US9341296B2 (en) | 2011-10-27 | 2016-05-17 | Asm America, Inc. | Heater jacket for a fluid line |
US9017481B1 (en) | 2011-10-28 | 2015-04-28 | Asm America, Inc. | Process feed management for semiconductor substrate processing |
US9005539B2 (en) | 2011-11-23 | 2015-04-14 | Asm Ip Holding B.V. | Chamber sealing member |
US9167625B2 (en) | 2011-11-23 | 2015-10-20 | Asm Ip Holding B.V. | Radiation shielding for a substrate holder |
US9202727B2 (en) | 2012-03-02 | 2015-12-01 | ASM IP Holding | Susceptor heater shim |
US8946830B2 (en) | 2012-04-04 | 2015-02-03 | Asm Ip Holdings B.V. | Metal oxide protective layer for a semiconductor device |
US9029253B2 (en) | 2012-05-02 | 2015-05-12 | Asm Ip Holding B.V. | Phase-stabilized thin films, structures and devices including the thin films, and methods of forming same |
US8728832B2 (en) | 2012-05-07 | 2014-05-20 | Asm Ip Holdings B.V. | Semiconductor device dielectric interface layer |
US8933375B2 (en) | 2012-06-27 | 2015-01-13 | Asm Ip Holding B.V. | Susceptor heater and method of heating a substrate |
US9558931B2 (en) | 2012-07-27 | 2017-01-31 | Asm Ip Holding B.V. | System and method for gas-phase sulfur passivation of a semiconductor surface |
US9117866B2 (en) | 2012-07-31 | 2015-08-25 | Asm Ip Holding B.V. | Apparatus and method for calculating a wafer position in a processing chamber under process conditions |
US9169975B2 (en) | 2012-08-28 | 2015-10-27 | Asm Ip Holding B.V. | Systems and methods for mass flow controller verification |
US9659799B2 (en) | 2012-08-28 | 2017-05-23 | Asm Ip Holding B.V. | Systems and methods for dynamic semiconductor process scheduling |
CN103681269B (en) * | 2012-09-03 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | The method of selectively formed high-K dielectric layer |
US9021985B2 (en) | 2012-09-12 | 2015-05-05 | Asm Ip Holdings B.V. | Process gas management for an inductively-coupled plasma deposition reactor |
US9324811B2 (en) | 2012-09-26 | 2016-04-26 | Asm Ip Holding B.V. | Structures and devices including a tensile-stressed silicon arsenic layer and methods of forming same |
JP6147480B2 (en) * | 2012-09-26 | 2017-06-14 | 株式会社日立国際電気 | Semiconductor device manufacturing method, substrate processing apparatus, and program |
US10714315B2 (en) | 2012-10-12 | 2020-07-14 | Asm Ip Holdings B.V. | Semiconductor reaction chamber showerhead |
US9640416B2 (en) | 2012-12-26 | 2017-05-02 | Asm Ip Holding B.V. | Single-and dual-chamber module-attachable wafer-handling chamber |
US8894870B2 (en) | 2013-02-01 | 2014-11-25 | Asm Ip Holding B.V. | Multi-step method and apparatus for etching compounds containing a metal |
US9484191B2 (en) | 2013-03-08 | 2016-11-01 | Asm Ip Holding B.V. | Pulsed remote plasma method and system |
US9589770B2 (en) | 2013-03-08 | 2017-03-07 | Asm Ip Holding B.V. | Method and systems for in-situ formation of intermediate reactive species |
US8993054B2 (en) | 2013-07-12 | 2015-03-31 | Asm Ip Holding B.V. | Method and system to reduce outgassing in a reaction chamber |
US9018111B2 (en) | 2013-07-22 | 2015-04-28 | Asm Ip Holding B.V. | Semiconductor reaction chamber with plasma capabilities |
US9793115B2 (en) | 2013-08-14 | 2017-10-17 | Asm Ip Holding B.V. | Structures and devices including germanium-tin films and methods of forming same |
US9396934B2 (en) | 2013-08-14 | 2016-07-19 | Asm Ip Holding B.V. | Methods of forming films including germanium tin and structures and devices including the films |
US9240412B2 (en) | 2013-09-27 | 2016-01-19 | Asm Ip Holding B.V. | Semiconductor structure and device and methods of forming same using selective epitaxial process |
US9556516B2 (en) | 2013-10-09 | 2017-01-31 | ASM IP Holding B.V | Method for forming Ti-containing film by PEALD using TDMAT or TDEAT |
US9605343B2 (en) | 2013-11-13 | 2017-03-28 | Asm Ip Holding B.V. | Method for forming conformal carbon films, structures conformal carbon film, and system of forming same |
US10179947B2 (en) | 2013-11-26 | 2019-01-15 | Asm Ip Holding B.V. | Method for forming conformal nitrided, oxidized, or carbonized dielectric film by atomic layer deposition |
US10683571B2 (en) | 2014-02-25 | 2020-06-16 | Asm Ip Holding B.V. | Gas supply manifold and method of supplying gases to chamber using same |
US10167557B2 (en) | 2014-03-18 | 2019-01-01 | Asm Ip Holding B.V. | Gas distribution system, reactor including the system, and methods of using the same |
US9447498B2 (en) | 2014-03-18 | 2016-09-20 | Asm Ip Holding B.V. | Method for performing uniform processing in gas system-sharing multiple reaction chambers |
US11015245B2 (en) | 2014-03-19 | 2021-05-25 | Asm Ip Holding B.V. | Gas-phase reactor and system having exhaust plenum and components thereof |
US9404587B2 (en) | 2014-04-24 | 2016-08-02 | ASM IP Holding B.V | Lockout tagout for semiconductor vacuum valve |
US10858737B2 (en) | 2014-07-28 | 2020-12-08 | Asm Ip Holding B.V. | Showerhead assembly and components thereof |
US9543180B2 (en) | 2014-08-01 | 2017-01-10 | Asm Ip Holding B.V. | Apparatus and method for transporting wafers between wafer carrier and process tool under vacuum |
US9890456B2 (en) | 2014-08-21 | 2018-02-13 | Asm Ip Holding B.V. | Method and system for in situ formation of gas-phase compounds |
US10941490B2 (en) | 2014-10-07 | 2021-03-09 | Asm Ip Holding B.V. | Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same |
US9657845B2 (en) | 2014-10-07 | 2017-05-23 | Asm Ip Holding B.V. | Variable conductance gas distribution apparatus and method |
KR102300403B1 (en) | 2014-11-19 | 2021-09-09 | 에이에스엠 아이피 홀딩 비.브이. | Method of depositing thin film |
KR102263121B1 (en) | 2014-12-22 | 2021-06-09 | 에이에스엠 아이피 홀딩 비.브이. | Semiconductor device and manufacuring method thereof |
US9478415B2 (en) | 2015-02-13 | 2016-10-25 | Asm Ip Holding B.V. | Method for forming film having low resistance and shallow junction depth |
US10529542B2 (en) | 2015-03-11 | 2020-01-07 | Asm Ip Holdings B.V. | Cross-flow reactor and method |
US10276355B2 (en) | 2015-03-12 | 2019-04-30 | Asm Ip Holding B.V. | Multi-zone reactor, system including the reactor, and method of using the same |
US10458018B2 (en) | 2015-06-26 | 2019-10-29 | Asm Ip Holding B.V. | Structures including metal carbide material, devices including the structures, and methods of forming same |
US9613870B2 (en) | 2015-06-30 | 2017-04-04 | International Business Machines Corporation | Gate stack formed with interrupted deposition processes and laser annealing |
US10600673B2 (en) | 2015-07-07 | 2020-03-24 | Asm Ip Holding B.V. | Magnetic susceptor to baseplate seal |
US9899291B2 (en) | 2015-07-13 | 2018-02-20 | Asm Ip Holding B.V. | Method for protecting layer by forming hydrocarbon-based extremely thin film |
US10043661B2 (en) | 2015-07-13 | 2018-08-07 | Asm Ip Holding B.V. | Method for protecting layer by forming hydrocarbon-based extremely thin film |
US10083836B2 (en) | 2015-07-24 | 2018-09-25 | Asm Ip Holding B.V. | Formation of boron-doped titanium metal films with high work function |
US10087525B2 (en) | 2015-08-04 | 2018-10-02 | Asm Ip Holding B.V. | Variable gap hard stop design |
US9647114B2 (en) | 2015-08-14 | 2017-05-09 | Asm Ip Holding B.V. | Methods of forming highly p-type doped germanium tin films and structures and devices including the films |
US9711345B2 (en) | 2015-08-25 | 2017-07-18 | Asm Ip Holding B.V. | Method for forming aluminum nitride-based film by PEALD |
US9960072B2 (en) | 2015-09-29 | 2018-05-01 | Asm Ip Holding B.V. | Variable adjustment for precise matching of multiple chamber cavity housings |
US9909214B2 (en) | 2015-10-15 | 2018-03-06 | Asm Ip Holding B.V. | Method for depositing dielectric film in trenches by PEALD |
US10211308B2 (en) | 2015-10-21 | 2019-02-19 | Asm Ip Holding B.V. | NbMC layers |
US10322384B2 (en) | 2015-11-09 | 2019-06-18 | Asm Ip Holding B.V. | Counter flow mixer for process chamber |
US9455138B1 (en) | 2015-11-10 | 2016-09-27 | Asm Ip Holding B.V. | Method for forming dielectric film in trenches by PEALD using H-containing gas |
US9905420B2 (en) | 2015-12-01 | 2018-02-27 | Asm Ip Holding B.V. | Methods of forming silicon germanium tin films and structures and devices including the films |
US9607837B1 (en) | 2015-12-21 | 2017-03-28 | Asm Ip Holding B.V. | Method for forming silicon oxide cap layer for solid state diffusion process |
US9627221B1 (en) | 2015-12-28 | 2017-04-18 | Asm Ip Holding B.V. | Continuous process incorporating atomic layer etching |
US9735024B2 (en) | 2015-12-28 | 2017-08-15 | Asm Ip Holding B.V. | Method of atomic layer etching using functional group-containing fluorocarbon |
US11139308B2 (en) | 2015-12-29 | 2021-10-05 | Asm Ip Holding B.V. | Atomic layer deposition of III-V compounds to form V-NAND devices |
US10468251B2 (en) | 2016-02-19 | 2019-11-05 | Asm Ip Holding B.V. | Method for forming spacers using silicon nitride film for spacer-defined multiple patterning |
US9754779B1 (en) | 2016-02-19 | 2017-09-05 | Asm Ip Holding B.V. | Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches |
US10529554B2 (en) | 2016-02-19 | 2020-01-07 | Asm Ip Holding B.V. | Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches |
US10501866B2 (en) | 2016-03-09 | 2019-12-10 | Asm Ip Holding B.V. | Gas distribution apparatus for improved film uniformity in an epitaxial system |
US10343920B2 (en) | 2016-03-18 | 2019-07-09 | Asm Ip Holding B.V. | Aligned carbon nanotubes |
US9892913B2 (en) | 2016-03-24 | 2018-02-13 | Asm Ip Holding B.V. | Radial and thickness control via biased multi-port injection settings |
US10865475B2 (en) | 2016-04-21 | 2020-12-15 | Asm Ip Holding B.V. | Deposition of metal borides and silicides |
US10087522B2 (en) | 2016-04-21 | 2018-10-02 | Asm Ip Holding B.V. | Deposition of metal borides |
US10190213B2 (en) | 2016-04-21 | 2019-01-29 | Asm Ip Holding B.V. | Deposition of metal borides |
US10032628B2 (en) | 2016-05-02 | 2018-07-24 | Asm Ip Holding B.V. | Source/drain performance through conformal solid state doping |
US10367080B2 (en) | 2016-05-02 | 2019-07-30 | Asm Ip Holding B.V. | Method of forming a germanium oxynitride film |
KR102592471B1 (en) | 2016-05-17 | 2023-10-20 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming metal interconnection and method of fabricating semiconductor device using the same |
US11453943B2 (en) | 2016-05-25 | 2022-09-27 | Asm Ip Holding B.V. | Method for forming carbon-containing silicon/metal oxide or nitride film by ALD using silicon precursor and hydrocarbon precursor |
US10388509B2 (en) | 2016-06-28 | 2019-08-20 | Asm Ip Holding B.V. | Formation of epitaxial layers via dislocation filtering |
US9859151B1 (en) | 2016-07-08 | 2018-01-02 | Asm Ip Holding B.V. | Selective film deposition method to form air gaps |
US10612137B2 (en) | 2016-07-08 | 2020-04-07 | Asm Ip Holdings B.V. | Organic reactants for atomic layer deposition |
US9793135B1 (en) | 2016-07-14 | 2017-10-17 | ASM IP Holding B.V | Method of cyclic dry etching using etchant film |
US10714385B2 (en) | 2016-07-19 | 2020-07-14 | Asm Ip Holding B.V. | Selective deposition of tungsten |
US10381226B2 (en) | 2016-07-27 | 2019-08-13 | Asm Ip Holding B.V. | Method of processing substrate |
US10395919B2 (en) | 2016-07-28 | 2019-08-27 | Asm Ip Holding B.V. | Method and apparatus for filling a gap |
KR102532607B1 (en) | 2016-07-28 | 2023-05-15 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus and method of operating the same |
US9812320B1 (en) | 2016-07-28 | 2017-11-07 | Asm Ip Holding B.V. | Method and apparatus for filling a gap |
US9887082B1 (en) | 2016-07-28 | 2018-02-06 | Asm Ip Holding B.V. | Method and apparatus for filling a gap |
US10177025B2 (en) | 2016-07-28 | 2019-01-08 | Asm Ip Holding B.V. | Method and apparatus for filling a gap |
US10090316B2 (en) | 2016-09-01 | 2018-10-02 | Asm Ip Holding B.V. | 3D stacked multilayer semiconductor memory using doped select transistor channel |
US10410943B2 (en) | 2016-10-13 | 2019-09-10 | Asm Ip Holding B.V. | Method for passivating a surface of a semiconductor and related systems |
US10643826B2 (en) | 2016-10-26 | 2020-05-05 | Asm Ip Holdings B.V. | Methods for thermally calibrating reaction chambers |
US11532757B2 (en) | 2016-10-27 | 2022-12-20 | Asm Ip Holding B.V. | Deposition of charge trapping layers |
US10435790B2 (en) | 2016-11-01 | 2019-10-08 | Asm Ip Holding B.V. | Method of subatmospheric plasma-enhanced ALD using capacitively coupled electrodes with narrow gap |
US10714350B2 (en) | 2016-11-01 | 2020-07-14 | ASM IP Holdings, B.V. | Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures |
US10229833B2 (en) | 2016-11-01 | 2019-03-12 | Asm Ip Holding B.V. | Methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures |
US10643904B2 (en) | 2016-11-01 | 2020-05-05 | Asm Ip Holdings B.V. | Methods for forming a semiconductor device and related semiconductor device structures |
US10134757B2 (en) | 2016-11-07 | 2018-11-20 | Asm Ip Holding B.V. | Method of processing a substrate and a device manufactured by using the method |
KR102546317B1 (en) | 2016-11-15 | 2023-06-21 | 에이에스엠 아이피 홀딩 비.브이. | Gas supply unit and substrate processing apparatus including the same |
US10340135B2 (en) | 2016-11-28 | 2019-07-02 | Asm Ip Holding B.V. | Method of topologically restricted plasma-enhanced cyclic deposition of silicon or metal nitride |
KR20180068582A (en) | 2016-12-14 | 2018-06-22 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US11447861B2 (en) | 2016-12-15 | 2022-09-20 | Asm Ip Holding B.V. | Sequential infiltration synthesis apparatus and a method of forming a patterned structure |
US9916980B1 (en) | 2016-12-15 | 2018-03-13 | Asm Ip Holding B.V. | Method of forming a structure on a substrate |
US11581186B2 (en) | 2016-12-15 | 2023-02-14 | Asm Ip Holding B.V. | Sequential infiltration synthesis apparatus |
KR20180070971A (en) | 2016-12-19 | 2018-06-27 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US10269558B2 (en) | 2016-12-22 | 2019-04-23 | Asm Ip Holding B.V. | Method of forming a structure on a substrate |
US10867788B2 (en) | 2016-12-28 | 2020-12-15 | Asm Ip Holding B.V. | Method of forming a structure on a substrate |
US11390950B2 (en) | 2017-01-10 | 2022-07-19 | Asm Ip Holding B.V. | Reactor system and method to reduce residue buildup during a film deposition process |
US10655221B2 (en) | 2017-02-09 | 2020-05-19 | Asm Ip Holding B.V. | Method for depositing oxide film by thermal ALD and PEALD |
US10468261B2 (en) | 2017-02-15 | 2019-11-05 | Asm Ip Holding B.V. | Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures |
US10283353B2 (en) | 2017-03-29 | 2019-05-07 | Asm Ip Holding B.V. | Method of reforming insulating film deposited on substrate with recess pattern |
US10529563B2 (en) | 2017-03-29 | 2020-01-07 | Asm Ip Holdings B.V. | Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures |
US10103040B1 (en) | 2017-03-31 | 2018-10-16 | Asm Ip Holding B.V. | Apparatus and method for manufacturing a semiconductor device |
USD830981S1 (en) | 2017-04-07 | 2018-10-16 | Asm Ip Holding B.V. | Susceptor for semiconductor substrate processing apparatus |
KR102457289B1 (en) | 2017-04-25 | 2022-10-21 | 에이에스엠 아이피 홀딩 비.브이. | Method for depositing a thin film and manufacturing a semiconductor device |
US10892156B2 (en) | 2017-05-08 | 2021-01-12 | Asm Ip Holding B.V. | Methods for forming a silicon nitride film on a substrate and related semiconductor device structures |
US10446393B2 (en) | 2017-05-08 | 2019-10-15 | Asm Ip Holding B.V. | Methods for forming silicon-containing epitaxial layers and related semiconductor device structures |
US10770286B2 (en) | 2017-05-08 | 2020-09-08 | Asm Ip Holdings B.V. | Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures |
US10504742B2 (en) | 2017-05-31 | 2019-12-10 | Asm Ip Holding B.V. | Method of atomic layer etching using hydrogen plasma |
US10886123B2 (en) | 2017-06-02 | 2021-01-05 | Asm Ip Holding B.V. | Methods for forming low temperature semiconductor layers and related semiconductor device structures |
US11306395B2 (en) | 2017-06-28 | 2022-04-19 | Asm Ip Holding B.V. | Methods for depositing a transition metal nitride film on a substrate by atomic layer deposition and related deposition apparatus |
US10685834B2 (en) | 2017-07-05 | 2020-06-16 | Asm Ip Holdings B.V. | Methods for forming a silicon germanium tin layer and related semiconductor device structures |
KR20190009245A (en) | 2017-07-18 | 2019-01-28 | 에이에스엠 아이피 홀딩 비.브이. | Methods for forming a semiconductor device structure and related semiconductor device structures |
US10541333B2 (en) | 2017-07-19 | 2020-01-21 | Asm Ip Holding B.V. | Method for depositing a group IV semiconductor and related semiconductor device structures |
US11374112B2 (en) | 2017-07-19 | 2022-06-28 | Asm Ip Holding B.V. | Method for depositing a group IV semiconductor and related semiconductor device structures |
US11018002B2 (en) | 2017-07-19 | 2021-05-25 | Asm Ip Holding B.V. | Method for selectively depositing a Group IV semiconductor and related semiconductor device structures |
US10590535B2 (en) | 2017-07-26 | 2020-03-17 | Asm Ip Holdings B.V. | Chemical treatment, deposition and/or infiltration apparatus and method for using the same |
US10312055B2 (en) | 2017-07-26 | 2019-06-04 | Asm Ip Holding B.V. | Method of depositing film by PEALD using negative bias |
US10605530B2 (en) | 2017-07-26 | 2020-03-31 | Asm Ip Holding B.V. | Assembly of a liner and a flange for a vertical furnace as well as the liner and the vertical furnace |
US10692741B2 (en) | 2017-08-08 | 2020-06-23 | Asm Ip Holdings B.V. | Radiation shield |
US10770336B2 (en) | 2017-08-08 | 2020-09-08 | Asm Ip Holding B.V. | Substrate lift mechanism and reactor including same |
US11769682B2 (en) | 2017-08-09 | 2023-09-26 | Asm Ip Holding B.V. | Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith |
US10249524B2 (en) | 2017-08-09 | 2019-04-02 | Asm Ip Holding B.V. | Cassette holder assembly for a substrate cassette and holding member for use in such assembly |
US11139191B2 (en) | 2017-08-09 | 2021-10-05 | Asm Ip Holding B.V. | Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith |
US10236177B1 (en) | 2017-08-22 | 2019-03-19 | ASM IP Holding B.V.. | Methods for depositing a doped germanium tin semiconductor and related semiconductor device structures |
USD900036S1 (en) | 2017-08-24 | 2020-10-27 | Asm Ip Holding B.V. | Heater electrical connector and adapter |
US11830730B2 (en) | 2017-08-29 | 2023-11-28 | Asm Ip Holding B.V. | Layer forming method and apparatus |
US11295980B2 (en) | 2017-08-30 | 2022-04-05 | Asm Ip Holding B.V. | Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures |
KR102491945B1 (en) | 2017-08-30 | 2023-01-26 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US11056344B2 (en) | 2017-08-30 | 2021-07-06 | Asm Ip Holding B.V. | Layer forming method |
US10607895B2 (en) | 2017-09-18 | 2020-03-31 | Asm Ip Holdings B.V. | Method for forming a semiconductor device structure comprising a gate fill metal |
KR102630301B1 (en) | 2017-09-21 | 2024-01-29 | 에이에스엠 아이피 홀딩 비.브이. | Method of sequential infiltration synthesis treatment of infiltrateable material and structures and devices formed using same |
US10844484B2 (en) | 2017-09-22 | 2020-11-24 | Asm Ip Holding B.V. | Apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods |
US10658205B2 (en) | 2017-09-28 | 2020-05-19 | Asm Ip Holdings B.V. | Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber |
US10403504B2 (en) | 2017-10-05 | 2019-09-03 | Asm Ip Holding B.V. | Method for selectively depositing a metallic film on a substrate |
US10319588B2 (en) | 2017-10-10 | 2019-06-11 | Asm Ip Holding B.V. | Method for depositing a metal chalcogenide on a substrate by cyclical deposition |
US10923344B2 (en) | 2017-10-30 | 2021-02-16 | Asm Ip Holding B.V. | Methods for forming a semiconductor structure and related semiconductor structures |
US10910262B2 (en) | 2017-11-16 | 2021-02-02 | Asm Ip Holding B.V. | Method of selectively depositing a capping layer structure on a semiconductor device structure |
KR102443047B1 (en) | 2017-11-16 | 2022-09-14 | 에이에스엠 아이피 홀딩 비.브이. | Method of processing a substrate and a device manufactured by the same |
US11022879B2 (en) | 2017-11-24 | 2021-06-01 | Asm Ip Holding B.V. | Method of forming an enhanced unexposed photoresist layer |
CN111316417B (en) | 2017-11-27 | 2023-12-22 | 阿斯莫Ip控股公司 | Storage device for storing wafer cassettes for use with batch ovens |
JP7206265B2 (en) | 2017-11-27 | 2023-01-17 | エーエスエム アイピー ホールディング ビー.ブイ. | Equipment with a clean mini-environment |
US10290508B1 (en) | 2017-12-05 | 2019-05-14 | Asm Ip Holding B.V. | Method for forming vertical spacers for spacer-defined patterning |
US10872771B2 (en) | 2018-01-16 | 2020-12-22 | Asm Ip Holding B. V. | Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures |
TW202325889A (en) | 2018-01-19 | 2023-07-01 | 荷蘭商Asm 智慧財產控股公司 | Deposition method |
CN111630203A (en) | 2018-01-19 | 2020-09-04 | Asm Ip私人控股有限公司 | Method for depositing gap filling layer by plasma auxiliary deposition |
USD903477S1 (en) | 2018-01-24 | 2020-12-01 | Asm Ip Holdings B.V. | Metal clamp |
US11018047B2 (en) | 2018-01-25 | 2021-05-25 | Asm Ip Holding B.V. | Hybrid lift pin |
USD880437S1 (en) | 2018-02-01 | 2020-04-07 | Asm Ip Holding B.V. | Gas supply plate for semiconductor manufacturing apparatus |
US10535516B2 (en) | 2018-02-01 | 2020-01-14 | Asm Ip Holdings B.V. | Method for depositing a semiconductor structure on a surface of a substrate and related semiconductor structures |
US11081345B2 (en) | 2018-02-06 | 2021-08-03 | Asm Ip Holding B.V. | Method of post-deposition treatment for silicon oxide film |
US10896820B2 (en) | 2018-02-14 | 2021-01-19 | Asm Ip Holding B.V. | Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process |
WO2019158960A1 (en) | 2018-02-14 | 2019-08-22 | Asm Ip Holding B.V. | A method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process |
US10731249B2 (en) | 2018-02-15 | 2020-08-04 | Asm Ip Holding B.V. | Method of forming a transition metal containing film on a substrate by a cyclical deposition process, a method for supplying a transition metal halide compound to a reaction chamber, and related vapor deposition apparatus |
KR102636427B1 (en) | 2018-02-20 | 2024-02-13 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing method and apparatus |
US10658181B2 (en) | 2018-02-20 | 2020-05-19 | Asm Ip Holding B.V. | Method of spacer-defined direct patterning in semiconductor fabrication |
US10975470B2 (en) | 2018-02-23 | 2021-04-13 | Asm Ip Holding B.V. | Apparatus for detecting or monitoring for a chemical precursor in a high temperature environment |
US11473195B2 (en) | 2018-03-01 | 2022-10-18 | Asm Ip Holding B.V. | Semiconductor processing apparatus and a method for processing a substrate |
US11629406B2 (en) | 2018-03-09 | 2023-04-18 | Asm Ip Holding B.V. | Semiconductor processing apparatus comprising one or more pyrometers for measuring a temperature of a substrate during transfer of the substrate |
US11114283B2 (en) | 2018-03-16 | 2021-09-07 | Asm Ip Holding B.V. | Reactor, system including the reactor, and methods of manufacturing and using same |
KR102646467B1 (en) | 2018-03-27 | 2024-03-11 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming an electrode on a substrate and a semiconductor device structure including an electrode |
US11088002B2 (en) | 2018-03-29 | 2021-08-10 | Asm Ip Holding B.V. | Substrate rack and a substrate processing system and method |
US11230766B2 (en) | 2018-03-29 | 2022-01-25 | Asm Ip Holding B.V. | Substrate processing apparatus and method |
US10510536B2 (en) | 2018-03-29 | 2019-12-17 | Asm Ip Holding B.V. | Method of depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber |
KR102501472B1 (en) | 2018-03-30 | 2023-02-20 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing method |
KR20190128558A (en) | 2018-05-08 | 2019-11-18 | 에이에스엠 아이피 홀딩 비.브이. | Methods for depositing an oxide film on a substrate by a cyclical deposition process and related device structures |
TW202349473A (en) | 2018-05-11 | 2023-12-16 | 荷蘭商Asm Ip私人控股有限公司 | Methods for forming a doped metal carbide film on a substrate and related semiconductor device structures |
KR102596988B1 (en) | 2018-05-28 | 2023-10-31 | 에이에스엠 아이피 홀딩 비.브이. | Method of processing a substrate and a device manufactured by the same |
US11718913B2 (en) | 2018-06-04 | 2023-08-08 | Asm Ip Holding B.V. | Gas distribution system and reactor system including same |
TW202013553A (en) | 2018-06-04 | 2020-04-01 | 荷蘭商Asm 智慧財產控股公司 | Wafer handling chamber with moisture reduction |
US11286562B2 (en) | 2018-06-08 | 2022-03-29 | Asm Ip Holding B.V. | Gas-phase chemical reactor and method of using same |
KR102568797B1 (en) | 2018-06-21 | 2023-08-21 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing system |
US10797133B2 (en) | 2018-06-21 | 2020-10-06 | Asm Ip Holding B.V. | Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures |
WO2020003000A1 (en) | 2018-06-27 | 2020-01-02 | Asm Ip Holding B.V. | Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material |
CN112292478A (en) | 2018-06-27 | 2021-01-29 | Asm Ip私人控股有限公司 | Cyclic deposition methods for forming metal-containing materials and films and structures containing metal-containing materials |
KR20200002519A (en) | 2018-06-29 | 2020-01-08 | 에이에스엠 아이피 홀딩 비.브이. | Method for depositing a thin film and manufacturing a semiconductor device |
US10612136B2 (en) | 2018-06-29 | 2020-04-07 | ASM IP Holding, B.V. | Temperature-controlled flange and reactor system including same |
US10388513B1 (en) | 2018-07-03 | 2019-08-20 | Asm Ip Holding B.V. | Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition |
US10755922B2 (en) | 2018-07-03 | 2020-08-25 | Asm Ip Holding B.V. | Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition |
US10767789B2 (en) | 2018-07-16 | 2020-09-08 | Asm Ip Holding B.V. | Diaphragm valves, valve components, and methods for forming valve components |
US10483099B1 (en) | 2018-07-26 | 2019-11-19 | Asm Ip Holding B.V. | Method for forming thermally stable organosilicon polymer film |
US11053591B2 (en) | 2018-08-06 | 2021-07-06 | Asm Ip Holding B.V. | Multi-port gas injection system and reactor system including same |
US10883175B2 (en) | 2018-08-09 | 2021-01-05 | Asm Ip Holding B.V. | Vertical furnace for processing substrates and a liner for use therein |
US10829852B2 (en) | 2018-08-16 | 2020-11-10 | Asm Ip Holding B.V. | Gas distribution device for a wafer processing apparatus |
US11430674B2 (en) | 2018-08-22 | 2022-08-30 | Asm Ip Holding B.V. | Sensor array, apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods |
US11024523B2 (en) | 2018-09-11 | 2021-06-01 | Asm Ip Holding B.V. | Substrate processing apparatus and method |
KR20200030162A (en) | 2018-09-11 | 2020-03-20 | 에이에스엠 아이피 홀딩 비.브이. | Method for deposition of a thin film |
US11049751B2 (en) | 2018-09-14 | 2021-06-29 | Asm Ip Holding B.V. | Cassette supply system to store and handle cassettes and processing apparatus equipped therewith |
CN110970344A (en) | 2018-10-01 | 2020-04-07 | Asm Ip控股有限公司 | Substrate holding apparatus, system including the same, and method of using the same |
US11232963B2 (en) | 2018-10-03 | 2022-01-25 | Asm Ip Holding B.V. | Substrate processing apparatus and method |
KR102592699B1 (en) | 2018-10-08 | 2023-10-23 | 에이에스엠 아이피 홀딩 비.브이. | Substrate support unit and apparatuses for depositing thin film and processing the substrate including the same |
US10847365B2 (en) | 2018-10-11 | 2020-11-24 | Asm Ip Holding B.V. | Method of forming conformal silicon carbide film by cyclic CVD |
US10811256B2 (en) | 2018-10-16 | 2020-10-20 | Asm Ip Holding B.V. | Method for etching a carbon-containing feature |
KR102605121B1 (en) | 2018-10-19 | 2023-11-23 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus and substrate processing method |
KR102546322B1 (en) | 2018-10-19 | 2023-06-21 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus and substrate processing method |
USD948463S1 (en) | 2018-10-24 | 2022-04-12 | Asm Ip Holding B.V. | Susceptor for semiconductor substrate supporting apparatus |
US10381219B1 (en) | 2018-10-25 | 2019-08-13 | Asm Ip Holding B.V. | Methods for forming a silicon nitride film |
US11087997B2 (en) | 2018-10-31 | 2021-08-10 | Asm Ip Holding B.V. | Substrate processing apparatus for processing substrates |
KR20200051105A (en) | 2018-11-02 | 2020-05-13 | 에이에스엠 아이피 홀딩 비.브이. | Substrate support unit and substrate processing apparatus including the same |
US11572620B2 (en) | 2018-11-06 | 2023-02-07 | Asm Ip Holding B.V. | Methods for selectively depositing an amorphous silicon film on a substrate |
US11031242B2 (en) | 2018-11-07 | 2021-06-08 | Asm Ip Holding B.V. | Methods for depositing a boron doped silicon germanium film |
US10847366B2 (en) | 2018-11-16 | 2020-11-24 | Asm Ip Holding B.V. | Methods for depositing a transition metal chalcogenide film on a substrate by a cyclical deposition process |
US10818758B2 (en) | 2018-11-16 | 2020-10-27 | Asm Ip Holding B.V. | Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures |
US10559458B1 (en) | 2018-11-26 | 2020-02-11 | Asm Ip Holding B.V. | Method of forming oxynitride film |
US11217444B2 (en) | 2018-11-30 | 2022-01-04 | Asm Ip Holding B.V. | Method for forming an ultraviolet radiation responsive metal oxide-containing film |
KR102636428B1 (en) | 2018-12-04 | 2024-02-13 | 에이에스엠 아이피 홀딩 비.브이. | A method for cleaning a substrate processing apparatus |
US11158513B2 (en) | 2018-12-13 | 2021-10-26 | Asm Ip Holding B.V. | Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures |
TW202037745A (en) | 2018-12-14 | 2020-10-16 | 荷蘭商Asm Ip私人控股有限公司 | Method of forming device structure, structure formed by the method and system for performing the method |
TWI819180B (en) | 2019-01-17 | 2023-10-21 | 荷蘭商Asm 智慧財產控股公司 | Methods of forming a transition metal containing film on a substrate by a cyclical deposition process |
KR20200091543A (en) | 2019-01-22 | 2020-07-31 | 에이에스엠 아이피 홀딩 비.브이. | Semiconductor processing device |
CN111524788B (en) | 2019-02-01 | 2023-11-24 | Asm Ip私人控股有限公司 | Method for topologically selective film formation of silicon oxide |
KR102626263B1 (en) | 2019-02-20 | 2024-01-16 | 에이에스엠 아이피 홀딩 비.브이. | Cyclical deposition method including treatment step and apparatus for same |
US11482533B2 (en) | 2019-02-20 | 2022-10-25 | Asm Ip Holding B.V. | Apparatus and methods for plug fill deposition in 3-D NAND applications |
TW202104632A (en) | 2019-02-20 | 2021-02-01 | 荷蘭商Asm Ip私人控股有限公司 | Cyclical deposition method and apparatus for filling a recess formed within a substrate surface |
JP2020136678A (en) | 2019-02-20 | 2020-08-31 | エーエスエム・アイピー・ホールディング・ベー・フェー | Method for filing concave part formed inside front surface of base material, and device |
TW202100794A (en) | 2019-02-22 | 2021-01-01 | 荷蘭商Asm Ip私人控股有限公司 | Substrate processing apparatus and method for processing substrate |
US11742198B2 (en) | 2019-03-08 | 2023-08-29 | Asm Ip Holding B.V. | Structure including SiOCN layer and method of forming same |
KR20200108243A (en) | 2019-03-08 | 2020-09-17 | 에이에스엠 아이피 홀딩 비.브이. | Structure Including SiOC Layer and Method of Forming Same |
KR20200108242A (en) | 2019-03-08 | 2020-09-17 | 에이에스엠 아이피 홀딩 비.브이. | Method for Selective Deposition of Silicon Nitride Layer and Structure Including Selectively-Deposited Silicon Nitride Layer |
JP2020167398A (en) | 2019-03-28 | 2020-10-08 | エーエスエム・アイピー・ホールディング・ベー・フェー | Door opener and substrate processing apparatus provided therewith |
KR20200116855A (en) | 2019-04-01 | 2020-10-13 | 에이에스엠 아이피 홀딩 비.브이. | Method of manufacturing semiconductor device |
KR20200123380A (en) | 2019-04-19 | 2020-10-29 | 에이에스엠 아이피 홀딩 비.브이. | Layer forming method and apparatus |
KR20200125453A (en) | 2019-04-24 | 2020-11-04 | 에이에스엠 아이피 홀딩 비.브이. | Gas-phase reactor system and method of using same |
KR20200130121A (en) | 2019-05-07 | 2020-11-18 | 에이에스엠 아이피 홀딩 비.브이. | Chemical source vessel with dip tube |
KR20200130118A (en) | 2019-05-07 | 2020-11-18 | 에이에스엠 아이피 홀딩 비.브이. | Method for Reforming Amorphous Carbon Polymer Film |
KR20200130652A (en) | 2019-05-10 | 2020-11-19 | 에이에스엠 아이피 홀딩 비.브이. | Method of depositing material onto a surface and structure formed according to the method |
JP2020188255A (en) | 2019-05-16 | 2020-11-19 | エーエスエム アイピー ホールディング ビー.ブイ. | Wafer boat handling device, vertical batch furnace, and method |
USD947913S1 (en) | 2019-05-17 | 2022-04-05 | Asm Ip Holding B.V. | Susceptor shaft |
USD975665S1 (en) | 2019-05-17 | 2023-01-17 | Asm Ip Holding B.V. | Susceptor shaft |
USD935572S1 (en) | 2019-05-24 | 2021-11-09 | Asm Ip Holding B.V. | Gas channel plate |
USD922229S1 (en) | 2019-06-05 | 2021-06-15 | Asm Ip Holding B.V. | Device for controlling a temperature of a gas supply unit |
KR20200141002A (en) | 2019-06-06 | 2020-12-17 | 에이에스엠 아이피 홀딩 비.브이. | Method of using a gas-phase reactor system including analyzing exhausted gas |
KR20200143254A (en) | 2019-06-11 | 2020-12-23 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming an electronic structure using an reforming gas, system for performing the method, and structure formed using the method |
USD944946S1 (en) | 2019-06-14 | 2022-03-01 | Asm Ip Holding B.V. | Shower plate |
USD931978S1 (en) | 2019-06-27 | 2021-09-28 | Asm Ip Holding B.V. | Showerhead vacuum transport |
KR20210005515A (en) | 2019-07-03 | 2021-01-14 | 에이에스엠 아이피 홀딩 비.브이. | Temperature control assembly for substrate processing apparatus and method of using same |
JP2021015791A (en) | 2019-07-09 | 2021-02-12 | エーエスエム アイピー ホールディング ビー.ブイ. | Plasma device and substrate processing method using coaxial waveguide |
CN112216646A (en) | 2019-07-10 | 2021-01-12 | Asm Ip私人控股有限公司 | Substrate supporting assembly and substrate processing device comprising same |
KR20210010307A (en) | 2019-07-16 | 2021-01-27 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
KR20210010816A (en) | 2019-07-17 | 2021-01-28 | 에이에스엠 아이피 홀딩 비.브이. | Radical assist ignition plasma system and method |
KR20210010820A (en) | 2019-07-17 | 2021-01-28 | 에이에스엠 아이피 홀딩 비.브이. | Methods of forming silicon germanium structures |
US11643724B2 (en) | 2019-07-18 | 2023-05-09 | Asm Ip Holding B.V. | Method of forming structures using a neutral beam |
TW202121506A (en) | 2019-07-19 | 2021-06-01 | 荷蘭商Asm Ip私人控股有限公司 | Method of forming topology-controlled amorphous carbon polymer film |
CN112309843A (en) | 2019-07-29 | 2021-02-02 | Asm Ip私人控股有限公司 | Selective deposition method for achieving high dopant doping |
CN112309899A (en) | 2019-07-30 | 2021-02-02 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
CN112309900A (en) | 2019-07-30 | 2021-02-02 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
US11227782B2 (en) | 2019-07-31 | 2022-01-18 | Asm Ip Holding B.V. | Vertical batch furnace assembly |
US11587815B2 (en) | 2019-07-31 | 2023-02-21 | Asm Ip Holding B.V. | Vertical batch furnace assembly |
US11587814B2 (en) | 2019-07-31 | 2023-02-21 | Asm Ip Holding B.V. | Vertical batch furnace assembly |
CN112323048B (en) | 2019-08-05 | 2024-02-09 | Asm Ip私人控股有限公司 | Liquid level sensor for chemical source container |
USD965524S1 (en) | 2019-08-19 | 2022-10-04 | Asm Ip Holding B.V. | Susceptor support |
USD965044S1 (en) | 2019-08-19 | 2022-09-27 | Asm Ip Holding B.V. | Susceptor shaft |
JP2021031769A (en) | 2019-08-21 | 2021-03-01 | エーエスエム アイピー ホールディング ビー.ブイ. | Production apparatus of mixed gas of film deposition raw material and film deposition apparatus |
USD940837S1 (en) | 2019-08-22 | 2022-01-11 | Asm Ip Holding B.V. | Electrode |
KR20210024423A (en) | 2019-08-22 | 2021-03-05 | 에이에스엠 아이피 홀딩 비.브이. | Method for forming a structure with a hole |
USD949319S1 (en) | 2019-08-22 | 2022-04-19 | Asm Ip Holding B.V. | Exhaust duct |
USD930782S1 (en) | 2019-08-22 | 2021-09-14 | Asm Ip Holding B.V. | Gas distributor |
USD979506S1 (en) | 2019-08-22 | 2023-02-28 | Asm Ip Holding B.V. | Insulator |
US11286558B2 (en) | 2019-08-23 | 2022-03-29 | Asm Ip Holding B.V. | Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film |
KR20210024420A (en) | 2019-08-23 | 2021-03-05 | 에이에스엠 아이피 홀딩 비.브이. | Method for depositing silicon oxide film having improved quality by peald using bis(diethylamino)silane |
KR20210029090A (en) | 2019-09-04 | 2021-03-15 | 에이에스엠 아이피 홀딩 비.브이. | Methods for selective deposition using a sacrificial capping layer |
KR20210029663A (en) | 2019-09-05 | 2021-03-16 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US11562901B2 (en) | 2019-09-25 | 2023-01-24 | Asm Ip Holding B.V. | Substrate processing method |
CN112593212B (en) | 2019-10-02 | 2023-12-22 | Asm Ip私人控股有限公司 | Method for forming topologically selective silicon oxide film by cyclic plasma enhanced deposition process |
TW202129060A (en) | 2019-10-08 | 2021-08-01 | 荷蘭商Asm Ip控股公司 | Substrate processing device, and substrate processing method |
TW202115273A (en) | 2019-10-10 | 2021-04-16 | 荷蘭商Asm Ip私人控股有限公司 | Method of forming a photoresist underlayer and structure including same |
KR20210045930A (en) | 2019-10-16 | 2021-04-27 | 에이에스엠 아이피 홀딩 비.브이. | Method of Topology-Selective Film Formation of Silicon Oxide |
US11637014B2 (en) | 2019-10-17 | 2023-04-25 | Asm Ip Holding B.V. | Methods for selective deposition of doped semiconductor material |
KR20210047808A (en) | 2019-10-21 | 2021-04-30 | 에이에스엠 아이피 홀딩 비.브이. | Apparatus and methods for selectively etching films |
US11646205B2 (en) | 2019-10-29 | 2023-05-09 | Asm Ip Holding B.V. | Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same |
KR20210054983A (en) | 2019-11-05 | 2021-05-14 | 에이에스엠 아이피 홀딩 비.브이. | Structures with doped semiconductor layers and methods and systems for forming same |
US11501968B2 (en) | 2019-11-15 | 2022-11-15 | Asm Ip Holding B.V. | Method for providing a semiconductor device with silicon filled gaps |
KR20210062561A (en) | 2019-11-20 | 2021-05-31 | 에이에스엠 아이피 홀딩 비.브이. | Method of depositing carbon-containing material on a surface of a substrate, structure formed using the method, and system for forming the structure |
CN112951697A (en) | 2019-11-26 | 2021-06-11 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
KR20210065848A (en) | 2019-11-26 | 2021-06-04 | 에이에스엠 아이피 홀딩 비.브이. | Methods for selectivley forming a target film on a substrate comprising a first dielectric surface and a second metallic surface |
CN112885693A (en) | 2019-11-29 | 2021-06-01 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
CN112885692A (en) | 2019-11-29 | 2021-06-01 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
JP2021090042A (en) | 2019-12-02 | 2021-06-10 | エーエスエム アイピー ホールディング ビー.ブイ. | Substrate processing apparatus and substrate processing method |
KR20210070898A (en) | 2019-12-04 | 2021-06-15 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
KR20210078405A (en) | 2019-12-17 | 2021-06-28 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming vanadium nitride layer and structure including the vanadium nitride layer |
US11527403B2 (en) | 2019-12-19 | 2022-12-13 | Asm Ip Holding B.V. | Methods for filling a gap feature on a substrate surface and related semiconductor structures |
KR20210095050A (en) | 2020-01-20 | 2021-07-30 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming thin film and method of modifying surface of thin film |
TW202130846A (en) | 2020-02-03 | 2021-08-16 | 荷蘭商Asm Ip私人控股有限公司 | Method of forming structures including a vanadium or indium layer |
TW202146882A (en) | 2020-02-04 | 2021-12-16 | 荷蘭商Asm Ip私人控股有限公司 | Method of verifying an article, apparatus for verifying an article, and system for verifying a reaction chamber |
US11776846B2 (en) | 2020-02-07 | 2023-10-03 | Asm Ip Holding B.V. | Methods for depositing gap filling fluids and related systems and devices |
TW202146715A (en) | 2020-02-17 | 2021-12-16 | 荷蘭商Asm Ip私人控股有限公司 | Method for growing phosphorous-doped silicon layer and system of the same |
KR20210116240A (en) | 2020-03-11 | 2021-09-27 | 에이에스엠 아이피 홀딩 비.브이. | Substrate handling device with adjustable joints |
US11876356B2 (en) | 2020-03-11 | 2024-01-16 | Asm Ip Holding B.V. | Lockout tagout assembly and system and method of using same |
KR20210124042A (en) | 2020-04-02 | 2021-10-14 | 에이에스엠 아이피 홀딩 비.브이. | Thin film forming method |
TW202146689A (en) | 2020-04-03 | 2021-12-16 | 荷蘭商Asm Ip控股公司 | Method for forming barrier layer and method for manufacturing semiconductor device |
TW202145344A (en) | 2020-04-08 | 2021-12-01 | 荷蘭商Asm Ip私人控股有限公司 | Apparatus and methods for selectively etching silcon oxide films |
US11821078B2 (en) | 2020-04-15 | 2023-11-21 | Asm Ip Holding B.V. | Method for forming precoat film and method for forming silicon-containing film |
KR20210132605A (en) | 2020-04-24 | 2021-11-04 | 에이에스엠 아이피 홀딩 비.브이. | Vertical batch furnace assembly comprising a cooling gas supply |
KR20210132600A (en) | 2020-04-24 | 2021-11-04 | 에이에스엠 아이피 홀딩 비.브이. | Methods and systems for depositing a layer comprising vanadium, nitrogen, and a further element |
US11898243B2 (en) | 2020-04-24 | 2024-02-13 | Asm Ip Holding B.V. | Method of forming vanadium nitride-containing layer |
KR20210134869A (en) | 2020-05-01 | 2021-11-11 | 에이에스엠 아이피 홀딩 비.브이. | Fast FOUP swapping with a FOUP handler |
KR20210141379A (en) | 2020-05-13 | 2021-11-23 | 에이에스엠 아이피 홀딩 비.브이. | Laser alignment fixture for a reactor system |
KR20210143653A (en) | 2020-05-19 | 2021-11-29 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
KR20210145078A (en) | 2020-05-21 | 2021-12-01 | 에이에스엠 아이피 홀딩 비.브이. | Structures including multiple carbon layers and methods of forming and using same |
TW202201602A (en) | 2020-05-29 | 2022-01-01 | 荷蘭商Asm Ip私人控股有限公司 | Substrate processing device |
TW202218133A (en) | 2020-06-24 | 2022-05-01 | 荷蘭商Asm Ip私人控股有限公司 | Method for forming a layer provided with silicon |
TW202217953A (en) | 2020-06-30 | 2022-05-01 | 荷蘭商Asm Ip私人控股有限公司 | Substrate processing method |
KR20220010438A (en) | 2020-07-17 | 2022-01-25 | 에이에스엠 아이피 홀딩 비.브이. | Structures and methods for use in photolithography |
TW202204662A (en) | 2020-07-20 | 2022-02-01 | 荷蘭商Asm Ip私人控股有限公司 | Method and system for depositing molybdenum layers |
TW202212623A (en) | 2020-08-26 | 2022-04-01 | 荷蘭商Asm Ip私人控股有限公司 | Method of forming metal silicon oxide layer and metal silicon oxynitride layer, semiconductor structure, and system |
USD990534S1 (en) | 2020-09-11 | 2023-06-27 | Asm Ip Holding B.V. | Weighted lift pin |
USD1012873S1 (en) | 2020-09-24 | 2024-01-30 | Asm Ip Holding B.V. | Electrode for semiconductor processing apparatus |
TW202229613A (en) | 2020-10-14 | 2022-08-01 | 荷蘭商Asm Ip私人控股有限公司 | Method of depositing material on stepped structure |
TW202217037A (en) | 2020-10-22 | 2022-05-01 | 荷蘭商Asm Ip私人控股有限公司 | Method of depositing vanadium metal, structure, device and a deposition assembly |
TW202223136A (en) | 2020-10-28 | 2022-06-16 | 荷蘭商Asm Ip私人控股有限公司 | Method for forming layer on substrate, and semiconductor processing system |
TW202235675A (en) | 2020-11-30 | 2022-09-16 | 荷蘭商Asm Ip私人控股有限公司 | Injector, and substrate processing apparatus |
US11946137B2 (en) | 2020-12-16 | 2024-04-02 | Asm Ip Holding B.V. | Runout and wobble measurement fixtures |
TW202231903A (en) | 2020-12-22 | 2022-08-16 | 荷蘭商Asm Ip私人控股有限公司 | Transition metal deposition method, transition metal layer, and deposition assembly for depositing transition metal on substrate |
USD981973S1 (en) | 2021-05-11 | 2023-03-28 | Asm Ip Holding B.V. | Reactor wall for substrate processing apparatus |
USD980813S1 (en) | 2021-05-11 | 2023-03-14 | Asm Ip Holding B.V. | Gas flow control plate for substrate processing apparatus |
USD980814S1 (en) | 2021-05-11 | 2023-03-14 | Asm Ip Holding B.V. | Gas distributor for substrate processing apparatus |
USD990441S1 (en) | 2021-09-07 | 2023-06-27 | Asm Ip Holding B.V. | Gas flow control plate |
Citations (81)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4993358A (en) * | 1989-07-28 | 1991-02-19 | Watkins-Johnson Company | Chemical vapor deposition reactor and method of operation |
US6013553A (en) * | 1997-07-24 | 2000-01-11 | Texas Instruments Incorporated | Zirconium and/or hafnium oxynitride gate dielectric |
US6020024A (en) * | 1997-08-04 | 2000-02-01 | Motorola, Inc. | Method for forming high dielectric constant metal oxides |
US6025627A (en) * | 1998-05-29 | 2000-02-15 | Micron Technology, Inc. | Alternate method and structure for improved floating gate tunneling devices |
US6171900B1 (en) * | 1999-04-15 | 2001-01-09 | Taiwan Semiconductor Manufacturing Company | CVD Ta2O5/oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFET |
US6187484B1 (en) * | 1999-08-31 | 2001-02-13 | Micron Technology, Inc. | Irradiation mask |
US20020001971A1 (en) * | 2000-06-27 | 2002-01-03 | Hag-Ju Cho | Methods of manufacturing integrated circuit devices that include a metal oxide layer disposed on another layer to protect the other layer from diffusion of impurities and integrated circuit devices manufactured using same |
US20020004276A1 (en) * | 2000-02-28 | 2002-01-10 | Micron Technology, Inc. | Structure and method for dual gate oxide thicknesses |
US20020019125A1 (en) * | 1997-10-09 | 2002-02-14 | Werner Juengling | Methods of forming materials between conductive electrical components, and insulating materials |
US6348386B1 (en) * | 2001-04-16 | 2002-02-19 | Motorola, Inc. | Method for making a hafnium-based insulating film |
US6350704B1 (en) * | 1997-10-14 | 2002-02-26 | Micron Technology Inc. | Porous silicon oxycarbide integrated circuit insulator |
US20020024080A1 (en) * | 2000-08-31 | 2002-02-28 | Derderian Garo J. | Capacitor fabrication methods and capacitor constructions |
US20020025628A1 (en) * | 2000-08-31 | 2002-02-28 | Derderian Garo J. | Capacitor fabrication methods and capacitor constructions |
US20030003730A1 (en) * | 2001-02-13 | 2003-01-02 | Micron Technology, Inc. | Sequential pulse deposition |
US20030003635A1 (en) * | 2001-05-23 | 2003-01-02 | Paranjpe Ajit P. | Atomic layer deposition for fabricating thin films |
US20030003722A1 (en) * | 1998-09-01 | 2003-01-02 | Micron Technology, Inc. | Chemical vapor deposition systems including metal complexes with chelating O- and/or N-donor ligands |
US20030004051A1 (en) * | 2001-05-18 | 2003-01-02 | Kim Dong-Wan | Dielectric ceramic composition and method for manufacturing multilayered components using the same |
US20030003702A1 (en) * | 2001-02-09 | 2003-01-02 | Micron Technology, Inc. | Formation of metal oxide gate dielectric |
US20030008243A1 (en) * | 2001-07-09 | 2003-01-09 | Micron Technology, Inc. | Copper electroless deposition technology for ULSI metalization |
US6509280B2 (en) * | 2001-02-22 | 2003-01-21 | Samsung Electronics Co., Ltd. | Method for forming a dielectric layer of a semiconductor device |
US20030017717A1 (en) * | 2001-07-18 | 2003-01-23 | Ahn Kie Y. | Methods for forming dielectric materials and methods for forming semiconductor devices |
US20030020169A1 (en) * | 2001-07-24 | 2003-01-30 | Ahn Kie Y. | Copper technology for ULSI metallization |
US6514828B2 (en) * | 2001-04-20 | 2003-02-04 | Micron Technology, Inc. | Method of fabricating a highly reliable gate oxide |
US6515510B2 (en) * | 1998-08-04 | 2003-02-04 | Micron Technology, Inc. | Programmable logic array with vertical transistors |
US6514820B2 (en) * | 1998-08-27 | 2003-02-04 | Micron Technology, Inc. | Method for forming single electron resistor memory |
US6518634B1 (en) * | 2000-09-01 | 2003-02-11 | Motorola, Inc. | Strontium nitride or strontium oxynitride gate dielectric |
US20030032270A1 (en) * | 2001-08-10 | 2003-02-13 | John Snyder | Fabrication method for a device for regulating flow of electric current with high dielectric constant gate insulating layer and source/drain forming schottky contact or schottky-like region with substrate |
US6521911B2 (en) * | 2000-07-20 | 2003-02-18 | North Carolina State University | High dielectric constant metal silicates formed by controlled metal-surface reactions |
US6524867B2 (en) * | 2000-12-28 | 2003-02-25 | Micron Technology, Inc. | Method for forming platinum-rhodium stack as an oxygen barrier |
US6673701B1 (en) * | 2002-08-27 | 2004-01-06 | Micron Technology, Inc. | Atomic layer deposition methods |
US6674138B1 (en) * | 2001-12-31 | 2004-01-06 | Advanced Micro Devices, Inc. | Use of high-k dielectric materials in modified ONO structure for semiconductor devices |
US20040004859A1 (en) * | 2002-07-08 | 2004-01-08 | Micron Technology, Inc. | Memory utilizing oxide nanolaminates |
US20040005982A1 (en) * | 2002-07-05 | 2004-01-08 | Samsung Electro-Mechanics Co., Ltd. | Non-reducible, low temperature sinterable dielectric ceramic composition, multilayer ceramic chip capacitor using the composition and method for preparing the multilayer ceramic chip capacitor |
US20040004244A1 (en) * | 2001-03-15 | 2004-01-08 | Micron Technology, Inc. | Structures, methods, and systems for ferroelectric memory transistors |
US20040005625A1 (en) * | 2000-12-12 | 2004-01-08 | Masumi Abe | Method of analyzing expression of gene |
US20040004247A1 (en) * | 2002-07-08 | 2004-01-08 | Micron Technology, Inc. | Memory utilizing oxide-nitride nanolaminates |
US6677250B2 (en) * | 2001-08-17 | 2004-01-13 | Micron Technology, Inc. | CVD apparatuses and methods of forming a layer over a semiconductor substrate |
US20040009679A1 (en) * | 2001-01-19 | 2004-01-15 | Yeo Jae-Hyun | Method of forming material using atomic layer deposition and method of forming capacitor of semiconductor device using the same |
US6683005B2 (en) * | 2001-08-30 | 2004-01-27 | Micron Technology, Inc. | Method of forming capacitor constructions |
US6683011B2 (en) * | 2001-11-14 | 2004-01-27 | Regents Of The University Of Minnesota | Process for forming hafnium oxide films |
US6686212B1 (en) * | 2002-10-31 | 2004-02-03 | Sharp Laboratories Of America, Inc. | Method to deposit a stacked high-κ gate dielectric for CMOS applications |
US20040023461A1 (en) * | 2002-07-30 | 2004-02-05 | Micron Technology, Inc. | Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics |
US20040033661A1 (en) * | 2002-08-16 | 2004-02-19 | Yeo Jae-Hyun | Semiconductor device and method for manufacturing the same |
US20040033681A1 (en) * | 2002-08-15 | 2004-02-19 | Micron Technology, Inc. | Lanthanide doped TiOx dielectric films by plasma oxidation |
US20040033701A1 (en) * | 2002-08-15 | 2004-02-19 | Micron Technology, Inc. | Lanthanide doped tiox dielectric films |
US6696332B2 (en) * | 2001-12-26 | 2004-02-24 | Texas Instruments Incorporated | Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing |
US20040038554A1 (en) * | 2002-08-21 | 2004-02-26 | Ahn Kie Y. | Composite dielectric forming methods and composite dielectrics |
US20040038525A1 (en) * | 2002-08-26 | 2004-02-26 | Shuang Meng | Enhanced atomic layer deposition |
US6844203B2 (en) * | 2001-08-30 | 2005-01-18 | Micron Technology, Inc. | Gate oxides, and methods of forming |
US20050020017A1 (en) * | 2003-06-24 | 2005-01-27 | Micron Technology, Inc. | Lanthanide oxide / hafnium oxide dielectric layers |
US20050026458A1 (en) * | 2003-07-03 | 2005-02-03 | Cem Basceri | Methods of forming hafnium-containing materials, methods of forming hafnium oxide, and constructions comprising hafnium oxide |
US20050026349A1 (en) * | 2001-08-30 | 2005-02-03 | Micron Technology, Inc. | Flash memory with low tunnel barrier interpoly insulators |
US20050023625A1 (en) * | 2002-08-28 | 2005-02-03 | Micron Technology, Inc. | Atomic layer deposited HfSiON dielectric films |
US20050023626A1 (en) * | 2003-06-24 | 2005-02-03 | Micron Technology, Inc. | Lanthanide oxide / hafnium oxide dielectrics |
US20050023584A1 (en) * | 2002-05-02 | 2005-02-03 | Micron Technology, Inc. | Atomic layer deposition and conversion |
US20050026374A1 (en) * | 2002-03-13 | 2005-02-03 | Micron Technology, Inc. | Evaporation of Y-Si-O films for medium-K dielectrics |
US20050023595A1 (en) * | 2001-08-30 | 2005-02-03 | Micron Technology, Inc. | Programmable array logic or memory devices with asymmetrical tunnel barriers |
US20050023594A1 (en) * | 2002-06-05 | 2005-02-03 | Micron Technology, Inc. | Pr2O3-based la-oxide gate dielectrics |
US20050023624A1 (en) * | 2002-06-05 | 2005-02-03 | Micron Technology, Inc. | Atomic layer-deposited HfAlO3 films for gate dielectrics |
US6852167B2 (en) * | 2001-03-01 | 2005-02-08 | Micron Technology, Inc. | Methods, systems, and apparatus for uniform chemical-vapor depositions |
US6852645B2 (en) * | 2003-02-13 | 2005-02-08 | Texas Instruments Incorporated | High temperature interface layer growth for high-k gate dielectric |
US20050029604A1 (en) * | 2002-12-04 | 2005-02-10 | Micron Technology, Inc. | Atomic layer deposited Zr-Sn-Ti-O films using TiI4 |
US20050029605A1 (en) * | 2001-08-30 | 2005-02-10 | Micron Technology, Inc. | Highly reliable amorphous high-k gate oxide ZrO2 |
US20050037563A1 (en) * | 2001-06-13 | 2005-02-17 | Ahn Kie Y. | Capacitor structures |
US6858120B2 (en) * | 2001-03-15 | 2005-02-22 | Micron Technology, Inc. | Method and apparatus for the fabrication of ferroelectric films |
US6858865B2 (en) * | 2001-02-23 | 2005-02-22 | Micron Technology, Inc. | Doped aluminum oxide dielectrics |
US6982230B2 (en) * | 2002-11-08 | 2006-01-03 | International Business Machines Corporation | Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures |
US20060000412A1 (en) * | 2002-05-02 | 2006-01-05 | Micron Technology, Inc. | Systems and apparatus for atomic-layer deposition |
US20060001151A1 (en) * | 2003-03-04 | 2006-01-05 | Micron Technology, Inc. | Atomic layer deposited dielectric layers |
US20060008966A1 (en) * | 2002-07-08 | 2006-01-12 | Micron Technology, Inc. | Memory utilizing oxide-conductor nanolaminates |
US6989573B2 (en) * | 2003-10-10 | 2006-01-24 | Micron Technology, Inc. | Lanthanide oxide/zirconium oxide atomic layer deposited nanolaminate gate dielectrics |
US20060024975A1 (en) * | 2004-08-02 | 2006-02-02 | Micron Technology, Inc. | Atomic layer deposition of zirconium-doped tantalum oxide films |
US20060023513A1 (en) * | 2004-07-27 | 2006-02-02 | Micron Technology, Inc. | High density stepped, non-planar nitride read only memory |
US20060028867A1 (en) * | 2004-08-03 | 2006-02-09 | Micron Technology, Inc. | Non-planar flash memory having shielding between floating gates |
US20060028869A1 (en) * | 2004-08-03 | 2006-02-09 | Micron Technology, Inc. | High density stepped, non-planar flash memory |
US20070007635A1 (en) * | 2005-07-07 | 2007-01-11 | Micron Technology, Inc. | Self aligned metal gates on high-k dielectrics |
US7166886B2 (en) * | 2001-08-30 | 2007-01-23 | Micron Technology, Inc. | DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators |
US20070018214A1 (en) * | 2005-07-25 | 2007-01-25 | Micron Technology, Inc. | Magnesium titanium oxide films |
US20070020835A1 (en) * | 2005-02-10 | 2007-01-25 | Micron Technology, Inc. | Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics |
US20070037415A1 (en) * | 2004-12-13 | 2007-02-15 | Micron Technology, Inc. | Lanthanum hafnium oxide dielectrics |
US7183186B2 (en) * | 2003-04-22 | 2007-02-27 | Micro Technology, Inc. | Atomic layer deposited ZrTiO4 films |
Family Cites Families (90)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3357961A (en) | 1965-05-24 | 1967-12-12 | Exxon Research Engineering Co | Copolymers of ethylene and hexadiene 1, 5 |
SE393967B (en) | 1974-11-29 | 1977-05-31 | Sateko Oy | PROCEDURE AND PERFORMANCE OF LAYING BETWEEN THE STORAGE IN A LABOR PACKAGE |
FI57975C (en) | 1979-02-28 | 1980-11-10 | Lohja Ab Oy | OVER ANCHORING VIDEO UPDATE FOR AVAILABILITY |
US6120531A (en) | 1987-05-20 | 2000-09-19 | Micron, Technology | Physiotherapy fiber, shoes, fabric, and clothes utilizing electromagnetic energy |
US5055319A (en) | 1990-04-02 | 1991-10-08 | The Regents Of The University Of California | Controlled high rate deposition of metal oxide films |
US5302461A (en) * | 1992-06-05 | 1994-04-12 | Hewlett-Packard Company | Dielectric films for use in magnetoresistive transducers |
US5828080A (en) | 1994-08-17 | 1998-10-27 | Tdk Corporation | Oxide thin film, electronic device substrate and electronic device |
US5625233A (en) * | 1995-01-13 | 1997-04-29 | Ibm Corporation | Thin film multi-layer oxygen diffusion barrier consisting of refractory metal, refractory metal aluminide, and aluminum oxide |
US5753934A (en) | 1995-08-04 | 1998-05-19 | Tok Corporation | Multilayer thin film, substrate for electronic device, electronic device, and preparation of multilayer oxide thin film |
US6342277B1 (en) | 1996-08-16 | 2002-01-29 | Licensee For Microelectronics: Asm America, Inc. | Sequential chemical vapor deposition |
JP3193302B2 (en) * | 1996-06-26 | 2001-07-30 | ティーディーケイ株式会社 | Film structure, electronic device, recording medium, and method of manufacturing ferroelectric thin film |
US5916365A (en) * | 1996-08-16 | 1999-06-29 | Sherman; Arthur | Sequential chemical vapor deposition |
US5912797A (en) * | 1997-09-24 | 1999-06-15 | Lucent Technologies Inc. | Dielectric materials of amorphous compositions and devices employing same |
US6710538B1 (en) | 1998-08-26 | 2004-03-23 | Micron Technology, Inc. | Field emission display having reduced power requirements and method |
US6281042B1 (en) | 1998-08-31 | 2001-08-28 | Micron Technology, Inc. | Structure and method for a high performance electronic packaging assembly |
US6274937B1 (en) | 1999-02-01 | 2001-08-14 | Micron Technology, Inc. | Silicon multi-chip module packaging with integrated passive components and method of making |
US6200893B1 (en) * | 1999-03-11 | 2001-03-13 | Genus, Inc | Radical-assisted sequential CVD |
US6273951B1 (en) | 1999-06-16 | 2001-08-14 | Micron Technology, Inc. | Precursor mixtures for use in preparing layers on substrates |
US6060755A (en) * | 1999-07-19 | 2000-05-09 | Sharp Laboratories Of America, Inc. | Aluminum-doped zirconium dielectric film transistor structure and deposition method for same |
US6297539B1 (en) | 1999-07-19 | 2001-10-02 | Sharp Laboratories Of America, Inc. | Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same |
US6498362B1 (en) | 1999-08-26 | 2002-12-24 | Micron Technology, Inc. | Weak ferroelectric transistor |
US6653209B1 (en) | 1999-09-30 | 2003-11-25 | Canon Kabushiki Kaisha | Method of producing silicon thin film, method of constructing SOI substrate and semiconductor device |
FI117942B (en) * | 1999-10-14 | 2007-04-30 | Asm Int | Process for making oxide thin films |
US6203613B1 (en) * | 1999-10-19 | 2001-03-20 | International Business Machines Corporation | Atomic layer deposition with nitrate containing precursors |
KR100304714B1 (en) | 1999-10-20 | 2001-11-02 | 윤종용 | Method for fabricating metal layer of semiconductor device using metal-halide gas |
US6541079B1 (en) * | 1999-10-25 | 2003-04-01 | International Business Machines Corporation | Engineered high dielectric constant oxide and oxynitride heterostructure gate dielectrics by an atomic beam deposition technique |
US6780704B1 (en) | 1999-12-03 | 2004-08-24 | Asm International Nv | Conformal thin films over textured capacitor electrodes |
US6503330B1 (en) | 1999-12-22 | 2003-01-07 | Genus, Inc. | Apparatus and method to achieve continuous interface and ultrathin film during atomic layer deposition |
FI20000099A0 (en) * | 2000-01-18 | 2000-01-18 | Asm Microchemistry Ltd | A method for growing thin metal films |
WO2001054200A1 (en) * | 2000-01-19 | 2001-07-26 | North Carolina State University | Lanthanum oxide-based gate dielectrics for integrated circuit field effect transistors and methods of fabricating same |
US6404027B1 (en) | 2000-02-07 | 2002-06-11 | Agere Systems Guardian Corp. | High dielectric constant gate oxides for silicon-based devices |
US6527866B1 (en) * | 2000-02-09 | 2003-03-04 | Conductus, Inc. | Apparatus and method for deposition of thin films |
US6407435B1 (en) | 2000-02-11 | 2002-06-18 | Sharp Laboratories Of America, Inc. | Multilayer dielectric stack and method |
DE10010821A1 (en) * | 2000-02-29 | 2001-09-13 | Infineon Technologies Ag | Increasing capacity in a storage trench comprises depositing a first silicon oxide layer in the trench, depositing a silicon layer over the first layer to sufficiently |
JP2001242384A (en) * | 2000-03-01 | 2001-09-07 | Olympus Optical Co Ltd | Objective lens for microscope and microscope using the same |
US6537613B1 (en) * | 2000-04-10 | 2003-03-25 | Air Products And Chemicals, Inc. | Process for metal metalloid oxides and nitrides with compositional gradients |
FI117979B (en) | 2000-04-14 | 2007-05-15 | Asm Int | Process for making oxide thin films |
TW508658B (en) | 2000-05-15 | 2002-11-01 | Asm Microchemistry Oy | Process for producing integrated circuits |
US6444592B1 (en) | 2000-06-20 | 2002-09-03 | International Business Machines Corporation | Interfacial oxidation process for high-k gate dielectric process integration |
US6551929B1 (en) * | 2000-06-28 | 2003-04-22 | Applied Materials, Inc. | Bifurcated deposition process for depositing refractory metal layers employing atomic layer deposition and chemical vapor deposition techniques |
US6592942B1 (en) | 2000-07-07 | 2003-07-15 | Asm International N.V. | Method for vapour deposition of a film onto a substrate |
US6458416B1 (en) | 2000-07-19 | 2002-10-01 | Micron Technology, Inc. | Deposition methods |
JP2002141503A (en) | 2000-08-24 | 2002-05-17 | National Institute Of Advanced Industrial & Technology | Manufacturing method of self-alignment transistor |
US7112503B1 (en) * | 2000-08-31 | 2006-09-26 | Micron Technology, Inc. | Enhanced surface area capacitor fabrication methods |
US6541353B1 (en) * | 2000-08-31 | 2003-04-01 | Micron Technology, Inc. | Atomic layer doping apparatus and method |
US6465334B1 (en) | 2000-10-05 | 2002-10-15 | Advanced Micro Devices, Inc. | Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors |
US6660660B2 (en) | 2000-10-10 | 2003-12-09 | Asm International, Nv. | Methods for making a dielectric stack in an integrated circuit |
JP3681632B2 (en) | 2000-11-06 | 2005-08-10 | 松下電器産業株式会社 | Semiconductor device and manufacturing method thereof |
AU2002241496A1 (en) * | 2000-11-20 | 2002-06-18 | Applied Epi, Inc. | Surface sealing showerhead for vapor deposition reactor having integrated flow diverters |
US6355561B1 (en) * | 2000-11-21 | 2002-03-12 | Micron Technology, Inc. | ALD method to improve surface coverage |
US7112543B2 (en) * | 2001-01-04 | 2006-09-26 | Micron Technology, Inc. | Methods of forming assemblies comprising silicon-doped aluminum oxide |
US20020089023A1 (en) * | 2001-01-05 | 2002-07-11 | Motorola, Inc. | Low leakage current metal oxide-nitrides and method of fabricating same |
US6713846B1 (en) * | 2001-01-26 | 2004-03-30 | Aviza Technology, Inc. | Multilayer high κ dielectric films |
US6528374B2 (en) * | 2001-02-05 | 2003-03-04 | International Business Machines Corporation | Method for forming dielectric stack without interfacial layer |
US6518610B2 (en) * | 2001-02-20 | 2003-02-11 | Micron Technology, Inc. | Rhodium-rich oxygen barriers |
US6441417B1 (en) | 2001-03-28 | 2002-08-27 | Sharp Laboratories Of America, Inc. | Single c-axis PGO thin film on ZrO2 for non-volatile memory applications and methods of making the same |
US6448192B1 (en) | 2001-04-16 | 2002-09-10 | Motorola, Inc. | Method for forming a high dielectric constant material |
US6552383B2 (en) * | 2001-05-11 | 2003-04-22 | Micron Technology, Inc. | Integrated decoupling capacitors |
KR100363332B1 (en) * | 2001-05-23 | 2002-12-05 | Samsung Electronics Co Ltd | Method for forming semiconductor device having gate all-around type transistor |
US6709989B2 (en) * | 2001-06-21 | 2004-03-23 | Motorola, Inc. | Method for fabricating a semiconductor structure including a metal oxide interface with silicon |
US6420279B1 (en) * | 2001-06-28 | 2002-07-16 | Sharp Laboratories Of America, Inc. | Methods of using atomic layer deposition to deposit a high dielectric constant material on a substrate |
KR100427030B1 (en) | 2001-08-27 | 2004-04-14 | 주식회사 하이닉스반도체 | Method for forming film with muli-elements and fabricating capacitor using the same |
US7129128B2 (en) * | 2001-08-29 | 2006-10-31 | Micron Technology, Inc. | Method of improved high K dielectric-polysilicon interface for CMOS devices |
US7476925B2 (en) * | 2001-08-30 | 2009-01-13 | Micron Technology, Inc. | Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators |
US6730575B2 (en) | 2001-08-30 | 2004-05-04 | Micron Technology, Inc. | Methods of forming perovskite-type material and capacitor dielectric having perovskite-type crystalline structure |
US7135734B2 (en) * | 2001-08-30 | 2006-11-14 | Micron Technology, Inc. | Graded composition metal oxide tunnel barrier interpoly insulators |
US6806145B2 (en) * | 2001-08-31 | 2004-10-19 | Asm International, N.V. | Low temperature method of forming a gate stack with a high k layer deposited over an interfacial oxide layer |
US20030059535A1 (en) * | 2001-09-25 | 2003-03-27 | Lee Luo | Cycling deposition of low temperature films in a cold wall single wafer process chamber |
US6551893B1 (en) * | 2001-11-27 | 2003-04-22 | Micron Technology, Inc. | Atomic layer deposition of capacitor dielectric |
US6593610B2 (en) | 2001-12-13 | 2003-07-15 | Micron Technology, Inc. | Memory cell arrays |
US6953730B2 (en) * | 2001-12-20 | 2005-10-11 | Micron Technology, Inc. | Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics |
US6900122B2 (en) * | 2001-12-20 | 2005-05-31 | Micron Technology, Inc. | Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics |
FR2834387B1 (en) * | 2001-12-31 | 2004-02-27 | Memscap | ELECTRONIC COMPONENT INCORPORATING AN INTEGRATED CIRCUIT AND A MICRO-CAPACITOR |
US6645882B1 (en) | 2002-01-17 | 2003-11-11 | Advanced Micro Devices, Inc. | Preparation of composite high-K/standard-K dielectrics for semiconductor devices |
US6767795B2 (en) | 2002-01-17 | 2004-07-27 | Micron Technology, Inc. | Highly reliable amorphous high-k gate dielectric ZrOXNY |
US6620670B2 (en) | 2002-01-18 | 2003-09-16 | Applied Materials, Inc. | Process conditions and precursors for atomic layer deposition (ALD) of AL2O3 |
US6893984B2 (en) * | 2002-02-20 | 2005-05-17 | Micron Technology Inc. | Evaporated LaA1O3 films for gate dielectrics |
US6586349B1 (en) | 2002-02-21 | 2003-07-01 | Advanced Micro Devices, Inc. | Integrated process for fabrication of graded composite dielectric material layers for semiconductor devices |
US6451641B1 (en) | 2002-02-27 | 2002-09-17 | Advanced Micro Devices, Inc. | Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material |
US6642573B1 (en) | 2002-03-13 | 2003-11-04 | Advanced Micro Devices, Inc. | Use of high-K dielectric material in modified ONO structure for semiconductor devices |
US6750066B1 (en) * | 2002-04-08 | 2004-06-15 | Advanced Micro Devices, Inc. | Precision high-K intergate dielectric layer |
US6617639B1 (en) | 2002-06-21 | 2003-09-09 | Advanced Micro Devices, Inc. | Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling |
US7253122B2 (en) * | 2002-08-28 | 2007-08-07 | Micron Technology, Inc. | Systems and methods for forming metal oxides using metal diketonates and/or ketoimines |
US7084078B2 (en) * | 2002-08-29 | 2006-08-01 | Micron Technology, Inc. | Atomic layer deposited lanthanide doped TiOx dielectric films |
KR100474072B1 (en) | 2002-09-17 | 2005-03-10 | 주식회사 하이닉스반도체 | Method for forming noble metal films |
US6770536B2 (en) | 2002-10-03 | 2004-08-03 | Agere Systems Inc. | Process for semiconductor device fabrication in which a insulating layer is formed on a semiconductor substrate |
US20040099889A1 (en) * | 2002-11-27 | 2004-05-27 | Agere Systems, Inc. | Process for fabricating a semiconductor device having an insulating layer formed over a semiconductor substrate |
US7101813B2 (en) * | 2002-12-04 | 2006-09-05 | Micron Technology Inc. | Atomic layer deposited Zr-Sn-Ti-O films |
US6844260B2 (en) * | 2003-01-30 | 2005-01-18 | Micron Technology, Inc. | Insitu post atomic layer deposition destruction of active species |
US7135369B2 (en) * | 2003-03-31 | 2006-11-14 | Micron Technology, Inc. | Atomic layer deposited ZrAlxOy dielectric layers including Zr4AlO9 |
-
2003
- 2003-06-24 US US10/602,323 patent/US7192824B2/en not_active Expired - Lifetime
-
2004
- 2004-08-31 US US10/931,343 patent/US7312494B2/en not_active Expired - Lifetime
-
2006
- 2006-07-26 US US11/493,074 patent/US20060261397A1/en not_active Abandoned
Patent Citations (99)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4993358A (en) * | 1989-07-28 | 1991-02-19 | Watkins-Johnson Company | Chemical vapor deposition reactor and method of operation |
US6013553A (en) * | 1997-07-24 | 2000-01-11 | Texas Instruments Incorporated | Zirconium and/or hafnium oxynitride gate dielectric |
US6020243A (en) * | 1997-07-24 | 2000-02-01 | Texas Instruments Incorporated | Zirconium and/or hafnium silicon-oxynitride gate dielectric |
US6020024A (en) * | 1997-08-04 | 2000-02-01 | Motorola, Inc. | Method for forming high dielectric constant metal oxides |
US20020019125A1 (en) * | 1997-10-09 | 2002-02-14 | Werner Juengling | Methods of forming materials between conductive electrical components, and insulating materials |
US6350704B1 (en) * | 1997-10-14 | 2002-02-26 | Micron Technology Inc. | Porous silicon oxycarbide integrated circuit insulator |
US6025627A (en) * | 1998-05-29 | 2000-02-15 | Micron Technology, Inc. | Alternate method and structure for improved floating gate tunneling devices |
US6515510B2 (en) * | 1998-08-04 | 2003-02-04 | Micron Technology, Inc. | Programmable logic array with vertical transistors |
US6514820B2 (en) * | 1998-08-27 | 2003-02-04 | Micron Technology, Inc. | Method for forming single electron resistor memory |
US20030003722A1 (en) * | 1998-09-01 | 2003-01-02 | Micron Technology, Inc. | Chemical vapor deposition systems including metal complexes with chelating O- and/or N-donor ligands |
US6171900B1 (en) * | 1999-04-15 | 2001-01-09 | Taiwan Semiconductor Manufacturing Company | CVD Ta2O5/oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFET |
US6187484B1 (en) * | 1999-08-31 | 2001-02-13 | Micron Technology, Inc. | Irradiation mask |
US20020004277A1 (en) * | 2000-02-28 | 2002-01-10 | Micron Technology, Inc. | Structure and method for dual gate oxide thicknesses |
US20020004276A1 (en) * | 2000-02-28 | 2002-01-10 | Micron Technology, Inc. | Structure and method for dual gate oxide thicknesses |
US20020001971A1 (en) * | 2000-06-27 | 2002-01-03 | Hag-Ju Cho | Methods of manufacturing integrated circuit devices that include a metal oxide layer disposed on another layer to protect the other layer from diffusion of impurities and integrated circuit devices manufactured using same |
US6521911B2 (en) * | 2000-07-20 | 2003-02-18 | North Carolina State University | High dielectric constant metal silicates formed by controlled metal-surface reactions |
US20020025628A1 (en) * | 2000-08-31 | 2002-02-28 | Derderian Garo J. | Capacitor fabrication methods and capacitor constructions |
US20020024080A1 (en) * | 2000-08-31 | 2002-02-28 | Derderian Garo J. | Capacitor fabrication methods and capacitor constructions |
US6518634B1 (en) * | 2000-09-01 | 2003-02-11 | Motorola, Inc. | Strontium nitride or strontium oxynitride gate dielectric |
US20040005625A1 (en) * | 2000-12-12 | 2004-01-08 | Masumi Abe | Method of analyzing expression of gene |
US6524867B2 (en) * | 2000-12-28 | 2003-02-25 | Micron Technology, Inc. | Method for forming platinum-rhodium stack as an oxygen barrier |
US20040009679A1 (en) * | 2001-01-19 | 2004-01-15 | Yeo Jae-Hyun | Method of forming material using atomic layer deposition and method of forming capacitor of semiconductor device using the same |
US20030003702A1 (en) * | 2001-02-09 | 2003-01-02 | Micron Technology, Inc. | Formation of metal oxide gate dielectric |
US20030003730A1 (en) * | 2001-02-13 | 2003-01-02 | Micron Technology, Inc. | Sequential pulse deposition |
US6509280B2 (en) * | 2001-02-22 | 2003-01-21 | Samsung Electronics Co., Ltd. | Method for forming a dielectric layer of a semiconductor device |
US6858865B2 (en) * | 2001-02-23 | 2005-02-22 | Micron Technology, Inc. | Doped aluminum oxide dielectrics |
US6852167B2 (en) * | 2001-03-01 | 2005-02-08 | Micron Technology, Inc. | Methods, systems, and apparatus for uniform chemical-vapor depositions |
US20050034662A1 (en) * | 2001-03-01 | 2005-02-17 | Micro Technology, Inc. | Methods, systems, and apparatus for uniform chemical-vapor depositions |
US20050030825A1 (en) * | 2001-03-15 | 2005-02-10 | Micron Technology, Inc. | Structures, methods, and systems for ferroelectric memory transistors |
US6858444B2 (en) * | 2001-03-15 | 2005-02-22 | Micron Technology, Inc. | Method for making a ferroelectric memory transistor |
US6858120B2 (en) * | 2001-03-15 | 2005-02-22 | Micron Technology, Inc. | Method and apparatus for the fabrication of ferroelectric films |
US20040004244A1 (en) * | 2001-03-15 | 2004-01-08 | Micron Technology, Inc. | Structures, methods, and systems for ferroelectric memory transistors |
US6348386B1 (en) * | 2001-04-16 | 2002-02-19 | Motorola, Inc. | Method for making a hafnium-based insulating film |
US6514828B2 (en) * | 2001-04-20 | 2003-02-04 | Micron Technology, Inc. | Method of fabricating a highly reliable gate oxide |
US20030004051A1 (en) * | 2001-05-18 | 2003-01-02 | Kim Dong-Wan | Dielectric ceramic composition and method for manufacturing multilayered components using the same |
US20030003635A1 (en) * | 2001-05-23 | 2003-01-02 | Paranjpe Ajit P. | Atomic layer deposition for fabricating thin films |
US20050037563A1 (en) * | 2001-06-13 | 2005-02-17 | Ahn Kie Y. | Capacitor structures |
US20030008243A1 (en) * | 2001-07-09 | 2003-01-09 | Micron Technology, Inc. | Copper electroless deposition technology for ULSI metalization |
US20030017717A1 (en) * | 2001-07-18 | 2003-01-23 | Ahn Kie Y. | Methods for forming dielectric materials and methods for forming semiconductor devices |
US20030020169A1 (en) * | 2001-07-24 | 2003-01-30 | Ahn Kie Y. | Copper technology for ULSI metallization |
US20030020180A1 (en) * | 2001-07-24 | 2003-01-30 | Ahn Kie Y. | Copper technology for ULSI metallization |
US20030032270A1 (en) * | 2001-08-10 | 2003-02-13 | John Snyder | Fabrication method for a device for regulating flow of electric current with high dielectric constant gate insulating layer and source/drain forming schottky contact or schottky-like region with substrate |
US6677250B2 (en) * | 2001-08-17 | 2004-01-13 | Micron Technology, Inc. | CVD apparatuses and methods of forming a layer over a semiconductor substrate |
US20050032292A1 (en) * | 2001-08-30 | 2005-02-10 | Micron Technology, Inc. | Crystalline or amorphous medium-K gate oxides, Y2O3 and Gd2O3 |
US7166886B2 (en) * | 2001-08-30 | 2007-01-23 | Micron Technology, Inc. | DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators |
US20050029605A1 (en) * | 2001-08-30 | 2005-02-10 | Micron Technology, Inc. | Highly reliable amorphous high-k gate oxide ZrO2 |
US6683005B2 (en) * | 2001-08-30 | 2004-01-27 | Micron Technology, Inc. | Method of forming capacitor constructions |
US20050023595A1 (en) * | 2001-08-30 | 2005-02-03 | Micron Technology, Inc. | Programmable array logic or memory devices with asymmetrical tunnel barriers |
US20050026349A1 (en) * | 2001-08-30 | 2005-02-03 | Micron Technology, Inc. | Flash memory with low tunnel barrier interpoly insulators |
US6844203B2 (en) * | 2001-08-30 | 2005-01-18 | Micron Technology, Inc. | Gate oxides, and methods of forming |
US6683011B2 (en) * | 2001-11-14 | 2004-01-27 | Regents Of The University Of Minnesota | Process for forming hafnium oxide films |
US6696332B2 (en) * | 2001-12-26 | 2004-02-24 | Texas Instruments Incorporated | Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing |
US6674138B1 (en) * | 2001-12-31 | 2004-01-06 | Advanced Micro Devices, Inc. | Use of high-k dielectric materials in modified ONO structure for semiconductor devices |
US20050026374A1 (en) * | 2002-03-13 | 2005-02-03 | Micron Technology, Inc. | Evaporation of Y-Si-O films for medium-K dielectrics |
US7160577B2 (en) * | 2002-05-02 | 2007-01-09 | Micron Technology, Inc. | Methods for atomic-layer deposition of aluminum oxides in integrated circuits |
US20060000412A1 (en) * | 2002-05-02 | 2006-01-05 | Micron Technology, Inc. | Systems and apparatus for atomic-layer deposition |
US20050023584A1 (en) * | 2002-05-02 | 2005-02-03 | Micron Technology, Inc. | Atomic layer deposition and conversion |
US20050023624A1 (en) * | 2002-06-05 | 2005-02-03 | Micron Technology, Inc. | Atomic layer-deposited HfAlO3 films for gate dielectrics |
US20050023594A1 (en) * | 2002-06-05 | 2005-02-03 | Micron Technology, Inc. | Pr2O3-based la-oxide gate dielectrics |
US20040005982A1 (en) * | 2002-07-05 | 2004-01-08 | Samsung Electro-Mechanics Co., Ltd. | Non-reducible, low temperature sinterable dielectric ceramic composition, multilayer ceramic chip capacitor using the composition and method for preparing the multilayer ceramic chip capacitor |
US20060008966A1 (en) * | 2002-07-08 | 2006-01-12 | Micron Technology, Inc. | Memory utilizing oxide-conductor nanolaminates |
US20040004859A1 (en) * | 2002-07-08 | 2004-01-08 | Micron Technology, Inc. | Memory utilizing oxide nanolaminates |
US20050023574A1 (en) * | 2002-07-08 | 2005-02-03 | Micron Technology, Inc. | Memory utilizing oxide-nitride nanolaminates |
US20040004247A1 (en) * | 2002-07-08 | 2004-01-08 | Micron Technology, Inc. | Memory utilizing oxide-nitride nanolaminates |
US20040023461A1 (en) * | 2002-07-30 | 2004-02-05 | Micron Technology, Inc. | Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics |
US7169673B2 (en) * | 2002-07-30 | 2007-01-30 | Micron Technology, Inc. | Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics |
US20050023627A1 (en) * | 2002-08-15 | 2005-02-03 | Micron Technology, Inc. | Lanthanide doped TiOx dielectric films by plasma oxidation |
US20040033681A1 (en) * | 2002-08-15 | 2004-02-19 | Micron Technology, Inc. | Lanthanide doped TiOx dielectric films by plasma oxidation |
US20040033701A1 (en) * | 2002-08-15 | 2004-02-19 | Micron Technology, Inc. | Lanthanide doped tiox dielectric films |
US20040033661A1 (en) * | 2002-08-16 | 2004-02-19 | Yeo Jae-Hyun | Semiconductor device and method for manufacturing the same |
US20050009370A1 (en) * | 2002-08-21 | 2005-01-13 | Ahn Kie Y. | Composite dielectric forming methods and composite dielectrics |
US20040038554A1 (en) * | 2002-08-21 | 2004-02-26 | Ahn Kie Y. | Composite dielectric forming methods and composite dielectrics |
US20040038525A1 (en) * | 2002-08-26 | 2004-02-26 | Shuang Meng | Enhanced atomic layer deposition |
US6673701B1 (en) * | 2002-08-27 | 2004-01-06 | Micron Technology, Inc. | Atomic layer deposition methods |
US20050023625A1 (en) * | 2002-08-28 | 2005-02-03 | Micron Technology, Inc. | Atomic layer deposited HfSiON dielectric films |
US7326980B2 (en) * | 2002-08-28 | 2008-02-05 | Micron Technology, Inc. | Devices with HfSiON dielectric films which are Hf-O rich |
US6686212B1 (en) * | 2002-10-31 | 2004-02-03 | Sharp Laboratories Of America, Inc. | Method to deposit a stacked high-κ gate dielectric for CMOS applications |
US6982230B2 (en) * | 2002-11-08 | 2006-01-03 | International Business Machines Corporation | Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures |
US20060003517A1 (en) * | 2002-12-04 | 2006-01-05 | Micron Technology, Inc. | Atomic layer deposited Zr-Sn-Ti-O films using TiI4 |
US20050029604A1 (en) * | 2002-12-04 | 2005-02-10 | Micron Technology, Inc. | Atomic layer deposited Zr-Sn-Ti-O films using TiI4 |
US6852645B2 (en) * | 2003-02-13 | 2005-02-08 | Texas Instruments Incorporated | High temperature interface layer growth for high-k gate dielectric |
US20060001151A1 (en) * | 2003-03-04 | 2006-01-05 | Micron Technology, Inc. | Atomic layer deposited dielectric layers |
US7183186B2 (en) * | 2003-04-22 | 2007-02-27 | Micro Technology, Inc. | Atomic layer deposited ZrTiO4 films |
US20050020017A1 (en) * | 2003-06-24 | 2005-01-27 | Micron Technology, Inc. | Lanthanide oxide / hafnium oxide dielectric layers |
US20050023626A1 (en) * | 2003-06-24 | 2005-02-03 | Micron Technology, Inc. | Lanthanide oxide / hafnium oxide dielectrics |
US20050029547A1 (en) * | 2003-06-24 | 2005-02-10 | Micron Technology, Inc. | Lanthanide oxide / hafnium oxide dielectric layers |
US20050026458A1 (en) * | 2003-07-03 | 2005-02-03 | Cem Basceri | Methods of forming hafnium-containing materials, methods of forming hafnium oxide, and constructions comprising hafnium oxide |
US6989573B2 (en) * | 2003-10-10 | 2006-01-24 | Micron Technology, Inc. | Lanthanide oxide/zirconium oxide atomic layer deposited nanolaminate gate dielectrics |
US20060023513A1 (en) * | 2004-07-27 | 2006-02-02 | Micron Technology, Inc. | High density stepped, non-planar nitride read only memory |
US20060024975A1 (en) * | 2004-08-02 | 2006-02-02 | Micron Technology, Inc. | Atomic layer deposition of zirconium-doped tantalum oxide films |
US20060028867A1 (en) * | 2004-08-03 | 2006-02-09 | Micron Technology, Inc. | Non-planar flash memory having shielding between floating gates |
US20060028869A1 (en) * | 2004-08-03 | 2006-02-09 | Micron Technology, Inc. | High density stepped, non-planar flash memory |
US20070037415A1 (en) * | 2004-12-13 | 2007-02-15 | Micron Technology, Inc. | Lanthanum hafnium oxide dielectrics |
US20070020835A1 (en) * | 2005-02-10 | 2007-01-25 | Micron Technology, Inc. | Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics |
US20070010061A1 (en) * | 2005-07-07 | 2007-01-11 | Micron Technology, Inc. | Metal-substituted transistor gates |
US20070010060A1 (en) * | 2005-07-07 | 2007-01-11 | Micron Technology, Inc. | Metal-substituted transistor gates |
US20070007560A1 (en) * | 2005-07-07 | 2007-01-11 | Micron Technology, Inc. | Metal-substituted transistor gates |
US20070007635A1 (en) * | 2005-07-07 | 2007-01-11 | Micron Technology, Inc. | Self aligned metal gates on high-k dielectrics |
US20070018214A1 (en) * | 2005-07-25 | 2007-01-25 | Micron Technology, Inc. | Magnesium titanium oxide films |
Cited By (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7670646B2 (en) | 2002-05-02 | 2010-03-02 | Micron Technology, Inc. | Methods for atomic-layer deposition |
US7923381B2 (en) | 2002-12-04 | 2011-04-12 | Micron Technology, Inc. | Methods of forming electronic devices containing Zr-Sn-Ti-O films |
US8445952B2 (en) | 2002-12-04 | 2013-05-21 | Micron Technology, Inc. | Zr-Sn-Ti-O films |
US8765616B2 (en) | 2004-08-02 | 2014-07-01 | Micron Technology, Inc. | Zirconium-doped tantalum oxide films |
US7727905B2 (en) | 2004-08-02 | 2010-06-01 | Micron Technology, Inc. | Zirconium-doped tantalum oxide films |
US8288809B2 (en) | 2004-08-02 | 2012-10-16 | Micron Technology, Inc. | Zirconium-doped tantalum oxide films |
US7776762B2 (en) | 2004-08-02 | 2010-08-17 | Micron Technology, Inc. | Zirconium-doped tantalum oxide films |
US8907486B2 (en) | 2004-08-26 | 2014-12-09 | Micron Technology, Inc. | Ruthenium for a dielectric containing a lanthanide |
US8558325B2 (en) | 2004-08-26 | 2013-10-15 | Micron Technology, Inc. | Ruthenium for a dielectric containing a lanthanide |
US7719065B2 (en) | 2004-08-26 | 2010-05-18 | Micron Technology, Inc. | Ruthenium layer for a dielectric layer containing a lanthanide oxide |
US8154066B2 (en) | 2004-08-31 | 2012-04-10 | Micron Technology, Inc. | Titanium aluminum oxide films |
US8237216B2 (en) | 2004-08-31 | 2012-08-07 | Micron Technology, Inc. | Apparatus having a lanthanum-metal oxide semiconductor device |
US7867919B2 (en) | 2004-08-31 | 2011-01-11 | Micron Technology, Inc. | Method of fabricating an apparatus having a lanthanum-metal oxide dielectric layer |
US8541276B2 (en) | 2004-08-31 | 2013-09-24 | Micron Technology, Inc. | Methods of forming an insulating metal oxide |
US8524618B2 (en) | 2005-01-05 | 2013-09-03 | Micron Technology, Inc. | Hafnium tantalum oxide dielectrics |
US8278225B2 (en) | 2005-01-05 | 2012-10-02 | Micron Technology, Inc. | Hafnium tantalum oxide dielectrics |
US7754618B2 (en) | 2005-02-10 | 2010-07-13 | Micron Technology, Inc. | Method of forming an apparatus having a dielectric containing cerium oxide and aluminum oxide |
US7687409B2 (en) | 2005-03-29 | 2010-03-30 | Micron Technology, Inc. | Atomic layer deposited titanium silicon oxide films |
US8076249B2 (en) | 2005-03-29 | 2011-12-13 | Micron Technology, Inc. | Structures containing titanium silicon oxide |
US8102013B2 (en) | 2005-03-29 | 2012-01-24 | Micron Technology, Inc. | Lanthanide doped TiOx films |
US8399365B2 (en) | 2005-03-29 | 2013-03-19 | Micron Technology, Inc. | Methods of forming titanium silicon oxide |
US8084808B2 (en) | 2005-04-28 | 2011-12-27 | Micron Technology, Inc. | Zirconium silicon oxide films |
US7662729B2 (en) | 2005-04-28 | 2010-02-16 | Micron Technology, Inc. | Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer |
US8501563B2 (en) | 2005-07-20 | 2013-08-06 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
US8288818B2 (en) | 2005-07-20 | 2012-10-16 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
US8921914B2 (en) | 2005-07-20 | 2014-12-30 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
US7989290B2 (en) | 2005-08-04 | 2011-08-02 | Micron Technology, Inc. | Methods for forming rhodium-based charge traps and apparatus including rhodium-based charge traps |
US8314456B2 (en) | 2005-08-04 | 2012-11-20 | Micron Technology, Inc. | Apparatus including rhodium-based charge traps |
US9496355B2 (en) | 2005-08-04 | 2016-11-15 | Micron Technology, Inc. | Conductive nanoparticles |
US8110469B2 (en) | 2005-08-30 | 2012-02-07 | Micron Technology, Inc. | Graded dielectric layers |
US8951903B2 (en) | 2005-08-30 | 2015-02-10 | Micron Technology, Inc. | Graded dielectric structures |
US9627501B2 (en) | 2005-08-30 | 2017-04-18 | Micron Technology, Inc. | Graded dielectric structures |
US7709402B2 (en) | 2006-02-16 | 2010-05-04 | Micron Technology, Inc. | Conductive layers for hafnium silicon oxynitride films |
US8785312B2 (en) | 2006-02-16 | 2014-07-22 | Micron Technology, Inc. | Conductive layers for hafnium silicon oxynitride |
US8466016B2 (en) | 2006-08-31 | 2013-06-18 | Micron Technolgy, Inc. | Hafnium tantalum oxynitride dielectric |
US8759170B2 (en) | 2006-08-31 | 2014-06-24 | Micron Technology, Inc. | Hafnium tantalum oxynitride dielectric |
US8084370B2 (en) | 2006-08-31 | 2011-12-27 | Micron Technology, Inc. | Hafnium tantalum oxynitride dielectric |
US7635634B2 (en) * | 2007-04-16 | 2009-12-22 | Infineon Technologies Ag | Dielectric apparatus and associated methods |
US8016945B2 (en) | 2007-12-21 | 2011-09-13 | Applied Materials, Inc. | Hafnium oxide ALD process |
US20090162551A1 (en) * | 2007-12-21 | 2009-06-25 | Thomas Zilbauer | Hafnium oxide ald process |
Also Published As
Publication number | Publication date |
---|---|
US7192824B2 (en) | 2007-03-20 |
US20050020017A1 (en) | 2005-01-27 |
US20050029547A1 (en) | 2005-02-10 |
US7312494B2 (en) | 2007-12-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7312494B2 (en) | Lanthanide oxide / hafnium oxide dielectric layers | |
US7183186B2 (en) | Atomic layer deposited ZrTiO4 films | |
US8154066B2 (en) | Titanium aluminum oxide films | |
US8524618B2 (en) | Hafnium tantalum oxide dielectrics | |
US7754618B2 (en) | Method of forming an apparatus having a dielectric containing cerium oxide and aluminum oxide | |
US7875912B2 (en) | Zrx Hfy Sn1-x-y O2 films as high k gate dielectrics | |
US8765616B2 (en) | Zirconium-doped tantalum oxide films | |
US7411237B2 (en) | Lanthanum hafnium oxide dielectrics | |
US7531869B2 (en) | Lanthanum aluminum oxynitride dielectric films | |
US7135369B2 (en) | Atomic layer deposited ZrAlxOy dielectric layers including Zr4AlO9 | |
US8237216B2 (en) | Apparatus having a lanthanum-metal oxide semiconductor device | |
US20070049023A1 (en) | Zirconium-doped gadolinium oxide films |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |