US20050133820A1 - Heterojunction bipolar transistor and method of fabricating the same - Google Patents
Heterojunction bipolar transistor and method of fabricating the same Download PDFInfo
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- US20050133820A1 US20050133820A1 US10/857,655 US85765504A US2005133820A1 US 20050133820 A1 US20050133820 A1 US 20050133820A1 US 85765504 A US85765504 A US 85765504A US 2005133820 A1 US2005133820 A1 US 2005133820A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
- H01L29/66318—Heterojunction transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
Definitions
- the present invention relates to a heterojunction bipolar transistor and a method of fabricating the same. More specifically, the present invention relates to a heterojunction bipolar transistor using a compound semiconductor and a method of fabricating the same.
- a heterojunction bipolar transistor using a compound semiconductor such as GaAs and InP is actively used as an essential element having various functions for communications because the heterojunction bipolar transistor has very high speed, very high frequency, large current driving capability, signal linearity, and uniform operation voltage.
- the heterojunction bipolar transistor is used as a high-efficiency large-power amplifier in an output amplifier of a mobile terminal.
- a mixed signal heterojunction bipolar transistor technique greatly affects the construction of an optical communication system.
- the heterojunction bipolar transistor is disclosed in Korean Patent No. 347520.
- FIG. 1 is a cross-sectional view of the heterojunction bipolar transistor.
- a sub-collector layer 102 , a collector layer 103 , a base layer 104 , an emitter layer 105 , and an emitter cap layer 106 are sequentially epitaxial-grown on a compound semiconductor substrate 101 .
- An emitter electrode 111 is formed on the emitter cap layer 106 .
- the emitter cap layer 106 and the emitter layer 105 are etched into a mesa, and base electrodes 112 are formed on the base layer 104 .
- the base layer 104 and the collector layer 103 are etched into a mesa, and collector electrodes 113 are formed on the sub-collector layer 102 .
- a predetermined isolation region is defined, and a dielectric insulating layer 121 is formed on the overall surface of the substrate.
- via holes are formed in the insulating layer 121 to expose the emitter, base, and collector electrodes, and a metal 122 is deposited or plated on the exposed emitter, base, and collector electrodes to form transmission lines.
- the transmission lines 122 are connected to other active or passive elements of the transistor.
- the dielectric insulating layer 121 forms interfaces with the side of the emitter mesa, the side of the base-collector mesa, the exposed portion of the surface of the emitter layer, the exposed portion of the surface of the base layer, and the exposed portion of the surface of the sub-collector layer.
- the dielectric insulating layer 121 is formed of SiO2, Si3N4, or SiOxNy.
- recombination sites are formed at the interface of the compound semiconductor and the dielectric insulating layer because bonding coherence or smooth transition between the compound semiconductor and the dielectric insulating layer is difficult to form at the interface. This reduces a current gain of the bipolar transistor.
- FIGS. 2 a and 2 b respectively show DC current gains before and after deposition of a SiNx dielectric insulating layer of a heterojunction bipolar transistor having an InP emitter layer and an InGaAs base layer.
- FIGS. 2 a and 2 b show a collector current Ic, a base current Ib, and a current gain according to a variation in a base-emitter voltage Vbe.
- the current gain corresponds to a value obtained by dividing the collector current Ic by the base current Ib.
- the current gain after deposition of the SiNx dielectric insulating layer is considerably reduced as the base current Ib is increased, compared to the current gain before deposition of the SiNx insulating layer.
- a conventional technique has employed interface control layers. Specifically, a method of forming an interface layer between a compound semiconductor and an insulating layer was used.
- the interface layer is formed of one of the following combination layers.
- Oxide or insulator interface control layers such as Al 2 O 3 /In(PO 3 ) 3 /InP, SiO 2 /ECR oxide/InP, SiNx/anodic oxide/InP, and SiNx/PN/sulfur-treated InP.
- Interface control layers including sulfur such as SiO 2 /S/InP, SiO 2 /SiS 2 /InP, Si 3 N 4 /polysulfide/InP, and SiNx/InS/InP.
- Interface control layers using an ultra thin Si layer such as SiO 2 /Si/InGaAs, Si 3 N 4 /Si/InGaAs, SiO 2 /Si 3 N 4 /Si/InGaAs, SiO 2 /Si/InP, and Si 3 N 4 SiNx/Si/InP.
- the conventional interface control layer forming technique appropriately compensates a difference between the compound semiconductor and the insulating layer to prevent interface characteristic from being abruptly varied
- the conventional technique is not an appropriate method for solving the aforementioned problem. That is, the problem caused by the surface recombination effect is not solved because of non-continuity between the compound semiconductor and interface control layer and between the interface control layer and the insulating layer.
- a method of fabricating a heterojunction bipolar transistor comprises sequentially forming a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer on a substrate; forming an emitter electrode on a first region of the emitter cap layer; selectively etching the emitter cap layer and the emitter layer to expose a portion of the base layer; forming a base electrode on a second region of the exposed portion of the base layer; selectively etching the base layer and the collector layer to expose a portion of the sub-collector layer; forming a collector electrode on a third region of the exposed portion of the sub-collector layer; forming a first dielectric layer on the overall surface of the substrate; selectively etching the first dielectric layer and the sub-collector layer to define an isolation region; forming a second dielectric layer on the overall surface of the substrate; selectively etching the second dielectric layer to form via holes on the emitter, base, and collector electrodes, respectively;
- a heterojunction bipolar transistor comprises a sub-collector layer formed on a substrate; a collector layer formed on a first region of the sub-collector layer; a collector electrode formed on a second region of the sub-collector layer; a base layer formed on the collector layer; an emitter layer formed on a third region of the base layer; a base electrode formed on a fourth region of the base layer; an emitter cap layer formed on the emitter layer; an emitter electrode formed on a fifth region of the emitter cap layer; and a first dielectric layer formed on the substrate, the first dielectric layer having via holes that expose at least portions of the collector, base, and emitter electrodes.
- FIG. 1 is a cross-sectional view of a conventional heterojunction bipolar transistor
- FIGS. 2 a and 2 b respectively show DC current gains before and after deposition of a dielectric insulating layer of a heterojunction bipolar transistor
- FIGS. 3 through 14 are cross-sectional views showing a process of fabricating a heterojunction bipolar transistor according to an embodiment of the present invention.
- a heterojunction bipolar transistor and a method of fabricating the same according to an embodiment of the present invention are explained below.
- FIGS. 3 through 14 are cross-sectional views showing a process of fabricating the heterojunction bipolar transistor according to the embodiment of the present invention.
- a sub-collector layer 20 , a collector layer 30 , a base layer 40 , an emitter layer 50 , and an emitter cap layer 60 are sequentially formed on a semiconductor substrate 10 .
- These layers 20 , 30 , 40 , 50 , and 60 are grown on the semiconductor substrate 10 using an epitaxial growth such as molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD).
- MBE molecular beam epitaxy
- MOCVD metal organic chemical vapor deposition
- the emitter cap layer 60 is formed for the purpose of reducing a contact resistance between the emitter layer 50 and an emitter electrode that will be formed later. Thus, the emitter cap layer 60 can be omitted.
- the substrate 10 is an electrically semi-insulating compound semiconductor substrate.
- a GaAs or InP compound semiconductor substrate can be used as the substrate 10 .
- Each of the sub-collector layer 20 , collector layer 30 , base layer 40 , emitter layer 50 , and emitter cap layer 60 can be formed of a combination of various III-V compound semiconductors, such as GaAs, InP, InAlAs, InGaAs, InGaP, AlGaAs, and so on, to construct the heterojunction bipolar transistor on the substrate 10 .
- an n+ GaAs sub-collector layer 20 , an n-type GaAs collector layer 30 , and a p+ GaAs base layer 40 are sequentially grown on the GaAs substrate 10 .
- an n-type AlGaAs emitter layer 50 and an n+ InGaAs emitter cap layer 60 are grown on the emitter layer 50 .
- the sub-collector layer 20 , collector layer 30 , and base layer are formed of AlGaAs on the InP substrate, and an InP emitter layer 50 and an InGaAs emitter cap layer 60 are sequentially grown thereon.
- an emitter electrode 62 is formed on a predetermined region of the emitter cap layer 60 .
- the emitter electrode 62 is formed in such a manner that a conventional electrode material is deposited and patterned through photolithography and lift-off processes.
- the emitter electrode 62 can be formed of Ti/Pt/Au, Au—Ge, Pd/In, Al/Ni/Ge, Ni/Au—Ge, or Pd/Au—Ge.
- the emitter cap layer 60 and the emitter layer 50 are selectively etched using the emitter electrode 62 or a predetermined photoresist pattern (not shown) formed by photolithography as a mask, to form an emitter mesa, that is, an intrinsic base region.
- base electrodes 42 are formed of a conventional electrode material on predetermined regions of the base layer 40 . As shown in FIG. 7 , predetermined portions of the base layer 40 and collector layer 30 are selectively etched to form a base-collector mesa 200 .
- collector electrodes 22 are formed of a conventional electrode material on predetermined regions of the sub-collector layer 20 .
- a dielectric layer 70 is coated by tens of nm on the overall surface of the substrate 10 .
- the dielectric layer 70 is formed of an oxide or a nitride.
- a photoresist pattern 72 is formed as an etch mask on the dielectric layer 70 formed on the emitter electrode 62 , base electrode 42 , and collector electrode 22 in order to define an isolation region. Then, exposed portions of the dielectric layer 70 and sub-collector layer 20 are sequentially etched using the photoresist pattern 72 as a mask.
- the dielectric layer 70 can be etched through dry etching such as reactive ion etching (RIE) or wet etching using a buffered oxide etchant (BOE).
- RIE reactive ion etching
- BOE buffered oxide etchant
- the sub-collector 20 can be also etched using dry etching or wet etching.
- the photoresist pattern is removed, and then a dielectric layer 80 is coated on the dielectric layer 70 .
- the dielectric layer 80 is formed of a material different from the dielectric layer 70 through a deposition method and conditions different from those of the dielectric layer 70 , such that the dielectric layer 80 is harder to etch than the dielectric layer 70 or an etch rate of the dielectric layer 80 is lower than that of the dielectric layer 70 .
- the dielectric layer 70 is formed of SiOx rapidly deposited at the normal temperature
- the dielectric layer 80 can be formed of Al 2 O 3 slowly deposited at a high temperature.
- via holes 82 that connect the emitter, base, and collector electrodes 62 , 42 , and 22 to other elements of the bipolar transistor are formed.
- a photoresist pattern 82 is formed as a mask on the dielectric layer 80 through photolithography, and the dielectric layer 80 is etched using the photoresist pattern 84 as a mask such that the etched dielectric layer 80 has no undercut, to form the via holes 82 .
- the via holes 82 have vertical cross sections.
- ICP inductively coupled plasma
- the portions of the dielectric layer 80 in which the via holes 82 are formed must be removed.
- the portions of the dielectric layer 70 formed under the dielectric layer 80 in which the via holes are formed, can be partially or completely removed.
- the dielectric layer 70 and the photoresist pattern are removed through the via holes 82 .
- the dielectric layer 70 is etched through wet etching using a BOE or dry etching having isotropic etch characteristics.
- the dielectric layer 80 is etched at an etch rate considerably lower than the etch rate of the dielectric layer 70 .
- a specific gap is formed between the dielectric layer 80 and the side of the emitter mesa 100 , the side of the base-collector mesa 200 , the exposed portion of the surface of the base layer 40 , and the exposed portion of the surface of the sub-collector layer 20 . If the dielectric layer 70 is not completely etched, the dielectric layer 70 is partially left in the gap.
- transmission lines 90 are connected to the emitter, base, and collector electrodes 62 , 42 , and 22 to achieve the heterojunction bipolar transistor according to the present invention.
- the present invention can reduce a surface recombination current generated at the interface of the surface of a compound semiconductor and an insulating layer so as to improve a DC current gain of a heterojunction bipolar transistor. Accordingly, the performance of the heterojunction bipolar transistor can be maximized.
Abstract
Description
- This application claims priority to and the benefit of Korea Patent Application No. 2003-94071 filed on Dec. 19, 2003 in the Korean Intellectual Property Office, the content of which is incorporated herein by reference.
- (a) Field of the Invention
- The present invention relates to a heterojunction bipolar transistor and a method of fabricating the same. More specifically, the present invention relates to a heterojunction bipolar transistor using a compound semiconductor and a method of fabricating the same.
- (b) Description of the Related Art
- A heterojunction bipolar transistor using a compound semiconductor such as GaAs and InP is actively used as an essential element having various functions for communications because the heterojunction bipolar transistor has very high speed, very high frequency, large current driving capability, signal linearity, and uniform operation voltage. For instance, the heterojunction bipolar transistor is used as a high-efficiency large-power amplifier in an output amplifier of a mobile terminal. Furthermore, a mixed signal heterojunction bipolar transistor technique greatly affects the construction of an optical communication system. The heterojunction bipolar transistor is disclosed in Korean Patent No. 347520.
FIG. 1 is a cross-sectional view of the heterojunction bipolar transistor. - To fabricate the heterojunction bipolar transistor shown in
FIG. 1 , asub-collector layer 102, acollector layer 103, abase layer 104, anemitter layer 105, and anemitter cap layer 106 are sequentially epitaxial-grown on acompound semiconductor substrate 101. Anemitter electrode 111 is formed on theemitter cap layer 106. Then, theemitter cap layer 106 and theemitter layer 105 are etched into a mesa, andbase electrodes 112 are formed on thebase layer 104. Subsequently, thebase layer 104 and thecollector layer 103 are etched into a mesa, andcollector electrodes 113 are formed on thesub-collector layer 102. Then, a predetermined isolation region is defined, and adielectric insulating layer 121 is formed on the overall surface of the substrate. Finally, via holes are formed in theinsulating layer 121 to expose the emitter, base, and collector electrodes, and ametal 122 is deposited or plated on the exposed emitter, base, and collector electrodes to form transmission lines. Thetransmission lines 122 are connected to other active or passive elements of the transistor. - In the above-described conventional method of fabricating the heterojunction bipolar transistor, the
dielectric insulating layer 121 forms interfaces with the side of the emitter mesa, the side of the base-collector mesa, the exposed portion of the surface of the emitter layer, the exposed portion of the surface of the base layer, and the exposed portion of the surface of the sub-collector layer. Thedielectric insulating layer 121 is formed of SiO2, Si3N4, or SiOxNy. However, recombination sites are formed at the interface of the compound semiconductor and the dielectric insulating layer because bonding coherence or smooth transition between the compound semiconductor and the dielectric insulating layer is difficult to form at the interface. This reduces a current gain of the bipolar transistor. -
FIGS. 2 a and 2 b respectively show DC current gains before and after deposition of a SiNx dielectric insulating layer of a heterojunction bipolar transistor having an InP emitter layer and an InGaAs base layer.FIGS. 2 a and 2 b show a collector current Ic, a base current Ib, and a current gain according to a variation in a base-emitter voltage Vbe. The current gain corresponds to a value obtained by dividing the collector current Ic by the base current Ib. As shown inFIGS. 2 a and 2 b, the current gain after deposition of the SiNx dielectric insulating layer is considerably reduced as the base current Ib is increased, compared to the current gain before deposition of the SiNx insulating layer. This is because of a strong interaction of the insulating layer and an extrinsic base surface having a large surface recombination rate due to a high doping concentration (1019 to 1020 cm−3), such as at the side of the base-collector mesa and the exposed portion of the surface of the base layer. The surface recombination effect becomes stronger as the size of the transistor is decreased in order to improve the performance of the transistor. - To reduce the interface effect, a conventional technique has employed interface control layers. Specifically, a method of forming an interface layer between a compound semiconductor and an insulating layer was used. The interface layer is formed of one of the following combination layers.
- 1) Oxide or insulator interface control layers such as Al2O3/In(PO3)3/InP, SiO2/ECR oxide/InP, SiNx/anodic oxide/InP, and SiNx/PN/sulfur-treated InP.
- 2) Interface control layers including sulfur such as SiO2/S/InP, SiO2/SiS2/InP, Si3N4/polysulfide/InP, and SiNx/InS/InP.
- 3) Interface control layers using an ultra thin Si layer such as SiO2/Si/InGaAs, Si3N4/Si/InGaAs, SiO2/Si3N4/Si/InGaAs, SiO2/Si/InP, and Si3N4SiNx/Si/InP.
- Although the conventional interface control layer forming technique appropriately compensates a difference between the compound semiconductor and the insulating layer to prevent interface characteristic from being abruptly varied, the conventional technique is not an appropriate method for solving the aforementioned problem. That is, the problem caused by the surface recombination effect is not solved because of non-continuity between the compound semiconductor and interface control layer and between the interface control layer and the insulating layer.
- It is an object of the present invention to provide a heterojunction bipolar transistor using a compound semiconductor, and a method of fabricating the same.
- In one aspect of the present invention, a method of fabricating a heterojunction bipolar transistor comprises sequentially forming a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer on a substrate; forming an emitter electrode on a first region of the emitter cap layer; selectively etching the emitter cap layer and the emitter layer to expose a portion of the base layer; forming a base electrode on a second region of the exposed portion of the base layer; selectively etching the base layer and the collector layer to expose a portion of the sub-collector layer; forming a collector electrode on a third region of the exposed portion of the sub-collector layer; forming a first dielectric layer on the overall surface of the substrate; selectively etching the first dielectric layer and the sub-collector layer to define an isolation region; forming a second dielectric layer on the overall surface of the substrate; selectively etching the second dielectric layer to form via holes on the emitter, base, and collector electrodes, respectively; and etching the first dielectric layer through the via holes.
- In another aspect of the present invention, a heterojunction bipolar transistor comprises a sub-collector layer formed on a substrate; a collector layer formed on a first region of the sub-collector layer; a collector electrode formed on a second region of the sub-collector layer; a base layer formed on the collector layer; an emitter layer formed on a third region of the base layer; a base electrode formed on a fourth region of the base layer; an emitter cap layer formed on the emitter layer; an emitter electrode formed on a fifth region of the emitter cap layer; and a first dielectric layer formed on the substrate, the first dielectric layer having via holes that expose at least portions of the collector, base, and emitter electrodes. There is a predetermined gap between the first dielectric layer and at least a portion of the surface of the sub-collector layer, the surface of the emitter layer, the side of the collector layer, the side of the base layer, the side of the emitter layer, and the side of the emitter cap layer.
- The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention, and, together with the description, serve to explain the principles of the invention:
-
FIG. 1 is a cross-sectional view of a conventional heterojunction bipolar transistor; -
FIGS. 2 a and 2 b respectively show DC current gains before and after deposition of a dielectric insulating layer of a heterojunction bipolar transistor; and -
FIGS. 3 through 14 are cross-sectional views showing a process of fabricating a heterojunction bipolar transistor according to an embodiment of the present invention. - In the following detailed description, only the preferred embodiment of the invention has been shown and described, simply by way of illustration of the best mode contemplated by the inventor(s) of carrying out the invention. As will be realized, the invention is capable of modification in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not restrictive.
- In the drawings, thicknesses of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals in the drawings denote like elements, and thus their description will be omitted.
- A heterojunction bipolar transistor and a method of fabricating the same according to an embodiment of the present invention are explained below.
-
FIGS. 3 through 14 are cross-sectional views showing a process of fabricating the heterojunction bipolar transistor according to the embodiment of the present invention. - Referring to
FIG. 3 , asub-collector layer 20, acollector layer 30, abase layer 40, anemitter layer 50, and anemitter cap layer 60 are sequentially formed on asemiconductor substrate 10. Theselayers semiconductor substrate 10 using an epitaxial growth such as molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD). Theemitter cap layer 60 is formed for the purpose of reducing a contact resistance between theemitter layer 50 and an emitter electrode that will be formed later. Thus, theemitter cap layer 60 can be omitted. - The
substrate 10 is an electrically semi-insulating compound semiconductor substrate. A GaAs or InP compound semiconductor substrate can be used as thesubstrate 10. Each of thesub-collector layer 20,collector layer 30,base layer 40,emitter layer 50, andemitter cap layer 60 can be formed of a combination of various III-V compound semiconductors, such as GaAs, InP, InAlAs, InGaAs, InGaP, AlGaAs, and so on, to construct the heterojunction bipolar transistor on thesubstrate 10. - For example, in the case of a
GaAs substrate 10, an n+GaAs sub-collector layer 20, an n-typeGaAs collector layer 30, and a p+GaAs base layer 40 are sequentially grown on theGaAs substrate 10. Subsequently, an n-typeAlGaAs emitter layer 50 and an n+ InGaAsemitter cap layer 60 are grown on theemitter layer 50. In the case of a InP substrate, thesub-collector layer 20,collector layer 30, and base layer are formed of AlGaAs on the InP substrate, and anInP emitter layer 50 and an InGaAsemitter cap layer 60 are sequentially grown thereon. - Referring to
FIG. 4 , anemitter electrode 62 is formed on a predetermined region of theemitter cap layer 60. Specifically, theemitter electrode 62 is formed in such a manner that a conventional electrode material is deposited and patterned through photolithography and lift-off processes. Theemitter electrode 62 can be formed of Ti/Pt/Au, Au—Ge, Pd/In, Al/Ni/Ge, Ni/Au—Ge, or Pd/Au—Ge. - Referring to
FIG. 5 , theemitter cap layer 60 and theemitter layer 50 are selectively etched using theemitter electrode 62 or a predetermined photoresist pattern (not shown) formed by photolithography as a mask, to form an emitter mesa, that is, an intrinsic base region. - Referring to
FIG. 6 ,base electrodes 42 are formed of a conventional electrode material on predetermined regions of thebase layer 40. As shown inFIG. 7 , predetermined portions of thebase layer 40 andcollector layer 30 are selectively etched to form a base-collector mesa 200. - Referring to
FIG. 8 ,collector electrodes 22 are formed of a conventional electrode material on predetermined regions of thesub-collector layer 20. Referring toFIG. 9 , adielectric layer 70 is coated by tens of nm on the overall surface of thesubstrate 10. Thedielectric layer 70 is formed of an oxide or a nitride. - Referring to
FIG. 10 , aphotoresist pattern 72 is formed as an etch mask on thedielectric layer 70 formed on theemitter electrode 62,base electrode 42, andcollector electrode 22 in order to define an isolation region. Then, exposed portions of thedielectric layer 70 andsub-collector layer 20 are sequentially etched using thephotoresist pattern 72 as a mask. Thedielectric layer 70 can be etched through dry etching such as reactive ion etching (RIE) or wet etching using a buffered oxide etchant (BOE). The sub-collector 20 can be also etched using dry etching or wet etching. - Referring to
FIG. 11 , the photoresist pattern is removed, and then adielectric layer 80 is coated on thedielectric layer 70. Thedielectric layer 80 is formed of a material different from thedielectric layer 70 through a deposition method and conditions different from those of thedielectric layer 70, such that thedielectric layer 80 is harder to etch than thedielectric layer 70 or an etch rate of thedielectric layer 80 is lower than that of thedielectric layer 70. For instance, if thedielectric layer 70 is formed of SiOx rapidly deposited at the normal temperature, thedielectric layer 80 can be formed of Al2O3 slowly deposited at a high temperature. - Referring to
FIG. 12 , viaholes 82 that connect the emitter, base, andcollector electrodes photoresist pattern 82 is formed as a mask on thedielectric layer 80 through photolithography, and thedielectric layer 80 is etched using thephotoresist pattern 84 as a mask such that the etcheddielectric layer 80 has no undercut, to form the via holes 82. It is preferable that the via holes 82 have vertical cross sections. For this, inductively coupled plasma (ICP) using a high induced bias or RIE dry etching are used to form the via holes. Here, the portions of thedielectric layer 80 in which the via holes 82 are formed must be removed. On the other hand, the portions of thedielectric layer 70 formed under thedielectric layer 80, in which the via holes are formed, can be partially or completely removed. - Referring to
FIG. 13 , thedielectric layer 70 and the photoresist pattern are removed through the via holes 82. Thedielectric layer 70 is etched through wet etching using a BOE or dry etching having isotropic etch characteristics. Then, thedielectric layer 80 is etched at an etch rate considerably lower than the etch rate of thedielectric layer 70. Here, when thedielectric layer 70 is etched, a specific gap is formed between thedielectric layer 80 and the side of theemitter mesa 100, the side of the base-collector mesa 200, the exposed portion of the surface of thebase layer 40, and the exposed portion of the surface of thesub-collector layer 20. If thedielectric layer 70 is not completely etched, thedielectric layer 70 is partially left in the gap. - Referring to
FIG. 14 ,transmission lines 90 are connected to the emitter, base, andcollector electrodes - As described above, the present invention can reduce a surface recombination current generated at the interface of the surface of a compound semiconductor and an insulating layer so as to improve a DC current gain of a heterojunction bipolar transistor. Accordingly, the performance of the heterojunction bipolar transistor can be maximized.
- While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (11)
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US20090166753A1 (en) * | 2006-06-14 | 2009-07-02 | Nxp B.V. | Semiconductor Device and Method of Manufacturing Such a Device |
US20110140175A1 (en) * | 2009-12-11 | 2011-06-16 | Electronics And Telecommunications Research Institute | Monolithic microwave integrated circuit device and method of forming the same |
US20220416062A1 (en) * | 2021-06-29 | 2022-12-29 | Win Semiconductors Corp. | Heterojunction bipolar transistor and power amplifier |
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JP2010021274A (en) * | 2008-07-09 | 2010-01-28 | Mitsubishi Electric Corp | Semiconductor device |
US9059138B2 (en) | 2012-01-25 | 2015-06-16 | International Business Machines Corporation | Heterojunction bipolar transistor with reduced sub-collector length, method of manufacture and design structure |
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US4751201A (en) * | 1987-03-04 | 1988-06-14 | Bell Communications Research, Inc. | Passivation of gallium arsenide devices with sodium sulfide |
US5949097A (en) * | 1995-03-17 | 1999-09-07 | Hitachi, Ltd. | Semiconductor device, method for manufacturing same, communication system and electric circuit system |
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US5150185A (en) * | 1990-04-18 | 1992-09-22 | Fujitsu Limited | Semiconductor device |
KR100347520B1 (en) | 2000-01-25 | 2002-08-07 | 한국전자통신연구원 | A Heterojunction Bipolar Transistor and, A Method Manufacturing the HBT |
US6998320B2 (en) * | 2003-04-23 | 2006-02-14 | Triquint Semiconductor, Inc. | Passivation layer for group III-V semiconductor devices |
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US4751201A (en) * | 1987-03-04 | 1988-06-14 | Bell Communications Research, Inc. | Passivation of gallium arsenide devices with sodium sulfide |
US5949097A (en) * | 1995-03-17 | 1999-09-07 | Hitachi, Ltd. | Semiconductor device, method for manufacturing same, communication system and electric circuit system |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US20090166753A1 (en) * | 2006-06-14 | 2009-07-02 | Nxp B.V. | Semiconductor Device and Method of Manufacturing Such a Device |
US8373236B2 (en) * | 2006-06-14 | 2013-02-12 | Nxp, B.V. | Semiconductor device and method of manufacturing such a device |
US20110140175A1 (en) * | 2009-12-11 | 2011-06-16 | Electronics And Telecommunications Research Institute | Monolithic microwave integrated circuit device and method of forming the same |
US8124489B2 (en) * | 2009-12-11 | 2012-02-28 | Electronics And Telecommunications Research Institute | Monolithic microwave integrated circuit device and method of forming the same |
US20220416062A1 (en) * | 2021-06-29 | 2022-12-29 | Win Semiconductors Corp. | Heterojunction bipolar transistor and power amplifier |
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