US20050127410A1 - Method of making a MOS transistor - Google Patents

Method of making a MOS transistor Download PDF

Info

Publication number
US20050127410A1
US20050127410A1 US11/044,331 US4433105A US2005127410A1 US 20050127410 A1 US20050127410 A1 US 20050127410A1 US 4433105 A US4433105 A US 4433105A US 2005127410 A1 US2005127410 A1 US 2005127410A1
Authority
US
United States
Prior art keywords
gate electrode
polysilicon gate
mos transistor
metal layer
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/044,331
Inventor
Young Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DB HiTek Co Ltd
Original Assignee
Dongbu Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dongbu Electronics Co Ltd filed Critical Dongbu Electronics Co Ltd
Priority to US11/044,331 priority Critical patent/US20050127410A1/en
Assigned to DONGBUANAM SEMICONDUCTOR, INC. reassignment DONGBUANAM SEMICONDUCTOR, INC. MERGER (SEE DOCUMENT FOR DETAILS). Assignors: DONGBU SEMICONDUCTOR INC.
Publication of US20050127410A1 publication Critical patent/US20050127410A1/en
Assigned to DONGBU ELECTRONICS CO., LTD. reassignment DONGBU ELECTRONICS CO., LTD. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: DONGBU ANAM SEMICONDUCTORS, INC
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Definitions

  • the present disclosure relates to semiconductors and, more particularly, to a method of making a metal-oxide-semiconductor (MOS) transistor.
  • MOS metal-oxide-semiconductor
  • a damascene process has been proposed to solve such problems.
  • the damascene process uses a chemical mechanical polishing (CMP) process repeatedly, thereby complicating the process, although CMP solved the problems of an existing metal gate process.
  • CMP chemical mechanical polishing
  • FIGS. 1 a through 1 c are cross-sectional views illustrating a MOS transistor fabricated according to a known process.
  • a polysilicon gate electrode 5 is formed on a semiconductor substrate 1
  • lightly doped drain (LDD) regions 2 are formed on the substrate 1 at both sides of the polysilicon gate electrode 5 .
  • a spacer 6 is formed on both lateral walls of the polysilicon gate electrode 5 , and source and drain regions 3 are formed on the substrate 1 at both sides of the polysilicon gate electrode 5 .
  • a silicide layer 7 is coated on the top of the polysilicon gate electrode 5 and the surface of the source and drain regions 3 , and a nitride layer 8 is formed on the entire area of the semiconductor substrate having the source and drain regions 3 and the LDD regions 2 so that the polysilicon gate electrode 5 can be covered.
  • an insulating layer 9 is formed on the nitride layer 8 .
  • the nitride layer 8 is usually between about 300 and about 1000 ⁇ in thickness, and is formed by a plasma enhanced chemical vapor deposition (PECVD) process.
  • PECVD plasma enhanced chemical vapor deposition
  • the nitride layer 8 and the insulating layer 9 are polished by a CMP process until the top of the polysilicon gate electrode 5 is exposed.
  • the CMP process is performed by over polishing so that the top of the polysilicon gate electrode 5 , in uniform thickness, can be exposed completely.
  • a metal layer 10 is deposited, in uniform thickness, on the exposed region of the polysilicon gate electrode 5 , the nitride layer 8 and the insulating layer 9 .
  • the metal layer 10 is usually less than about 1000 ⁇ and, in some cases, may be between about 500 and about 1000 ⁇ in thickness.
  • the metal layer 10 may be a multilayer of Ti/TiN, Co/TiN, or Co/Ti/TiN.
  • a thermal treatment is performed on the substrate having the metal layer 10 to transform the polysilicon gate electrode 5 into a metal silicide gate electrode 7 .
  • the thermal treatment process may be performed through two steps, i.e., a first step at a temperature of about 400° C. to about 600° C., and a second step using a rapid thermal process (RTP) at a temperature of about 800° C. to about 1000° C. Subsequently, the residual metal layer, which has not reacted, is removed.
  • RTP rapid thermal process
  • FIGS. 1 a through 1 c are cross-sectional views illustrating a known process of fabricating a MOS transistor.
  • FIGS. 2 a through 2 e are cross-sectional views illustrating the disclosed process of fabricating a MOS transistor.
  • a polysilicon gate electrode may be completely transformed into a metal silicide gate electrode by performing a thermal treatment process for a short time because the exposed area of the polysilicon gate electrode, which is in contact with the metal layer, is increased prior to performing the silicide process.
  • a gate oxide 24 and a polysilicon gate electrode 25 are formed on a semiconductor substrate 21 .
  • LDD regions 22 are formed on the surface of the substrate at both sides of the polysilicon gate electrode 25 .
  • a spacer 26 is formed on both lateral walls of the polysilicon gate electrode 25 , and source and drain regions 23 are formed on the surface of the substrate at both sides of the polysilicon gate electrode 25 including the spacer 26 .
  • a self-aligned silicide layer 27 is formed on the top of the polysilicon gate electrode 25 and on the surface of the source and drain regions 23 .
  • the entire area of the semiconductor substrate 21 including the polysilicon gate electrode 25 and source and drain regions 23 are coated with an insulating layer 29 .
  • the insulating layer 29 may be formed by using the same material as the spacer 26 .
  • the insulating layer 29 is polished by, for example, a CMP process until the top of the polysilicon gate electrode 25 is exposed. Then, some part of the insulating layer 29 and the spacer 26 are etched by the method of dry-etching and/or wet-etching until the polysilicon gate electrode 25 is exposed to more than about 2 ⁇ 3 of its height. In one particular example, the polysilicon gate electrode 25 is exposed from about ⁇ fraction (4/6) ⁇ to about 5 ⁇ 6 of its height.
  • the exposed area of the polysilicon gate electrode 25 is increased, the contact area between the polysilicon gate electrode 25 and a metal layer 30 is expanded, and the polysilicon gate electrode 25 can be completely transformed into a metal silicide gate electrode 31 .
  • the entire area of semiconductor substrate shown in FIG. 2 c is coated with a metal layer 30 of uniform thickness.
  • the metal layer 30 is less than 1000 ⁇ thick and may be, for example, between about 500 and about 1000 ⁇ in thickness.
  • the metal layer 30 may be a multilayer comprising transition metals and their alloys such as, for example, Ti/TiN, Co/TiN, or Co/Ti/TiN.
  • a thermal treatment process is performed on the substrate coated with the metal layer 30 to transform completely the polysilicon gate electrode 25 into a metal silicide gate electrode 31 .
  • the thermal treatment may be a rapid thermal process and may be performed through two steps, i.e., a first step at a temperature of about 400° C. to about 600° C., and a second step using RTP at a temperature of about 800° C. to about 1000° C.
  • the contact area between the metal layer and the polysilicon gate electrode is increased because the exposed area of the polysilicon gate electrode is extended or expanded prior to the formation of the metal layer. Therefore, the polysilicon gate electrode reacts actively with the metal layer, and can be completely transformed into the metal silicide electrode. Subsequently, the residual metal layer that has not reacted is removed to complete a disclosed MOS transistor. Accordingly, the disclosed techniques can completely transform the polysilicon gate electrode into the metal silicide electrode through a brief thermal treatment process by extending the contact area between the polysilicide gate electrode and the metal layer prior to the formation of the metal silicide.
  • the disclosed techniques may be used to produce MOS transistors, each having a gate oxide, a spacer and a gate electrode the top and some part of lateral walls of which are exposed.
  • the MOS transistor further includes a metal layer that is made of transition metals and their alloys.
  • the disclosed MOS transistors each have a gate electrode that is fully silicided.

Abstract

A method of making a MOS transistor is disclosed. The disclosed techniques can completely transform a polysilicon gate electrode into a metal silicide electrode through a brief thermal treatment process by extending the contact area between the polysilicide gate electrode and a metal layer prior to a formation of a metal silicide. The disclosed MOS transistor fabricating method comprises providing a semiconductor substrate further comprising a polysilicon gate electrode with a silicide layer thereon, a spacer, and source and drain regions with LDD regions; forming an insulating layer on the area of the substrate; polishing the insulating layer so that the top of the polysilicon gate electrode can be exposed; etching some part of the insulating layer and the spacer so that both lateral walls of the polysilicon gate electrode can be exposed; forming a metal layer on the substrate resulted from the preceding step so that the polysilicon gate electrode can be covered with the metal layer; and transforming completely the polysilicon gate electrode into a metal silicide gate electrode by performing a thermal treatment process.

Description

    RELATED APPLICATIONS
  • This is a divisional of U.S. application Ser. No. 10/627,059, filed Jul. 25, 2003.
    • TECHNICAL FIELD
  • The present disclosure relates to semiconductors and, more particularly, to a method of making a metal-oxide-semiconductor (MOS) transistor.
    • BACKGROUND
  • As MOS devices have been integrated at a rapid speed, an existing process using polysilicon as a gate electrode has caused many problems such as high gate resistance, depletion of polysilicon, and boron penetration into a channel area. Such problems have been solved by a process including a metal gate electrode. However, the process of forming a metal gate has caused new problems, such as difficulty in etching a metal and limitations in enduring high-temperature thermal treatment.
  • Accordingly, a damascene process has been proposed to solve such problems. However, the damascene process uses a chemical mechanical polishing (CMP) process repeatedly, thereby complicating the process, although CMP solved the problems of an existing metal gate process.
  • To obviate such process complexity, a method of making a MOS transistor using a single CMP process has been proposed. Reference will now be made in detail to a known MOS transistor fabricating method using a single CMP process, examples of which are illustrated in the accompanying drawings. FIGS. 1 a through 1 c are cross-sectional views illustrating a MOS transistor fabricated according to a known process. Referring to FIG. 1 a, a polysilicon gate electrode 5 is formed on a semiconductor substrate 1, and lightly doped drain (LDD) regions 2 are formed on the substrate 1 at both sides of the polysilicon gate electrode 5. Then, a spacer 6 is formed on both lateral walls of the polysilicon gate electrode 5, and source and drain regions 3 are formed on the substrate 1 at both sides of the polysilicon gate electrode 5. Subsequently, a silicide layer 7 is coated on the top of the polysilicon gate electrode 5 and the surface of the source and drain regions 3, and a nitride layer 8 is formed on the entire area of the semiconductor substrate having the source and drain regions 3 and the LDD regions 2 so that the polysilicon gate electrode 5 can be covered. Next, an insulating layer 9 is formed on the nitride layer 8. The nitride layer 8 is usually between about 300 and about 1000 Å in thickness, and is formed by a plasma enhanced chemical vapor deposition (PECVD) process.
  • Next, referring to FIG. 1 b, the nitride layer 8 and the insulating layer 9 are polished by a CMP process until the top of the polysilicon gate electrode 5 is exposed. The CMP process is performed by over polishing so that the top of the polysilicon gate electrode 5, in uniform thickness, can be exposed completely. Then, a metal layer 10 is deposited, in uniform thickness, on the exposed region of the polysilicon gate electrode 5, the nitride layer 8 and the insulating layer 9. The metal layer 10 is usually less than about 1000 Å and, in some cases, may be between about 500 and about 1000 Å in thickness. The metal layer 10 may be a multilayer of Ti/TiN, Co/TiN, or Co/Ti/TiN.
  • Referring to FIG. 1 c, a thermal treatment is performed on the substrate having the metal layer 10 to transform the polysilicon gate electrode 5 into a metal silicide gate electrode 7. The thermal treatment process may be performed through two steps, i.e., a first step at a temperature of about 400° C. to about 600° C., and a second step using a rapid thermal process (RTP) at a temperature of about 800° C. to about 1000° C. Subsequently, the residual metal layer, which has not reacted, is removed.
  • However, such a method of fabricating a MOS transistor cannot completely transform the polysilicon gate electrode 5 into the metal silicide gate electrode 7 because the area where the metal of the metal layer can be diffused while performing the thermal treatment is insufficient due to the small contact area between the polysilicon gate electrode 5 and the metal layer 10. To obviate such a disadvantage, the thermal treatment process to form the metal silicide gate electrode 7 has to be performed for many hours. However, such a long thermal treatment may cause deterioration of device characteristics because an impurity implanted in source and drain regions 3 may be diffused irregularly.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1 a through 1 c are cross-sectional views illustrating a known process of fabricating a MOS transistor.
  • FIGS. 2 a through 2 e are cross-sectional views illustrating the disclosed process of fabricating a MOS transistor.
    • DETAILED DESCRIPTION
  • As disclosed herein, a polysilicon gate electrode may be completely transformed into a metal silicide gate electrode by performing a thermal treatment process for a short time because the exposed area of the polysilicon gate electrode, which is in contact with the metal layer, is increased prior to performing the silicide process.
  • Referring to the example of FIG. 2 a, a gate oxide 24 and a polysilicon gate electrode 25 are formed on a semiconductor substrate 21. Then, LDD regions 22 are formed on the surface of the substrate at both sides of the polysilicon gate electrode 25. A spacer 26 is formed on both lateral walls of the polysilicon gate electrode 25, and source and drain regions 23 are formed on the surface of the substrate at both sides of the polysilicon gate electrode 25 including the spacer 26. A self-aligned silicide layer 27 is formed on the top of the polysilicon gate electrode 25 and on the surface of the source and drain regions 23.
  • As shown in the example of FIG. 2 b, the entire area of the semiconductor substrate 21 including the polysilicon gate electrode 25 and source and drain regions 23 are coated with an insulating layer 29. The insulating layer 29 may be formed by using the same material as the spacer 26.
  • Referring to FIG. 2 c, the insulating layer 29 is polished by, for example, a CMP process until the top of the polysilicon gate electrode 25 is exposed. Then, some part of the insulating layer 29 and the spacer 26 are etched by the method of dry-etching and/or wet-etching until the polysilicon gate electrode 25 is exposed to more than about ⅔ of its height. In one particular example, the polysilicon gate electrode 25 is exposed from about {fraction (4/6)} to about ⅚ of its height. Accordingly, as explained below, as the exposed area of the polysilicon gate electrode 25 is increased, the contact area between the polysilicon gate electrode 25 and a metal layer 30 is expanded, and the polysilicon gate electrode 25 can be completely transformed into a metal silicide gate electrode 31.
  • Next, referring to FIG. 2 d, the entire area of semiconductor substrate shown in FIG. 2 c is coated with a metal layer 30 of uniform thickness. In one example, the metal layer 30 is less than 1000 Å thick and may be, for example, between about 500 and about 1000 Å in thickness. The metal layer 30 may be a multilayer comprising transition metals and their alloys such as, for example, Ti/TiN, Co/TiN, or Co/Ti/TiN.
  • Finally, referring to FIG. 2 e, a thermal treatment process is performed on the substrate coated with the metal layer 30 to transform completely the polysilicon gate electrode 25 into a metal silicide gate electrode 31. The thermal treatment may be a rapid thermal process and may be performed through two steps, i.e., a first step at a temperature of about 400° C. to about 600° C., and a second step using RTP at a temperature of about 800° C. to about 1000° C.
  • As described previously, the contact area between the metal layer and the polysilicon gate electrode is increased because the exposed area of the polysilicon gate electrode is extended or expanded prior to the formation of the metal layer. Therefore, the polysilicon gate electrode reacts actively with the metal layer, and can be completely transformed into the metal silicide electrode. Subsequently, the residual metal layer that has not reacted is removed to complete a disclosed MOS transistor. Accordingly, the disclosed techniques can completely transform the polysilicon gate electrode into the metal silicide electrode through a brief thermal treatment process by extending the contact area between the polysilicide gate electrode and the metal layer prior to the formation of the metal silicide.
  • The disclosed techniques may be used to produce MOS transistors, each having a gate oxide, a spacer and a gate electrode the top and some part of lateral walls of which are exposed. In addition, the MOS transistor further includes a metal layer that is made of transition metals and their alloys. The disclosed MOS transistors each have a gate electrode that is fully silicided.
  • Although certain apparatus constructed in accordance with the teachings of the invention have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers every apparatus, method and article of manufacture fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.

Claims (7)

1. A MOS transistor comprising:
a gate oxide;
a spacer; and
a gate electrode including a top and lateral walls, wherein the top and some part of lateral walls are exposed.
2. A MOS transistor as defined by claim 7, wherein said gate electrode is fully silicided.
3. A MOS transistor as defined by claim 7 further comprising a metal layer comprising transition metals and their alloys, said metal layer being formed on a surface of said gate electrode.
4. A MOS transistor as defined by claim 9, wherein said gate electrode is fully silicided.
5. A MOS transistor as defined by claim 9, wherein said metal layer has a thickness between about 500 Å and about 1000 Å.
6. A MOS transistor as defined by claim 9, wherein said metal layer comprises one or more of Ti/TiN, Co/TiN and Co/Ti/TiN.
7. A MOS transistor as defined by claim 12, wherein said metal layer has a thickness between about 500 Å and about 1000 Å.
US11/044,331 2002-07-25 2005-01-27 Method of making a MOS transistor Abandoned US20050127410A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/044,331 US20050127410A1 (en) 2002-07-25 2005-01-27 Method of making a MOS transistor

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2002-0043796A KR100429007B1 (en) 2002-07-25 2002-07-25 Method of manufacturing MOS Transistor
KR10-2002-0043796 2002-07-25
US10/627,059 US6864178B1 (en) 2002-07-25 2003-07-25 Method of making a MOS transistor
US11/044,331 US20050127410A1 (en) 2002-07-25 2005-01-27 Method of making a MOS transistor

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/627,059 Division US6864178B1 (en) 2002-07-25 2003-07-25 Method of making a MOS transistor

Publications (1)

Publication Number Publication Date
US20050127410A1 true US20050127410A1 (en) 2005-06-16

Family

ID=34214630

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/627,059 Expired - Lifetime US6864178B1 (en) 2002-07-25 2003-07-25 Method of making a MOS transistor
US11/044,331 Abandoned US20050127410A1 (en) 2002-07-25 2005-01-27 Method of making a MOS transistor

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10/627,059 Expired - Lifetime US6864178B1 (en) 2002-07-25 2003-07-25 Method of making a MOS transistor

Country Status (2)

Country Link
US (2) US6864178B1 (en)
KR (1) KR100429007B1 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100563095B1 (en) * 2003-09-24 2006-03-27 동부아남반도체 주식회사 Method for fabricating silicide of semiconductor device
KR100562301B1 (en) * 2003-12-27 2006-03-22 동부아남반도체 주식회사 Gate structure of transistor and manufacturing method therefor
KR101059562B1 (en) * 2004-02-20 2011-08-26 삼성전자주식회사 Sensitivity Bio FET
US7338888B2 (en) * 2004-03-26 2008-03-04 Texas Instruments Incorporated Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same
KR100653689B1 (en) * 2004-06-09 2006-12-04 삼성전자주식회사 salicide process using bi-metal layer and method of fabricating a semiconductor device using the same
KR100550345B1 (en) * 2004-10-11 2006-02-08 삼성전자주식회사 Method for forming silicide layer of semiconductor device
US7560331B2 (en) * 2005-07-28 2009-07-14 Samsung Electronics Co., Ltd. Method for forming a silicided gate
KR100732338B1 (en) 2005-08-11 2007-06-25 동부일렉트로닉스 주식회사 Method for manufacturing semiconductor device
KR100685904B1 (en) * 2005-10-04 2007-02-26 동부일렉트로닉스 주식회사 Method for fabricating fully silicided gate and semiconductor device having it
KR100685905B1 (en) * 2005-10-04 2007-02-26 동부일렉트로닉스 주식회사 Method for fabricating fully silicided gate and semiconductor device with the same
KR100823707B1 (en) * 2006-07-21 2008-04-21 삼성전자주식회사 Method of manufacturing a semiconductor device
US7732878B2 (en) * 2006-10-18 2010-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with continuous contact etch stop layer
CN103632946B (en) * 2012-08-29 2016-03-16 中芯国际集成电路制造(上海)有限公司 The formation method of full-silicide metal gate

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5672544A (en) * 1996-04-22 1997-09-30 Pan; Yang Method for reducing silicided poly gate resistance for very small transistors
US5726477A (en) * 1992-03-20 1998-03-10 Siliconix Incorporated Threshold adjustment in field effect semiconductor devices
US5792699A (en) * 1996-06-03 1998-08-11 Industrial Technology Research Institute Method for reduction of reverse short channel effect in MOSFET
US5920774A (en) * 1998-02-17 1999-07-06 Texas Instruments - Acer Incorporate Method to fabricate short-channel MOSFETS with an improvement in ESD resistance
US6008099A (en) * 1998-03-30 1999-12-28 Advanced Micro Devices, Inc. Fabrication process employing a single dopant implant for formation of a drain extension region and a drain region of an LDD MOSFET using enhanced lateral diffusion
US6100173A (en) * 1998-07-15 2000-08-08 Advanced Micro Devices, Inc. Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process
US6153485A (en) * 1998-11-09 2000-11-28 Chartered Semiconductor Manufacturing Ltd. Salicide formation on narrow poly lines by pulling back of spacer
US6153520A (en) * 1999-01-08 2000-11-28 United Microelectronics Corp. Method for fabricating self-aligned silicide
US6214656B1 (en) * 1999-05-17 2001-04-10 Taiwian Semiconductor Manufacturing Company Partial silicide gate in sac (self-aligned contact) process
US6221746B1 (en) * 1998-12-30 2001-04-24 United Microelectronics Corp. Method for forming a poly gate structure
US6323094B1 (en) * 1998-02-06 2001-11-27 Tsmc Acer Semiconductor Manufacturing Inc. Method to fabricate deep sub-μm CMOSFETs
US6512266B1 (en) * 2001-07-11 2003-01-28 International Business Machines Corporation Method of fabricating SiO2 spacers and annealing caps
US6524939B2 (en) * 2001-02-23 2003-02-25 Vanguard International Semiconductor Corporation Dual salicidation process
US6562718B1 (en) * 2000-12-06 2003-05-13 Advanced Micro Devices, Inc. Process for forming fully silicided gates
US6630721B1 (en) * 2000-05-16 2003-10-07 Advanced Micro Devices, Inc. Polysilicon sidewall with silicide formation to produce high performance MOSFETS
US20040038435A1 (en) * 2002-07-31 2004-02-26 Karsten Wieczorek Method of forming a metal silicide gate in a standard MOS process sequence
US6784098B1 (en) * 2001-04-30 2004-08-31 Taiwan Semiconductor Manufacturing Company Method for forming salicide process

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2764427B1 (en) 1997-06-05 1999-08-20 Atea RACK FOR STORING NUCLEAR FUEL ASSEMBLIES AND MANUFACTURING METHOD THEREOF
KR20000001969A (en) 1998-06-16 2000-01-15 정원포 Method for operating an mp3 player
KR20000004832A (en) 1998-06-30 2000-01-25 허태학 Bionical riverside constuction method

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5726477A (en) * 1992-03-20 1998-03-10 Siliconix Incorporated Threshold adjustment in field effect semiconductor devices
US5672544A (en) * 1996-04-22 1997-09-30 Pan; Yang Method for reducing silicided poly gate resistance for very small transistors
US5792699A (en) * 1996-06-03 1998-08-11 Industrial Technology Research Institute Method for reduction of reverse short channel effect in MOSFET
US6323094B1 (en) * 1998-02-06 2001-11-27 Tsmc Acer Semiconductor Manufacturing Inc. Method to fabricate deep sub-μm CMOSFETs
US5920774A (en) * 1998-02-17 1999-07-06 Texas Instruments - Acer Incorporate Method to fabricate short-channel MOSFETS with an improvement in ESD resistance
US6008099A (en) * 1998-03-30 1999-12-28 Advanced Micro Devices, Inc. Fabrication process employing a single dopant implant for formation of a drain extension region and a drain region of an LDD MOSFET using enhanced lateral diffusion
US6100173A (en) * 1998-07-15 2000-08-08 Advanced Micro Devices, Inc. Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process
US6153485A (en) * 1998-11-09 2000-11-28 Chartered Semiconductor Manufacturing Ltd. Salicide formation on narrow poly lines by pulling back of spacer
US6221746B1 (en) * 1998-12-30 2001-04-24 United Microelectronics Corp. Method for forming a poly gate structure
US6153520A (en) * 1999-01-08 2000-11-28 United Microelectronics Corp. Method for fabricating self-aligned silicide
US6214656B1 (en) * 1999-05-17 2001-04-10 Taiwian Semiconductor Manufacturing Company Partial silicide gate in sac (self-aligned contact) process
US6630721B1 (en) * 2000-05-16 2003-10-07 Advanced Micro Devices, Inc. Polysilicon sidewall with silicide formation to produce high performance MOSFETS
US6562718B1 (en) * 2000-12-06 2003-05-13 Advanced Micro Devices, Inc. Process for forming fully silicided gates
US6524939B2 (en) * 2001-02-23 2003-02-25 Vanguard International Semiconductor Corporation Dual salicidation process
US6784098B1 (en) * 2001-04-30 2004-08-31 Taiwan Semiconductor Manufacturing Company Method for forming salicide process
US6512266B1 (en) * 2001-07-11 2003-01-28 International Business Machines Corporation Method of fabricating SiO2 spacers and annealing caps
US20040038435A1 (en) * 2002-07-31 2004-02-26 Karsten Wieczorek Method of forming a metal silicide gate in a standard MOS process sequence
US6821887B2 (en) * 2002-07-31 2004-11-23 Advanced Micro Devices, Inc. Method of forming a metal silicide gate in a standard MOS process sequence

Also Published As

Publication number Publication date
KR20040009750A (en) 2004-01-31
US6864178B1 (en) 2005-03-08
KR100429007B1 (en) 2004-04-29

Similar Documents

Publication Publication Date Title
US20050127410A1 (en) Method of making a MOS transistor
US6521519B2 (en) MIS transistor and manufacturing method thereof
US5322809A (en) Self-aligned silicide process
US6653700B2 (en) Transistor structure and method of fabrication
US7338898B2 (en) MOS transistor and fabrication thereof
US5447875A (en) Self-aligned silicided gate process
US7342289B2 (en) Strained silicon MOS devices
JPH0870053A (en) Manufacture of semiconductor device
US6319783B1 (en) Process to fabricate a novel source-drain extension
US6054386A (en) Process for forming silicon-on-insulator devices using a nitriding agent
US20060172556A1 (en) Semiconductor device having a high carbon content strain inducing film and a method of manufacture therefor
US7468303B2 (en) Semiconductor device and manufacturing method thereof
US4774201A (en) Tungsten-silicide reoxidation technique using a CVD oxide cap
US5982001A (en) MOSFETS structure with a recessed self-aligned silicide contact and an extended source/drain junction
US7320938B2 (en) Method for reducing dendrite formation in nickel silicon salicide processes
US6531781B2 (en) Fabrication of transistor having elevated source-drain and metal silicide
US6855592B2 (en) Method for manufacturing semiconductor device
US20010053601A1 (en) Method of manufacturing MIS semiconductor device that can control gate depletion and has low resistance gate electrode to which germanium is added
US6063680A (en) MOSFETS with a recessed self-aligned silicide contact and an extended source/drain junction
US6653227B1 (en) Method of cobalt silicidation using an oxide-Titanium interlayer
US6627527B1 (en) Method to reduce metal silicide void formation
US6482739B2 (en) Method for decreasing the resistivity of the gate and the leaky junction of the source/drain
US6773978B1 (en) Methods for improved metal gate fabrication
US6429110B1 (en) MOSFET with both elevated source-drain and metal gate and fabricating method
US6939770B1 (en) Method of fabricating semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process

Legal Events

Date Code Title Description
AS Assignment

Owner name: DONGBUANAM SEMICONDUCTOR, INC., KOREA, REPUBLIC OF

Free format text: MERGER;ASSIGNOR:DONGBU SEMICONDUCTOR INC.;REEL/FRAME:016593/0667

Effective date: 20041221

AS Assignment

Owner name: DONGBU ELECTRONICS CO., LTD., KOREA, REPUBLIC OF

Free format text: CHANGE OF NAME;ASSIGNOR:DONGBU ANAM SEMICONDUCTORS, INC;REEL/FRAME:017718/0964

Effective date: 20060410

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION