US20050121706A1 - Semiconductor nano-rod devices - Google Patents

Semiconductor nano-rod devices Download PDF

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US20050121706A1
US20050121706A1 US11/031,703 US3170305A US2005121706A1 US 20050121706 A1 US20050121706 A1 US 20050121706A1 US 3170305 A US3170305 A US 3170305A US 2005121706 A1 US2005121706 A1 US 2005121706A1
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semiconductor device
nano
silicon
gate
region
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Hao-Yu Chen
Yee-Chia Yeo
Fu-Liang Yang
Chenming Hu
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET

Definitions

  • the present invention relates generally to methods for manufacturing semiconductor devices.
  • the present invention relates to a method of forming a nano-rod structure for a channel of a field effect transistor.
  • MOSFET Metal-oxide-semiconductor field effect transistor
  • ULSI ultra-large scale integrated circuits
  • MOSFET Metal-oxide-semiconductor field effect transistor
  • the gate length of the MOSFET is scaled down into the sub-30 nm regime for improved performance and density, the source and drain increasingly interact with the channel to sometimes gain influence on the channel potential.
  • a transistor with a short gate length often suffers from problems related to the inability of the gate to substantially control the on/off states of the channel, which is often called short-channel effects.
  • a highly scalable device structure that offers superior control of short-channel effects is a wrap-around gate structure for a transistor (a.k.a., surround-gate or gate-all-around transistor structure).
  • a wrap-around gate structure typically has a gate that surrounds or wraps around a channel region. This structure effectively improves the capacitance coupling between the gate and the channel, as compared to conventional bulk silicon substrate transistor structures, double-gate transistor structures, and triple-gate transistor structures. With the wrap-around gate structure, the gate gains significant influence on the channel potential, and therefore improves suppression of short-channel effects.
  • a wrap-around gate structure typically allows the gate length to be scaled down by about 50% more compared to a double-gate structure.
  • the transistor channel may be oriented vertically or horizontally.
  • Many of the existing designs for horizontally oriented channels have a square or rectangular shaped cross-section.
  • enhanced field effect at the corners of the rectangle may cause that part of the transistor to turn on earlier (i.e., having a lower threshold voltage) than parts of the transistor at the flat sides of the rectangular channel cross-section. This may result in a parasitic off-state leakage.
  • a cylindrical channel cross-section is preferred over a rectangular channel cross-section.
  • a method of manufacturing a semiconductor device includes the following steps.
  • a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer.
  • the channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region.
  • the annealing may occur in a reaction chamber having an environment therein including a gas of hydrogen, nitrogen, a mixed gas including hydrogen and argon, a mixed gas including hydrogen and nitrogen, or an inert gas.
  • the annealing environment may be H 2 gas at a pressure ranging from about 1.0 ⁇ 10 ⁇ 9 torr to about 800 torr.
  • the annealing environment may be N 2 gas at a pressure ranging from about 1.0 ⁇ 10 ⁇ 9 torr to about 800 torr.
  • the annealing may occur in a reaction chamber having an evacuated environment.
  • the annealing environment may be a vacuum environment at a pressure ranging from about 1.0 ⁇ 10 ⁇ 10 torr to about 1.0 ⁇ 10 ⁇ 3 torr.
  • the annealing may occur in a reaction chamber having a temperature ranging from about 600° C. to about 1200° C. therein.
  • the annealing occurs at an anneal time ranging from about 1 second to about 2 hours.
  • the annealing may be performed in a hydrogen gas (H 2 ) environment at about 900° C. for about 2 minutes.
  • H 2 hydrogen gas
  • a method of manufacturing a semiconductor device includes the following steps.
  • a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer.
  • the channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region.
  • the insulating layer is etched using an etch chemistry selective against etching the semiconductor layer. The etching is performed long enough so that at least a segment of the rounded channel region is suspended above a proximate portion of the insulating layer.
  • a gate dielectric material is formed on a surface of and about the rounded channel region.
  • a gate electrode material is formed on the gate dielectric and about the rounded channel region.
  • the gate electrode material is patterned to form a gate electrode.
  • the gate electrode includes a gate wrap region that wraps around the rounded channel region and a gate contact region extending therefrom.
  • a semiconductor device which includes an insulating layer, an underlying layer, a layer of semiconductor material, a gate dielectric, and a gate electrode.
  • the insulating layer is over the underlying layer.
  • the layer of semiconductor material is over the insulating layer.
  • the semiconductor layer has a source region, a drain region, and an annealed nano-rod structure extending between the source and drain regions.
  • the gate dielectric is formed on the surface of at least a segment of the nano-rod structure.
  • the gate electrode is formed on the surface of the gate dielectric at the segment.
  • the gate dielectric and the gate electrode are both formed completely around the nano-rod structure at the segment.
  • the nano-rod structure has a cross-section diameter less than about 65 nm.
  • a semiconductor device including a plurality of transistors.
  • Each of the plurality of transistors includes an annealed semiconductor layer, a gate dielectric surface layer, and a gate electrode.
  • the annealed semiconductor layer has a source region, a drain region, and a channel region formed therein.
  • the channel region extends between the source region and the drain region.
  • the source region has a substantially flat source contact portion.
  • the drain region has a substantially flat drain contact portion.
  • the channel region has a substantially circular cross-section shape.
  • the gate dielectric surface layer wraps around a segment of the channel region.
  • the gate electrode has a gate wrap region that wraps around the segment of the channel region and a gate contact region extending therefrom.
  • the gate dielectric layer is between the segment of the channel region and the gate wrap region of the gate electrode.
  • FIGS. 1A, 2A , 3 A, 4 A, 5 A, and 6 A show simplified perspective views of one transistor device being manufactured on a semiconductor device in accordance with a preferred embodiment of the present invention
  • FIGS. 1B, 2B , 3 B, 4 B, 5 B, and 6 B are simplified cross-section views of FIGS. 1A, 2A , 3 A, 4 A, 5 A, and 6 A, respectively, as taken along lines 1 B- 1 B, 2 B- 2 B, 3 B- 3 B, 4 B- 4 B, 5 B- 5 B, and 6 B- 6 B, respectively; and
  • FIGS. 7A-7D show some possible variations of the nano-rod structure formed after an annealing processing in accordance with the present invention.
  • Example embodiments of the present invention will be described herein in a specific context of making semiconductor devices, such as transistors. In other embodiments not shown, embodiments of the present invention also may include nano-wires or quantum-wires formed in accordance with the present invention. The present invention may also be applied, however, to other situations.
  • a preferred manufacturing process in accordance with the present invention may be used to make a transistor device. Some of the manufacturing steps of this preferred embodiment being used to make a transistor embodiment are illustrated in FIGS. 1A-6B . While describing the structure formation steps shown in FIGS. 1A-6B , process parameters and steps for the preferred embodiment will described, as well as some of the possible alternatives or variations of the process parameters and steps. However, the process parameters shown and/or described herein are merely examples to illustrate and describe the present invention. With the benefit of this disclosure, one of ordinary skill in the art will likely realize other variations and embodiments of the present invention within the scope and spirit of the appended patent claims.
  • FIGS. 1A, 2A , 3 A, 4 A, 5 A, and 6 A show simplified perspective views of one transistor device 20 being manufactured on a semiconductor device. Such a semiconductor device will often have millions of these transistors 20 . However, for purposes of illustration and discussion, only one transistor device 20 is shown and the remainder of the semiconductor device is not shown.
  • FIGS. 1B, 2B , 3 B, 4 B, 5 B, and 6 B are simplified cross-section views of FIGS. 1A, 2A , 3 A, 4 A, 5 A, and 6 A, respectively, as taken along lines 1 B- 1 B, 2 B- 2 B, 3 B- 3 B, 4 B- 4 B, 5 B- 5 B, and 6 B- 6 B, respectively.
  • an intermediate structure is shown having an insulating layer 22 formed on an underlying layer 24 .
  • a semiconductor layer 26 is formed on the insulating layer 22 .
  • This type of structure is sometimes referred to as a silicon-on-insulator substrate and is commonly available as a starting material.
  • a patterned active region mask 28 is formed on the semiconductor layer 26 .
  • the mask 28 may be formed from a pad silicon oxide layer 30 and a silicon nitride layer 32 , for example. With the mask 28 in place having a pattern desired to be formed in the semiconductor layer 26 , the semiconductor layer 26 is preferably anisotropically etched (e.g., dry plasma etching) to conform the semiconductor layer 26 to the pattern of the mask 28 .
  • the underlying layer 24 will often be a silicon wafer, for example.
  • the underlying layer 24 may be another type of layer, including but not limited to: an elemental semiconductor, such as germanium; an alloy semiconductor, such as silicon-germanium; or a compound semiconductor, such as gallium arsenide or indium phosphide, for example.
  • the insulating layer 22 in some embodiments may be referred to as a “buried oxide” layer.
  • the insulating layer 22 may be composed of a material or a combination of materials from a large variety of materials, including but not limited to: silicon dioxide, silicon nitride, aluminum oxide, plastic, or polymer, for example.
  • the insulating layer 22 is composed of silicon dioxide (SiO 2 ).
  • the semiconductor layer 26 may be composed of a material or a combination of materials from a large variety of materials, including but not limited to: any semiconductor material, silicon, carbon, elemental semiconductor material (e.g., germanium), alloy semiconductor material (e.g., silicon-germanium, silicon-germanium-carbon), compound semiconductor material (e.g., indium phosphide, gallium arsenide), plastic, or polymer, for example. Such materials may be in crystalline or amorphous forms.
  • the semiconductor layer 26 is composed of silicon.
  • the semiconductor layer 26 is a silicon layer.
  • the mask 28 has been removed and the patterned semiconductor layer 26 remains in the form of an H-shaped, thin silicon island.
  • the patterned semiconductor layer 26 may have other shapes (e.g., U-shaped, V-shaped, I-shaped, L-shaped, etc.).
  • the thickness of the patterned silicon layer or island 26 may range from about two angstroms to about 1000 angstroms, for example.
  • the patterned silicon layer 26 has a source region 40 , a drain region 42 , and a channel region 44 .
  • the channel region 44 extends between the source region 40 and the drain region 42 . As shown in FIG. 2A , the channel region 44 has a width that is much narrower than the contact pad portions 50 and 52 of the source and drain regions 40 and 42 , respectively.
  • the silicon atoms in the patterned silicon layer 26 are re-arranged by annealing the silicon layer 26 at elevated temperatures.
  • the re-arrangement is induced by surface migration of silicon atoms driven by a tendency to minimize surface tension.
  • the re-arrangement of the atoms at the narrow channel region 44 causes the corners of the channel region 44 to be rounded, as shown in FIGS. 3A and 3B , to transform the channel region 44 into a nano-rod structure 60 . If carried out long enough and/or under sufficient heat, the resulting nano-rod structure 60 may be completely rounded having a circular-shaped cross-section, as shown in FIG. 3B .
  • the contact pad portions 50 and 52 of the source and drain regions 40 and 42 will also likely experience slight shape changes, such as rounding of at least some of their corners. But because the contact pad portions 50 and 52 are much wider than the channel region, these contact pad portions 50 and 52 will typically still be substantially flat in shape or with only a slight curvature.
  • the contact pad portions of the source and drain regions serve to provide a portion onto which metallic or conductive materials form electrical connection with the source and drain regions. It is understood that the contact pad is an optional feature of this invention. If the contact pad portions of the source and drain regions are omitted, the patterned semiconductor layer may be I-shaped, for example. In this case, the electrical connection between the metallic or conductive material and the source and drain regions may be formed directly on the nano-rod structure.
  • the temperature for the annealing process may range from about 600° C. to about 1200° C.
  • the anneal time may range from about 1 second to about 2 hours.
  • the pressure in the reaction chamber (not shown) used for the annealing process may vary, depending in part upon the environment within the reaction chamber.
  • the reaction chamber may be a chemical vapor deposition (CVD) epitaxial reactor, for example.
  • the annealing process may occur in a reaction chamber having an environment of hydrogen gas (H 2 ) at a partial pressure ranging from about 1 . 0 ⁇ 10 ⁇ 9 torr to about 800 torr.
  • the annealing environment may be evacuated (i.e., a vacuum environment) at a pressure ranging from about 1.0 ⁇ 10 ⁇ 10 torr to about 1.0 ⁇ 10 ⁇ 3 torr.
  • the annealing environment may be nitrogen gas (N 2 ) at a pressure ranging from about 1.0 ⁇ 10 ⁇ 9 torr to about 800 torr.
  • the annealing environment may also be one of the following environments (but not limited to): an environment of a mixed gas including hydrogen and argon; an environment of a mixed gas including hydrogen and nitrogen; an environment with other gases in addition to hydrogen to form a mixed gas ambient; or an environment of an inert gas, for example.
  • the annealing process is performed in a hydrogen gas (H 2 ) ambient at about 900° C. for about 2 minutes. During testing, annealing a 28 nm thick silicon channel region 44 under such conditions did not reveal crystal defects.
  • H 2 hydrogen gas
  • the insulating layer 22 may be etched to expose the bottom surface of the nano-rod 60 , as shown in FIGS. 4A and 4B .
  • the nano-rod 60 is supported by the contact portions 50 and 52 of the source and drain regions 40 and 42 . It is preferred to etch away the insulating layer 22 beneath the nano-rod 60 at least enough to allow the gate to wrap around the nano-rod 60 for optimum gate control performance.
  • the use of the annealing process of the present invention to form a nano-rod structure 60 may also be applied to a non-wrap-around gate design (i.e., where the gate electrode only covers three sides of the gate channel, or where the gate electrode does not completely wrap around the gate channel).
  • a gate dielectric material 62 is formed on the surface of and about the nano-rod structure 60 (as well as on the other exposed portions of the silicon layer 26 ), as shown in FIGS. 5A and 5B .
  • the gate dielectric material 62 may be formed completely around the nano-rod surface.
  • the gate dielectric material 62 may be an oxide formed by thermal oxidation or atomic-layer CVD for uniform deposition, for example. Hence, the gate dielectric will likely form on all exposed areas, including the contact portions 50 , 52 of the source and drain regions 40 , 42 .
  • the gate dielectric material may take the form of a variety of compositions, including but not limited to: silicon dioxide (SiO 2 ), silicon oxynitride (SiO x N y ), HfO 2 , ZrO 2 , Al 2 O 3 , La 2 O 3 , or other high permittivity materials, for example.
  • the gate electrode material is then deposited, masked, and etched to form the gate electrode 64 , as shown in FIGS. 6A and 6B .
  • the gate electrode material may be selected from a variety of materials, including but not limited to: a semiconductor material (e.g., poly-silicon, poly-silicon-germanium); a metal material (e.g., molybdenum, tungsten, titanium); a metallic nitride (e.g., tantalum nitride, titanium nitride); or any combination thereof, for example.
  • a semiconductor material e.g., poly-silicon, poly-silicon-germanium
  • a metal material e.g., molybdenum, tungsten, titanium
  • a metallic nitride e.g., tantalum nitride, titanium nitride
  • the gate electrode 64 may be formed completely around the nano-rod 60 , as preferred.
  • the gate dielectric material 62 may be removed from the source and drain regions, as shown in FIG. 6A .
  • the gate dielectric 62 is preferably aligned with the gate electrode 64 at the channel, the gate dielectric 62 can be self-aligned with the gate electrode 64 by simply etching the gate electrode material with an etch chemistry that will also etch away the gate dielectric material 62 while being selective against etching the silicon layer 26 . Also, because the gate dielectric 62 at the gate channel is shielded by the gate electrode 64 , the ion implantation processes for doping the silicon layer 26 outside of the channel (i.e., to form the source and drain of the transistor 20 ) may be self-aligning as well.
  • the resulting shape of the nano-rod 60 formed at the channel region 44 may vary, depending on the annealing parameters used.
  • the nano-rod portion 60 shown in FIG. 7A has a generally rectangular shaped cross-section with rounded corners (i.e., more than 4 crystal faces).
  • the nano-rod portion 60 shown in FIG. 7B has a generally oval-shaped cross-section.
  • the nano-rod cross-section may have a rounded but arbitrarily shaped or somewhat arbitrarily shaped, as shown in FIG. 7C for example.
  • the preferred shape of the nano-rod cross-section for a preferred transistor embodiment is circular, as shown in FIG. 7D .
  • the nano-rod 60 has a diameter no larger than about 65 nm.
  • the diameter of the nano-rod cross-section may be in the order of nanometers (e.g., about 4 nm), and such nano-rods may be used for the channel of a field-effect transistor, for example.
  • part of the insulating layer 22 may be etched away before the annealing process for rounding the corners of the channel region 44 .
  • the gate dielectric material 62 may be patterned and etched (to leave a gate dielectric portion around the nano-rod 60 where the gate channel will be formed) before the deposition of the gate electrode material.
  • the gate electrode material may be etched using a first etch chemistry to form the gate electrode 64 , and then the gate dielectric material 62 may be etched using a second etch chemistry after forming the gate electrode 64 .
  • the gate electrode 64 may act as a self-aligning mask for the etching of the gate dielectric material 62 to shield the gate dielectric between the gate electrode 64 and the nano-rod 60 .

Abstract

In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region to form a nano-rod structure. Part of the nano-rod structure is then used as a gate channel. Preferably, a gate dielectric and a gate electrode both wrap around the nano-rod structure, with the gate dielectric being between the nano-rod structure and the gate electrode, to form a transistor device.

Description

  • This application is a divisional of patent application Ser. No. 10/370,792, entitled “Semiconductor Nano-Rod Devices,” filed on Feb. 20, 2003, which application is incorporated herein by reference.
    • TECHNICAL FIELD
  • The present invention relates generally to methods for manufacturing semiconductor devices. In one aspect, the present invention relates to a method of forming a nano-rod structure for a channel of a field effect transistor.
    • BACKGROUND
  • Metal-oxide-semiconductor field effect transistor (MOSFET) technology is currently the dominant semiconductor technology used for manufacturing ultra-large scale integrated (ULSI) circuits. As the gate length of the MOSFET is scaled down into the sub-30 nm regime for improved performance and density, the source and drain increasingly interact with the channel to sometimes gain influence on the channel potential. Hence, a transistor with a short gate length often suffers from problems related to the inability of the gate to substantially control the on/off states of the channel, which is often called short-channel effects.
  • Increased body doping concentration, reduced gate oxide thickness, and junction depths are some ways to suppress short-channel effects. However, for device scaling well into the sub-30 nm regime, the requirements for body-doping concentration, gate oxide thickness, and source/drain doping profiles become increasingly difficult to meet using conventional device structures based on bulk silicon substrates. Thus, alternative device structures that offer better control of short-channel effects are being considered to enable the continued scaling down of transistor sizes.
  • A highly scalable device structure that offers superior control of short-channel effects is a wrap-around gate structure for a transistor (a.k.a., surround-gate or gate-all-around transistor structure). A wrap-around gate structure typically has a gate that surrounds or wraps around a channel region. This structure effectively improves the capacitance coupling between the gate and the channel, as compared to conventional bulk silicon substrate transistor structures, double-gate transistor structures, and triple-gate transistor structures. With the wrap-around gate structure, the gate gains significant influence on the channel potential, and therefore improves suppression of short-channel effects. A wrap-around gate structure typically allows the gate length to be scaled down by about 50% more compared to a double-gate structure.
  • There are several different ways to implement a wrap-around gate transistor structure. For example, the transistor channel may be oriented vertically or horizontally. Many of the existing designs for horizontally oriented channels have a square or rectangular shaped cross-section. When the channel cross-section is rectangular or square, enhanced field effect at the corners of the rectangle may cause that part of the transistor to turn on earlier (i.e., having a lower threshold voltage) than parts of the transistor at the flat sides of the rectangular channel cross-section. This may result in a parasitic off-state leakage. Hence, a cylindrical channel cross-section is preferred over a rectangular channel cross-section.
  • Current attempts at obtaining a more circular channel cross-section are made by oxidizing the silicon beam forming the channel to round the corners of the rectangular channel cross-section. However, this method requires a large amount of oxidation, and hence a large amount of oxide formation, to convert the rectangular channel cross-section shape to a rounded or circular channel cross-section. Hence, there is a need for a way to manufacture a transistor channel having a rounded or circular cross-section shape without having to form excessive oxide about the channel.
    • SUMMARY
  • The problems and needs outlined above are addressed by embodiments of the present invention. In accordance with one aspect of the present invention, a method of manufacturing a semiconductor device is provided. This method includes the following steps. A semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region.
  • Next, some example annealing parameters that may be used are described. The annealing may occur in a reaction chamber having an environment therein including a gas of hydrogen, nitrogen, a mixed gas including hydrogen and argon, a mixed gas including hydrogen and nitrogen, or an inert gas. The annealing environment may be H2 gas at a pressure ranging from about 1.0×10−9 torr to about 800 torr. The annealing environment may be N2 gas at a pressure ranging from about 1.0×10−9 torr to about 800 torr. The annealing may occur in a reaction chamber having an evacuated environment. The annealing environment may be a vacuum environment at a pressure ranging from about 1.0×10−10 torr to about 1.0×10 −3 torr. The annealing may occur in a reaction chamber having a temperature ranging from about 600° C. to about 1200° C. therein. The annealing occurs at an anneal time ranging from about 1 second to about 2 hours. The annealing may be performed in a hydrogen gas (H2) environment at about 900° C. for about 2 minutes.
  • In accordance with another aspect of the present invention, a method of manufacturing a semiconductor device is provided. This method includes the following steps. A semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region. The insulating layer is etched using an etch chemistry selective against etching the semiconductor layer. The etching is performed long enough so that at least a segment of the rounded channel region is suspended above a proximate portion of the insulating layer. A gate dielectric material is formed on a surface of and about the rounded channel region. A gate electrode material is formed on the gate dielectric and about the rounded channel region. The gate electrode material is patterned to form a gate electrode. The gate electrode includes a gate wrap region that wraps around the rounded channel region and a gate contact region extending therefrom.
  • In accordance with yet another aspect of the present invention, a semiconductor device is provided, which includes an insulating layer, an underlying layer, a layer of semiconductor material, a gate dielectric, and a gate electrode. The insulating layer is over the underlying layer. The layer of semiconductor material is over the insulating layer. The semiconductor layer has a source region, a drain region, and an annealed nano-rod structure extending between the source and drain regions. The gate dielectric is formed on the surface of at least a segment of the nano-rod structure. The gate electrode is formed on the surface of the gate dielectric at the segment. Preferably, the gate dielectric and the gate electrode are both formed completely around the nano-rod structure at the segment. Preferably, the nano-rod structure has a cross-section diameter less than about 65 nm.
  • In accordance with still another aspect of the present invention, a semiconductor device including a plurality of transistors, is provided. Each of the plurality of transistors includes an annealed semiconductor layer, a gate dielectric surface layer, and a gate electrode. The annealed semiconductor layer has a source region, a drain region, and a channel region formed therein. The channel region extends between the source region and the drain region. The source region has a substantially flat source contact portion. The drain region has a substantially flat drain contact portion. The channel region has a substantially circular cross-section shape. The gate dielectric surface layer wraps around a segment of the channel region. The gate electrode has a gate wrap region that wraps around the segment of the channel region and a gate contact region extending therefrom. The gate dielectric layer is between the segment of the channel region and the gate wrap region of the gate electrode.
    • BRIEF DESCRIPTION
  • For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
  • FIGS. 1A, 2A, 3A, 4A, 5A, and 6A show simplified perspective views of one transistor device being manufactured on a semiconductor device in accordance with a preferred embodiment of the present invention;
  • FIGS. 1B, 2B, 3B, 4B, 5B, and 6B are simplified cross-section views of FIGS. 1A, 2A, 3A, 4A, 5A, and 6A, respectively, as taken along lines 1B-1B, 2B-2B, 3B-3B, 4B-4B, 5B-5B, and 6B-6B, respectively; and
  • FIGS. 7A-7D show some possible variations of the nano-rod structure formed after an annealing processing in accordance with the present invention.
    • DETAILED DESCRIPTION
  • The use of presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
  • Example embodiments of the present invention will be described herein in a specific context of making semiconductor devices, such as transistors. In other embodiments not shown, embodiments of the present invention also may include nano-wires or quantum-wires formed in accordance with the present invention. The present invention may also be applied, however, to other situations.
  • A preferred manufacturing process in accordance with the present invention may be used to make a transistor device. Some of the manufacturing steps of this preferred embodiment being used to make a transistor embodiment are illustrated in FIGS. 1A-6B. While describing the structure formation steps shown in FIGS. 1A-6B, process parameters and steps for the preferred embodiment will described, as well as some of the possible alternatives or variations of the process parameters and steps. However, the process parameters shown and/or described herein are merely examples to illustrate and describe the present invention. With the benefit of this disclosure, one of ordinary skill in the art will likely realize other variations and embodiments of the present invention within the scope and spirit of the appended patent claims.
  • FIGS. 1A, 2A, 3A, 4A, 5A, and 6A show simplified perspective views of one transistor device 20 being manufactured on a semiconductor device. Such a semiconductor device will often have millions of these transistors 20. However, for purposes of illustration and discussion, only one transistor device 20 is shown and the remainder of the semiconductor device is not shown. FIGS. 1B, 2B, 3B, 4B, 5B, and 6B are simplified cross-section views of FIGS. 1A, 2A, 3A, 4A, 5A, and 6A, respectively, as taken along lines 1B-1B, 2B-2B, 3B-3B, 4B-4B, 5B-5B, and 6B-6B, respectively.
  • Referring to FIGS. 1A and 1B, an intermediate structure is shown having an insulating layer 22 formed on an underlying layer 24. A semiconductor layer 26 is formed on the insulating layer 22. This type of structure is sometimes referred to as a silicon-on-insulator substrate and is commonly available as a starting material. A patterned active region mask 28 is formed on the semiconductor layer 26. The mask 28 may be formed from a pad silicon oxide layer 30 and a silicon nitride layer 32, for example. With the mask 28 in place having a pattern desired to be formed in the semiconductor layer 26, the semiconductor layer 26 is preferably anisotropically etched (e.g., dry plasma etching) to conform the semiconductor layer 26 to the pattern of the mask 28.
  • The underlying layer 24 will often be a silicon wafer, for example. However, the underlying layer 24 may be another type of layer, including but not limited to: an elemental semiconductor, such as germanium; an alloy semiconductor, such as silicon-germanium; or a compound semiconductor, such as gallium arsenide or indium phosphide, for example.
  • The insulating layer 22 in some embodiments may be referred to as a “buried oxide” layer. However, the insulating layer 22 may be composed of a material or a combination of materials from a large variety of materials, including but not limited to: silicon dioxide, silicon nitride, aluminum oxide, plastic, or polymer, for example. In a currently preferred embodiment, the insulating layer 22 is composed of silicon dioxide (SiO2).
  • The semiconductor layer 26 may be composed of a material or a combination of materials from a large variety of materials, including but not limited to: any semiconductor material, silicon, carbon, elemental semiconductor material (e.g., germanium), alloy semiconductor material (e.g., silicon-germanium, silicon-germanium-carbon), compound semiconductor material (e.g., indium phosphide, gallium arsenide), plastic, or polymer, for example. Such materials may be in crystalline or amorphous forms. In a currently preferred embodiment, the semiconductor layer 26 is composed of silicon. Hence, in the preferred embodiment shown in FIGS. 1A-6B, the semiconductor layer 26 is a silicon layer.
  • In FIGS. 2A and 2B the mask 28 has been removed and the patterned semiconductor layer 26 remains in the form of an H-shaped, thin silicon island. However, in other embodiments (not shown), the patterned semiconductor layer 26 may have other shapes (e.g., U-shaped, V-shaped, I-shaped, L-shaped, etc.). The thickness of the patterned silicon layer or island 26 may range from about two angstroms to about 1000 angstroms, for example. The patterned silicon layer 26 has a source region 40, a drain region 42, and a channel region 44. The channel region 44 extends between the source region 40 and the drain region 42. As shown in FIG. 2A, the channel region 44 has a width that is much narrower than the contact pad portions 50 and 52 of the source and drain regions 40 and 42, respectively.
  • Next, the silicon atoms in the patterned silicon layer 26 are re-arranged by annealing the silicon layer 26 at elevated temperatures. The re-arrangement is induced by surface migration of silicon atoms driven by a tendency to minimize surface tension. During the annealing, the re-arrangement of the atoms at the narrow channel region 44 causes the corners of the channel region 44 to be rounded, as shown in FIGS. 3A and 3B, to transform the channel region 44 into a nano-rod structure 60. If carried out long enough and/or under sufficient heat, the resulting nano-rod structure 60 may be completely rounded having a circular-shaped cross-section, as shown in FIG. 3B. The contact pad portions 50 and 52 of the source and drain regions 40 and 42 will also likely experience slight shape changes, such as rounding of at least some of their corners. But because the contact pad portions 50 and 52 are much wider than the channel region, these contact pad portions 50 and 52 will typically still be substantially flat in shape or with only a slight curvature. The contact pad portions of the source and drain regions serve to provide a portion onto which metallic or conductive materials form electrical connection with the source and drain regions. It is understood that the contact pad is an optional feature of this invention. If the contact pad portions of the source and drain regions are omitted, the patterned semiconductor layer may be I-shaped, for example. In this case, the electrical connection between the metallic or conductive material and the source and drain regions may be formed directly on the nano-rod structure.
  • Example parameters for the annealing process used to round the corners of the channel region 44 will be described next. The temperature for the annealing process may range from about 600° C. to about 1200° C. The anneal time may range from about 1 second to about 2 hours. The pressure in the reaction chamber (not shown) used for the annealing process may vary, depending in part upon the environment within the reaction chamber. The reaction chamber may be a chemical vapor deposition (CVD) epitaxial reactor, for example. The annealing process may occur in a reaction chamber having an environment of hydrogen gas (H2) at a partial pressure ranging from about 1.0×10 −9 torr to about 800 torr. In another embodiment, the annealing environment may be evacuated (i.e., a vacuum environment) at a pressure ranging from about 1.0×10−10 torr to about 1.0×10−3 torr. In still another embodiment, the annealing environment may be nitrogen gas (N2) at a pressure ranging from about 1.0×10−9 torr to about 800 torr. The annealing environment may also be one of the following environments (but not limited to): an environment of a mixed gas including hydrogen and argon; an environment of a mixed gas including hydrogen and nitrogen; an environment with other gases in addition to hydrogen to form a mixed gas ambient; or an environment of an inert gas, for example.
  • In a preferred embodiment, the annealing process is performed in a hydrogen gas (H2) ambient at about 900° C. for about 2 minutes. During testing, annealing a 28 nm thick silicon channel region 44 under such conditions did not reveal crystal defects.
  • After forming the nano-rod structure 60, the insulating layer 22 may be etched to expose the bottom surface of the nano-rod 60, as shown in FIGS. 4A and 4B. The nano-rod 60 is supported by the contact portions 50 and 52 of the source and drain regions 40 and 42. It is preferred to etch away the insulating layer 22 beneath the nano-rod 60 at least enough to allow the gate to wrap around the nano-rod 60 for optimum gate control performance. The use of the annealing process of the present invention to form a nano-rod structure 60 (described above) may also be applied to a non-wrap-around gate design (i.e., where the gate electrode only covers three sides of the gate channel, or where the gate electrode does not completely wrap around the gate channel).
  • Next, a gate dielectric material 62 is formed on the surface of and about the nano-rod structure 60 (as well as on the other exposed portions of the silicon layer 26), as shown in FIGS. 5A and 5B. As shown in FIG. 5B, because the nano-rod 60 is exposed on all sides after etching away part of the insulting layer 22, the gate dielectric material 62 may be formed completely around the nano-rod surface. The gate dielectric material 62 may be an oxide formed by thermal oxidation or atomic-layer CVD for uniform deposition, for example. Hence, the gate dielectric will likely form on all exposed areas, including the contact portions 50, 52 of the source and drain regions 40, 42. The gate dielectric material may take the form of a variety of compositions, including but not limited to: silicon dioxide (SiO2), silicon oxynitride (SiOxNy), HfO2, ZrO2, Al2O3, La2O3, or other high permittivity materials, for example.
  • A gate electrode material is then deposited, masked, and etched to form the gate electrode 64, as shown in FIGS. 6A and 6B. The gate electrode material may be selected from a variety of materials, including but not limited to: a semiconductor material (e.g., poly-silicon, poly-silicon-germanium); a metal material (e.g., molybdenum, tungsten, titanium); a metallic nitride (e.g., tantalum nitride, titanium nitride); or any combination thereof, for example. As shown in FIG. 6B, because the nano-rod 60 is elevated above the insulating layer 22 (at least where the channel will be formed), the gate electrode 64 may be formed completely around the nano-rod 60, as preferred. During or after the etching of the gate electrode material to form the patterned gate electrode 64, the gate dielectric material 62 may be removed from the source and drain regions, as shown in FIG. 6A.
  • Because the gate dielectric 62 is preferably aligned with the gate electrode 64 at the channel, the gate dielectric 62 can be self-aligned with the gate electrode 64 by simply etching the gate electrode material with an etch chemistry that will also etch away the gate dielectric material 62 while being selective against etching the silicon layer 26. Also, because the gate dielectric 62 at the gate channel is shielded by the gate electrode 64, the ion implantation processes for doping the silicon layer 26 outside of the channel (i.e., to form the source and drain of the transistor 20) may be self-aligning as well.
  • As shown in FIGS. 7A, 7B, 7C, and 7D, the resulting shape of the nano-rod 60 formed at the channel region 44 may vary, depending on the annealing parameters used. For example, the nano-rod portion 60 shown in FIG. 7A has a generally rectangular shaped cross-section with rounded corners (i.e., more than 4 crystal faces). The nano-rod portion 60 shown in FIG. 7B has a generally oval-shaped cross-section. In other embodiments, the nano-rod cross-section may have a rounded but arbitrarily shaped or somewhat arbitrarily shaped, as shown in FIG. 7C for example. However, as described above, the preferred shape of the nano-rod cross-section for a preferred transistor embodiment is circular, as shown in FIG. 7D. Preferably, the nano-rod 60 has a diameter no larger than about 65 nm. The diameter of the nano-rod cross-section may be in the order of nanometers (e.g., about 4 nm), and such nano-rods may be used for the channel of a field-effect transistor, for example.
  • In another manufacturing embodiment (not shown) of present invention, after FIG. 2A, part of the insulating layer 22 may be etched away before the annealing process for rounding the corners of the channel region 44. Also, after FIG. 5A, the gate dielectric material 62 may be patterned and etched (to leave a gate dielectric portion around the nano-rod 60 where the gate channel will be formed) before the deposition of the gate electrode material. In still another embodiment, after FIG. 5A, the gate electrode material may be etched using a first etch chemistry to form the gate electrode 64, and then the gate dielectric material 62 may be etched using a second etch chemistry after forming the gate electrode 64. In such case, the gate electrode 64 may act as a self-aligning mask for the etching of the gate dielectric material 62 to shield the gate dielectric between the gate electrode 64 and the nano-rod 60.
  • Although several embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the processes, machines, manufactures, compositions of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufactures, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function and/or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufactures, compositions of matter, means, methods, or steps.

Claims (20)

1. A semiconductor device comprising:
an insulating layer over an underlying layer;
a layer of semiconductor material over the insulating layer, the semiconductor layer having a source region, a drain region, and an annealed nano-rod structure extending between the source and drain regions;
a gate dielectric formed on the surface of at least a segment of the nano-rod structure; and
a gate electrode formed on the surface of the gate dielectric at the segment.
2. The semiconductor device of claim 1, wherein the gate dielectric is formed completely around the nano-rod structure at the segment.
3. The semiconductor device of claim 2, wherein the gate electrode is formed completely around the nano-rod structure at the segment.
4. The semiconductor device of claim 1, wherein the semiconductor material is selected from a group consisting of silicon, germanium, silicon-germanium alloy, silicon-germanium-carbon alloy, indium phosphide compound, and gallium arsenide compound.
5. The semiconductor device of claim 1, wherein the insulating layer comprises a material selected from a group consisting of silicon dioxide, silicon nitride, and aluminum oxide.
6. The semiconductor device of claim 1, wherein the underlying layer is a silicon substrate.
7. The semiconductor device of claim 1, wherein the gate dielectric comprises a material selected from a group consisting of silicon dioxide, silicon oxynitride, HfO2, ZrO2, Al2O3, and La2O3.
8. The semiconductor device of claim 1, wherein the gate electrode comprises a material selected from a group consisting of a semiconducting material, a metal, and a metal nitride.
9. The semiconductor device of claim 1, wherein the nano-rod structure has a cross-section diameter less than about 65 nm.
10. The semiconductor device of claim 1, wherein the nano-rod structure has a substantially circular cross-section.
11. The semiconductor device of claim 1, wherein the nano-rod structure has rounded corners.
12. A semiconductor device comprising a plurality of transistors, wherein each of the plurality of transistors comprises:
an annealed semiconductor layer having a source region, a drain region, and a channel region formed therein, the channel region extending between the source region and the drain region, the channel region comprising a nano-rod structure with rounded corners;
a gate dielectric formed on the surface of at least a segment of the nano-rod structure; and
a gate electrode formed on the surface of the gate dielectric at the segment, the gate electrode having a gate contact region extending therefrom.
13. The semiconductor device of claim 12, wherein the gate dielectric is formed completely around the nano-rod structure at the segment.
14. The semiconductor device of claim 13, wherein the gate electrode is formed completely around the nano-rod structure at the segment.
15. The semiconductor device of claim 12, wherein the semiconductor material is selected from a group consisting of silicon, germanium, silicon-germanium alloy, silicon-germanium-carbon alloy, indium phosphide compound, and gallium arsenide compound.
16. The semiconductor device of claim 12, further comprising an insulating layer over an underlying layer, wherein the semiconductor layer is formed over the insulating layer.
17. The semiconductor device of claim 16, wherein the insulating layer comprises a material selected from a group consisting of silicon dioxide, silicon nitride, and aluminum oxide, and wherein the underlying layer is a silicon substrate.
18. The semiconductor device of claim 12, wherein the gate dielectric comprises a material selected from a group consisting of silicon dioxide, silicon oxynitride, HfO2, ZrO2, Al2O3, and La2O3, and wherein the gate electrode comprises a material selected from a group consisting of a semiconducting material, a metal, and a metal nitride.
19. The semiconductor device of claim 12, wherein the nano-rod structure has a cross-section diameter less than about 65 nm.
20. A semiconductor device comprising a plurality of transistors, wherein each of the plurality of transistors comprises:
an annealed semiconductor layer having a source region, a drain region, and a channel region formed therein, the channel region extending between the source region and the drain region, the channel region having a substantially circular cross-section shape,
a gate dielectric layer around a segment of the channel region, and
a gate electrode having a gate wrap region that wraps around the segment of the channel region and a gate contact region extending therefrom, wherein the gate dielectric layer is between the segment of the channel region and the gate wrap region of the gate electrode.
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Cited By (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050275010A1 (en) * 2004-06-10 2005-12-15 Hung-Wei Chen Semiconductor nano-wire devices and methods of fabrication
US20060216897A1 (en) * 2005-03-24 2006-09-28 Samsung Electronics Co., Ltd. Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same
US20060220133A1 (en) * 2003-04-29 2006-10-05 Yee-Chia Yeo Doping of semiconductor fin devices
US20070040491A1 (en) * 2005-06-02 2007-02-22 Ping Mei Thin film devices and methods for forming the same
US20070072335A1 (en) * 2005-06-08 2007-03-29 Seung-Jae Baik Semiconductor Devices Having Nano-Line Channels and Methods of Fabricating the Same
US20070262344A1 (en) * 2005-08-18 2007-11-15 Anwar A F M Insulated gate silicon nanowire transistor and method of manufacture
US20080246021A1 (en) * 2006-10-04 2008-10-09 Samsung Electronic Co., Ltd., Single electron transistor and method of manufacturing the same
US20080272366A1 (en) * 2007-05-03 2008-11-06 Moon Chang-Wook Field effect transistor having germanium nanorod and method of manufacturing the same
US20090101967A1 (en) * 2007-10-18 2009-04-23 Macronix International Co., Ltd. Semiconductor device and method for manufacturing the same
US20090203203A1 (en) * 2006-05-04 2009-08-13 Commissariat A L'energie Atomique Method for the fabrication of a transistor gate that includes the breakdown of a precursor material into at least one metallic material, using at least one
US20100025658A1 (en) * 2008-07-29 2010-02-04 Alan Colli Lithographic process using a nanowire mask, and nanoscale devices fabricated using the process
US20100090197A1 (en) * 2008-10-10 2010-04-15 Electonics And Telecommunications Research Institute Method of manufacturing semiconductor nanowire sensor device and semiconductor nanowire sensor device manufactured according to the method
US20100112778A1 (en) * 2006-08-09 2010-05-06 Micron Technology, Inc. Nanoscale floating gate and methods of formation
US20110018065A1 (en) * 2008-02-26 2011-01-27 Nxp B.V. Method for manufacturing semiconductor device and semiconductor device
CN102074577A (en) * 2010-10-09 2011-05-25 北京大学 Vertical channel field effect transistor and preparation method thereof
US20110133162A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Gate-All-Around Nanowire Field Effect Transistors
US20110133164A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Omega Shaped Nanowire Field Effect Transistors
US20110133165A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Self-aligned contacts for nanowire field effect transistors
US20110133167A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Planar and nanowire field effect transistors
US20110133169A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Gate-All-Around Nanowire Tunnel Field Effect Transistors
US20110133161A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Omega Shaped Nanowire Tunnel Field Effect Transistors
US20110168982A1 (en) * 2010-01-08 2011-07-14 International Business Machines Corporation Nanowire pin tunnel field effect devices
US20110297962A1 (en) * 2010-06-08 2011-12-08 Jenn-Chang Hwang Schottky diode with diamond rod and method for manufacturing the same
CN102290447A (en) * 2010-06-18 2011-12-21 国立清华大学 Columnar diamond Schottky diode and production method thereof
US20110315953A1 (en) * 2010-06-28 2011-12-29 International Business Machines Corporation Method of forming compound semiconductor
US8324940B2 (en) 2010-04-13 2012-12-04 International Business Machines Corporation Nanowire circuits in matched devices
US8324030B2 (en) 2010-05-12 2012-12-04 International Business Machines Corporation Nanowire tunnel field effect transistors
US8361907B2 (en) 2010-05-10 2013-01-29 International Business Machines Corporation Directionally etched nanowire field effect transistors
US20130207079A1 (en) * 2012-02-09 2013-08-15 International Business Machines Corporation Tapered Nanowire Structure With Reduced Off Current
US8513068B2 (en) 2010-09-17 2013-08-20 International Business Machines Corporation Nanowire field effect transistors
US8586966B2 (en) 2010-08-16 2013-11-19 International Business Machines Corporation Contacts for nanowire field effect transistors
KR101406224B1 (en) * 2007-10-26 2014-06-12 삼성전자주식회사 Nanowire transistor and manufacturing method of the same
US20140183643A1 (en) * 2012-12-28 2014-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. Transistors with Wrapped-Around Gates and Methods for Forming the Same
US20140217509A1 (en) * 2013-02-07 2014-08-07 International Business Machines Corporation Diode Structure and Method for Gate All Around Silicon Nanowire Technologies
US8852998B1 (en) * 2011-08-30 2014-10-07 Sandia Corporation Method to fabricate micro and nano diamond devices
US20140299835A1 (en) * 2011-10-04 2014-10-09 Centre National De La Recherche Scientifique Ram memory point with a transistor
US9349850B2 (en) 2013-07-17 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally tuning strain in semiconductor devices
US9419098B2 (en) 2013-05-30 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Tuning strain in semiconductor devices
CN110299400A (en) * 2019-06-27 2019-10-01 中国科学院半导体研究所 The silicon substrate foreign atom transistor and preparation method thereof of three-dimensional potential barrier limitation

Families Citing this family (116)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050106794A1 (en) * 2002-03-26 2005-05-19 Fuji Electric Holdings Co., Ltd. Method of manufacturing a semiconductor device
JP4123961B2 (en) * 2002-03-26 2008-07-23 富士電機デバイステクノロジー株式会社 Manufacturing method of semiconductor device
US7358121B2 (en) * 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US7795647B2 (en) * 2003-06-06 2010-09-14 Northrop Grumman Systems Corporation Curled semiconductor transistor
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7105390B2 (en) 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes
US7624192B2 (en) * 2003-12-30 2009-11-24 Microsoft Corporation Framework for user interaction with multiple network devices
US7268058B2 (en) 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
DE102004003374A1 (en) * 2004-01-22 2005-08-25 Infineon Technologies Ag Semiconductor circuit breaker as well as a suitable manufacturing process
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7579280B2 (en) * 2004-06-01 2009-08-25 Intel Corporation Method of patterning a film
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7332439B2 (en) * 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7361958B2 (en) * 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US20060086977A1 (en) * 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7193279B2 (en) * 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20060202266A1 (en) 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
KR101100887B1 (en) 2005-03-17 2012-01-02 삼성전자주식회사 Thin film transistor, thin film transistor array panel, and manufacturing method thereof
FR2884648B1 (en) * 2005-04-13 2007-09-07 Commissariat Energie Atomique STRUCTURE AND METHOD FOR PRODUCING A MICROELECTRONIC DEVICE HAVING ONE OR MORE QUANTUM THREADS FOR FORMING A CHANNEL OR MORE CHANNELS OF TRANSISTORS
KR101054345B1 (en) * 2005-04-14 2011-08-04 삼성전자주식회사 Transistor, display device including same and manufacturing method thereof
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7709054B2 (en) * 2005-07-19 2010-05-04 Wayne State University Particle-rod nano structures and method of forming same by spin coating
US7323389B2 (en) * 2005-07-27 2008-01-29 Freescale Semiconductor, Inc. Method of forming a FINFET structure
FR2889622A1 (en) * 2005-08-08 2007-02-09 St Microelectronics Crolles 2 PROCESS FOR MANUFACTURING A PARALLEL SEMICONDUCTOR NANODOIGT TRANSISTOR
US7402875B2 (en) 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US20070090416A1 (en) * 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070090408A1 (en) * 2005-09-29 2007-04-26 Amlan Majumdar Narrow-body multiple-gate FET with dominant body transistor for high performance
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US7396711B2 (en) * 2005-12-27 2008-07-08 Intel Corporation Method of fabricating a multi-cornered film
KR100712543B1 (en) * 2005-12-31 2007-04-30 삼성전자주식회사 Semiconductor device having a plurality of channels method of fabrication the same
US7803668B2 (en) * 2006-02-24 2010-09-28 Stmicroelectronics (Crolles 2) Sas Transistor and fabrication process
US7449373B2 (en) * 2006-03-31 2008-11-11 Intel Corporation Method of ion implanting for tri-gate devices
CN101432852B (en) * 2006-04-26 2013-01-02 Nxp股份有限公司 Non-volatile memory device
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
FR2905197B1 (en) * 2006-08-25 2008-12-19 Commissariat Energie Atomique METHOD FOR PRODUCING A DEVICE COMPRISING A STRUCTURE PROVIDED WITH ONE OR MORE MICROWIRES OR NANO-THREADS BASED ON A COMPOUND OF SI AND GE, BY GERMANIUM CONDENSATION
KR100801063B1 (en) 2006-10-02 2008-02-04 삼성전자주식회사 Gate all around type semiconductor device and method of manufacturing the same
US20080157225A1 (en) * 2006-12-29 2008-07-03 Suman Datta SRAM and logic transistors with variable height multi-gate transistor architecture
US7935599B2 (en) * 2007-04-04 2011-05-03 Sharp Laboratories Of America, Inc. Nanowire transistor and method for forming same
KR101361129B1 (en) * 2007-07-03 2014-02-13 삼성전자주식회사 luminous device and method of manufacturing the same
US8609333B2 (en) * 2007-10-01 2013-12-17 University Of Southern California Detection of methylated DNA and DNA mutations
FR2923646A1 (en) * 2007-11-09 2009-05-15 Commissariat Energie Atomique MEMORY CELL SRAM WITH TRANSISTORS WITH VERTICAL MULTI-CHANNEL STRUCTURE
FR2923652B1 (en) * 2007-11-09 2010-06-11 Commissariat Energie Atomique METHOD FOR MANUFACTURING PARALLEL NANOWILS WITH THEIR SUPPORT SUBSTRATE
US20110012090A1 (en) * 2007-12-07 2011-01-20 Agency For Science, Technology And Research Silicon-germanium nanowire structure and a method of forming the same
WO2009108173A2 (en) * 2007-12-14 2009-09-03 Nanosys, Inc. Methods for formation of substrate elements
EP2073256A1 (en) * 2007-12-20 2009-06-24 Interuniversitair Microelektronica Centrum vzw ( IMEC) Method for fabricating a semiconductor device and the semiconductor device made thereof
KR20090089108A (en) * 2008-02-18 2009-08-21 삼성전자주식회사 Method of manufacturing a semiconductor device and a semiconductor device manufactured using the same
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US20100204062A1 (en) * 2008-11-07 2010-08-12 University Of Southern California Calibration methods for multiplexed sensor arrays
US7884004B2 (en) * 2009-02-04 2011-02-08 International Business Machines Corporation Maskless process for suspending and thinning nanowires
WO2010115143A1 (en) * 2009-04-03 2010-10-07 University Of Southern California Surface modification of nanosensor platforms to increase sensitivity and reproducibility
US8546269B2 (en) * 2009-04-03 2013-10-01 International Business Machines Corporation Top-down nanowire thinning processes
US8080456B2 (en) * 2009-05-20 2011-12-20 International Business Machines Corporation Robust top-down silicon nanowire structure using a conformal nitride
US8084308B2 (en) 2009-05-21 2011-12-27 International Business Machines Corporation Single gate inverter nanowire mesh
US8519479B2 (en) * 2010-05-12 2013-08-27 International Business Machines Corporation Generation of multiple diameter nanowire field effect transistors
US8420455B2 (en) * 2010-05-12 2013-04-16 International Business Machines Corporation Generation of multiple diameter nanowire field effect transistors
US9029834B2 (en) 2010-07-06 2015-05-12 International Business Machines Corporation Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric
CN102214595B (en) * 2011-05-26 2012-10-10 北京大学 Manufacturing method of fence silicon nanowire transistor with air as side wall
CN102315170B (en) * 2011-05-26 2013-07-31 北京大学 Method for manufacturing silicon nanowire FET (field effect transistor) based on wet etching
CN102214596B (en) * 2011-05-26 2012-08-29 北京大学 Manufacturing method of fence silicon nanowire transistor with air as side wall
CN102208351B (en) * 2011-05-27 2012-10-10 北京大学 Preparation method of fence silicon nanowire transistor of air side wall
CN102214611B (en) * 2011-05-27 2012-10-10 北京大学 Preparation method for gate-all-round silicon nanowire transistor by using air as side wall
CN102280454B (en) * 2011-08-22 2013-02-06 中国科学院半导体研究所 Semiconductor transistor structure and making method thereof
DE112011106023T5 (en) * 2011-12-23 2014-09-11 Intel Corporation Nanowire structures with non-discrete source and drain regions
US9501738B1 (en) * 2012-08-16 2016-11-22 Sandia Corporation Cellular computational platform and neurally inspired elements thereof
US8735869B2 (en) 2012-09-27 2014-05-27 Intel Corporation Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates
CN103824775B (en) * 2012-11-16 2018-04-24 中国科学院微电子研究所 FinFET and its manufacture method
US8927405B2 (en) * 2012-12-18 2015-01-06 International Business Machines Corporation Accurate control of distance between suspended semiconductor nanowires and substrate surface
US9583414B2 (en) 2013-10-31 2017-02-28 Qorvo Us, Inc. Silicon-on-plastic semiconductor device and method of making the same
US9214337B2 (en) 2013-03-06 2015-12-15 Rf Micro Devices, Inc. Patterned silicon-on-plastic (SOP) technology and methods of manufacturing the same
US9812350B2 (en) 2013-03-06 2017-11-07 Qorvo Us, Inc. Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
US10553718B2 (en) * 2014-03-14 2020-02-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices with core-shell structures
US9698261B2 (en) 2014-06-30 2017-07-04 Taiwan Semiconductor Manufacturing Co., Ltd. Vertical device architecture
EP2996143B1 (en) 2014-09-12 2018-12-26 Qorvo US, Inc. Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same
US10085352B2 (en) 2014-10-01 2018-09-25 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US10121718B2 (en) 2014-11-03 2018-11-06 Qorvo Us, Inc. Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
US20170345896A1 (en) * 2014-12-24 2017-11-30 Intel Corporation Field effect transistor structures using germanium nanowires
CN106033725B (en) 2015-03-13 2020-10-16 联华电子股份有限公司 Semiconductor element and manufacturing process thereof
US9613831B2 (en) 2015-03-25 2017-04-04 Qorvo Us, Inc. Encapsulated dies with enhanced thermal performance
US9960145B2 (en) 2015-03-25 2018-05-01 Qorvo Us, Inc. Flip chip module with enhanced properties
US20160343604A1 (en) 2015-05-22 2016-11-24 Rf Micro Devices, Inc. Substrate structure with embedded layer for post-processing silicon handle elimination
US10276495B2 (en) 2015-09-11 2019-04-30 Qorvo Us, Inc. Backside semiconductor die trimming
US10020405B2 (en) 2016-01-19 2018-07-10 Qorvo Us, Inc. Microelectronics package with integrated sensors
US10090262B2 (en) 2016-05-09 2018-10-02 Qorvo Us, Inc. Microelectronics package with inductive element and magnetically enhanced mold compound component
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10468329B2 (en) 2016-07-18 2019-11-05 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10103080B2 (en) 2016-06-10 2018-10-16 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
JP7022112B2 (en) 2016-08-12 2022-02-17 コーボ ユーエス，インコーポレイティド Wafer level package with improved performance
CN109844938B (en) 2016-08-12 2023-07-18 Qorvo美国公司 Wafer level package with enhanced performance
JP7035014B2 (en) 2016-08-12 2022-03-14 コーボ ユーエス，インコーポレイティド Wafer level package with enhanced performance
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10090339B2 (en) 2016-10-21 2018-10-02 Qorvo Us, Inc. Radio frequency (RF) switch
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US10068831B2 (en) 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
US10755992B2 (en) 2017-07-06 2020-08-25 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US10366972B2 (en) 2017-09-05 2019-07-30 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10784233B2 (en) 2017-09-05 2020-09-22 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US20200235040A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
KR20210129656A (en) 2019-01-23 2021-10-28 코르보 유에스, 인크. RF semiconductor device and method of forming same
US11705428B2 (en) 2019-01-23 2023-07-18 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
CN110034015B (en) 2019-04-19 2021-07-23 中国科学院微电子研究所 Method for forming nanowire fence device
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive

Citations (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933298A (en) * 1987-12-18 1990-06-12 Fujitsu Limited Method of making high speed semiconductor device having a silicon-on-insulator structure
US4946799A (en) * 1988-07-08 1990-08-07 Texas Instruments, Incorporated Process for making high performance silicon-on-insulator transistor with body node to source node connection
US5115289A (en) * 1988-11-21 1992-05-19 Hitachi, Ltd. Semiconductor device and semiconductor memory device
US5317175A (en) * 1991-02-08 1994-05-31 Nissan Motor Co., Ltd. CMOS device with perpendicular channel current directions
US5317178A (en) * 1992-05-18 1994-05-31 Industrial Technology Research Institute Offset dual gate thin film field effect transistor
US5464783A (en) * 1993-03-24 1995-11-07 At&T Corp. Oxynitride-dioxide composite gate dielectric process for MOS manufacture
US5607865A (en) * 1995-01-27 1997-03-04 Goldstar Electron Co., Ltd. Structure and fabrication method for a thin film transistor
US5801397A (en) * 1994-09-30 1998-09-01 Sgs-Thomson Microelectronics, Inc. Device having a self-aligned gate electrode wrapped around the channel
US5814895A (en) * 1995-12-22 1998-09-29 Sony Corporation Static random access memory having transistor elements formed on side walls of a trench in a semiconductor substrate
US5998852A (en) * 1996-11-22 1999-12-07 International Business Machines Corporation Geometrical control of device corner threshold
US6114725A (en) * 1997-01-22 2000-09-05 International Business Machines Corporation Structure for folded architecture pillar memory cell
US6157061A (en) * 1997-08-29 2000-12-05 Nec Corporation Nonvolatile semiconductor memory device and method of manufacturing the same
US6222234B1 (en) * 1998-04-15 2001-04-24 Nec Corporation Semiconductor device having partially and fully depleted SOI elements on a common substrate
US6252284B1 (en) * 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
US6300182B1 (en) * 2000-12-11 2001-10-09 Advanced Micro Devices, Inc. Field effect transistor having dual gates with asymmetrical doping for reduced threshold voltage
US6342410B1 (en) * 2000-07-10 2002-01-29 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with three sided gate structure on semiconductor on insulator
US20020011612A1 (en) * 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US6344392B1 (en) * 1998-11-16 2002-02-05 Vanguard International Semiconductor Corporation Methods of manufacture of crown or stack capacitor with a monolithic fin structure made with a different oxide etching rate in hydrogen fluoride vapor
US6380024B1 (en) * 2000-02-07 2002-04-30 Taiwan Semiconductor Manufacturing Company Method of fabricating an SRAM cell featuring dual silicide gates and four buried contact regions
US6387739B1 (en) * 1998-08-07 2002-05-14 International Business Machines Corporation Method and improved SOI body contact structure for transistors
US6391796B1 (en) * 1998-09-14 2002-05-21 Shin-Etsu Handotai Co., Ltd. Method for heat-treating silicon wafer and silicon wafer
US6391782B1 (en) * 2000-06-20 2002-05-21 Advanced Micro Devices, Inc. Process for forming multiple active lines and gate-all-around MOSFET
US6391695B1 (en) * 2000-08-07 2002-05-21 Advanced Micro Devices, Inc. Double-gate transistor formed in a thermal process
US6411725B1 (en) * 1995-07-27 2002-06-25 Digimarc Corporation Watermark enabled video objects
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6451656B1 (en) * 2001-02-28 2002-09-17 Advanced Micro Devices, Inc. CMOS inverter configured from double gate MOSFET and method of fabricating same
US6475890B1 (en) * 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
US6475869B1 (en) * 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
US6492212B1 (en) * 2001-10-05 2002-12-10 International Business Machines Corporation Variable threshold voltage double gated transistors and method of fabrication
US20030011080A1 (en) * 2001-07-11 2003-01-16 International Business Machines Corporation Method of fabricating sio2 spacers and annealing caps
US6514808B1 (en) * 2001-11-30 2003-02-04 Motorola, Inc. Transistor having a high K dielectric and short gate length and method therefor
US6521949B2 (en) * 2001-05-03 2003-02-18 International Business Machines Corporation SOI transistor with polysilicon seed
US6525403B2 (en) * 2000-09-28 2003-02-25 Kabushiki Kaisha Toshiba Semiconductor device having MIS field effect transistors or three-dimensional structure
US20030042528A1 (en) * 2001-08-30 2003-03-06 Leonard Forbes Sram cells with repressed floating gate memory, low tunnel barrier interpoly insulators
US6534807B2 (en) * 2001-08-13 2003-03-18 International Business Machines Corporation Local interconnect junction on insulator (JOI) structure
US20030057486A1 (en) * 2001-09-27 2003-03-27 International Business Machines Corporation Fin field effect transistor with self-aligned gate
US6573549B1 (en) * 2002-06-21 2003-06-03 Texas Instruments Incorporated Dynamic threshold voltage 6T SRAM cell
US20030102497A1 (en) * 2001-12-04 2003-06-05 International Business Machines Corporation Multiple-plane finFET CMOS
US20030113970A1 (en) * 2001-12-14 2003-06-19 Fried David M. Implanted asymmetric doped polysilicon gate FinFET
US20030111678A1 (en) * 2001-12-14 2003-06-19 Luigi Colombo CVD deposition of M-SION gate dielectrics
US6596599B1 (en) * 2001-07-16 2003-07-22 Taiwan Semiconductor Manufacturing Company Gate stack for high performance sub-micron CMOS devices
US6605514B1 (en) * 2002-07-31 2003-08-12 Advanced Micro Devices, Inc. Planar finFET patterning using amorphous carbon
US6610576B2 (en) * 2001-12-13 2003-08-26 International Business Machines Corporation Method for forming asymmetric dual gate transistor
US6611029B1 (en) * 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6617210B1 (en) * 2002-05-31 2003-09-09 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US20030178670A1 (en) * 2002-03-19 2003-09-25 International Business Machines Corporation Finfet CMOS with NVRAM capability
US6635909B2 (en) * 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
US6642090B1 (en) * 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
US20040007715A1 (en) * 2002-07-09 2004-01-15 Webb Douglas A. Heterojunction field effect transistors using silicon-germanium and silicon-carbon alloys
US6686231B1 (en) * 2002-12-06 2004-02-03 Advanced Micro Devices, Inc. Damascene gate process with sacrificial oxide in semiconductor devices
US20040031979A1 (en) * 2002-06-07 2004-02-19 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US6706571B1 (en) * 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US20040061178A1 (en) * 2002-09-30 2004-04-01 Advanced Micro Devices Inc. Finfet having improved carrier mobility and method of its formation
US6720231B2 (en) * 2002-01-28 2004-04-13 International Business Machines Corporation Fin-type resistors
US20040075122A1 (en) * 2002-10-22 2004-04-22 Ming-Ren Lin Double and triple gate MOSFET devices and methods for making same
US20040119100A1 (en) * 2002-12-19 2004-06-24 International Business Machines Corporation Dense dual-plane devices
US6768158B2 (en) * 2001-09-04 2004-07-27 Korea Advanced Institute Of Science And Technology Flash memory element and manufacturing method thereof
US20040145000A1 (en) * 2003-01-23 2004-07-29 An Judy Xilin Tri-gate and gate around MOSFET devices and methods for making same
US6992354B2 (en) * 2003-06-25 2006-01-31 International Business Machines Corporation FinFET having suppressed parasitic device characteristics

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2617642A1 (en) * 1987-06-30 1989-01-06 Thomson Semiconducteurs Field-effect transistor
JPH0215675A (en) * 1988-07-01 1990-01-19 Fujitsu Ltd Field effect transistor and manufacture thereof

Patent Citations (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933298A (en) * 1987-12-18 1990-06-12 Fujitsu Limited Method of making high speed semiconductor device having a silicon-on-insulator structure
US4946799A (en) * 1988-07-08 1990-08-07 Texas Instruments, Incorporated Process for making high performance silicon-on-insulator transistor with body node to source node connection
US5115289A (en) * 1988-11-21 1992-05-19 Hitachi, Ltd. Semiconductor device and semiconductor memory device
US5317175A (en) * 1991-02-08 1994-05-31 Nissan Motor Co., Ltd. CMOS device with perpendicular channel current directions
US5317178A (en) * 1992-05-18 1994-05-31 Industrial Technology Research Institute Offset dual gate thin film field effect transistor
US5464783A (en) * 1993-03-24 1995-11-07 At&T Corp. Oxynitride-dioxide composite gate dielectric process for MOS manufacture
US5801397A (en) * 1994-09-30 1998-09-01 Sgs-Thomson Microelectronics, Inc. Device having a self-aligned gate electrode wrapped around the channel
US5607865A (en) * 1995-01-27 1997-03-04 Goldstar Electron Co., Ltd. Structure and fabrication method for a thin film transistor
US6411725B1 (en) * 1995-07-27 2002-06-25 Digimarc Corporation Watermark enabled video objects
US5814895A (en) * 1995-12-22 1998-09-29 Sony Corporation Static random access memory having transistor elements formed on side walls of a trench in a semiconductor substrate
US5998852A (en) * 1996-11-22 1999-12-07 International Business Machines Corporation Geometrical control of device corner threshold
US6114725A (en) * 1997-01-22 2000-09-05 International Business Machines Corporation Structure for folded architecture pillar memory cell
US6157061A (en) * 1997-08-29 2000-12-05 Nec Corporation Nonvolatile semiconductor memory device and method of manufacturing the same
US6222234B1 (en) * 1998-04-15 2001-04-24 Nec Corporation Semiconductor device having partially and fully depleted SOI elements on a common substrate
US6387739B1 (en) * 1998-08-07 2002-05-14 International Business Machines Corporation Method and improved SOI body contact structure for transistors
US6391796B1 (en) * 1998-09-14 2002-05-21 Shin-Etsu Handotai Co., Ltd. Method for heat-treating silicon wafer and silicon wafer
US6476437B2 (en) * 1998-11-16 2002-11-05 Vanguard International Semiconductor Corp. Crown or stack capacitor with a monolithic fin structure
US6344392B1 (en) * 1998-11-16 2002-02-05 Vanguard International Semiconductor Corporation Methods of manufacture of crown or stack capacitor with a monolithic fin structure made with a different oxide etching rate in hydrogen fluoride vapor
US6252284B1 (en) * 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
US6432829B2 (en) * 1999-12-09 2002-08-13 International Business Machines Corporation Process for making planarized silicon fin device
US6380024B1 (en) * 2000-02-07 2002-04-30 Taiwan Semiconductor Manufacturing Company Method of fabricating an SRAM cell featuring dual silicide gates and four buried contact regions
US6391782B1 (en) * 2000-06-20 2002-05-21 Advanced Micro Devices, Inc. Process for forming multiple active lines and gate-all-around MOSFET
US6342410B1 (en) * 2000-07-10 2002-01-29 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with three sided gate structure on semiconductor on insulator
US20020011612A1 (en) * 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US6391695B1 (en) * 2000-08-07 2002-05-21 Advanced Micro Devices, Inc. Double-gate transistor formed in a thermal process
US6525403B2 (en) * 2000-09-28 2003-02-25 Kabushiki Kaisha Toshiba Semiconductor device having MIS field effect transistors or three-dimensional structure
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6300182B1 (en) * 2000-12-11 2001-10-09 Advanced Micro Devices, Inc. Field effect transistor having dual gates with asymmetrical doping for reduced threshold voltage
US6475890B1 (en) * 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
US6475869B1 (en) * 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
US6451656B1 (en) * 2001-02-28 2002-09-17 Advanced Micro Devices, Inc. CMOS inverter configured from double gate MOSFET and method of fabricating same
US6521949B2 (en) * 2001-05-03 2003-02-18 International Business Machines Corporation SOI transistor with polysilicon seed
US20030011080A1 (en) * 2001-07-11 2003-01-16 International Business Machines Corporation Method of fabricating sio2 spacers and annealing caps
US6596599B1 (en) * 2001-07-16 2003-07-22 Taiwan Semiconductor Manufacturing Company Gate stack for high performance sub-micron CMOS devices
US6534807B2 (en) * 2001-08-13 2003-03-18 International Business Machines Corporation Local interconnect junction on insulator (JOI) structure
US20030042528A1 (en) * 2001-08-30 2003-03-06 Leonard Forbes Sram cells with repressed floating gate memory, low tunnel barrier interpoly insulators
US6768158B2 (en) * 2001-09-04 2004-07-27 Korea Advanced Institute Of Science And Technology Flash memory element and manufacturing method thereof
US20030057486A1 (en) * 2001-09-27 2003-03-27 International Business Machines Corporation Fin field effect transistor with self-aligned gate
US6492212B1 (en) * 2001-10-05 2002-12-10 International Business Machines Corporation Variable threshold voltage double gated transistors and method of fabrication
US20030067017A1 (en) * 2001-10-05 2003-04-10 Meikei Ieong Variable threshold voltage double gated transistors and method of fabrication
US6514808B1 (en) * 2001-11-30 2003-02-04 Motorola, Inc. Transistor having a high K dielectric and short gate length and method therefor
US20030102497A1 (en) * 2001-12-04 2003-06-05 International Business Machines Corporation Multiple-plane finFET CMOS
US20040038464A1 (en) * 2001-12-04 2004-02-26 Fried David M. Multiple-plane FinFET CMOS
US6610576B2 (en) * 2001-12-13 2003-08-26 International Business Machines Corporation Method for forming asymmetric dual gate transistor
US20030111678A1 (en) * 2001-12-14 2003-06-19 Luigi Colombo CVD deposition of M-SION gate dielectrics
US20030113970A1 (en) * 2001-12-14 2003-06-19 Fried David M. Implanted asymmetric doped polysilicon gate FinFET
US6720231B2 (en) * 2002-01-28 2004-04-13 International Business Machines Corporation Fin-type resistors
US6657252B2 (en) * 2002-03-19 2003-12-02 International Business Machines Corporation FinFET CMOS with NVRAM capability
US20030178670A1 (en) * 2002-03-19 2003-09-25 International Business Machines Corporation Finfet CMOS with NVRAM capability
US6635909B2 (en) * 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
US6617210B1 (en) * 2002-05-31 2003-09-09 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US6642090B1 (en) * 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
US20040031979A1 (en) * 2002-06-07 2004-02-19 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US6573549B1 (en) * 2002-06-21 2003-06-03 Texas Instruments Incorporated Dynamic threshold voltage 6T SRAM cell
US20040007715A1 (en) * 2002-07-09 2004-01-15 Webb Douglas A. Heterojunction field effect transistors using silicon-germanium and silicon-carbon alloys
US6605514B1 (en) * 2002-07-31 2003-08-12 Advanced Micro Devices, Inc. Planar finFET patterning using amorphous carbon
US20040061178A1 (en) * 2002-09-30 2004-04-01 Advanced Micro Devices Inc. Finfet having improved carrier mobility and method of its formation
US6706571B1 (en) * 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US20040075122A1 (en) * 2002-10-22 2004-04-22 Ming-Ren Lin Double and triple gate MOSFET devices and methods for making same
US6611029B1 (en) * 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6686231B1 (en) * 2002-12-06 2004-02-03 Advanced Micro Devices, Inc. Damascene gate process with sacrificial oxide in semiconductor devices
US20040119100A1 (en) * 2002-12-19 2004-06-24 International Business Machines Corporation Dense dual-plane devices
US20040145000A1 (en) * 2003-01-23 2004-07-29 An Judy Xilin Tri-gate and gate around MOSFET devices and methods for making same
US6992354B2 (en) * 2003-06-25 2006-01-31 International Business Machines Corporation FinFET having suppressed parasitic device characteristics

Cited By (95)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8053839B2 (en) 2003-04-29 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of semiconductor fin devices
US20060220133A1 (en) * 2003-04-29 2006-10-05 Yee-Chia Yeo Doping of semiconductor fin devices
US20060234431A1 (en) * 2003-04-29 2006-10-19 Yee-Chia Yeo Doping of semiconductor fin devices
US20100176424A1 (en) * 2003-04-29 2010-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of Semiconductor Fin Devices
US8790970B2 (en) 2003-04-29 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of semiconductor fin devices
US7701008B2 (en) 2003-04-29 2010-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of semiconductor fin devices
US20050275010A1 (en) * 2004-06-10 2005-12-15 Hung-Wei Chen Semiconductor nano-wire devices and methods of fabrication
US7452778B2 (en) 2004-06-10 2008-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-wire devices and methods of fabrication
US20100068862A1 (en) * 2005-03-24 2010-03-18 Samsung Electronics Co., Ltd. Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same
US8110471B2 (en) 2005-03-24 2012-02-07 Samsung Electronics Co., Ltd. Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same
US20060216897A1 (en) * 2005-03-24 2006-09-28 Samsung Electronics Co., Ltd. Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same
US7642578B2 (en) * 2005-03-24 2010-01-05 Samsung Electronics Co., Ltd. Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same
US20070040491A1 (en) * 2005-06-02 2007-02-22 Ping Mei Thin film devices and methods for forming the same
US7541227B2 (en) 2005-06-02 2009-06-02 Hewlett-Packard Development Company, L.P. Thin film devices and methods for forming the same
US7482206B2 (en) 2005-06-08 2009-01-27 Samsung Electronics Co., Ltd. Semiconductor devices having nano-line channels and methods of fabricating the same
US20090114904A1 (en) * 2005-06-08 2009-05-07 Samsung Electronics Co., Ltd. Semiconductor devices having nano-line channels
US20070072335A1 (en) * 2005-06-08 2007-03-29 Seung-Jae Baik Semiconductor Devices Having Nano-Line Channels and Methods of Fabricating the Same
US20070262344A1 (en) * 2005-08-18 2007-11-15 Anwar A F M Insulated gate silicon nanowire transistor and method of manufacture
US7485908B2 (en) * 2005-08-18 2009-02-03 United States Of America As Represented By The Secretary Of The Air Force Insulated gate silicon nanowire transistor and method of manufacture
US8173545B2 (en) * 2006-05-04 2012-05-08 Commissariat A L'energie Atomique Method for the fabrication of a transistor gate using at least one electron beam
US20090203203A1 (en) * 2006-05-04 2009-08-13 Commissariat A L'energie Atomique Method for the fabrication of a transistor gate that includes the breakdown of a precursor material into at least one metallic material, using at least one
US9240495B2 (en) * 2006-08-09 2016-01-19 Micron Technology, Inc. Methods of forming nanoscale floating gate
US8017481B2 (en) * 2006-08-09 2011-09-13 Micron Technology, Inc. Methods of forming nanoscale floating gate
US20100112778A1 (en) * 2006-08-09 2010-05-06 Micron Technology, Inc. Nanoscale floating gate and methods of formation
US8395202B2 (en) 2006-08-09 2013-03-12 Micron Technology, Inc. Nanoscale floating gate
US7955932B2 (en) * 2006-10-04 2011-06-07 Samsung Electronics Co., Ltd. Single electron transistor and method of manufacturing the same
US8124961B2 (en) * 2006-10-04 2012-02-28 Samsung Electronics Co., Ltd. Single electron transistor
US20110233523A1 (en) * 2006-10-04 2011-09-29 Samsung Electronics Co., Ltd. Single electron transistor
US20080246021A1 (en) * 2006-10-04 2008-10-09 Samsung Electronic Co., Ltd., Single electron transistor and method of manufacturing the same
US20080272366A1 (en) * 2007-05-03 2008-11-06 Moon Chang-Wook Field effect transistor having germanium nanorod and method of manufacturing the same
US9318573B2 (en) 2007-05-03 2016-04-19 Samsung Electronics Co., Ltd. Field effect transistor having germanium nanorod and method of manufacturing the same
US8101483B2 (en) * 2007-10-18 2012-01-24 Macronix International Co., Ltd. Semiconductor device and method for manufacturing the same
US7781825B2 (en) * 2007-10-18 2010-08-24 Macronix International Co., Ltd. Semiconductor device and method for manufacturing the same
US20110003446A1 (en) * 2007-10-18 2011-01-06 Macronix International Co., Ltd. Semiconductor Device and Method for Manufacturing the Same
US20090101967A1 (en) * 2007-10-18 2009-04-23 Macronix International Co., Ltd. Semiconductor device and method for manufacturing the same
KR101406224B1 (en) * 2007-10-26 2014-06-12 삼성전자주식회사 Nanowire transistor and manufacturing method of the same
US20110018065A1 (en) * 2008-02-26 2011-01-27 Nxp B.V. Method for manufacturing semiconductor device and semiconductor device
KR101213861B1 (en) * 2008-07-29 2012-12-18 노키아 코포레이션 A lithographic process using a nanowire mask, and nanoscale devices fabricated using the process
US8022393B2 (en) * 2008-07-29 2011-09-20 Nokia Corporation Lithographic process using a nanowire mask, and nanoscale devices fabricated using the process
US20100025658A1 (en) * 2008-07-29 2010-02-04 Alan Colli Lithographic process using a nanowire mask, and nanoscale devices fabricated using the process
US8119430B2 (en) * 2008-10-10 2012-02-21 Electronics And Telecommunications Research Institute Method of manufacturing semiconductor nanowire sensor device and semiconductor nanowire sensor device manufactured according to the method
US20100090197A1 (en) * 2008-10-10 2010-04-15 Electonics And Telecommunications Research Institute Method of manufacturing semiconductor nanowire sensor device and semiconductor nanowire sensor device manufactured according to the method
US20120146000A1 (en) * 2009-12-04 2012-06-14 International Business Machines Corporation Omega Shaped Nanowire Field Effect Transistors
US8507892B2 (en) 2009-12-04 2013-08-13 International Business Machines Corporation Omega shaped nanowire tunnel field effect transistors
US8173993B2 (en) 2009-12-04 2012-05-08 International Business Machines Corporation Gate-all-around nanowire tunnel field effect transistors
US8680589B2 (en) * 2009-12-04 2014-03-25 International Business Machines Corporation Omega shaped nanowire field effect transistors
US20110133161A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Omega Shaped Nanowire Tunnel Field Effect Transistors
US8129247B2 (en) * 2009-12-04 2012-03-06 International Business Machines Corporation Omega shaped nanowire field effect transistors
US8143113B2 (en) * 2009-12-04 2012-03-27 International Business Machines Corporation Omega shaped nanowire tunnel field effect transistors fabrication
US20110133169A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Gate-All-Around Nanowire Tunnel Field Effect Transistors
US9184301B2 (en) 2009-12-04 2015-11-10 Globalfoundries Inc. Planar and nanowire field effect transistors
US8097515B2 (en) 2009-12-04 2012-01-17 International Business Machines Corporation Self-aligned contacts for nanowire field effect transistors
US20110133162A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Gate-All-Around Nanowire Field Effect Transistors
US8455334B2 (en) 2009-12-04 2013-06-04 International Business Machines Corporation Planar and nanowire field effect transistors
US20110133164A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Omega Shaped Nanowire Field Effect Transistors
US20110133167A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Planar and nanowire field effect transistors
US20110133165A1 (en) * 2009-12-04 2011-06-09 International Business Machines Corporation Self-aligned contacts for nanowire field effect transistors
US8384065B2 (en) 2009-12-04 2013-02-26 International Business Machines Corporation Gate-all-around nanowire field effect transistors
US8722492B2 (en) 2010-01-08 2014-05-13 International Business Machines Corporation Nanowire pin tunnel field effect devices
US9105482B2 (en) 2010-01-08 2015-08-11 International Business Machines Corporation Nanowire PIN tunnel field effect devices
US20110168982A1 (en) * 2010-01-08 2011-07-14 International Business Machines Corporation Nanowire pin tunnel field effect devices
US8324940B2 (en) 2010-04-13 2012-12-04 International Business Machines Corporation Nanowire circuits in matched devices
US8520430B2 (en) 2010-04-13 2013-08-27 International Business Machines Corporation Nanowire circuits in matched devices
US8772755B2 (en) 2010-05-10 2014-07-08 International Business Machines Corporation Directionally etched nanowire field effect transistors
US8361907B2 (en) 2010-05-10 2013-01-29 International Business Machines Corporation Directionally etched nanowire field effect transistors
US8723162B2 (en) 2010-05-12 2014-05-13 International Business Machines Corporation Nanowire tunnel field effect transistors
US8324030B2 (en) 2010-05-12 2012-12-04 International Business Machines Corporation Nanowire tunnel field effect transistors
US20110297962A1 (en) * 2010-06-08 2011-12-08 Jenn-Chang Hwang Schottky diode with diamond rod and method for manufacturing the same
US8309968B2 (en) * 2010-06-08 2012-11-13 National Tsing Hua University Schottky diode with diamond rod and method for manufacturing the same
CN102290447A (en) * 2010-06-18 2011-12-21 国立清华大学 Columnar diamond Schottky diode and production method thereof
US8680510B2 (en) * 2010-06-28 2014-03-25 International Business Machines Corporation Method of forming compound semiconductor
US20110315953A1 (en) * 2010-06-28 2011-12-29 International Business Machines Corporation Method of forming compound semiconductor
US8586966B2 (en) 2010-08-16 2013-11-19 International Business Machines Corporation Contacts for nanowire field effect transistors
US8835231B2 (en) 2010-08-16 2014-09-16 International Business Machines Corporation Methods of forming contacts for nanowire field effect transistors
US8513068B2 (en) 2010-09-17 2013-08-20 International Business Machines Corporation Nanowire field effect transistors
US8536563B2 (en) 2010-09-17 2013-09-17 International Business Machines Corporation Nanowire field effect transistors
CN102074577A (en) * 2010-10-09 2011-05-25 北京大学 Vertical channel field effect transistor and preparation method thereof
US8901644B2 (en) 2010-10-09 2014-12-02 Peking University Field effect transistor with a vertical channel and fabrication method thereof
US9620596B2 (en) * 2011-08-30 2017-04-11 Sandia Corporation Method to fabricate micro and nano diamond devices
US20150041810A1 (en) * 2011-08-30 2015-02-12 Sandia Corporation Method to fabricate micro and nano diamond devices
US8852998B1 (en) * 2011-08-30 2014-10-07 Sandia Corporation Method to fabricate micro and nano diamond devices
US9099544B2 (en) * 2011-10-04 2015-08-04 Universidad De Granada RAM memory point with a transistor
US20140299835A1 (en) * 2011-10-04 2014-10-09 Centre National De La Recherche Scientifique Ram memory point with a transistor
US20130207079A1 (en) * 2012-02-09 2013-08-15 International Business Machines Corporation Tapered Nanowire Structure With Reduced Off Current
US8901659B2 (en) * 2012-02-09 2014-12-02 International Business Machines Corporation Tapered nanowire structure with reduced off current
US9514937B2 (en) 2012-02-09 2016-12-06 International Business Machines Corporation Tapered nanowire structure with reduced off current
US9224849B2 (en) * 2012-12-28 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Transistors with wrapped-around gates and methods for forming the same
US20140183643A1 (en) * 2012-12-28 2014-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. Transistors with Wrapped-Around Gates and Methods for Forming the Same
US20140217509A1 (en) * 2013-02-07 2014-08-07 International Business Machines Corporation Diode Structure and Method for Gate All Around Silicon Nanowire Technologies
US8901655B2 (en) * 2013-02-07 2014-12-02 International Business Machines Corporation Diode structure for gate all around silicon nanowire technologies
US9419098B2 (en) 2013-05-30 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Tuning strain in semiconductor devices
US9941404B2 (en) 2013-05-30 2018-04-10 Taiwan Semiconductor Manufacturing Company, Ltd. Tuning strain in semiconductor devices
US9349850B2 (en) 2013-07-17 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally tuning strain in semiconductor devices
US9871141B2 (en) 2013-07-17 2018-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally tuning strain in semiconductor devices
CN110299400A (en) * 2019-06-27 2019-10-01 中国科学院半导体研究所 The silicon substrate foreign atom transistor and preparation method thereof of three-dimensional potential barrier limitation

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