US20050088898A1 - Low power flash memory cell and method - Google Patents
Low power flash memory cell and method Download PDFInfo
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- US20050088898A1 US20050088898A1 US10/976,596 US97659604A US2005088898A1 US 20050088898 A1 US20050088898 A1 US 20050088898A1 US 97659604 A US97659604 A US 97659604A US 2005088898 A1 US2005088898 A1 US 2005088898A1
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 64
- 229920005591 polysilicon Polymers 0.000 claims abstract description 64
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical group [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 11
- 238000000151 deposition Methods 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 238000000059 patterning Methods 0.000 abstract description 4
- 239000003989 dielectric material Substances 0.000 description 9
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000003247 decreasing effect Effects 0.000 description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000002365 hybrid physical--chemical vapour deposition Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Definitions
- a flash memory cell may be formed on a substrate using a double polysilicon structure, with inter-poly oxide interposed between a floating polysilicon gate and a control polysilicon gate.
- a tunnel oxide is interposed between the floating polysilicon gate and the substrate.
- the programming voltage of a flash memory cell is determined by the field required to generate tunnel current through the tunnel oxide, which is interposed between the floating polysilicon gate and the substrate, for example bulk silicon.
- the required charge retention time sets the lower limit of the thickness of both the tunnel oxide and the inter-poly oxide.
- the programming voltage can be reduced.
- V G The programming voltage (V G ) is applied to the control gate, to produce a voltage at the floating gate (V FG ).
- T and P denote that the parameter relates to the tunnel oxide or the inter-poly oxide, respectively.
- the floating gate voltage increases with increasing tunnel oxide thickness (t T ), decreasing inter-poly oxide thickness (t P ), and increasing inter-poly oxide dielectric constant ( ⁇ P ).
- Increasing the dielectric constant and decreasing the thickness of the inter-poly oxide is one preferred method of increasing the floating gate voltage, which corresponds to decreasing the programming voltage.
- increasing the tunnel oxide thickness would also increase the floating gate voltage, this option is not preferred, because the tunnel current decreases exponentially with increasing thickness of the tunnel oxide.
- the tunnel oxide is preferably maintained as thin as possible. Therefore, one of the preferred methods of reducing the programming voltage is to replace the inter-poly silicon dioxide with a high-k dielectric material.
- a flash memory cell structure comprising a high-k dielectric material, for example hafnium oxide or zirconium oxide, interposed between a control gate and a polysilicon floating gate.
- a tunnel oxide is interposed between the floating gate and a substrate.
- Methods of forming flash memory cells comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. A high-k dielectric layer may then be deposited over the first polysilicon layer. A third polysilicon layer may then be deposited over the high-k dielectric layer and patterned using photoresist to form a flash memory gate structure.
- the high-k dielectric layer may be patterned to allow for formation of non-memory transistors in conjunction with the process of forming the flash memory cells.
- FIG. 1 is a cross section view of a device structure during processing.
- FIG. 2 is a cross section view of a device structure during processing.
- FIG. 3 is a cross section view of a device structure during processing.
- FIG. 4 is a cross section view of a device structure during processing.
- FIG. 5 is a cross section view of a device structure during processing.
- FIG. 6 is a cross section view of a device structure during processing.
- FIG. 7 is a cross section view of a device structure during processing.
- FIG. 8 is a cross section view of a device structure during processing.
- FIG. 9 is a cross section view of a device structure as in FIG. 8 , but rotated ninety degrees.
- FIG. 10 is a cross section view of a device structure, similar to FIG. 9 following additional processing.
- FIG. 11 is a cross section view of a device structure, similar to FIG. 10 following formation of the source and drain regions.
- a semiconductor substrate is provided.
- An n-well or a p-well may be formed if desired prior to isolating adjacent device areas. Threshold voltage adjustment may also be performed, if desired.
- a device structure 10 is formed by growing, or growing and depositing a tunnel oxide layer 12 overlying a semiconductor substrate 14 and depositing a first polysilicon layer 16 , which may also be referred to as poly 1 throughout this description, overlying the tunnel oxide layer 12 , following formation of n-wells or p-wells, if any.
- the first polysilicon layer 16 serves as a floating polysilicon gate.
- the thickness of poly 1 is referred to as T p1 .
- FIG. 2 shows a cross-section of the device structure 10 comprising two adjacent device regions 17 following etching of the semiconductor substrate 14 to form trenches 18 .
- the depth of the trenches 18 which is referred to as X STI , extends from the top of the substrate surface 20 to the bottom 22 of the trenches 18 .
- the uncertainty, or variation, in the trench depth is referred to as ⁇ X STI .
- a cleaning may be performed to reduce, or eliminate, etch damage.
- FIG. 3 shows the device structure 10 following the deposition of an oxide layer 30 .
- the oxide layer 30 is deposited to refill the trenches with oxide.
- the oxide layer 30 has a minimum thickness that is greater than the maximum possible depth of the trench. Referring to the oxide thickness as T OX , and the uncertainty, or variation, in oxide thickness as ⁇ T OX , the oxide layer 30 should be deposited and processed so that the final processed thickness satisfies the condition that: T OX ⁇ T OX >X STI + ⁇ X STI
- the oxide may comprise a thin thermal oxide to provide a good interface between the oxide and silicon in the field followed by a deposited oxide.
- the deposited oxide can be formed by a variety of methods including chemical vapor deposition (CVD) methods, such as, LTO, HPCVD, PECVD, or other CVD methods. Non-CVD methods such as sputtering may also be used. Following deposition of oxide by any suitable method, the oxide may then be densified at a higher temperature, if necessary or desired.
- CVD chemical vapor deposition
- Non-CVD methods such as sputtering may also be used.
- a second polysilicon layer 40 also referred to herein as poly 2 , or field poly, is deposited overlying a device structure 10 .
- the thickness of poly 2 is referred to as T p2 .
- Poly 2 should have a thickness selected such that the maximum thickness of poly 2 plus the maximum thickness of oxide layer 30 is thinner than the minimum depth of the trench plus the minimum thickness of poly 1 . Accordingly, the thickness of poly 2 should satisfy the condition: T p2 + ⁇ T p2 +T OX + ⁇ T OX ⁇ X STI ⁇ X STI +T p1 ⁇ T p1 To satisfy this condition and still have a meaningful thickness of poly 2 , there is a maximum desired oxide thickness.
- the maximum oxide layer 30 thickness should satisfy the condition: T OX + ⁇ T OX ⁇ X STI ⁇ X STI +T p1 ⁇ T p1 ⁇ T p2 ⁇ T p2 This should result in the top level of the oxide within the trench being above the bottom level of poly 1 , and the top level of poly 2 within the trench being below the top level of poly 1 .
- a sacrificial oxide layer is deposited overlying the device structure 10 .
- the sacrificial oxide layer may be, for example, undensified TEOS.
- the sacrificial oxide layer is one and a half times thicker than the maximum thickness of poly 1 .
- the sacrificial oxide layer should have a thickness such that the combined thickness of the tunnel oxide layer 12 , poly 1 , the oxide layer 30 , poly 2 , and the sacrificial oxide layer is approximately two times the total step height of the active area features, which corresponds to the actual physical relief of the top surfaces.
- the device structure 10 is polished using CMP to polish the oxide layer 30 and stop at the top of the second polysilicon layer 40 in the field region.
- CMP CMP to polish the oxide layer 30 and stop at the top of the second polysilicon layer 40 in the field region.
- This may be achieved using a two step process.
- a non-selective slurry is used to remove the overlying oxide and the portion of the second polysilicon layer 40 overlying active areas within the device regions.
- the second step utilizes a selective polish, which continues to remove oxide and stops at the first polysilicon layer 16 in the active areas and at the second polysilicon layer 40 in the field regions.
- the actual field oxide is not polished in this step.
- the active areas are much smaller than the field areas and the polish rate of oxide can be selected to be sufficiently higher than that of polysilicon, for example greater than 5:1 oxide to polysilicon etch ratio, so this CMP process can be readily achieved. Since, T p2 + ⁇ T p2 +T OX + ⁇ T OX ⁇ X STI ⁇ X STI +T p1 ⁇ T p1 the oxide on poly 1 is completely removed before the CMP stop at the field poly 2 .
- a high-k dielectric material 58 is deposited overlying the device structure 10 following CMP.
- a high-k dielectric material refers to a dielectric material with a dielectric constant higher than that of silicon dioxide.
- Possible preferred high-k dielectric materials include, ZrO 2 and HfO 2 .
- a 12.9 nm thick film of ZrO 2 has a relative dielectric constant of 18 and a leakage current of 200 nA/cm 2 at 2 volts.
- An 8 nm thick film of HfO 2 has a relative dielectric constant of 15 and a leakage current of 170 nA/cm 2 at 1.5 volts. The leakage current decreases exponentially with the inverse of the square root of thickness.
- High-k dielectric materials may provide a suitable replacement for the poly-oxide material, which is currently being used for flash memory transistors.
- a third polysilicon layer 60 also referred to herein as poly 3 , is deposited overlying the high-k dielectric material 58 .
- the flash memory cells will be fabricated on a substrate that also comprises non-memory transistors.
- a layer of photoresist is applied and patterned to protect the high-k material overlying the flash memory cells. The high-k material may then be etched from the areas overlying the non-memory transistors. The photoresist is then stripped.
- the third polysilicon layer 60 is deposited over the remaining high-k dielectric material 58 in the regions where the flash memory cells will be formed, and is deposited over the poly 1 layer 16 in the non-memory transistor regions, as shown in FIG. 7 .
- the actual gate polysilicon thickness of the non-memory transistors will correspond to the sum of the poly 3 thickness plus the thickness of poly 1 that remains after CMP.
- a layer of sacrificial polysilicon is deposited over the high-k material prior applying and patterning the photoresist.
- the sacrificial polysilicon will be removed from areas overlying non-memory transistors prior to, or in conjunction with, the removal of the high-k material from those areas.
- This sacrificial polysilicon layer may protect the high-k material during patterning processes, including photoresist strip.
- the third polysilicon layer 60 is then deposited it will overly the remaining sacrificial polysilicon over areas with high-k material. Together the sacrificial polysilicon and the polysilicon 60 may form the control gate of the flash memory cell.
- photoresist 70 is applied and patterned to define a flash memory gate structure 72 .
- non-memory transistor gate structures 74 may be defined together with the definition of the flash memory gate structure 72 .
- a multi-step etch process may be used to etch the poly 3 /high-k/poly 1 stack and the poly 3 /poly 2 stack, possibly along with the poly 3 /poly 1 stack, in the case of non-memory transistor structures.
- Some poly 2 remains under the poly 3 and the photoresist, including under the high-k material if present. Since T OX ⁇ T OX >X STI + ⁇ X STI , poly 1 is not completely removed from the active region, as shown in FIG.
- FIG. 9 which is a cross-sectional view of the device structure shown in FIG. 8 rotated ninety degrees to show the cross-section along the source/channel/drain of a flash memory transistor structure.
- the thickness of the remaining poly 1 should be independent of the CMP process.
- a highly selective etch is used to etch the remaining portion of the first polysilicon layer 16 that is not covered by photoresist.
- micro-trenching may be reduced, or eliminated.
- the remainder of poly 1 can be selectively removed without excessive removal of tunnel oxide 12 in the source and drain region.
- the photoresist is then stripped leaving the flash memory gate structure 72 that comprises the remaining portions of poly 1 , high-k material, and poly 3 over each active area, as shown in FIG. 10 .
- Some poly 2 remains under the portion of poly 3 extending beyond the active region, which is not visible in FIG. 10 .
- ion implantation may be used to form source and drain regions that are self-aligned to the gate structure.
- Poly 1 , poly 2 , and poly 3 are also converted to n + or p + polysilicon as is common in conventional processes.
- the flash memory gate structure may alternatively be doped prior to the gate electrode etch, and prior to the source and drain ion implant.
- the polysilicon gate may also be salicided. Several methods of polysilicon gate doping, silicide or self aligned processes, including salicide processes, may be applied to the present process.
- the flash memory gate structure 72 following doping is shown in FIG. 11 , which also shows the implanted source and drain regions 76 .
Abstract
Flash memory cells are provided with a high-k material interposed between a floating polysilicon gate and a control gate. A tunnel oxide is interposed between the floating polysilicon gate and a substrate. Methods of forming flash memory cells are also provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. A high-k dielectric layer may then be deposited over the first polysilicon layer. A third polysilicon layer may then be deposited over the high-k dielectric layer and patterned using photoresist to form a flash memory gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process. The high-k dielectric layer may be patterned to allow for formation of non-memory transistors in conjunction with the process of forming the flash memory cells.
Description
- This application is a continuation-in-part of U.S. patent application Ser. No. 10/112,014, filed on Mar. 29, 2002, entitled Method of Making Self-Aligned Shallow Trench Isolation, which is incorporated herein by reference.
- A flash memory cell may be formed on a substrate using a double polysilicon structure, with inter-poly oxide interposed between a floating polysilicon gate and a control polysilicon gate. A tunnel oxide is interposed between the floating polysilicon gate and the substrate.
- The programming voltage of a flash memory cell is determined by the field required to generate tunnel current through the tunnel oxide, which is interposed between the floating polysilicon gate and the substrate, for example bulk silicon. The thinner the tunnel oxide and the inter-poly oxide the lower the programming voltage will be. As the oxide layers are thinned, the leakage current increases and the charge retention time is reduced. The required charge retention time sets the lower limit of the thickness of both the tunnel oxide and the inter-poly oxide.
- By replacing the inter-poly oxide, which has been silicon dioxide, with a material having a high-k dielectric constant and low leakage current, the programming voltage can be reduced.
- The programming voltage (VG) is applied to the control gate, to produce a voltage at the floating gate (VFG). The voltage at the floating gate is given by:
where, C is capacitance, t is thickness and ε is the dielectric constant of the insulator. The subscripts T and P denote that the parameter relates to the tunnel oxide or the inter-poly oxide, respectively. The floating gate voltage increases with increasing tunnel oxide thickness (tT), decreasing inter-poly oxide thickness (tP), and increasing inter-poly oxide dielectric constant (εP). Increasing the dielectric constant and decreasing the thickness of the inter-poly oxide is one preferred method of increasing the floating gate voltage, which corresponds to decreasing the programming voltage. Although increasing the tunnel oxide thickness would also increase the floating gate voltage, this option is not preferred, because the tunnel current decreases exponentially with increasing thickness of the tunnel oxide. To maintain desirable tunnel current, the tunnel oxide is preferably maintained as thin as possible. Therefore, one of the preferred methods of reducing the programming voltage is to replace the inter-poly silicon dioxide with a high-k dielectric material. - Accordingly, a flash memory cell structure is provided comprising a high-k dielectric material, for example hafnium oxide or zirconium oxide, interposed between a control gate and a polysilicon floating gate. A tunnel oxide is interposed between the floating gate and a substrate.
- Methods of forming flash memory cells are also provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. A high-k dielectric layer may then be deposited over the first polysilicon layer. A third polysilicon layer may then be deposited over the high-k dielectric layer and patterned using photoresist to form a flash memory gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process. The high-k dielectric layer may be patterned to allow for formation of non-memory transistors in conjunction with the process of forming the flash memory cells.
-
FIG. 1 is a cross section view of a device structure during processing. -
FIG. 2 is a cross section view of a device structure during processing. -
FIG. 3 is a cross section view of a device structure during processing. -
FIG. 4 is a cross section view of a device structure during processing. -
FIG. 5 is a cross section view of a device structure during processing. -
FIG. 6 is a cross section view of a device structure during processing. -
FIG. 7 is a cross section view of a device structure during processing. -
FIG. 8 is a cross section view of a device structure during processing. -
FIG. 9 is a cross section view of a device structure as inFIG. 8 , but rotated ninety degrees. -
FIG. 10 is a cross section view of a device structure, similar toFIG. 9 following additional processing. -
FIG. 11 is a cross section view of a device structure, similar toFIG. 10 following formation of the source and drain regions. - For the present method, a semiconductor substrate is provided. An n-well or a p-well may be formed if desired prior to isolating adjacent device areas. Threshold voltage adjustment may also be performed, if desired. Referring now to
FIG. 1 , adevice structure 10 is formed by growing, or growing and depositing atunnel oxide layer 12 overlying asemiconductor substrate 14 and depositing afirst polysilicon layer 16, which may also be referred to as poly 1 throughout this description, overlying thetunnel oxide layer 12, following formation of n-wells or p-wells, if any. Thefirst polysilicon layer 16 serves as a floating polysilicon gate. The thickness of poly 1 is referred to as Tp1. -
FIG. 2 shows a cross-section of thedevice structure 10 comprising two adjacent device regions 17 following etching of thesemiconductor substrate 14 to formtrenches 18. The depth of thetrenches 18, which is referred to as XSTI, extends from the top of thesubstrate surface 20 to the bottom 22 of thetrenches 18. The uncertainty, or variation, in the trench depth is referred to as ΔXSTI. Following etching of the substrate, a cleaning may be performed to reduce, or eliminate, etch damage. -
FIG. 3 shows thedevice structure 10 following the deposition of anoxide layer 30. Theoxide layer 30 is deposited to refill the trenches with oxide. Theoxide layer 30 has a minimum thickness that is greater than the maximum possible depth of the trench. Referring to the oxide thickness as TOX, and the uncertainty, or variation, in oxide thickness as ΔTOX, theoxide layer 30 should be deposited and processed so that the final processed thickness satisfies the condition that:
TOX−ΔTOX>XSTI+ΔXSTI
The oxide may comprise a thin thermal oxide to provide a good interface between the oxide and silicon in the field followed by a deposited oxide. The deposited oxide can be formed by a variety of methods including chemical vapor deposition (CVD) methods, such as, LTO, HPCVD, PECVD, or other CVD methods. Non-CVD methods such as sputtering may also be used. Following deposition of oxide by any suitable method, the oxide may then be densified at a higher temperature, if necessary or desired. - As shown in
FIG. 4 , asecond polysilicon layer 40, also referred to herein as poly 2, or field poly, is deposited overlying adevice structure 10. The thickness of poly 2 is referred to as Tp2. Poly 2 should have a thickness selected such that the maximum thickness of poly 2 plus the maximum thickness ofoxide layer 30 is thinner than the minimum depth of the trench plus the minimum thickness of poly 1. Accordingly, the thickness of poly 2 should satisfy the condition:
Tp2+ΔTp2+TOX+ΔTOX<XSTI−ΔXSTI+Tp1−ΔTp1
To satisfy this condition and still have a meaningful thickness of poly 2, there is a maximum desired oxide thickness. Themaximum oxide layer 30 thickness should satisfy the condition:
TOX+ΔTOX<XSTI−ΔXSTI+Tp1−ΔTp1−Tp2−ΔTp2
This should result in the top level of the oxide within the trench being above the bottom level of poly 1, and the top level of poly 2 within the trench being below the top level of poly 1. - After poly 2 is deposited, a sacrificial oxide layer, not shown, is deposited overlying the
device structure 10. The sacrificial oxide layer may be, for example, undensified TEOS. In one embodiment the sacrificial oxide layer is one and a half times thicker than the maximum thickness of poly 1. In another embodiment, the sacrificial oxide layer should have a thickness such that the combined thickness of thetunnel oxide layer 12, poly 1, theoxide layer 30, poly 2, and the sacrificial oxide layer is approximately two times the total step height of the active area features, which corresponds to the actual physical relief of the top surfaces. - Next, as shown in
FIG. 5 , thedevice structure 10 is polished using CMP to polish theoxide layer 30 and stop at the top of thesecond polysilicon layer 40 in the field region. This may be achieved using a two step process. In the first step, a non-selective slurry is used to remove the overlying oxide and the portion of thesecond polysilicon layer 40 overlying active areas within the device regions. The second step utilizes a selective polish, which continues to remove oxide and stops at thefirst polysilicon layer 16 in the active areas and at thesecond polysilicon layer 40 in the field regions. The actual field oxide is not polished in this step. During the selective polish the active areas are much smaller than the field areas and the polish rate of oxide can be selected to be sufficiently higher than that of polysilicon, for example greater than 5:1 oxide to polysilicon etch ratio, so this CMP process can be readily achieved. Since,
Tp2+ΔTp2+TOX+ΔTOX<XSTI−ΔXSTI+Tp1−ΔTp1
the oxide on poly 1 is completely removed before the CMP stop at the field poly 2. - As shown in
FIG. 6 , a high-k dielectric material 58 is deposited overlying thedevice structure 10 following CMP. A high-k dielectric material refers to a dielectric material with a dielectric constant higher than that of silicon dioxide. Possible preferred high-k dielectric materials include, ZrO2 and HfO2. For example, a 12.9 nm thick film of ZrO2 has a relative dielectric constant of 18 and a leakage current of 200 nA/cm2 at 2 volts. An 8 nm thick film of HfO2 has a relative dielectric constant of 15 and a leakage current of 170 nA/cm2 at 1.5 volts. The leakage current decreases exponentially with the inverse of the square root of thickness. Therefore, the leakage current of thicker ZrO2 and HfO2 is no larger than that of the CVD oxide film. High-k dielectric materials may provide a suitable replacement for the poly-oxide material, which is currently being used for flash memory transistors. Athird polysilicon layer 60, also referred to herein as poly 3, is deposited overlying the high-k dielectric material 58. - Although it is possible to make flash memory cells without non-memory transistors, in one embodiment the flash memory cells will be fabricated on a substrate that also comprises non-memory transistors. When flash memory cells and non-memory transistors are fabricated together it would be preferred to make the process steps as compatible as possible. If non-memory transistors are fabricated with the flash memory cells, a layer of photoresist is applied and patterned to protect the high-k material overlying the flash memory cells. The high-k material may then be etched from the areas overlying the non-memory transistors. The photoresist is then stripped. The
third polysilicon layer 60, in this embodiment, is deposited over the remaining high-k dielectric material 58 in the regions where the flash memory cells will be formed, and is deposited over the poly 1layer 16 in the non-memory transistor regions, as shown inFIG. 7 . The actual gate polysilicon thickness of the non-memory transistors will correspond to the sum of the poly 3 thickness plus the thickness of poly 1 that remains after CMP. - In an alternative embodiment involving forming non-memory transistors together with flash memory cells, a layer of sacrificial polysilicon, not shown, is deposited over the high-k material prior applying and patterning the photoresist. The sacrificial polysilicon will be removed from areas overlying non-memory transistors prior to, or in conjunction with, the removal of the high-k material from those areas. This sacrificial polysilicon layer may protect the high-k material during patterning processes, including photoresist strip. When the
third polysilicon layer 60 is then deposited it will overly the remaining sacrificial polysilicon over areas with high-k material. Together the sacrificial polysilicon and thepolysilicon 60 may form the control gate of the flash memory cell. - Referring now to
FIG. 8 ,photoresist 70 is applied and patterned to define a flashmemory gate structure 72. In some embodiments, non-memorytransistor gate structures 74 may be defined together with the definition of the flashmemory gate structure 72. A multi-step etch process may be used to etch the poly 3/high-k/poly 1 stack and the poly 3/poly 2 stack, possibly along with the poly 3/poly 1 stack, in the case of non-memory transistor structures. Some poly 2 remains under the poly 3 and the photoresist, including under the high-k material if present. Since TOX−ΔTOX>XSTI+ΔXSTI, poly 1 is not completely removed from the active region, as shown inFIG. 9 , which is a cross-sectional view of the device structure shown inFIG. 8 rotated ninety degrees to show the cross-section along the source/channel/drain of a flash memory transistor structure. The thickness of the remaining poly 1 should be independent of the CMP process. After thesecond polysilicon layer 40 has been removed, except where it remains under the photoresist, a highly selective etch is used to etch the remaining portion of thefirst polysilicon layer 16 that is not covered by photoresist. By stopping at the bottom of poly 2 and leaving a thin layer of poly 1 over thetunnel oxide layer 12 and then performing a highly selective etch to remove the remaining thin layer of poly 1, micro-trenching may be reduced, or eliminated. By using high selectivity plasma etching, the remainder of poly 1 can be selectively removed without excessive removal oftunnel oxide 12 in the source and drain region. - The photoresist is then stripped leaving the flash
memory gate structure 72 that comprises the remaining portions of poly 1, high-k material, and poly 3 over each active area, as shown inFIG. 10 . Some poly 2 remains under the portion of poly 3 extending beyond the active region, which is not visible inFIG. 10 . - After formation of the gate structure, ion implantation may be used to form source and drain regions that are self-aligned to the gate structure. Poly 1, poly 2, and poly 3 are also converted to n+ or p+ polysilicon as is common in conventional processes. The flash memory gate structure may alternatively be doped prior to the gate electrode etch, and prior to the source and drain ion implant. The polysilicon gate may also be salicided. Several methods of polysilicon gate doping, silicide or self aligned processes, including salicide processes, may be applied to the present process. The flash
memory gate structure 72 following doping is shown inFIG. 11 , which also shows the implanted source and drainregions 76. - Although exemplary embodiments, including possible variations have been described, the present invention shall not be limited to these examples, but rather the scope of the present invention is to be determined by the following claims.
Claims (16)
1. (canceled)
2. (canceled)
3. (canceled)
4. (canceled)
5. (canceled)
6. (canceled)
7. (canceled)
8. (canceled)
9. A flash memory cell structure comprising a tunnel oxide overlying a substrate, a floating polysilicon gate overlying the tunnel oxide, a high-k dielectric layer overlying the floating polysilicon gate, and a control gate overlying the high-k dielectric layer.
10. The flash memory cell structure of claim 9 , wherein the high-k dielectric layer is hafnium oxide or zirconium oxide.
11. The flash memory cell structure of claim 9 , further comprising a source region and a drain region separated from each other by the gate stack comprising the tunnel oxide, the floating polysilicon gate, the high-k dielectric layer and the control gate.
12. The flash memory cell structure of claim 9 , further comprising non-memory transistors formed on the substrate.
13. The flash memory cell structure of claim 9 , wherein the control gate has a silicide upper surface formed by a salicide process.
14. The flash memory cell strcuture of claim 9 , wherein the control gate is doped polysilicon.
15. The flash memory cell structure of claim 9 , wherein the control gate is n+ doped polysilicon.
16. The flash memory cell structure of claim 9 , wherein the control gate is p+ doped polysilicon.
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EP (1) | EP1498945A3 (en) |
JP (1) | JP2005039280A (en) |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070187798A1 (en) * | 2006-02-15 | 2007-08-16 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing the same |
US20090050952A1 (en) * | 2007-08-20 | 2009-02-26 | Hynix Semiconductor Inc. | Flash memory device and fabrication method thereof |
CN105261622A (en) * | 2014-06-03 | 2016-01-20 | 上海丽恒光微电子科技有限公司 | Manufacturing method of imaging detector |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6429481B1 (en) * | 1997-11-14 | 2002-08-06 | Fairchild Semiconductor Corporation | Field effect transistor and method of its manufacture |
US7012021B2 (en) * | 2004-01-29 | 2006-03-14 | Taiwan Semiconductor Mfg | Method for end point detection polysilicon chemical mechanical polishing in an anti-fuse memory device |
US7323424B2 (en) * | 2004-06-29 | 2008-01-29 | Micron Technology, Inc. | Semiconductor constructions comprising cerium oxide and titanium oxide |
JP2006351881A (en) * | 2005-06-16 | 2006-12-28 | Toshiba Corp | Semiconductor memory device and its manufacturing method |
US20070056925A1 (en) * | 2005-09-09 | 2007-03-15 | Lam Research Corporation | Selective etch of films with high dielectric constant with H2 addition |
US8183161B2 (en) * | 2006-09-12 | 2012-05-22 | Tokyo Electron Limited | Method and system for dry etching a hafnium containing material |
US7879663B2 (en) * | 2007-03-08 | 2011-02-01 | Freescale Semiconductor, Inc. | Trench formation in a semiconductor material |
US9029255B2 (en) * | 2012-08-24 | 2015-05-12 | Nanya Technology Corporation | Semiconductor device and fabrication method therof |
CN106057669A (en) * | 2016-06-24 | 2016-10-26 | 上海华虹宏力半导体制造有限公司 | IGBT terminal field oxide technique |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5879990A (en) * | 1996-03-22 | 1999-03-09 | U.S. Philips Corporation | Semiconductor device having an embedded non-volatile memory and method of manufacturing such a semicondutor device |
US6548855B1 (en) * | 2002-05-16 | 2003-04-15 | Advanced Micro Devices, Inc. | Non-volatile memory dielectric as charge pump dielectric |
US6617639B1 (en) * | 2002-06-21 | 2003-09-09 | Advanced Micro Devices, Inc. | Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling |
US6642573B1 (en) * | 2002-03-13 | 2003-11-04 | Advanced Micro Devices, Inc. | Use of high-K dielectric material in modified ONO structure for semiconductor devices |
US6682973B1 (en) * | 2002-05-16 | 2004-01-27 | Advanced Micro Devices, Inc. | Formation of well-controlled thin SiO, SiN, SiON layer for multilayer high-K dielectric applications |
US20040051134A1 (en) * | 2002-09-12 | 2004-03-18 | Chuch Jang | Atomic layer deposition of interpoly oxides in a non-volatile memory device |
US6753570B1 (en) * | 2002-08-20 | 2004-06-22 | Advanced Micro Devices, Inc. | Memory device and method of making |
US20040124459A1 (en) * | 2002-04-19 | 2004-07-01 | Yoshitaka Sasago | Nonvolatile semiconductor memory devices and the fabrication process of them |
US6803272B1 (en) * | 2001-12-31 | 2004-10-12 | Advanced Micro Devices, Inc. | Use of high-K dielectric material in modified ONO structure for semiconductor devices |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6008112A (en) * | 1998-01-08 | 1999-12-28 | International Business Machines Corporation | Method for planarized self-aligned floating gate to isolation |
EP1080499A1 (en) * | 1999-03-09 | 2001-03-07 | Koninklijke Philips Electronics N.V. | Semiconductor device comprising a non-volatile memory |
US6232635B1 (en) * | 2000-04-06 | 2001-05-15 | Advanced Micro Devices, Inc. | Method to fabricate a high coupling flash cell with less silicide seam problem |
US6624022B1 (en) * | 2000-08-29 | 2003-09-23 | Micron Technology, Inc. | Method of forming FLASH memory |
TW494544B (en) * | 2001-05-03 | 2002-07-11 | Shr Min | Structure and manufacture method of non-volatile memory |
CN1192439C (en) * | 2001-06-25 | 2005-03-09 | 旺宏电子股份有限公司 | Flash memory structure |
KR20030002710A (en) * | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | Method for manufacturing a flash memory device |
KR100393229B1 (en) * | 2001-08-11 | 2003-07-31 | 삼성전자주식회사 | Method of manufacturing non-volatile memory device including self-aligned gate structure and device by the same |
KR20030043499A (en) * | 2001-11-28 | 2003-06-02 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory cell |
-
2003
- 2003-07-17 US US10/622,667 patent/US6858514B2/en not_active Expired - Lifetime
-
2004
- 2004-07-15 EP EP04016720A patent/EP1498945A3/en not_active Withdrawn
- 2004-07-16 KR KR1020040055777A patent/KR100587186B1/en not_active IP Right Cessation
- 2004-07-16 JP JP2004210860A patent/JP2005039280A/en active Pending
- 2004-07-16 TW TW093121384A patent/TWI248171B/en not_active IP Right Cessation
- 2004-07-19 CN CNB200410069696XA patent/CN100353526C/en not_active Expired - Fee Related
- 2004-10-29 US US10/976,596 patent/US20050088898A1/en not_active Abandoned
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5879990A (en) * | 1996-03-22 | 1999-03-09 | U.S. Philips Corporation | Semiconductor device having an embedded non-volatile memory and method of manufacturing such a semicondutor device |
US6803272B1 (en) * | 2001-12-31 | 2004-10-12 | Advanced Micro Devices, Inc. | Use of high-K dielectric material in modified ONO structure for semiconductor devices |
US6642573B1 (en) * | 2002-03-13 | 2003-11-04 | Advanced Micro Devices, Inc. | Use of high-K dielectric material in modified ONO structure for semiconductor devices |
US20040124459A1 (en) * | 2002-04-19 | 2004-07-01 | Yoshitaka Sasago | Nonvolatile semiconductor memory devices and the fabrication process of them |
US6548855B1 (en) * | 2002-05-16 | 2003-04-15 | Advanced Micro Devices, Inc. | Non-volatile memory dielectric as charge pump dielectric |
US6682973B1 (en) * | 2002-05-16 | 2004-01-27 | Advanced Micro Devices, Inc. | Formation of well-controlled thin SiO, SiN, SiON layer for multilayer high-K dielectric applications |
US6617639B1 (en) * | 2002-06-21 | 2003-09-09 | Advanced Micro Devices, Inc. | Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling |
US6753570B1 (en) * | 2002-08-20 | 2004-06-22 | Advanced Micro Devices, Inc. | Memory device and method of making |
US20040051134A1 (en) * | 2002-09-12 | 2004-03-18 | Chuch Jang | Atomic layer deposition of interpoly oxides in a non-volatile memory device |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070187798A1 (en) * | 2006-02-15 | 2007-08-16 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing the same |
US8044487B2 (en) * | 2006-02-15 | 2011-10-25 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing the same |
US20090050952A1 (en) * | 2007-08-20 | 2009-02-26 | Hynix Semiconductor Inc. | Flash memory device and fabrication method thereof |
US20110095352A1 (en) * | 2007-08-20 | 2011-04-28 | Hynix Semiconductor Inc. | Flash memory device and fabrication method thereof |
US8247299B2 (en) * | 2007-08-20 | 2012-08-21 | Hynix Semiconductor Inc. | Flash memory device and fabrication method thereof |
CN105261622A (en) * | 2014-06-03 | 2016-01-20 | 上海丽恒光微电子科技有限公司 | Manufacturing method of imaging detector |
Also Published As
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JP2005039280A (en) | 2005-02-10 |
EP1498945A3 (en) | 2007-09-26 |
TW200525705A (en) | 2005-08-01 |
US20040140504A1 (en) | 2004-07-22 |
EP1498945A2 (en) | 2005-01-19 |
KR100587186B1 (en) | 2006-06-08 |
CN1591832A (en) | 2005-03-09 |
KR20050009246A (en) | 2005-01-24 |
US6858514B2 (en) | 2005-02-22 |
CN100353526C (en) | 2007-12-05 |
TWI248171B (en) | 2006-01-21 |
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