US20050009288A1 - Process for producing semiconductor article using graded epitaxial growth - Google Patents
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- US20050009288A1 US20050009288A1 US10/802,186 US80218604A US2005009288A1 US 20050009288 A1 US20050009288 A1 US 20050009288A1 US 80218604 A US80218604 A US 80218604A US 2005009288 A1 US2005009288 A1 US 2005009288A1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/0251—Graded layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/933—Germanium or silicon or Ge-Si on III-V
Definitions
- the present invention relates to a production of a general substrate of relaxed Si 1-x Ge x -on-insulator (SGOI) for various electronics or optoelectronics applications, and the production of monocrystalline III-V or II-VI material-on-insulator substrate.
- SGOI relaxed Si 1-x Ge x -on-insulator
- Relaxed Si 1-x Ge x -on-insulator is a very promising technology as it combines the benefits of two advanced technologies: the conventional SOI technology and the disruptive SiGe technology.
- the SOI configuration offers various advantages associated with the insulating substrate, namely reduced parasitic capacitances, improved isolation, reduced short-channel-effect, etc.
- High mobility strained-Si, strained-Si 1-x Ge x or strained-Ge MOS devices can be made on SGOI substrates.
- III-V optoelectronic devices can also be integrated into the SGOI substrate by matching the lattice constants of III-V materials and the relaxed Si 1-x Ge x .
- a GaAs layer can be grown on Si 1-x Ge x -on-insulator where x is equal or close to 1.
- SGOI may serve as an ultimate platform for high speed, low power electronic and optoelectronic applications.
- SGOI has been fabricated by several methods in the prior art.
- the separation by implantation of oxygen (SIMOX) technology is used to produce SGOI.
- High dose oxygen implant was used to bury high concentrations of oxygen in a Si 1-x Ge x layer, which was then converted into a buried oxide (BOX) layer upon annealing at high temperature (for example, 1350° C.).
- BOX buried oxide
- One of the main drawbacks is the quality of the resulting Si 1-x Ge x film and BOX.
- Ge segregation during high temperature anneal also limits the maximum Ge composition to a low value.
- U.S. Pat. Nos. 5,461,243 and 5,759,898 describe a second method, in which a conventional silicon-on-insulator (SOI) substrate was used as a compliant substrate.
- SOI silicon-on-insulator
- an initially strained Si 1-x Ge x layer was deposited on a thin SOI substrate.
- the strain was transferred to the thin silicon film underneath, resulting in relaxation of the top Si 1-x Ge x film.
- the final structure is relaxed-SiGe/strained-Si/insulator, which is not an ideal SGOI structure.
- the silicon layer in the structure is unnecessary, and may complicate or undermine the performance of devices built on it. For example, it may form a parasitic back channel on this strained-Si, or may confine unwanted electrons due to the band gap offset between the strained-Si and SiGe layer.
- U.S. Pat. Nos. 5,906,951 and 6,059,895 describe the formation of a similar SGOI structure: strained-layer(s)/relaxed-SiGe/Si/insulator structure.
- the structure was produced by wafer bonding and etch back process using a P ++ layer as an etch stop.
- the presence of the silicon layer in the above structure may be for the purpose of facilitating Si-insulator wafer bonding, but is unnecessary for ideal SGOI substrates.
- the silicon layer may also complicate or undermine the performance of devices built on it. For example, it may form a parasitic back channel on this strained-Si, or may confine unwanted electrons due to the band gap offset between the strained-Si and SiGe layer.
- the etch stop of Pa in the above structure is not practical when the first graded Si 1-y Ge y layer described in the patents has a y value of larger than 0.2.
- Si 1-y Ge y with y larger than 0.2 is a very good etch stop for both KOH and TMAH, as described in a published PCT application WO 99/53539. Therefore, the KOH will not be able to remove the first graded SityGey layer and the second relaxed SiGe layer as described in the patents.
- an improved technique for production of wide range of high quality material is provided.
- the production of relaxed Si 1-x Ge x -on-insulator (SGOI) substrate or relaxed III-V or II-VI material-on-insulator, such as GaAs-on-insulator is described.
- High quality monocrystalline relaxed SiGe layer, relaxed Ge layer, or other relaxed III-V material layer is grown on a silicon substrate using a graded Si 1-x Ge x epitaxial growth technique.
- a thin film of the layer is transferred into an oxidized handle wafer by wafer bonding and wafer splitting using hydrogen ion implantation.
- the invention makes use of the graded Si 1-x Ge x buffer structure, resulting in a simplified and improved process.
- the invention also provides a method allowing a wide range of device materials to be integrated into the inexpensive silicon substrate. For example, it allows production of Si 1-x Ge x -on-insulator with wide range of Ge concentration, and allows production of many III-V or II-VI materials on insulator like GaAs, AlAs, ZnSe and InGaP.
- graded Si 1-x Ge x buffer in the invention allows high quality materials with limited dislocation defects to be produced and transferred.
- SGOI is produced using a SiGe structure in which a region in the graded buffer can act as a natural etch stop.
- the invention provides a process and method for producing monocrystalline semiconductor layers.
- a graded Si 1-x Ge x (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si 1-y Ge y layer, a thin strained Si 1-z Ge z layer and another relaxed Si 1-y Ge y layer. Hydrogen ions are then introduced into the strained Si z Ge z layer.
- the relaxed Si 1-y Ge y layer is bonded to a second oxidized substrate.
- An annealing treatment splits the bonded pair at the strained Si layer, whereby the second relaxed Si 1-y Ge y layer remains on said second substrate.
- a graded Si 1-x Ge x is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth. The relaxed GaAs layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the hydrogen ion rich layer, whereby the upper portion of relaxed GaAs layer remains on said second substrate.
- FIGS. 1A-1C are block diagrams showing the process of producing a SGOI substrate in accordance with the invention.
- FIGS. 2A and 2B are infrared transmission images of an as-bonded wafer pair and a final SGOI substrate after splitting, respectively;
- FIG. 3 is a TEM cross-section view of a SiGe layer that was transferred onto the top of a buried oxide
- FIG. 4 is an AFM for a transferred SGOI substrate showing surface roughness
- FIGS. 5-8 are block diagrams of various exemplary embodiments semiconductor structures in accordance with the invention.
- heteroepitaxial SiGe layers are formed by a graded epitaxial growth technology.
- a linearly stepwise compositionally graded Si 1-x Ge x buffer 102 is deposited with CVD, by increasing Ge concentration from zero to 25%.
- a 2.5 ⁇ m relaxed Si 0.75 Ge 0.25 cap layer 104 is deposited with the final Ge composition, as shown in FIG. 1A .
- the relaxed SiGe cap layer has high quality with very low dislocation defect density (less than 1E6/cm 2 ), as the graded buffer accommodates the lattice mismatch between Si and relaxed SiGe. A thin layer of this high quality SiGe will be transferred into the final SGOI structure.
- the surface of the as-grown relaxed SiGe layer shows a high roughness around 11 nm to 15 nm due to the underlying strain fields generated by misfit dislocations at the graded layer interfaces and thus chemical-mechanical polishing (CMP) is used to smooth the surface.
- CMP chemical-mechanical polishing
- the donor wafer is implanted with hydrogen ion (100 keV, 5E16H + /cm 2 ) to form a buried hydrogen-rich layer. After a surface clean step in a modified RCA solution, it is bonded to an oxidized 106 Si handle wafer 108 at room temperature as shown in FIG. 1B .
- the wafer bonding is one of the key steps, and the bonding energy should be strong enough in order to sustain the subsequent layer transfer in the next step.
- Good bonding requires a flat surface and a highly hydrophilic surface before bonding.
- the buried oxide in the final bonded structure is also required to have good electrical properties as it will influence the final device fabricated on it.
- thermal oxide on the donor wafer is commonly used before H + implantation and wafer bonding, which becomes the buried oxide in the resulting silicon-on-insulator structure.
- the thermal oxide of the Si donor wafer meets all the requirements, as it has good electrical properties, has flat surface and bonds very well to the handle wafer. Unlike the Si, however, the oxidation of SiGe film results in poor thermal oxide quality, and the Ge segregation during oxidation also degrades the SiGe film. Therefore the thermal oxide of SiGe is not suitable for the SGOI fabrication. In one exemplary experiment the SiGe film will be directly bonded to an oxidized Si handle wafer. The high quality thermal oxide in the handle wafer will become the buried oxide in the final SGOI structure. Having a flat surface after a CMP step, the SiGe wafer went through a clean step.
- one difficulty of SiGe film is that, SiGe surface becomes rougher during the standard RCA clean, as the NH 4 OH in RCA1 solution etches Ge faster than Si. Rough surface will lead to weak bonding as the contact area is reduced when bonded to the handle wafer.
- H 2 SO 4 —H 2 O 2 solution is used in the place of RCA I, which also meets the clean process requirement for the subsequent furnace annealing after bonding.
- the SiGe surface after H 2 SO 4 —H 2 O 2 clean shows better surface roughness compared to RCA1.
- the SiGe wafer is dipped in the diluted HF solution to remove the old native oxide. It is then rinsed in DI water thoroughly to make the surface hydrophilic by forming a fresh new native oxide layer that is highly active.
- the SiGe wafer is bonded to an oxidized handle wafer at room temperature, and then annealed at 600° C. for 3 hours. During anneal the bonded pair split into two sheets along the buried hydrogen-rich layer, and a thin relaxed Si 0.75 Ge 0.25 film 110 is transferred into the handle wafer, resulting in a SGOI substrate 112 , as shown in FIG. 1B . A final 850° C. anneal improves the Si 0.75 Ge 0.25 /SiO 2 bond. Thereafter, device layers 114 can be processed on the SGOI substrate 112 as shown in FIG. 1C .
- FIGS. 2A and 2B are infrared transmission images of the as-bonded wafer pair and the final SGOI substrate after splitting, respectively.
- TEM transmission electron microscopy
- AFM atomic force microscopy
- the TEM cross-section view in FIG. 3 shows a 640 nm SiGe layer was transferred onto the top of a 550 nm buried oxide (BOX). Surface damage is also shown clearly at the splitting surface with a damage depth of 100 nm.
- FIG. 4 shows a surface roughness of 11.3 nm in an area of 5 ⁇ 5 ⁇ m 2 by AFM for the as-transferred SGOI.
- the data is similar to those from as-transferred silicon film by smart-cut process, and suggests that a top layer of about 100 nm should be removed by a final CMP step.
- SiGe film transferring only a thin relaxed SiGe film is removed and the donor wafer can be used again for a donor wafer.
- various device structures can be realized by growing one or more device layers on the top, as shown in FIG. 2C .
- Bond strength is important to the process of the invention.
- AFM measurements were conducted to investigate the SiGe film surface roughness before bonding under different conditions.
- One experiment is designed to investigate how long the SiGe surface should be polished to have smooth surface and good bond strength, since the surface of the as-grown relaxed SiGe layer has a high roughness around 11 nm to 15 nm.
- Several identical 4-inch Si wafers with relaxed Si 0.75 Ge 0.25 films were CMPed with optimized polishing conditions for different times.
- the measured surface mircoroughness RMS at an area of 10 ⁇ m ⁇ 10 ⁇ m is 5.5 ⁇ , 4.5 ⁇ and 3.8 ⁇ , for wafer CMPed for 2 min., 4 min. and 6 min. respectively.
- the tested bond strength increases with decreasing RMS.
- a CMP time of 6 min. is necessary for good strength.
- two identical 4-inch Si wafers with relaxed Si 0.75 Ge 0.25 films were CMPed for 8 min.
- H 2 SO 4 :H 2 O 2 After two cleaning steps in H 2 SO 4 :H 2 O 2 solution and one step in diluted HF solution, one wafer was put in a new H 2 SO 4 :H 2 O 2 (3:1) solution and another in a new NH 4 OH:H 2 O 2 :H 2 O (1:1:5), i.e. the conventional RCA1 solution, both for 15 min.
- the resultant wafers were tested using AFM.
- the wafer after H 2 SO 4 :H 2 O 2 solution shows a surface roughness RMS of 2 ⁇ at an area of 1 ⁇ m ⁇ 1 ⁇ m, which after NH 4 OH:H 2 O 2 :H 2 O shows 4.4 ⁇ .
- the conventional RCA clean roughens the SiGe surface significantly, and H 2 SO 4 :H 2 O 2 should be used for SiGe clean.
- the clean procedure is optimized before bonding.
- SiGe-oxide bonding For direct SiGe wafer to oxidized handle wafer bonding (SiGe-oxide bonding), several different clean procedures were tested. It has been found that the H 2 SO 4 :H 2 O 2 (24:1) solution followed by DI water rinse and spin dry gives good bond strength. Alternatively, one can also deposit an oxide layer on the SiGe wafer and then CMP the oxide layer. In this case. SiGe/oxide is bonded to an oxidized handle wafer, i.e. oxide-oxide bonding. Among different clean procedures, it was found that NH 4 OH:H 2 O 2 :H 2 O clean and DI water rinse following by diluted HF, DI water rinse and spin dry gives very good bond strength.
- FIG. 5 is a block diagram of an exemplary embodiment of a semiconductor structure 500 in accordance with the invention.
- a graded Si 1-x Ge x buffer layer 504 is grown on a silicon substrate 502 , where the Ge concentration x is increased from zero to a value y in a stepwise manner, and y has a selected value between 0 and 1.
- a second relaxed Si 1-y Ge y layer 506 is then deposited, and hydrogen ions are implanted into this layer with a selected depth by adjusting implantation energy, forming a buried hydrogen-rich layer 508 .
- the wafer is cleaned and bonded to an oxidized handle wafer 510 .
- An anneal treatment at 500 ⁇ 600° C. splits the bonded pair at the hydrogen-rich layer 508 .
- the upper portion of the relaxed Si 1-y Ge y layer 506 remains on the oxidized handle wafer, forming a SGOI substrate.
- the above description also includes production of Ge-on-insuiator where y
- the standard RCA clean for the silicon surface is modified. Since the NH 4 OH in standard RCA1 solution etches Ge faster than Si, the SiGe surface will become rough, leading to a weak bond. A H 2 SO 4 —H 2 O 2 solution is used in the place of RCA1, which also meets the clean process requirement for the subsequent furnace annealing after bonding. The SiGe surface after the H 2 SO 4 —H 2 O 2 clean showed better surface roughness compared to RCA1. After the modified RCA clean, the wafers are then immersed in another fresh H 2 SO 4 —H 2 O 2 solution for 10 to 20 min. H 2 SO 4 —H 2 O 2 renders the SiGe surface hydrophilic. After a rinse in DI wafer and spin drying, the SiGe wafer is bonded to an oxidized handle wafer at room temperature immediately, and then annealed at 500 ⁇ 600° C. for wafer splitting.
- FIG. 6 is a block diagram of another exemplary embodiment of a semiconductor structure 600 .
- the structure 600 includes a graded Si 1-x Ge x buffer layer 604 grown on a silicon substrate 602 , where the Ge concentration x is increased from zero to 1. Then a relaxed pure Ge layer 606 and a III-V material layer 608 , such as a GaAs layer, are epitaxially grown on the Ge layer. Hydrogen ions are implanted into the GaAs layer 608 with a selected depth by adjusting implantation energy, forming a buried hydrogen-rich layer 610 . The wafer is cleaned and bonded to an oxidized handle wafer 612 . An anneal treatment splits the bonded pair at the hydrogen-rich layer 610 . As a result, the upper portion of the GaAs layer 608 remains on the oxidized handle wafer, forming a GaAs-on-insulator substrate.
- FIG. 7 is a block diagram of yet another exemplary embodiment of a semiconductor structure 700 .
- a graded Si 1-x Ge x buffer layer 704 is grown on a silicon substrate 702 , where the Ge concentration x is increased from zero to a selected value y, where y is less than 0.2.
- a second relaxed Si 1-z Ge z layer 706 is deposited, where z is between 0.2 to 0.25.
- Hydrogen ions are implanted into the graded Si 1-x Ge x buffer layer 704 with a selected depth, forming a buried hydrogen-rich layer 708 within layer 704 .
- the wafer is cleaned and bonded to an oxidized handle wafer 710 .
- An anneal treatment at 500 ⁇ 600° C. splits the bonded pair at the hydrogen-rich layer 708 .
- the upper portion of the graded Si 1-x Ge x buffer layer 704 and the relaxed Si 1-z Ge z layer 706 remains on the oxidized handle wafer 710 .
- the remaining graded Si 1-x Ge x buffer layer 704 is then selectively etched by either KOH or TMAH. KOH and TMAH etch Si 1-x Ge x fast when x is less 0.2, but becomes very slow when x is larger than 0.2.
- the graded Si 1-x Ge x buffer layer 704 can be etched selectively, leaving the relaxed Si 1-z Ge z layer 706 on the insulating substrate 710 and forming a relaxed SGOI substrate.
- the thickness of the relaxed Si 1-z Ge z film 706 on the final SGOI structure is defined by film growth, which is desired in some applications.
- FIG. 8 is a block diagram of yet another exemplary embodiment of a semiconductor structure 800 .
- a graded Si 1-x Ge x buffer layer 804 is grown on a silicon substrate 802 , where the Ge concentration x is increased from zero to a selected value y between 0 and 1.
- a second relaxed Si 1-y Ge y layer 806 is deposited, followed by a strained Si 1-z Ge z layer 808 and another relaxed Si 1-y Ge y layer 810 .
- the thickness of layers 806 , 808 , and 810 , and the value z are chosen such that the Si 1-z Ge z layer 808 is under equilibrium strain state while the Si 1-y Ge y layers 806 and 810 remain relaxed.
- hydrogen ions may be introduced into the strained Si 1-z Ge z layer 808 , forming a hydrogen-rich layer 812 .
- the wafer is cleaned and bonded to an oxidized handle wafer 814 .
- the bonded pair is then separated along the strained Si 1-z Ge z layer 808 .
- the crack propagates along this layer during separation.
- the separation can be accomplished by a variety of techniques, for example using a mechanical force or an anneal treatment at 500 ⁇ 600° C. when the hydrogen is also introduced. See, for example, U.S. Pat. Nos. 6,033,974 and 6,184,111, both of which are incorporated herein by reference.
- the relaxed Si 1-y Ge y layer 810 remains on the oxidized handle wafer, forming a relaxed SGOI substrate.
- the thickness of layers 806 , 808 , and 810 , and the value z may also be chosen such that there are a good amount of dislocations present in the Si 1-z Ge z layer 808 while the top Si 1-y Ge y layer 810 remains relaxed and having high quality and limited dislocation defects.
- the hydrogen ions may be introduced by various ways, such as ion implantation or ion diffusion or drift by means of electrolytic charging.
- the value of z may be chosen in such a way that the remaining Si 1-z Ge z layer 808 can be etched selectively by KOH or TMAH.
- the layers 806 and 810 may also be some other materials, for example pure Ge, or some III-V materials, under the condition that the Ge concentration x in the graded Si 1-x Ge x buffer layer 804 is increased from zero to 1.
- CMP maybe used to polish the surface.
Abstract
A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1-xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1-yGey layer, a thin strained Si1-zGez layer and another relaxed Si1-yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1-yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1-yGey layer remains on the second substrate. In another exemplary embodiment, a graded SixGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth. The relaxed GaAs layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the hydrogen ion rich layer, such that the upper portion of relaxed GaAs layer remains on the second substrate.
Description
- This application claims priority from provisional application Ser. No. 60/225,666 filed Aug. 16, 2000.
- The present invention relates to a production of a general substrate of relaxed Si1-xGex-on-insulator (SGOI) for various electronics or optoelectronics applications, and the production of monocrystalline III-V or II-VI material-on-insulator substrate.
- Relaxed Si1-xGex-on-insulator (SGOI) is a very promising technology as it combines the benefits of two advanced technologies: the conventional SOI technology and the disruptive SiGe technology. The SOI configuration offers various advantages associated with the insulating substrate, namely reduced parasitic capacitances, improved isolation, reduced short-channel-effect, etc. High mobility strained-Si, strained-Si1-xGex or strained-Ge MOS devices can be made on SGOI substrates.
- Other III-V optoelectronic devices can also be integrated into the SGOI substrate by matching the lattice constants of III-V materials and the relaxed Si1-xGex. For example a GaAs layer can be grown on Si1-xGex-on-insulator where x is equal or close to 1. SGOI may serve as an ultimate platform for high speed, low power electronic and optoelectronic applications.
- SGOI has been fabricated by several methods in the prior art. In one method, the separation by implantation of oxygen (SIMOX) technology is used to produce SGOI. High dose oxygen implant was used to bury high concentrations of oxygen in a Si1-xGex layer, which was then converted into a buried oxide (BOX) layer upon annealing at high temperature (for example, 1350° C.). See, for example, Mizuno et al. IEEE Electron Device Letters, Vol. 21, No. 5, pp. 230-232, 2000 and Ishilawa et al. Applied Physics Letters, Vol. 75, No. 7, pp. 983-985, 1999. One of the main drawbacks is the quality of the resulting Si1-xGex film and BOX. In addition, Ge segregation during high temperature anneal also limits the maximum Ge composition to a low value.
- U.S. Pat. Nos. 5,461,243 and 5,759,898 describe a second method, in which a conventional silicon-on-insulator (SOI) substrate was used as a compliant substrate. In the process, an initially strained Si1-xGex layer was deposited on a thin SOI substrate. Upon an anneal treatment, the strain was transferred to the thin silicon film underneath, resulting in relaxation of the top Si1-xGex film. The final structure is relaxed-SiGe/strained-Si/insulator, which is not an ideal SGOI structure. The silicon layer in the structure is unnecessary, and may complicate or undermine the performance of devices built on it. For example, it may form a parasitic back channel on this strained-Si, or may confine unwanted electrons due to the band gap offset between the strained-Si and SiGe layer.
- U.S. Pat. Nos. 5,906,951 and 6,059,895 describe the formation of a similar SGOI structure: strained-layer(s)/relaxed-SiGe/Si/insulator structure. The structure was produced by wafer bonding and etch back process using a P++ layer as an etch stop. The presence of the silicon layer in the above structure may be for the purpose of facilitating Si-insulator wafer bonding, but is unnecessary for ideal SGOI substrates. Again, the silicon layer may also complicate or undermine the performance of devices built on it. For example, it may form a parasitic back channel on this strained-Si, or may confine unwanted electrons due to the band gap offset between the strained-Si and SiGe layer. Moreover, the etch stop of Pa in the above structure is not practical when the first graded Si1-yGey layer described in the patents has a y value of larger than 0.2. Experiments from research shows Si1-yGey with y larger than 0.2 is a very good etch stop for both KOH and TMAH, as described in a published PCT application WO 99/53539. Therefore, the KOH will not be able to remove the first graded SityGey layer and the second relaxed SiGe layer as described in the patents.
- Other attempts include re-crystallization of an amorphous Si1-xGex layer deposited on the top of SOI (silicon-on-insulator) substrate, which is again not an ideal SGOI substrate and the silicon layer is unnecessary, and may complicate or undermine the performance of devices built on it. Note Yeo et al. IEEE Electron Device Letters, Vol. 21, No. 4, pp. 161-163, 2000. The relaxation of the resultant SiGe film and quality of the resulting structure are main concerns.
- From the above, there is a need for a simple technique for relaxed SGOI substrate production, a need for a technique for production of high quality SGOI and other III-V material-on-insulator, and a need for a technique for wide range of material transfer.
- According to the invention, there is provided an improved technique for production of wide range of high quality material is provided. In particular, the production of relaxed Si1-xGex-on-insulator (SGOI) substrate or relaxed III-V or II-VI material-on-insulator, such as GaAs-on-insulator, is described. High quality monocrystalline relaxed SiGe layer, relaxed Ge layer, or other relaxed III-V material layer is grown on a silicon substrate using a graded Si1-xGex epitaxial growth technique. A thin film of the layer is transferred into an oxidized handle wafer by wafer bonding and wafer splitting using hydrogen ion implantation. The invention makes use of the graded Si1-xGex buffer structure, resulting in a simplified and improved process.
- The invention also provides a method allowing a wide range of device materials to be integrated into the inexpensive silicon substrate. For example, it allows production of Si1-xGex-on-insulator with wide range of Ge concentration, and allows production of many III-V or II-VI materials on insulator like GaAs, AlAs, ZnSe and InGaP. The use of graded Si1-xGex buffer in the invention allows high quality materials with limited dislocation defects to be produced and transferred. In one example, SGOI is produced using a SiGe structure in which a region in the graded buffer can act as a natural etch stop.
- The invention provides a process and method for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1-xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1-yGey layer, a thin strained Si1-zGez layer and another relaxed Si1-yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1-yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, whereby the second relaxed Si1-yGey layer remains on said second substrate.
- In another exemplary embodiment, a graded Si1-xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth. The relaxed GaAs layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the hydrogen ion rich layer, whereby the upper portion of relaxed GaAs layer remains on said second substrate.
-
FIGS. 1A-1C are block diagrams showing the process of producing a SGOI substrate in accordance with the invention; -
FIGS. 2A and 2B are infrared transmission images of an as-bonded wafer pair and a final SGOI substrate after splitting, respectively; -
FIG. 3 is a TEM cross-section view of a SiGe layer that was transferred onto the top of a buried oxide; -
FIG. 4 is an AFM for a transferred SGOI substrate showing surface roughness; and -
FIGS. 5-8 are block diagrams of various exemplary embodiments semiconductor structures in accordance with the invention. - An example of a process in which SGOI is created by layer transfer is described. The experiment was performed in two stages. In the first stage, heteroepitaxial SiGe layers are formed by a graded epitaxial growth technology. Starting with a 4-inch Si (100)
donor wafer 100, a linearly stepwise compositionally graded Si1-xGex buffer 102 is deposited with CVD, by increasing Ge concentration from zero to 25%. Then a 2.5 μm relaxed Si0.75Ge0.25 cap layer 104 is deposited with the final Ge composition, as shown inFIG. 1A . - The relaxed SiGe cap layer has high quality with very low dislocation defect density (less than 1E6/cm2), as the graded buffer accommodates the lattice mismatch between Si and relaxed SiGe. A thin layer of this high quality SiGe will be transferred into the final SGOI structure. The surface of the as-grown relaxed SiGe layer shows a high roughness around 11 nm to 15 nm due to the underlying strain fields generated by misfit dislocations at the graded layer interfaces and thus chemical-mechanical polishing (CMP) is used to smooth the surface. In the second stage, the donor wafer is implanted with hydrogen ion (100 keV, 5E16H+/cm2) to form a buried hydrogen-rich layer. After a surface clean step in a modified RCA solution, it is bonded to an oxidized 106
Si handle wafer 108 at room temperature as shown inFIG. 1B . - The wafer bonding is one of the key steps, and the bonding energy should be strong enough in order to sustain the subsequent layer transfer in the next step. Good bonding requires a flat surface and a highly hydrophilic surface before bonding. On the other hand, the buried oxide in the final bonded structure is also required to have good electrical properties as it will influence the final device fabricated on it. In the conventional Si film transfer, thermal oxide on the donor wafer is commonly used before H+ implantation and wafer bonding, which becomes the buried oxide in the resulting silicon-on-insulator structure.
- The thermal oxide of the Si donor wafer meets all the requirements, as it has good electrical properties, has flat surface and bonds very well to the handle wafer. Unlike the Si, however, the oxidation of SiGe film results in poor thermal oxide quality, and the Ge segregation during oxidation also degrades the SiGe film. Therefore the thermal oxide of SiGe is not suitable for the SGOI fabrication. In one exemplary experiment the SiGe film will be directly bonded to an oxidized Si handle wafer. The high quality thermal oxide in the handle wafer will become the buried oxide in the final SGOI structure. Having a flat surface after a CMP step, the SiGe wafer went through a clean step.
- Compared to Si, one difficulty of SiGe film is that, SiGe surface becomes rougher during the standard RCA clean, as the NH4OH in RCA1 solution etches Ge faster than Si. Rough surface will lead to weak bonding as the contact area is reduced when bonded to the handle wafer. In this exemplary embodiment, H2SO4—H2O2 solution is used in the place of RCA I, which also meets the clean process requirement for the subsequent furnace annealing after bonding. The SiGe surface after H2SO4—H2O2 clean shows better surface roughness compared to RCA1.
- After this modified clean procedure, the SiGe wafer is dipped in the diluted HF solution to remove the old native oxide. It is then rinsed in DI water thoroughly to make the surface hydrophilic by forming a fresh new native oxide layer that is highly active. After spinning dry, the SiGe wafer is bonded to an oxidized handle wafer at room temperature, and then annealed at 600° C. for 3 hours. During anneal the bonded pair split into two sheets along the buried hydrogen-rich layer, and a thin relaxed Si0.75Ge0.25 film 110 is transferred into the handle wafer, resulting in a
SGOI substrate 112, as shown inFIG. 1B . A final 850° C. anneal improves the Si0.75Ge0.25/SiO2 bond. Thereafter, device layers 114 can be processed on theSGOI substrate 112 as shown inFIG. 1C . -
FIGS. 2A and 2B are infrared transmission images of the as-bonded wafer pair and the final SGOI substrate after splitting, respectively. To investigate the surface of the as-transferred SGOI substrate, transmission electron microscopy (TEM) and atomic force microscopy (AFM) were used. The TEM cross-section view inFIG. 3 shows a 640 nm SiGe layer was transferred onto the top of a 550 nm buried oxide (BOX). Surface damage is also shown clearly at the splitting surface with a damage depth of 100 nm. -
FIG. 4 shows a surface roughness of 11.3 nm in an area of 5×5 μm2 by AFM for the as-transferred SGOI. The data is similar to those from as-transferred silicon film by smart-cut process, and suggests that a top layer of about 100 nm should be removed by a final CMP step. After SiGe film transferring, only a thin relaxed SiGe film is removed and the donor wafer can be used again for a donor wafer. Starting from this general SGOI substrate, various device structures can be realized by growing one or more device layers on the top, as shown inFIG. 2C . - Electrical evaluation is in progress by growing a strain Si layer on the top of this SGOI substrate followed by fabrication of strained Si channel devices. Bond strength is important to the process of the invention. AFM measurements were conducted to investigate the SiGe film surface roughness before bonding under different conditions. One experiment is designed to investigate how long the SiGe surface should be polished to have smooth surface and good bond strength, since the surface of the as-grown relaxed SiGe layer has a high roughness around 11 nm to 15 nm. Several identical 4-inch Si wafers with relaxed Si0.75Ge0.25 films were CMPed with optimized polishing conditions for different times. Using AFM, the measured surface mircoroughness RMS at an area of 10 μm×10 μm is 5.5 Å, 4.5 Å and 3.8 Å, for wafer CMPed for 2 min., 4 min. and 6 min. respectively. After bonding to identical handle wafers, the tested bond strength increases with decreasing RMS. A CMP time of 6 min. is necessary for good strength. In another experiment, two identical 4-inch Si wafers with relaxed Si0.75Ge0.25 films were CMPed for 8 min. After two cleaning steps in H2SO4:H2O2 solution and one step in diluted HF solution, one wafer was put in a new H2SO4:H2O2 (3:1) solution and another in a new NH4OH:H2O2:H2O (1:1:5), i.e. the conventional RCA1 solution, both for 15 min. The resultant wafers were tested using AFM. The wafer after H2SO4:H2O2 solution shows a surface roughness RMS of 2 Å at an area of 1 μm×1 μm, which after NH4OH:H2O2:H2O shows 4.4 Å. Clearly, the conventional RCA clean roughens the SiGe surface significantly, and H2SO4:H2O2 should be used for SiGe clean.
- In yet another experiment, the clean procedure is optimized before bonding. For direct SiGe wafer to oxidized handle wafer bonding (SiGe-oxide bonding), several different clean procedures were tested. It has been found that the H2SO4:H2O2 (24:1) solution followed by DI water rinse and spin dry gives good bond strength. Alternatively, one can also deposit an oxide layer on the SiGe wafer and then CMP the oxide layer. In this case. SiGe/oxide is bonded to an oxidized handle wafer, i.e. oxide-oxide bonding. Among different clean procedures, it was found that NH4OH:H2O2:H2O clean and DI water rinse following by diluted HF, DI water rinse and spin dry gives very good bond strength.
-
FIG. 5 is a block diagram of an exemplary embodiment of asemiconductor structure 500 in accordance with the invention. A graded Si1-xGex buffer layer 504 is grown on asilicon substrate 502, where the Ge concentration x is increased from zero to a value y in a stepwise manner, and y has a selected value between 0 and 1. A second relaxed Si1-yGey layer 506 is then deposited, and hydrogen ions are implanted into this layer with a selected depth by adjusting implantation energy, forming a buried hydrogen-rich layer 508. The wafer is cleaned and bonded to an oxidizedhandle wafer 510. An anneal treatment at 500˜600° C. splits the bonded pair at the hydrogen-rich layer 508. As a result, the upper portion of the relaxed Si1-yGey layer 506 remains on the oxidized handle wafer, forming a SGOI substrate. The above description also includes production of Ge-on-insuiator where y=1. - During the wafer clean step prior to bonding, the standard RCA clean for the silicon surface is modified. Since the NH4OH in standard RCA1 solution etches Ge faster than Si, the SiGe surface will become rough, leading to a weak bond. A H2SO4—H2O2 solution is used in the place of RCA1, which also meets the clean process requirement for the subsequent furnace annealing after bonding. The SiGe surface after the H2SO4—H2O2 clean showed better surface roughness compared to RCA1. After the modified RCA clean, the wafers are then immersed in another fresh H2SO4—H2O2 solution for 10 to 20 min. H2SO4—H2O2 renders the SiGe surface hydrophilic. After a rinse in DI wafer and spin drying, the SiGe wafer is bonded to an oxidized handle wafer at room temperature immediately, and then annealed at 500˜600° C. for wafer splitting.
-
FIG. 6 is a block diagram of another exemplary embodiment of asemiconductor structure 600. Thestructure 600 includes a graded Si1-xGex buffer layer 604 grown on asilicon substrate 602, where the Ge concentration x is increased from zero to 1. Then a relaxedpure Ge layer 606 and a III-V material layer 608, such as a GaAs layer, are epitaxially grown on the Ge layer. Hydrogen ions are implanted into theGaAs layer 608 with a selected depth by adjusting implantation energy, forming a buried hydrogen-rich layer 610. The wafer is cleaned and bonded to an oxidizedhandle wafer 612. An anneal treatment splits the bonded pair at the hydrogen-rich layer 610. As a result, the upper portion of theGaAs layer 608 remains on the oxidized handle wafer, forming a GaAs-on-insulator substrate. -
FIG. 7 is a block diagram of yet another exemplary embodiment of asemiconductor structure 700. A graded Si1-xGex buffer layer 704 is grown on asilicon substrate 702, where the Ge concentration x is increased from zero to a selected value y, where y is less than 0.2. A second relaxed Si1-zGez layer 706 is deposited, where z is between 0.2 to 0.25. Hydrogen ions are implanted into the graded Si1-xGex buffer layer 704 with a selected depth, forming a buried hydrogen-rich layer 708 withinlayer 704. The wafer is cleaned and bonded to an oxidizedhandle wafer 710. An anneal treatment at 500˜600° C. splits the bonded pair at the hydrogen-rich layer 708. - As a result, the upper portion of the graded Si1-xGex buffer layer 704 and the relaxed Si1-zGez layer 706 remains on the oxidized
handle wafer 710. The remaining graded Si1-xGex buffer layer 704 is then selectively etched by either KOH or TMAH. KOH and TMAH etch Si1-xGex fast when x is less 0.2, but becomes very slow when x is larger than 0.2. Thus, the graded Si1-xGex buffer layer 704 can be etched selectively, leaving the relaxed Si1-zGez layer 706 on the insulatingsubstrate 710 and forming a relaxed SGOI substrate. In this process, the thickness of the relaxed Si1-zGez film 706 on the final SGOI structure is defined by film growth, which is desired in some applications. -
FIG. 8 is a block diagram of yet another exemplary embodiment of asemiconductor structure 800. A graded Si1-xGex buffer layer 804 is grown on asilicon substrate 802, where the Ge concentration x is increased from zero to a selected value y between 0 and 1. A second relaxed Si1-yGey layer 806 is deposited, followed by a strained Si1-zGez layer 808 and another relaxed Si1-yGey layer 810. The thickness oflayers rich layer 812. The wafer is cleaned and bonded to an oxidizedhandle wafer 814. The bonded pair is then separated along the strained Si1-zGez layer 808. - Since the strain makes the layer weaker, the crack propagates along this layer during separation. The separation can be accomplished by a variety of techniques, for example using a mechanical force or an anneal treatment at 500˜600° C. when the hydrogen is also introduced. See, for example, U.S. Pat. Nos. 6,033,974 and 6,184,111, both of which are incorporated herein by reference. As a result, the relaxed Si1-yGey layer 810 remains on the oxidized handle wafer, forming a relaxed SGOI substrate. The thickness of
layers - These dislocation defects in the Si1-zGez layer 808 can then act as hydrogen trap centers during the subsequent step of introducing ions. The hydrogen ions may be introduced by various ways, such as ion implantation or ion diffusion or drift by means of electrolytic charging. The value of z may be chosen in such a way that the remaining Si1-zGez layer 808 can be etched selectively by KOH or TMAH. The
layers - After all the semiconductor-on-insulator substrate obtained by the approaches described above, various device layers can be further grown on the top. Before the regrowth, CMP maybe used to polish the surface.
- Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.
Claims (21)
1-40. (cancelled)
41. A method for forming a semiconductor layer, the method comprising:
forming a first heterostructure by:
forming a graded Si1-xGex buffer layer on a first substrate, the graded Si1-xGex buffer layer having a Ge concentration x increasing from zero to a value y;
forming a relaxed Si1-yGey layer on the graded Si1-xGex buffer layer;
forming a separation layer on the relaxed Si1-yGey layer; and
forming a second relaxed layer over the separation layer;
bonding the first heterostructure to a second substrate to define a second heterostructure; and
splitting the second heterostructure along the separation layer,
wherein the second relaxed layer remains on the second substrate after the second heterostructure is split.
42. The method of claim 56 , wherein the strained layer comprises at least one of Si1-zGez with z≠y and a III-V material.
43. The method of claim 41 , wherein at least one of the relaxed layer and the separation layer comprises at least one material selected from the group consisting of Si1-wGew, Ge, GaAs, AlAs, ZnSe and InGaP.
44. The method of claim 41 , further comprising:
forming at least one of a device layer and a device, after the step of forming the second relaxed layer.
45. The method of claim 57 , further comprising:
forming an insulating layer before the step of introducing ions.,
46. The method of claim 57 , further comprising:
planarizing the second relaxed layer before the step of introducing ions.
47. The method of claim 57 , wherein the ions comprise at least one of hydrogen H+ ions and H2 + ions.
48. The method of claim 41 further comprising:
planarizing the second relaxed layer before bonding the first heterostructure to the second substrate.
49. The method of claim 41 , further comprising:
cleaning at least one of the first heterostructure and the second substrate before the step of bonding.
50. The method of claim 41 , wherein splitting the second heterostructure comprises annealing.
51. The method of claim 41 , further comprising:
removing at least one of (i) a remaining portion of the separation layer, and (ii) a top portion of the second relaxed layer from the second substrate after the step of splitting.
52. The method of claim 41 , further comprising:
forming at least one of a device layer and a device after the step of splitting.
53. The method of claim 41 , further comprising:
after splitting the second heterostructure along the separation layer, planarizing a portion of the first heterostructure split from the second substrate; and
forming new layers on the remaining first heterostructure portion.
54-55. (canceled)
56. The method of claim 41 wherein the separation layer comprises a strained layer.
57. The method of claim 41 , further comprising:
introducing ions into the separation layer, prior to bonding the first heterostructure to the second substrate.
58. The method of claim 41 wherein the separation layer comprises a defect layer.
59. The method of claim 41 wherein the second substrate comprises silicon.
60. The method of claim 41 wherein the second substrate comprises an insulator layer.
61. The method of claim 41 wherein bonding the first heterostructure to the second substrate comprises bonding to the insulator layer.
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US6703688B1 (en) | 2001-03-02 | 2004-03-09 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
US6723661B2 (en) * | 2001-03-02 | 2004-04-20 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
US6940089B2 (en) * | 2001-04-04 | 2005-09-06 | Massachusetts Institute Of Technology | Semiconductor device structure |
US20050026432A1 (en) * | 2001-04-17 | 2005-02-03 | Atwater Harry A. | Wafer bonded epitaxial templates for silicon heterostructures |
US6900094B2 (en) | 2001-06-14 | 2005-05-31 | Amberwave Systems Corporation | Method of selective removal of SiGe alloys |
US7301180B2 (en) * | 2001-06-18 | 2007-11-27 | Massachusetts Institute Of Technology | Structure and method for a high-speed semiconductor device having a Ge channel layer |
JP2004531901A (en) | 2001-06-21 | 2004-10-14 | マサチューセッツ インスティテュート オブ テクノロジー | MOSFET with strained semiconductor layer |
US6730551B2 (en) | 2001-08-06 | 2004-05-04 | Massachusetts Institute Of Technology | Formation of planar strained layers |
US7138649B2 (en) * | 2001-08-09 | 2006-11-21 | Amberwave Systems Corporation | Dual-channel CMOS transistors with differentially strained channels |
US6974735B2 (en) | 2001-08-09 | 2005-12-13 | Amberwave Systems Corporation | Dual layer Semiconductor Devices |
EP1428262A2 (en) | 2001-09-21 | 2004-06-16 | Amberwave Systems Corporation | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same |
AU2002341803A1 (en) | 2001-09-24 | 2003-04-07 | Amberwave Systems Corporation | Rf circuits including transistors having strained material layers |
JP2003205336A (en) * | 2002-01-08 | 2003-07-22 | Tori Techno:Kk | High strength stainless steel bolt and manufacturing method therefor |
US6805962B2 (en) * | 2002-01-23 | 2004-10-19 | International Business Machines Corporation | Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications |
US6746902B2 (en) * | 2002-01-31 | 2004-06-08 | Sharp Laboratories Of America, Inc. | Method to form relaxed sige layer with high ge content |
US6649492B2 (en) * | 2002-02-11 | 2003-11-18 | International Business Machines Corporation | Strained Si based layer made by UHV-CVD, and devices therein |
US6793731B2 (en) * | 2002-03-13 | 2004-09-21 | Sharp Laboratories Of America, Inc. | Method for recrystallizing an amorphized silicon germanium film overlying silicon |
US7132348B2 (en) * | 2002-03-25 | 2006-11-07 | Micron Technology, Inc. | Low k interconnect dielectric using surface transformation |
GB0209737D0 (en) * | 2002-04-29 | 2002-06-05 | Univ Newcastle | Method of isolating adjacent components of a semiconductor device |
WO2003105204A2 (en) | 2002-06-07 | 2003-12-18 | Amberwave Systems Corporation | Semiconductor devices having strained dual channel layers |
WO2003105189A2 (en) * | 2002-06-07 | 2003-12-18 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
US7307273B2 (en) * | 2002-06-07 | 2007-12-11 | Amberwave Systems Corporation | Control of strain in device layers by selective relaxation |
US7335545B2 (en) * | 2002-06-07 | 2008-02-26 | Amberwave Systems Corporation | Control of strain in device layers by prevention of relaxation |
US7615829B2 (en) * | 2002-06-07 | 2009-11-10 | Amberwave Systems Corporation | Elevated source and drain elements for strained-channel heterojuntion field-effect transistors |
WO2003105206A1 (en) | 2002-06-10 | 2003-12-18 | Amberwave Systems Corporation | Growing source and drain elements by selecive epitaxy |
US6982474B2 (en) * | 2002-06-25 | 2006-01-03 | Amberwave Systems Corporation | Reacted conductive gate electrodes |
US7157119B2 (en) | 2002-06-25 | 2007-01-02 | Ppg Industries Ohio, Inc. | Method and compositions for applying multiple overlying organic pigmented decorations on ceramic substrates |
US6953736B2 (en) * | 2002-07-09 | 2005-10-11 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Process for transferring a layer of strained semiconductor material |
FR2842349B1 (en) * | 2002-07-09 | 2005-02-18 | TRANSFERRING A THIN LAYER FROM A PLATE COMPRISING A BUFFER LAYER | |
FR2848334A1 (en) * | 2002-12-06 | 2004-06-11 | Soitec Silicon On Insulator | Multi-layer structure production of semiconductor materials with different mesh parameters comprises epitaxy of thin film on support substrate and adhesion on target substrate |
FR2842350B1 (en) * | 2002-07-09 | 2005-05-13 | METHOD FOR TRANSFERRING A LAYER OF CONCEALED SEMICONDUCTOR MATERIAL | |
US7018910B2 (en) | 2002-07-09 | 2006-03-28 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Transfer of a thin layer from a wafer comprising a buffer layer |
US7510949B2 (en) | 2002-07-09 | 2009-03-31 | S.O.I.Tec Silicon On Insulator Technologies | Methods for producing a multilayer semiconductor structure |
US6841457B2 (en) * | 2002-07-16 | 2005-01-11 | International Business Machines Corporation | Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion |
AU2003274922A1 (en) | 2002-08-23 | 2004-03-11 | Amberwave Systems Corporation | Semiconductor heterostructures having reduced dislocation pile-ups and related methods |
WO2004019403A2 (en) * | 2002-08-26 | 2004-03-04 | S.O.I.Tec Silicon On Insulator Technologies | Mechanical recycling of a wafer comprising a buffer layer, after having taken a layer therefrom |
FR2843827B1 (en) * | 2002-08-26 | 2005-05-27 | MECHANICAL RECYCLING OF A PLATE COMPRISING A STAMP LAYER AFTER SELECTING A THIN LAYER | |
US7008857B2 (en) * | 2002-08-26 | 2006-03-07 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Recycling a wafer comprising a buffer layer, after having separated a thin layer therefrom |
KR100931421B1 (en) * | 2002-08-26 | 2009-12-11 | 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 | Recycling a wafer comprising a buffer layer, after having taken off a thin layer therefrom |
FR2843826B1 (en) * | 2002-08-26 | 2006-12-22 | RECYCLING A PLATE COMPRISING A BUFFER LAYER AFTER SELECTING A THIN LAYER | |
US7594967B2 (en) * | 2002-08-30 | 2009-09-29 | Amberwave Systems Corporation | Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy |
FR2844634B1 (en) * | 2002-09-18 | 2005-05-27 | Soitec Silicon On Insulator | FORMATION OF A RELAXED USEFUL LAYER FROM A PLATE WITHOUT BUFFER LAYER |
KR100889886B1 (en) * | 2003-01-07 | 2009-03-20 | 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 | Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer |
KR100874788B1 (en) * | 2003-01-07 | 2008-12-18 | 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 | Recycling method by mechanical means of a wafer including a peeling structure after thin layer peeling |
US20090325362A1 (en) * | 2003-01-07 | 2009-12-31 | Nabil Chhaimi | Method of recycling an epitaxied donor wafer |
EP1439570A1 (en) * | 2003-01-14 | 2004-07-21 | Interuniversitair Microelektronica Centrum ( Imec) | SiGe strain relaxed buffer for high mobility devices and a method of fabricating it |
JP4659732B2 (en) * | 2003-01-27 | 2011-03-30 | 台湾積體電路製造股▲ふん▼有限公司 | Method for forming a semiconductor layer |
EP1443550A1 (en) * | 2003-01-29 | 2004-08-04 | S.O.I. Tec Silicon on Insulator Technologies S.A. | A method for fabricating a strained crystalline layer on an insulator, a semiconductor structure therefor, and a fabricated semiconductor structure |
US7176528B2 (en) * | 2003-02-18 | 2007-02-13 | Corning Incorporated | Glass-based SOI structures |
US7399681B2 (en) * | 2003-02-18 | 2008-07-15 | Corning Incorporated | Glass-based SOI structures |
FR2851848B1 (en) * | 2003-02-28 | 2005-07-08 | Soitec Silicon On Insulator | RELAXATION AT HIGH TEMPERATURE OF A THIN LAYER AFTER TRANSFER |
US7348260B2 (en) * | 2003-02-28 | 2008-03-25 | S.O.I.Tec Silicon On Insulator Technologies | Method for forming a relaxed or pseudo-relaxed useful layer on a substrate |
US7018909B2 (en) * | 2003-02-28 | 2006-03-28 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Forming structures that include a relaxed or pseudo-relaxed layer on a substrate |
US20040192067A1 (en) * | 2003-02-28 | 2004-09-30 | Bruno Ghyselen | Method for forming a relaxed or pseudo-relaxed useful layer on a substrate |
DE10310740A1 (en) * | 2003-03-10 | 2004-09-30 | Forschungszentrum Jülich GmbH | Method for producing a stress-relaxed layer structure on a non-lattice-matched substrate, and use of such a layer system in electronic and / or optoelectronic components |
US7682947B2 (en) * | 2003-03-13 | 2010-03-23 | Asm America, Inc. | Epitaxial semiconductor deposition methods and structures |
US7238595B2 (en) * | 2003-03-13 | 2007-07-03 | Asm America, Inc. | Epitaxial semiconductor deposition methods and structures |
DE10318284A1 (en) * | 2003-04-22 | 2004-11-25 | Forschungszentrum Jülich GmbH | Process for producing a strained layer on a substrate and layer structure |
JP4532846B2 (en) * | 2003-05-07 | 2010-08-25 | キヤノン株式会社 | Manufacturing method of semiconductor substrate |
US20050124137A1 (en) * | 2003-05-07 | 2005-06-09 | Canon Kabushiki Kaisha | Semiconductor substrate and manufacturing method therefor |
US7662701B2 (en) * | 2003-05-21 | 2010-02-16 | Micron Technology, Inc. | Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers |
US7501329B2 (en) * | 2003-05-21 | 2009-03-10 | Micron Technology, Inc. | Wafer gettering using relaxed silicon germanium epitaxial proximity layers |
DE60336543D1 (en) * | 2003-05-27 | 2011-05-12 | Soitec Silicon On Insulator | Process for producing a heteroepitaxial microstructure |
US7049660B2 (en) * | 2003-05-30 | 2006-05-23 | International Business Machines Corporation | High-quality SGOI by oxidation near the alloy melting temperature |
US7045401B2 (en) * | 2003-06-23 | 2006-05-16 | Sharp Laboratories Of America, Inc. | Strained silicon finFET device |
FR2857953B1 (en) * | 2003-07-21 | 2006-01-13 | Commissariat Energie Atomique | STACKED STRUCTURE, AND METHOD FOR MANUFACTURING THE SAME |
JP2007511892A (en) * | 2003-07-30 | 2007-05-10 | エーエスエム アメリカ インコーポレイテッド | Epitaxial growth of relaxed silicon germanium layers. |
US7153753B2 (en) * | 2003-08-05 | 2006-12-26 | Micron Technology, Inc. | Strained Si/SiGe/SOI islands and processes of making same |
US20050081910A1 (en) * | 2003-08-22 | 2005-04-21 | Danielson David T. | High efficiency tandem solar cells on silicon substrates using ultra thin germanium buffer layers |
US6855963B1 (en) * | 2003-08-29 | 2005-02-15 | International Business Machines Corporation | Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate |
WO2005027214A1 (en) * | 2003-09-10 | 2005-03-24 | Shin-Etsu Handotai Co., Ltd. | Multilayer substrate cleaning method, substrate bonding method, and bonded wafer manufacturing method |
EP1519409B1 (en) * | 2003-09-26 | 2008-08-20 | S.O.I. Tec Silicon on Insulator Technologies S.A. | A method of fabrication of a substrate for an epitaxial growth |
US20050070070A1 (en) * | 2003-09-29 | 2005-03-31 | International Business Machines | Method of forming strained silicon on insulator |
US6933219B1 (en) * | 2003-11-18 | 2005-08-23 | Advanced Micro Devices, Inc. | Tightly spaced gate formation through damascene process |
US6992025B2 (en) * | 2004-01-12 | 2006-01-31 | Sharp Laboratories Of America, Inc. | Strained silicon on insulator from film transfer and relaxation by hydrogen implantation |
US7166522B2 (en) * | 2004-01-23 | 2007-01-23 | Chartered Semiconductor Manufacturing Ltd. | Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch |
US6995078B2 (en) * | 2004-01-23 | 2006-02-07 | Chartered Semiconductor Manufacturing Ltd. | Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch |
US7312125B1 (en) * | 2004-02-05 | 2007-12-25 | Advanced Micro Devices, Inc. | Fully depleted strained semiconductor on insulator transistor and method of making the same |
JP3884439B2 (en) * | 2004-03-02 | 2007-02-21 | 株式会社東芝 | Semiconductor device |
FR2867310B1 (en) * | 2004-03-05 | 2006-05-26 | Soitec Silicon On Insulator | TECHNIQUE FOR IMPROVING THE QUALITY OF A THIN LAYER TAKEN |
FR2867307B1 (en) * | 2004-03-05 | 2006-05-26 | Soitec Silicon On Insulator | HEAT TREATMENT AFTER SMART-CUT DETACHMENT |
US7282449B2 (en) * | 2004-03-05 | 2007-10-16 | S.O.I.Tec Silicon On Insulator Technologies | Thermal treatment of a semiconductor layer |
US20060014363A1 (en) * | 2004-03-05 | 2006-01-19 | Nicolas Daval | Thermal treatment of a semiconductor layer |
US7319530B1 (en) | 2004-03-29 | 2008-01-15 | National Semiconductor Corporation | System and method for measuring germanium concentration for manufacturing control of BiCMOS films |
US6893936B1 (en) * | 2004-06-29 | 2005-05-17 | International Business Machines Corporation | Method of Forming strained SI/SIGE on insulator with silicon germanium buffer |
US7217949B2 (en) * | 2004-07-01 | 2007-05-15 | International Business Machines Corporation | Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) |
US7262466B2 (en) * | 2004-08-18 | 2007-08-28 | Corning Incorporated | Strained semiconductor-on-insulator structures and methods for making strained semiconductor-on-insulator structures |
US7241670B2 (en) * | 2004-09-07 | 2007-07-10 | Sharp Laboratories Of America, Inc | Method to form relaxed SiGe layer with high Ge content using co-implantation of silicon with boron or helium and hydrogen |
US7235812B2 (en) * | 2004-09-13 | 2007-06-26 | International Business Machines Corporation | Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques |
DE102004048096A1 (en) * | 2004-09-30 | 2006-04-27 | Forschungszentrum Jülich GmbH | Method for producing a strained layer on a substrate and layer structure |
US7202124B2 (en) * | 2004-10-01 | 2007-04-10 | Massachusetts Institute Of Technology | Strained gettering layers for semiconductor processes |
US7232759B2 (en) * | 2004-10-04 | 2007-06-19 | Applied Materials, Inc. | Ammonium hydroxide treatments for semiconductor substrates |
FR2876841B1 (en) * | 2004-10-19 | 2007-04-13 | Commissariat Energie Atomique | PROCESS FOR PRODUCING MULTILAYERS ON A SUBSTRATE |
US7247545B2 (en) * | 2004-11-10 | 2007-07-24 | Sharp Laboratories Of America, Inc. | Fabrication of a low defect germanium film by direct wafer bonding |
US7547609B2 (en) * | 2004-11-24 | 2009-06-16 | Silicon Genesis Corporation | Method and structure for implanting bonded substrates for electrical conductivity |
US7229901B2 (en) * | 2004-12-16 | 2007-06-12 | Wisconsin Alumni Research Foundation | Fabrication of strained heterojunction structures |
FR2880988B1 (en) * | 2005-01-19 | 2007-03-30 | Soitec Silicon On Insulator | TREATMENT OF A LAYER IN SI1-yGEy TAKEN |
US7585792B2 (en) * | 2005-02-09 | 2009-09-08 | S.O.I.Tec Silicon On Insulator Technologies | Relaxation of a strained layer using a molten layer |
US7687372B2 (en) * | 2005-04-08 | 2010-03-30 | Versatilis Llc | System and method for manufacturing thick and thin film devices using a donee layer cleaved from a crystalline donor |
FR2884647B1 (en) | 2005-04-15 | 2008-02-22 | Soitec Silicon On Insulator | TREATMENT OF SEMICONDUCTOR PLATES |
US20060234474A1 (en) * | 2005-04-15 | 2006-10-19 | The Regents Of The University Of California | Method of transferring a thin crystalline semiconductor layer |
US20060270190A1 (en) * | 2005-05-25 | 2006-11-30 | The Regents Of The University Of California | Method of transferring a thin crystalline semiconductor layer |
US7432177B2 (en) * | 2005-06-15 | 2008-10-07 | Applied Materials, Inc. | Post-ion implant cleaning for silicon on insulator substrate preparation |
US20070042566A1 (en) * | 2005-08-03 | 2007-02-22 | Memc Electronic Materials, Inc. | Strained silicon on insulator (ssoi) structure with improved crystallinity in the strained silicon layer |
US20070117350A1 (en) * | 2005-08-03 | 2007-05-24 | Memc Electronic Materials, Inc. | Strained silicon on insulator (ssoi) with layer transfer from oxidized donor |
WO2007024433A2 (en) * | 2005-08-26 | 2007-03-01 | Memc Electronic Materials, Inc. | Method for the manufacture of a strained silicon-on-insulator structure |
US20070045707A1 (en) * | 2005-08-31 | 2007-03-01 | Szu-Yu Wang | Memory device and manufacturing method thereof |
FR2891281B1 (en) * | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING A THIN FILM ELEMENT |
US7153761B1 (en) * | 2005-10-03 | 2006-12-26 | Los Alamos National Security, Llc | Method of transferring a thin crystalline semiconductor layer |
US7638410B2 (en) * | 2005-10-03 | 2009-12-29 | Los Alamos National Security, Llc | Method of transferring strained semiconductor structure |
FR2892230B1 (en) * | 2005-10-19 | 2008-07-04 | Soitec Silicon On Insulator | TREATMENT OF A GERMAMIUM LAYER |
FR2892733B1 (en) * | 2005-10-28 | 2008-02-01 | Soitec Silicon On Insulator | RELAXATION OF LAYERS |
CN1992173B (en) * | 2005-11-30 | 2010-04-21 | 硅起源股份有限公司 | Method and structure for implanting bonded substrates for electrical conductivity |
US7785995B2 (en) * | 2006-05-09 | 2010-08-31 | Asm America, Inc. | Semiconductor buffer structures |
US20070264796A1 (en) * | 2006-05-12 | 2007-11-15 | Stocker Mark A | Method for forming a semiconductor on insulator structure |
US7777290B2 (en) * | 2006-06-13 | 2010-08-17 | Wisconsin Alumni Research Foundation | PIN diodes for photodetection and high-speed, high-resolution image sensing |
US7485524B2 (en) * | 2006-06-21 | 2009-02-03 | International Business Machines Corporation | MOSFETs comprising source/drain regions with slanted upper surfaces, and method for fabricating the same |
US7648853B2 (en) | 2006-07-11 | 2010-01-19 | Asm America, Inc. | Dual channel heterostructure |
TW200806829A (en) * | 2006-07-20 | 2008-02-01 | Univ Nat Central | Method for producing single crystal gallium nitride substrate |
US7608526B2 (en) * | 2006-07-24 | 2009-10-27 | Asm America, Inc. | Strained layers within semiconductor buffer structures |
JP2008034411A (en) * | 2006-07-26 | 2008-02-14 | Toshiba Corp | Nitride semiconductor element |
US7960218B2 (en) * | 2006-09-08 | 2011-06-14 | Wisconsin Alumni Research Foundation | Method for fabricating high-speed thin-film transistors |
US7442599B2 (en) * | 2006-09-15 | 2008-10-28 | Sharp Laboratories Of America, Inc. | Silicon/germanium superlattice thermal sensor |
EP1928020B1 (en) * | 2006-11-30 | 2020-04-22 | Soitec | Method of manufacturing a semiconductor heterostructure |
JP2008198656A (en) * | 2007-02-08 | 2008-08-28 | Shin Etsu Chem Co Ltd | Method of manufacturing semiconductor substrate |
FR2912550A1 (en) * | 2007-02-14 | 2008-08-15 | Soitec Silicon On Insulator | Strained silicon on insulator structure/plate fabricating method, involves contacting germanium layer with silicon layer which presents germanium concentration of thirty percent and duration of over-etching phase lower than twenty seconds |
FR2916573A1 (en) * | 2007-05-21 | 2008-11-28 | Commissariat Energie Atomique | Silicon-on-insulator substrate fabricating method for complementary MOS circuit, involves eliminating silicium oxide layer to reveal germanium layer, and waxing galium arsenide base metal from silicium oxide layer |
US7791063B2 (en) * | 2007-08-30 | 2010-09-07 | Intel Corporation | High hole mobility p-channel Ge transistor structure on Si substrate |
US20100003828A1 (en) * | 2007-11-28 | 2010-01-07 | Guowen Ding | Methods for adjusting critical dimension uniformity in an etch process with a highly concentrated unsaturated hydrocarbon gas |
FR2929758B1 (en) * | 2008-04-07 | 2011-02-11 | Commissariat Energie Atomique | TRANSFER METHOD USING A FERROELECTRIC SUBSTRATE |
EP2151852B1 (en) * | 2008-08-06 | 2020-01-15 | Soitec | Relaxation and transfer of strained layers |
US8853745B2 (en) * | 2009-01-20 | 2014-10-07 | Raytheon Company | Silicon based opto-electric circuits |
US7834456B2 (en) * | 2009-01-20 | 2010-11-16 | Raytheon Company | Electrical contacts for CMOS devices and III-V devices formed on a silicon substrate |
US8058143B2 (en) * | 2009-01-21 | 2011-11-15 | Freescale Semiconductor, Inc. | Substrate bonding with metal germanium silicon material |
GB2467935B (en) * | 2009-02-19 | 2013-10-30 | Iqe Silicon Compounds Ltd | Formation of thin layers of GaAs and germanium materials |
GB2467934B (en) * | 2009-02-19 | 2013-10-30 | Iqe Silicon Compounds Ltd | Photovoltaic cell |
FR2943174B1 (en) * | 2009-03-12 | 2011-04-15 | Soitec Silicon On Insulator | ADAPTATION OF THE MESH PARAMETER OF A LAYER OF CONTAMINATED MATERIAL |
US7994550B2 (en) * | 2009-05-22 | 2011-08-09 | Raytheon Company | Semiconductor structures having both elemental and compound semiconductor devices on a common substrate |
US8119904B2 (en) | 2009-07-31 | 2012-02-21 | International Business Machines Corporation | Silicon wafer based structure for heterostructure solar cells |
US9455146B2 (en) * | 2009-12-17 | 2016-09-27 | California Institute Of Technology | Virtual substrates for epitaxial growth and methods of making the same |
WO2011126528A1 (en) * | 2010-04-08 | 2011-10-13 | California Institute Of Technology | Virtual substrates for epitaxial growth and methods of making the same |
CN101866875B (en) * | 2010-06-01 | 2011-12-07 | 中国科学院上海微系统与信息技术研究所 | Method for preparing silicon germanium on insulator (SGOI) by layer transfer and ion implantation technology |
CN101866874B (en) * | 2010-06-01 | 2013-05-22 | 中国科学院上海微系统与信息技术研究所 | Method for preparing silicon germanium on insulator (SGOI) by layer transfer technology |
US8124470B1 (en) | 2010-09-29 | 2012-02-28 | International Business Machines Corporation | Strained thin body semiconductor-on-insulator substrate and device |
WO2012087580A2 (en) | 2010-12-24 | 2012-06-28 | Io Semiconductor, Inc. | Trap rich layer for semiconductor devices |
US8481405B2 (en) | 2010-12-24 | 2013-07-09 | Io Semiconductor, Inc. | Trap rich layer with through-silicon-vias in semiconductor devices |
US9624096B2 (en) | 2010-12-24 | 2017-04-18 | Qualcomm Incorporated | Forming semiconductor structure with device layers and TRL |
US8536021B2 (en) | 2010-12-24 | 2013-09-17 | Io Semiconductor, Inc. | Trap rich layer formation techniques for semiconductor devices |
US9754860B2 (en) | 2010-12-24 | 2017-09-05 | Qualcomm Incorporated | Redistribution layer contacting first wafer through second wafer |
US9553013B2 (en) | 2010-12-24 | 2017-01-24 | Qualcomm Incorporated | Semiconductor structure with TRL and handle wafer cavities |
US9065000B2 (en) | 2011-03-02 | 2015-06-23 | Gregory Belenky | Compound semiconductor device on virtual substrate |
JP5830255B2 (en) * | 2011-03-03 | 2015-12-09 | 信越化学工業株式会社 | Manufacturing method of semiconductor substrate |
FR2972567B1 (en) * | 2011-03-09 | 2013-03-22 | Soitec Silicon On Insulator | METHOD OF FORMING A STRUCTURE OF GE ON III / V ON INSULATION |
US8476629B2 (en) * | 2011-09-27 | 2013-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Enhanced wafer test line structure |
JP5725430B2 (en) * | 2011-10-18 | 2015-05-27 | 富士電機株式会社 | Method for peeling support substrate of solid-phase bonded wafer and method for manufacturing semiconductor device |
CN103165511B (en) * | 2011-12-14 | 2015-07-22 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing germanium on insulator (GOI) |
US9127345B2 (en) | 2012-03-06 | 2015-09-08 | Asm America, Inc. | Methods for depositing an epitaxial silicon germanium layer having a germanium to silicon ratio greater than 1:1 using silylgermane and a diluent |
US9171715B2 (en) | 2012-09-05 | 2015-10-27 | Asm Ip Holding B.V. | Atomic layer deposition of GeO2 |
DE102013202851A1 (en) | 2013-02-21 | 2014-08-21 | Leibniz-Institut Für Festkörper- Und Werkstoffforschung Dresden E.V. | Layer system used for the determination from properties of the material of functional layers, comprises primary layer having specific crystal orientation, secondary layer with continuous change in composition |
US9218963B2 (en) | 2013-12-19 | 2015-12-22 | Asm Ip Holding B.V. | Cyclical deposition of germanium |
US9543323B2 (en) * | 2015-01-13 | 2017-01-10 | International Business Machines Corporation | Strain release in PFET regions |
US10032870B2 (en) | 2015-03-12 | 2018-07-24 | Globalfoundries Inc. | Low defect III-V semiconductor template on porous silicon |
US9754968B2 (en) | 2015-04-30 | 2017-09-05 | International Business Machines Corporation | Structure and method to form III-V, Ge and SiGe fins on insulator |
WO2017065692A1 (en) * | 2015-10-13 | 2017-04-20 | Nanyang Technological University | Method of manufacturing a germanium-on-insulator substrate |
US9466672B1 (en) | 2015-11-25 | 2016-10-11 | International Business Machines Corporation | Reduced defect densities in graded buffer layers by tensile strained interlayers |
US9570300B1 (en) * | 2016-02-08 | 2017-02-14 | International Business Machines Corporation | Strain relaxed buffer layers with virtually defect free regions |
US20180019169A1 (en) * | 2016-07-12 | 2018-01-18 | QMAT, Inc. | Backing substrate stabilizing donor substrate for implant or reclamation |
US9922941B1 (en) | 2016-09-21 | 2018-03-20 | International Business Machines Corporation | Thin low defect relaxed silicon germanium layers on bulk silicon substrates |
US10176991B1 (en) | 2017-07-06 | 2019-01-08 | Wisconsin Alumni Research Foundation | High-quality, single-crystalline silicon-germanium films |
CN108054203B (en) * | 2017-12-22 | 2020-01-10 | 重庆邮电大学 | Heterojunction bipolar transistor of silicon germanium substrate on insulator and manufacturing method thereof |
CN108878263B (en) * | 2018-06-25 | 2022-03-18 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
Citations (99)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US51140A (en) * | 1865-11-28 | Improved cotton-bale raft | ||
US52084A (en) * | 1866-01-16 | Improved hay and cotton press | ||
US4010045A (en) * | 1973-12-13 | 1977-03-01 | Ruehrwein Robert A | Process for production of III-V compound crystals |
US4570328A (en) * | 1983-03-07 | 1986-02-18 | Motorola, Inc. | Method of producing titanium nitride MOS device gate electrode |
US4987462A (en) * | 1987-01-06 | 1991-01-22 | Texas Instruments Incorporated | Power MISFET |
US4990979A (en) * | 1988-05-13 | 1991-02-05 | Eurosil Electronic Gmbh | Non-volatile memory cell |
US4997776A (en) * | 1989-03-06 | 1991-03-05 | International Business Machines Corp. | Complementary bipolar transistor structure and method for manufacture |
US5089872A (en) * | 1990-04-27 | 1992-02-18 | North Carolina State University | Selective germanium deposition on silicon and resulting structures |
US5091767A (en) * | 1991-03-18 | 1992-02-25 | At&T Bell Laboratories | Article comprising a lattice-mismatched semiconductor heterostructure |
US5177583A (en) * | 1990-02-20 | 1993-01-05 | Kabushiki Kaisha Toshiba | Heterojunction bipolar transistor |
US5202284A (en) * | 1989-12-01 | 1993-04-13 | Hewlett-Packard Company | Selective and non-selective deposition of Si1-x Gex on a Si subsrate that is partially masked with SiO2 |
US5285086A (en) * | 1990-08-02 | 1994-02-08 | At&T Bell Laboratories | Semiconductor devices with low dislocation defects |
US5291439A (en) * | 1991-09-12 | 1994-03-01 | International Business Machines Corporation | Semiconductor memory cell and memory array with inversion layer |
US5298452A (en) * | 1986-09-12 | 1994-03-29 | International Business Machines Corporation | Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers |
US5399522A (en) * | 1993-02-16 | 1995-03-21 | Fujitsu Limited | Method of growing compound semiconductor |
US5405802A (en) * | 1992-01-31 | 1995-04-11 | Canon Kabushiki Kaisha | Process of fabricating a semiconductor substrate |
US5484664A (en) * | 1988-04-27 | 1996-01-16 | Fujitsu Limited | Hetero-epitaxially grown compound semiconductor substrate |
US5596527A (en) * | 1992-12-07 | 1997-01-21 | Nippon Steel Corporation | Electrically alterable n-bit per cell non-volatile memory with reference cells |
US5607876A (en) * | 1991-10-28 | 1997-03-04 | Xerox Corporation | Fabrication of quantum confinement semiconductor light-emitting devices |
US5617351A (en) * | 1992-03-12 | 1997-04-01 | International Business Machines Corporation | Three-dimensional direct-write EEPROM arrays and fabrication methods |
US5705421A (en) * | 1994-11-24 | 1998-01-06 | Sony Corporation | A SOI substrate fabricating method |
US5714777A (en) * | 1997-02-19 | 1998-02-03 | International Business Machines Corporation | Si/SiGe vertical junction field effect transistor |
US5728623A (en) * | 1994-03-16 | 1998-03-17 | Nec Corporation | Method of bonding a III-V group compound semiconductor layer on a silicon substrate |
US5739567A (en) * | 1992-11-02 | 1998-04-14 | Wong; Chun Chiu D. | Highly compact memory device with nonvolatile vertical transistor memory cell |
US5855693A (en) * | 1994-10-13 | 1999-01-05 | Sgs-Thomson Microelectronics S.R.L. | Wafer of semiconductor material for fabricating integrated devices, and process for its fabrication |
US5863830A (en) * | 1994-09-22 | 1999-01-26 | Commissariat A L'energie Atomique | Process for the production of a structure having a thin semiconductor film on a substrate |
US5877070A (en) * | 1997-05-31 | 1999-03-02 | Max-Planck Society | Method for the transfer of thin layers of monocrystalline material to a desirable substrate |
US5882987A (en) * | 1997-08-26 | 1999-03-16 | International Business Machines Corporation | Smart-cut process for the production of thin semiconductor material films |
US5891769A (en) * | 1997-04-07 | 1999-04-06 | Motorola, Inc. | Method for forming a semiconductor device having a heteroepitaxial layer |
US6013563A (en) * | 1997-05-12 | 2000-01-11 | Silicon Genesis Corporation | Controlled cleaning process |
US6013553A (en) * | 1997-07-24 | 2000-01-11 | Texas Instruments Incorporated | Zirconium and/or hafnium oxynitride gate dielectric |
US6013134A (en) * | 1998-02-18 | 2000-01-11 | International Business Machines Corporation | Advance integrated chemical vapor deposition (AICVD) for semiconductor devices |
US6020252A (en) * | 1996-05-15 | 2000-02-01 | Commissariat A L'energie Atomique | Method of producing a thin layer of semiconductor material |
US6033974A (en) * | 1997-05-12 | 2000-03-07 | Silicon Genesis Corporation | Method for controlled cleaving process |
US6033995A (en) * | 1997-09-16 | 2000-03-07 | Trw Inc. | Inverted layer epitaxial liftoff process |
US6184111B1 (en) * | 1998-06-23 | 2001-02-06 | Silicon Genesis Corporation | Pre-semiconductor process implant and post-process film separation |
US6190998B1 (en) * | 1996-05-15 | 2001-02-20 | Commissariat A L'energie Atomique | Method for achieving a thin film of solid material and applications of this method |
US6191007B1 (en) * | 1997-04-28 | 2001-02-20 | Denso Corporation | Method for manufacturing a semiconductor substrate |
US6191432B1 (en) * | 1996-09-02 | 2001-02-20 | Kabushiki Kaisha Toshiba | Semiconductor device and memory device |
US6194722B1 (en) * | 1997-03-28 | 2001-02-27 | Interuniversitair Micro-Elektronica Centrum, Imec, Vzw | Method of fabrication of an infrared radiation detector and infrared detector device |
US6204529B1 (en) * | 1999-08-27 | 2001-03-20 | Hsing Lan Lung | 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate |
US6207977B1 (en) * | 1995-06-16 | 2001-03-27 | Interuniversitaire Microelektronica | Vertical MISFET devices |
US6210988B1 (en) * | 1999-01-15 | 2001-04-03 | The Regents Of The University Of California | Polycrystalline silicon germanium films for forming micro-electromechanical systems |
US6218677B1 (en) * | 1994-08-15 | 2001-04-17 | Texas Instruments Incorporated | III-V nitride resonant tunneling |
US6335546B1 (en) * | 1998-07-31 | 2002-01-01 | Sharp Kabushiki Kaisha | Nitride semiconductor structure, method for producing a nitride semiconductor structure, and light emitting device |
US6339232B1 (en) * | 1999-09-20 | 2002-01-15 | Kabushika Kaisha Toshiba | Semiconductor device |
US6344417B1 (en) * | 2000-02-18 | 2002-02-05 | Silicon Wafer Technologies | Method for micro-mechanical structures |
US6346459B1 (en) * | 1999-02-05 | 2002-02-12 | Silicon Wafer Technologies, Inc. | Process for lift off and transfer of semiconductor devices onto an alien substrate |
US6350311B1 (en) * | 1999-06-17 | 2002-02-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming an epitaxial silicon-germanium layer |
US6350993B1 (en) * | 1999-03-12 | 2002-02-26 | International Business Machines Corporation | High speed composite p-channel Si/SiGe heterostructure for field effect devices |
US6352909B1 (en) * | 2000-01-06 | 2002-03-05 | Silicon Wafer Technologies, Inc. | Process for lift-off of a layer from a substrate |
US6355493B1 (en) * | 1999-07-07 | 2002-03-12 | Silicon Wafer Technologies Inc. | Method for forming IC's comprising a highly-resistive or semi-insulating semiconductor substrate having a thin, low resistance active semiconductor layer thereon |
US20020043660A1 (en) * | 2000-06-27 | 2002-04-18 | Shunpei Yamazaki | Semiconductor device and fabrication method therefor |
US20030003679A1 (en) * | 2001-06-29 | 2003-01-02 | Doyle Brian S. | Creation of high mobility channels in thin-body SOI devices |
US20030013305A1 (en) * | 2001-07-12 | 2003-01-16 | Hitachi, Ltd. | Method of producing semiconductor device and semiconductor substrate |
US20030013323A1 (en) * | 2001-06-14 | 2003-01-16 | Richard Hammond | Method of selective removal of SiGe alloys |
US6514836B2 (en) * | 2001-06-04 | 2003-02-04 | Rona Elizabeth Belford | Methods of producing strained microelectronic and/or optical integrated and discrete devices |
US6515335B1 (en) * | 2002-01-04 | 2003-02-04 | International Business Machines Corporation | Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same |
US20030027381A1 (en) * | 2001-08-01 | 2003-02-06 | Advanced Micro Devices, Inc. | XE preamorphizing implantation |
US20030025131A1 (en) * | 2001-08-06 | 2003-02-06 | Massachusetts Institute Of Technology | Formation of planar strained layers |
US6521041B2 (en) * | 1998-04-10 | 2003-02-18 | Massachusetts Institute Of Technology | Etch stop layer system |
US20030034529A1 (en) * | 2000-12-04 | 2003-02-20 | Amberwave Systems Corporation | CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
US6524935B1 (en) * | 2000-09-29 | 2003-02-25 | International Business Machines Corporation | Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique |
US6534381B2 (en) * | 1999-01-08 | 2003-03-18 | Silicon Genesis Corporation | Method for fabricating multi-layered substrates |
US6534380B1 (en) * | 1997-07-18 | 2003-03-18 | Denso Corporation | Semiconductor substrate and method of manufacturing the same |
US6537370B1 (en) * | 1998-09-10 | 2003-03-25 | FRANCE TéLéCOM | Process for obtaining a layer of single-crystal germanium on a substrate of single-crystal silicon, and products obtained |
US20030057439A1 (en) * | 2001-08-09 | 2003-03-27 | Fitzgerald Eugene A. | Dual layer CMOS devices |
US6674150B2 (en) * | 1999-06-22 | 2004-01-06 | Matsushita Electric Industrial Co., Ltd. | Heterojunction bipolar transistor and method for fabricating the same |
US20040005740A1 (en) * | 2002-06-07 | 2004-01-08 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
US6677183B2 (en) * | 2001-01-31 | 2004-01-13 | Canon Kabushiki Kaisha | Method of separation of semiconductor device |
US6677192B1 (en) * | 2001-03-02 | 2004-01-13 | Amberwave Systems Corporation | Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits |
US20040007724A1 (en) * | 2002-07-12 | 2004-01-15 | Anand Murthy | Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby |
US20040009649A1 (en) * | 2002-07-12 | 2004-01-15 | Kub Francis J. | Wafer bonding of thinned electronic materials and circuits to high performance substrates |
US20040007715A1 (en) * | 2002-07-09 | 2004-01-15 | Webb Douglas A. | Heterojunction field effect transistors using silicon-germanium and silicon-carbon alloys |
US6680240B1 (en) * | 2002-06-25 | 2004-01-20 | Advanced Micro Devices, Inc. | Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide |
US6680260B2 (en) * | 1999-08-27 | 2004-01-20 | Shin-Etsu Handotai Co., Ltd. | Method of producing a bonded wafer and the bonded wafer |
US20040012075A1 (en) * | 2002-07-16 | 2004-01-22 | International Business Machines Corporation | Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion |
US20040012037A1 (en) * | 2002-07-18 | 2004-01-22 | Motorola, Inc. | Hetero-integration of semiconductor materials on silicon |
US20040014276A1 (en) * | 2002-07-16 | 2004-01-22 | Murthy Anand S. | Method of making a semiconductor transistor |
US20040014304A1 (en) * | 2002-07-18 | 2004-01-22 | Micron Technology, Inc. | Stable PD-SOI devices and methods |
US20040018699A1 (en) * | 2002-07-24 | 2004-01-29 | International Business Machines Corporation | SOI wafers with 30-100 A buried oxide (box) created by wafer bonding using 30-100 A thin oxide as bonding layer |
US6690043B1 (en) * | 1999-11-26 | 2004-02-10 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US6689211B1 (en) * | 1999-04-09 | 2004-02-10 | Massachusetts Institute Of Technology | Etch stop layer system |
US20040031979A1 (en) * | 2002-06-07 | 2004-02-19 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
US20040031990A1 (en) * | 2002-08-16 | 2004-02-19 | Been-Yih Jin | Semiconductor on insulator apparatus and method |
US20040041210A1 (en) * | 2002-04-05 | 2004-03-04 | Chandra Mouli | Semiconductor-on-insulator constructions |
US20040041174A1 (en) * | 2002-09-02 | 2004-03-04 | Masao Okihara | Strained SOI MOSFET device and method of fabricating same |
US6703144B2 (en) * | 2000-01-20 | 2004-03-09 | Amberwave Systems Corporation | Heterointegration of materials using deposition and bonding |
US6703688B1 (en) * | 2001-03-02 | 2004-03-09 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
US6703648B1 (en) * | 2002-10-29 | 2004-03-09 | Advanced Micro Devices, Inc. | Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication |
US20040048091A1 (en) * | 2002-09-11 | 2004-03-11 | Nobuhiko Sato | Substrate and manufacturing method therefor |
US20040048454A1 (en) * | 2002-09-10 | 2004-03-11 | Kiyofumi Sakaguchi | Substrate and manufacturing method therefor |
US6706614B1 (en) * | 2001-02-28 | 2004-03-16 | Advanced Micro Devices, Inc. | Silicon-on-insulator (SOI) transistor having partial hetero source/drain junctions fabricated with high energy germanium implantation. |
US6706618B2 (en) * | 1997-08-27 | 2004-03-16 | Canon Kabushiki Kaisha | Substrate processing apparatus, substrate support apparatus, substrate processing method, and substrate fabrication method |
US6707106B1 (en) * | 2002-10-18 | 2004-03-16 | Advanced Micro Devices, Inc. | Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer |
US20040053477A1 (en) * | 2002-07-09 | 2004-03-18 | S.O.I. Tec Silicon On Insulator Technologies S.A. | Process for transferring a layer of strained semiconductor material |
US6709903B2 (en) * | 2001-06-12 | 2004-03-23 | International Business Machines Corporation | Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing |
US6709909B2 (en) * | 2000-03-17 | 2004-03-23 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US6713326B2 (en) * | 2000-08-16 | 2004-03-30 | Masachusetts Institute Of Technology | Process for producing semiconductor article using graded epitaxial growth |
Family Cites Families (121)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0656887B2 (en) | 1982-02-03 | 1994-07-27 | 株式会社日立製作所 | Semiconductor device and manufacturing method thereof |
FR2563377B1 (en) | 1984-04-19 | 1987-01-23 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING AN INSULATING LAYER BURIED IN A SEMICONDUCTOR SUBSTRATE, BY ION IMPLANTATION |
DE3542482A1 (en) | 1985-11-30 | 1987-06-04 | Licentia Gmbh | MODULATION-Doped FIELD EFFECT TRANSISTOR |
US5250445A (en) | 1988-12-20 | 1993-10-05 | Texas Instruments Incorporated | Discretionary gettering of semiconductor circuits |
US5241197A (en) | 1989-01-25 | 1993-08-31 | Hitachi, Ltd. | Transistor provided with strained germanium layer |
US5013681A (en) | 1989-09-29 | 1991-05-07 | The United States Of America As Represented By The Secretary Of The Navy | Method of producing a thin silicon-on-insulator layer |
US5316958A (en) | 1990-05-31 | 1994-05-31 | International Business Machines Corporation | Method of dopant enhancement in an epitaxial silicon layer by using germanium |
US5155571A (en) | 1990-08-06 | 1992-10-13 | The Regents Of The University Of California | Complementary field effect transistors having strained superlattice structure |
DE4101167A1 (en) | 1991-01-17 | 1992-07-23 | Daimler Benz Ag | CMOS FET circuit layout - has common gate and drain electrodes in vertical or lateral configuration |
US5240876A (en) | 1991-02-22 | 1993-08-31 | Harris Corporation | Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process |
US5221413A (en) | 1991-04-24 | 1993-06-22 | At&T Bell Laboratories | Method for making low defect density semiconductor heterostructure and devices made thereby |
US5442205A (en) | 1991-04-24 | 1995-08-15 | At&T Corp. | Semiconductor heterostructure devices with strained semiconductor layers |
CA2062134C (en) | 1991-05-31 | 1997-03-25 | Ibm | Low Defect Densiry/Arbitrary Lattice Constant Heteroepitaxial Layers |
JPH07187892A (en) | 1991-06-28 | 1995-07-25 | Internatl Business Mach Corp <Ibm> | Silicon and its formation |
US5166084A (en) | 1991-09-03 | 1992-11-24 | Motorola, Inc. | Process for fabricating a silicon on insulator field effect transistor |
FR2681472B1 (en) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | PROCESS FOR PRODUCING THIN FILMS OF SEMICONDUCTOR MATERIAL. |
US5208182A (en) | 1991-11-12 | 1993-05-04 | Kopin Corporation | Dislocation density reduction in gallium arsenide on silicon heterostructures |
US5207864A (en) | 1991-12-30 | 1993-05-04 | Bell Communications Research | Low-temperature fusion of dissimilar semiconductors |
JP3191972B2 (en) | 1992-01-31 | 2001-07-23 | キヤノン株式会社 | Method for manufacturing semiconductor substrate and semiconductor substrate |
EP0553856B1 (en) | 1992-01-31 | 2002-04-17 | Canon Kabushiki Kaisha | Method of preparing a semiconductor substrate |
US5426069A (en) | 1992-04-09 | 1995-06-20 | Dalsa Inc. | Method for making silicon-germanium devices using germanium implantation |
US5212110A (en) | 1992-05-26 | 1993-05-18 | Motorola, Inc. | Method for forming isolation regions in a semiconductor device |
US5461250A (en) | 1992-08-10 | 1995-10-24 | International Business Machines Corporation | SiGe thin film or SOI MOSFET and method for making the same |
JPH06140624A (en) | 1992-10-22 | 1994-05-20 | Furukawa Electric Co Ltd:The | Schottky junction element |
US5523243A (en) | 1992-12-21 | 1996-06-04 | International Business Machines Corporation | Method of fabricating a triple heterojunction bipolar transistor |
US5523592A (en) | 1993-02-03 | 1996-06-04 | Hitachi, Ltd. | Semiconductor optical device, manufacturing method for the same, and opto-electronic integrated circuit using the same |
US5346848A (en) | 1993-06-01 | 1994-09-13 | Motorola, Inc. | Method of bonding silicon and III-V semiconductor materials |
US5413679A (en) | 1993-06-30 | 1995-05-09 | The United States Of America As Represented By The Secretary Of The Navy | Method of producing a silicon membrane using a silicon alloy etch stop layer |
US5310451A (en) | 1993-08-19 | 1994-05-10 | International Business Machines Corporation | Method of forming an ultra-uniform silicon-on-insulator layer |
US5792679A (en) | 1993-08-30 | 1998-08-11 | Sharp Microelectronics Technology, Inc. | Method for forming silicon-germanium/Si/silicon dioxide heterostructure using germanium implant |
JPH0794420A (en) | 1993-09-20 | 1995-04-07 | Fujitsu Ltd | Manufacture of compound semiconductor crystal substrate |
US5461243A (en) * | 1993-10-29 | 1995-10-24 | International Business Machines Corporation | Substrate for tensilely strained semiconductor |
JP2980497B2 (en) | 1993-11-15 | 1999-11-22 | 株式会社東芝 | Method of manufacturing dielectric-isolated bipolar transistor |
US5534713A (en) | 1994-05-20 | 1996-07-09 | International Business Machines Corporation | Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers |
US5479033A (en) | 1994-05-27 | 1995-12-26 | Sandia Corporation | Complementary junction heterostructure field-effect transistor |
JP3361922B2 (en) | 1994-09-13 | 2003-01-07 | 株式会社東芝 | Semiconductor device |
US5561302A (en) | 1994-09-26 | 1996-10-01 | Motorola, Inc. | Enhanced mobility MOSFET device and method |
WO1996015550A1 (en) | 1994-11-10 | 1996-05-23 | Lawrence Semiconductor Research Laboratory, Inc. | Silicon-germanium-carbon compositions and processes thereof |
US5548128A (en) | 1994-12-14 | 1996-08-20 | The United States Of America As Represented By The Secretary Of The Air Force | Direct-gap germanium-tin multiple-quantum-well electro-optical devices on silicon or germanium substrates |
US5539214A (en) | 1995-02-06 | 1996-07-23 | Regents Of The University Of California | Quantum bridges fabricated by selective etching of superlattice structures |
US5777347A (en) | 1995-03-07 | 1998-07-07 | Hewlett-Packard Company | Vertical CMOS digital multi-valued restoring logic device |
JP3403877B2 (en) | 1995-10-25 | 2003-05-06 | 三菱電機株式会社 | Semiconductor memory device and manufacturing method thereof |
WO1997023000A1 (en) | 1995-12-15 | 1997-06-26 | Philips Electronics N.V. | SEMICONDUCTOR FIELD EFFECT DEVICE COMPRISING A SiGe LAYER |
FR2744285B1 (en) | 1996-01-25 | 1998-03-06 | Commissariat Energie Atomique | METHOD FOR TRANSFERRING A THIN FILM FROM AN INITIAL SUBSTRATE TO A FINAL SUBSTRATE |
US6403975B1 (en) | 1996-04-09 | 2002-06-11 | Max-Planck Gesellschaft Zur Forderung Der Wissenschafteneev | Semiconductor components, in particular photodetectors, light emitting diodes, optical modulators and waveguides with multilayer structures grown on silicon substrates |
FR2747506B1 (en) | 1996-04-11 | 1998-05-15 | Commissariat Energie Atomique | PROCESS FOR OBTAINING A THIN FILM OF SEMICONDUCTOR MATERIAL INCLUDING IN PARTICULAR ELECTRONIC COMPONENTS |
US5943560A (en) | 1996-04-19 | 1999-08-24 | National Science Council | Method to fabricate the thin film transistor |
JP3217015B2 (en) | 1996-07-18 | 2001-10-09 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Method for forming field effect transistor |
JPH1041400A (en) | 1996-07-26 | 1998-02-13 | Sony Corp | Semiconductor device and manufacture thereof |
TW335558B (en) | 1996-09-03 | 1998-07-01 | Ibm | High temperature superconductivity in strained SiSiGe |
JP3320641B2 (en) * | 1996-09-13 | 2002-09-03 | 株式会社東芝 | Memory cell |
US6399970B2 (en) | 1996-09-17 | 2002-06-04 | Matsushita Electric Industrial Co., Ltd. | FET having a Si/SiGeC heterojunction channel |
US5847419A (en) | 1996-09-17 | 1998-12-08 | Kabushiki Kaisha Toshiba | Si-SiGe semiconductor device and method of fabricating the same |
DE59707274D1 (en) | 1996-09-27 | 2002-06-20 | Infineon Technologies Ag | Integrated CMOS circuit arrangement and method for its production |
EP0845815A3 (en) | 1996-11-28 | 1999-03-03 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device, method of designing the same and semiconductor integrated circuit device |
US5808344A (en) | 1996-12-13 | 1998-09-15 | International Business Machines Corporation | Single-transistor logic and CMOS inverters |
US5786614A (en) | 1997-04-08 | 1998-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Separated floating gate for EEPROM application |
US5906951A (en) | 1997-04-30 | 1999-05-25 | International Business Machines Corporation | Strained Si/SiGe layers on insulator |
DE19720008A1 (en) | 1997-05-13 | 1998-11-19 | Siemens Ag | Integrated CMOS circuit arrangement and method for its production |
KR100400808B1 (en) | 1997-06-24 | 2003-10-08 | 매사츄세츠 인스티튜트 오브 테크놀러지 | CONTROLLING THREADING DISLOCATION DENSITIES IN Ge ON Si USING GRADED GeSi LAYERS AND PLANARIZATION |
US5936274A (en) | 1997-07-08 | 1999-08-10 | Micron Technology, Inc. | High density flash memory |
US6103599A (en) | 1997-07-25 | 2000-08-15 | Silicon Genesis Corporation | Planarizing technique for multilayered substrates |
US6160303A (en) | 1997-08-29 | 2000-12-12 | Texas Instruments Incorporated | Monolithic inductor with guard rings |
US5966622A (en) | 1997-10-08 | 1999-10-12 | Lucent Technologies Inc. | Process for bonding crystalline substrates with different crystal lattices |
US5963817A (en) | 1997-10-16 | 1999-10-05 | International Business Machines Corporation | Bulk and strained silicon on insulator using local selective oxidation |
US6232138B1 (en) | 1997-12-01 | 2001-05-15 | Massachusetts Institute Of Technology | Relaxed InxGa(1-x)as buffers |
US6154475A (en) | 1997-12-04 | 2000-11-28 | The United States Of America As Represented By The Secretary Of The Air Force | Silicon-based strain-symmetrized GE-SI quantum lasers |
JP3447939B2 (en) | 1997-12-10 | 2003-09-16 | 株式会社東芝 | Nonvolatile semiconductor memory and data reading method |
FR2773177B1 (en) | 1997-12-29 | 2000-03-17 | France Telecom | PROCESS FOR OBTAINING A SINGLE-CRYSTAL GERMANIUM OR SILICON LAYER ON A SILICON OR SINGLE-CRYSTAL GERMANIUM SUBSTRATE, RESPECTIVELY, AND MULTILAYER PRODUCTS OBTAINED |
US6153495A (en) | 1998-03-09 | 2000-11-28 | Intersil Corporation | Advanced methods for making semiconductor devices by low temperature direct bonding |
JP4258034B2 (en) | 1998-05-27 | 2009-04-30 | ソニー株式会社 | Semiconductor device and manufacturing method of semiconductor device |
US6372356B1 (en) | 1998-06-04 | 2002-04-16 | Xerox Corporation | Compliant substrates for growing lattice mismatched films |
JPH11351344A (en) | 1998-06-11 | 1999-12-24 | Nippon Seiko Kk | Toroidal continuously variable transmission |
JP3403076B2 (en) | 1998-06-30 | 2003-05-06 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
US6368733B1 (en) | 1998-08-06 | 2002-04-09 | Showa Denko K.K. | ELO semiconductor substrate |
JP2000124325A (en) | 1998-10-16 | 2000-04-28 | Nec Corp | Semiconductor device and manufacture thereof |
JP2000124092A (en) * | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | Manufacture of soi wafer by hydrogen-ion implantation stripping method and soi wafer manufactured thereby |
US6329063B2 (en) | 1998-12-11 | 2001-12-11 | Nova Crystals, Inc. | Method for producing high quality heteroepitaxial growth using stress engineering and innovative substrates |
DE19859429A1 (en) * | 1998-12-22 | 2000-06-29 | Daimler Chrysler Ag | Process for the production of epitaxial silicon germanium layers |
US6369438B1 (en) * | 1998-12-24 | 2002-04-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
US6130453A (en) | 1999-01-04 | 2000-10-10 | International Business Machines Corporation | Flash memory structure with floating gate in vertical trench |
DE60042666D1 (en) | 1999-01-14 | 2009-09-17 | Panasonic Corp | Semiconductor component and method for its production |
US6162688A (en) | 1999-01-14 | 2000-12-19 | Advanced Micro Devices, Inc. | Method of fabricating a transistor with a dielectric underlayer and device incorporating same |
US6074919A (en) | 1999-01-20 | 2000-06-13 | Advanced Micro Devices, Inc. | Method of forming an ultrathin gate dielectric |
US20010042503A1 (en) | 1999-02-10 | 2001-11-22 | Lo Yu-Hwa | Method for design of epitaxial layer and substrate structures for high-quality epitaxial growth on lattice-mismatched substrates |
US6133799A (en) | 1999-02-25 | 2000-10-17 | International Business Machines Corporation | Voltage controlled oscillator utilizing threshold voltage control of silicon on insulator MOSFETS |
JP4521542B2 (en) | 1999-03-30 | 2010-08-11 | ルネサスエレクトロニクス株式会社 | Semiconductor device and semiconductor substrate |
US6103559A (en) | 1999-03-30 | 2000-08-15 | Amd, Inc. (Advanced Micro Devices) | Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication |
US6251755B1 (en) | 1999-04-22 | 2001-06-26 | International Business Machines Corporation | High resolution dopant/impurity incorporation in semiconductors via a scanned atomic force probe |
US6151248A (en) | 1999-06-30 | 2000-11-21 | Sandisk Corporation | Dual floating gate EEPROM cell array with steering gates shared by adjacent cells |
JP2001036054A (en) * | 1999-07-19 | 2001-02-09 | Mitsubishi Electric Corp | Manufacture of soi substrate |
US6323108B1 (en) * | 1999-07-27 | 2001-11-27 | The United States Of America As Represented By The Secretary Of The Navy | Fabrication ultra-thin bonded semiconductor layers |
US6242324B1 (en) | 1999-08-10 | 2001-06-05 | The United States Of America As Represented By The Secretary Of The Navy | Method for fabricating singe crystal materials over CMOS devices |
US6235567B1 (en) | 1999-08-31 | 2001-05-22 | International Business Machines Corporation | Silicon-germanium bicmos on soi |
US6368938B1 (en) * | 1999-10-05 | 2002-04-09 | Silicon Wafer Technologies, Inc. | Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate |
US6249022B1 (en) | 1999-10-22 | 2001-06-19 | United Microelectronics Corp. | Trench flash memory with nitride spacers for electron trapping |
US6271726B1 (en) | 2000-01-10 | 2001-08-07 | Conexant Systems, Inc. | Wideband, variable gain amplifier |
WO2001054202A1 (en) | 2000-01-20 | 2001-07-26 | Amberwave Systems Corporation | Strained-silicon metal oxide semiconductor field effect transistors |
US6261929B1 (en) | 2000-02-24 | 2001-07-17 | North Carolina State University | Methods of forming a plurality of semiconductor layers using spaced trench arrays |
US6316301B1 (en) | 2000-03-08 | 2001-11-13 | Sun Microsystems, Inc. | Method for sizing PMOS pull-up devices |
JP3603747B2 (en) | 2000-05-11 | 2004-12-22 | 三菱住友シリコン株式会社 | Method for forming SiGe film, method for manufacturing heterojunction transistor, and heterojunction bipolar transistor |
US6969875B2 (en) | 2000-05-26 | 2005-11-29 | Amberwave Systems Corporation | Buried channel strained silicon FET using a supply layer created through ion implantation |
AU2001268577A1 (en) | 2000-06-22 | 2002-01-02 | Massachusetts Institute Of Technology | Etch stop layer system |
US6429061B1 (en) | 2000-07-26 | 2002-08-06 | International Business Machines Corporation | Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation |
EP1307917A2 (en) | 2000-08-07 | 2003-05-07 | Amberwave Systems Corporation | Gate technology for strained surface channel and strained buried channel mosfet devices |
US6420937B1 (en) | 2000-08-29 | 2002-07-16 | Matsushita Electric Industrial Co., Ltd. | Voltage controlled oscillator with power amplifier |
JP2002076334A (en) | 2000-08-30 | 2002-03-15 | Hitachi Ltd | Semiconductor device and manufacturing method therefor |
JP2002164520A (en) | 2000-11-27 | 2002-06-07 | Shin Etsu Handotai Co Ltd | Method for manufacturing semiconductor wafer |
US6649480B2 (en) | 2000-12-04 | 2003-11-18 | Amberwave Systems Corporation | Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
US20020125471A1 (en) | 2000-12-04 | 2002-09-12 | Fitzgerald Eugene A. | CMOS inverter circuits utilizing strained silicon surface channel MOSFETS |
US6774010B2 (en) | 2001-01-25 | 2004-08-10 | International Business Machines Corporation | Transferable device-containing layer for silicon-on-insulator applications |
US6724008B2 (en) | 2001-03-02 | 2004-04-20 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
US6723661B2 (en) * | 2001-03-02 | 2004-04-20 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
US6830976B2 (en) | 2001-03-02 | 2004-12-14 | Amberwave Systems Corproation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
US6900103B2 (en) | 2001-03-02 | 2005-05-31 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
WO2002071495A1 (en) | 2001-03-02 | 2002-09-12 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed cmos electronics and high speed analog circuits |
JP2002289533A (en) | 2001-03-26 | 2002-10-04 | Kentaro Sawano | Method for polishing surface of semiconductor, method for fabricating semiconductor device and semiconductor device |
US6603156B2 (en) | 2001-03-31 | 2003-08-05 | International Business Machines Corporation | Strained silicon on insulator structures |
US6940089B2 (en) | 2001-04-04 | 2005-09-06 | Massachusetts Institute Of Technology | Semiconductor device structure |
US6621131B2 (en) * | 2001-11-01 | 2003-09-16 | Intel Corporation | Semiconductor transistor having a stressed channel |
US6759712B2 (en) * | 2002-09-12 | 2004-07-06 | Micron Technology, Inc. | Semiconductor-on-insulator thin film transistor constructions |
-
2001
- 2001-08-10 US US09/928,126 patent/US6573126B2/en not_active Expired - Lifetime
- 2001-08-10 JP JP2002520282A patent/JP2004507084A/en active Pending
- 2001-08-10 EP EP01973651A patent/EP1309989B1/en not_active Expired - Lifetime
- 2001-08-10 DE DE60125952T patent/DE60125952T2/en not_active Expired - Lifetime
- 2001-08-10 WO PCT/US2001/041680 patent/WO2002015244A2/en active IP Right Grant
-
2003
- 2003-03-04 US US10/379,355 patent/US6713326B2/en not_active Expired - Lifetime
- 2003-03-07 US US10/384,160 patent/US6737670B2/en not_active Expired - Fee Related
-
2004
- 2004-03-17 US US10/802,186 patent/US20050009288A1/en not_active Abandoned
- 2004-03-17 US US10/802,185 patent/US6921914B2/en not_active Expired - Lifetime
-
2009
- 2009-08-20 JP JP2009190647A patent/JP2010016390A/en active Pending
Patent Citations (99)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US52084A (en) * | 1866-01-16 | Improved hay and cotton press | ||
US51140A (en) * | 1865-11-28 | Improved cotton-bale raft | ||
US4010045A (en) * | 1973-12-13 | 1977-03-01 | Ruehrwein Robert A | Process for production of III-V compound crystals |
US4570328A (en) * | 1983-03-07 | 1986-02-18 | Motorola, Inc. | Method of producing titanium nitride MOS device gate electrode |
US5298452A (en) * | 1986-09-12 | 1994-03-29 | International Business Machines Corporation | Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers |
US4987462A (en) * | 1987-01-06 | 1991-01-22 | Texas Instruments Incorporated | Power MISFET |
US5484664A (en) * | 1988-04-27 | 1996-01-16 | Fujitsu Limited | Hetero-epitaxially grown compound semiconductor substrate |
US4990979A (en) * | 1988-05-13 | 1991-02-05 | Eurosil Electronic Gmbh | Non-volatile memory cell |
US4997776A (en) * | 1989-03-06 | 1991-03-05 | International Business Machines Corp. | Complementary bipolar transistor structure and method for manufacture |
US5202284A (en) * | 1989-12-01 | 1993-04-13 | Hewlett-Packard Company | Selective and non-selective deposition of Si1-x Gex on a Si subsrate that is partially masked with SiO2 |
US5177583A (en) * | 1990-02-20 | 1993-01-05 | Kabushiki Kaisha Toshiba | Heterojunction bipolar transistor |
US5089872A (en) * | 1990-04-27 | 1992-02-18 | North Carolina State University | Selective germanium deposition on silicon and resulting structures |
US5285086A (en) * | 1990-08-02 | 1994-02-08 | At&T Bell Laboratories | Semiconductor devices with low dislocation defects |
US5091767A (en) * | 1991-03-18 | 1992-02-25 | At&T Bell Laboratories | Article comprising a lattice-mismatched semiconductor heterostructure |
US5291439A (en) * | 1991-09-12 | 1994-03-01 | International Business Machines Corporation | Semiconductor memory cell and memory array with inversion layer |
US5607876A (en) * | 1991-10-28 | 1997-03-04 | Xerox Corporation | Fabrication of quantum confinement semiconductor light-emitting devices |
US5405802A (en) * | 1992-01-31 | 1995-04-11 | Canon Kabushiki Kaisha | Process of fabricating a semiconductor substrate |
US5617351A (en) * | 1992-03-12 | 1997-04-01 | International Business Machines Corporation | Three-dimensional direct-write EEPROM arrays and fabrication methods |
US5739567A (en) * | 1992-11-02 | 1998-04-14 | Wong; Chun Chiu D. | Highly compact memory device with nonvolatile vertical transistor memory cell |
US5596527A (en) * | 1992-12-07 | 1997-01-21 | Nippon Steel Corporation | Electrically alterable n-bit per cell non-volatile memory with reference cells |
US5399522A (en) * | 1993-02-16 | 1995-03-21 | Fujitsu Limited | Method of growing compound semiconductor |
US5728623A (en) * | 1994-03-16 | 1998-03-17 | Nec Corporation | Method of bonding a III-V group compound semiconductor layer on a silicon substrate |
US6218677B1 (en) * | 1994-08-15 | 2001-04-17 | Texas Instruments Incorporated | III-V nitride resonant tunneling |
US5863830A (en) * | 1994-09-22 | 1999-01-26 | Commissariat A L'energie Atomique | Process for the production of a structure having a thin semiconductor film on a substrate |
US5855693A (en) * | 1994-10-13 | 1999-01-05 | Sgs-Thomson Microelectronics S.R.L. | Wafer of semiconductor material for fabricating integrated devices, and process for its fabrication |
US5705421A (en) * | 1994-11-24 | 1998-01-06 | Sony Corporation | A SOI substrate fabricating method |
US6207977B1 (en) * | 1995-06-16 | 2001-03-27 | Interuniversitaire Microelektronica | Vertical MISFET devices |
US6190998B1 (en) * | 1996-05-15 | 2001-02-20 | Commissariat A L'energie Atomique | Method for achieving a thin film of solid material and applications of this method |
US6020252A (en) * | 1996-05-15 | 2000-02-01 | Commissariat A L'energie Atomique | Method of producing a thin layer of semiconductor material |
US6191432B1 (en) * | 1996-09-02 | 2001-02-20 | Kabushiki Kaisha Toshiba | Semiconductor device and memory device |
US5714777A (en) * | 1997-02-19 | 1998-02-03 | International Business Machines Corporation | Si/SiGe vertical junction field effect transistor |
US6194722B1 (en) * | 1997-03-28 | 2001-02-27 | Interuniversitair Micro-Elektronica Centrum, Imec, Vzw | Method of fabrication of an infrared radiation detector and infrared detector device |
US5891769A (en) * | 1997-04-07 | 1999-04-06 | Motorola, Inc. | Method for forming a semiconductor device having a heteroepitaxial layer |
US6191007B1 (en) * | 1997-04-28 | 2001-02-20 | Denso Corporation | Method for manufacturing a semiconductor substrate |
US6033974A (en) * | 1997-05-12 | 2000-03-07 | Silicon Genesis Corporation | Method for controlled cleaving process |
US6013563A (en) * | 1997-05-12 | 2000-01-11 | Silicon Genesis Corporation | Controlled cleaning process |
US5877070A (en) * | 1997-05-31 | 1999-03-02 | Max-Planck Society | Method for the transfer of thin layers of monocrystalline material to a desirable substrate |
US6534380B1 (en) * | 1997-07-18 | 2003-03-18 | Denso Corporation | Semiconductor substrate and method of manufacturing the same |
US6013553A (en) * | 1997-07-24 | 2000-01-11 | Texas Instruments Incorporated | Zirconium and/or hafnium oxynitride gate dielectric |
US5882987A (en) * | 1997-08-26 | 1999-03-16 | International Business Machines Corporation | Smart-cut process for the production of thin semiconductor material films |
US6706618B2 (en) * | 1997-08-27 | 2004-03-16 | Canon Kabushiki Kaisha | Substrate processing apparatus, substrate support apparatus, substrate processing method, and substrate fabrication method |
US6033995A (en) * | 1997-09-16 | 2000-03-07 | Trw Inc. | Inverted layer epitaxial liftoff process |
US6013134A (en) * | 1998-02-18 | 2000-01-11 | International Business Machines Corporation | Advance integrated chemical vapor deposition (AICVD) for semiconductor devices |
US6521041B2 (en) * | 1998-04-10 | 2003-02-18 | Massachusetts Institute Of Technology | Etch stop layer system |
US6184111B1 (en) * | 1998-06-23 | 2001-02-06 | Silicon Genesis Corporation | Pre-semiconductor process implant and post-process film separation |
US6335546B1 (en) * | 1998-07-31 | 2002-01-01 | Sharp Kabushiki Kaisha | Nitride semiconductor structure, method for producing a nitride semiconductor structure, and light emitting device |
US6537370B1 (en) * | 1998-09-10 | 2003-03-25 | FRANCE TéLéCOM | Process for obtaining a layer of single-crystal germanium on a substrate of single-crystal silicon, and products obtained |
US6534381B2 (en) * | 1999-01-08 | 2003-03-18 | Silicon Genesis Corporation | Method for fabricating multi-layered substrates |
US6210988B1 (en) * | 1999-01-15 | 2001-04-03 | The Regents Of The University Of California | Polycrystalline silicon germanium films for forming micro-electromechanical systems |
US6346459B1 (en) * | 1999-02-05 | 2002-02-12 | Silicon Wafer Technologies, Inc. | Process for lift off and transfer of semiconductor devices onto an alien substrate |
US6350993B1 (en) * | 1999-03-12 | 2002-02-26 | International Business Machines Corporation | High speed composite p-channel Si/SiGe heterostructure for field effect devices |
US6689211B1 (en) * | 1999-04-09 | 2004-02-10 | Massachusetts Institute Of Technology | Etch stop layer system |
US6350311B1 (en) * | 1999-06-17 | 2002-02-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming an epitaxial silicon-germanium layer |
US6674150B2 (en) * | 1999-06-22 | 2004-01-06 | Matsushita Electric Industrial Co., Ltd. | Heterojunction bipolar transistor and method for fabricating the same |
US6355493B1 (en) * | 1999-07-07 | 2002-03-12 | Silicon Wafer Technologies Inc. | Method for forming IC's comprising a highly-resistive or semi-insulating semiconductor substrate having a thin, low resistance active semiconductor layer thereon |
US6680260B2 (en) * | 1999-08-27 | 2004-01-20 | Shin-Etsu Handotai Co., Ltd. | Method of producing a bonded wafer and the bonded wafer |
US6204529B1 (en) * | 1999-08-27 | 2001-03-20 | Hsing Lan Lung | 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate |
US6339232B1 (en) * | 1999-09-20 | 2002-01-15 | Kabushika Kaisha Toshiba | Semiconductor device |
US6690043B1 (en) * | 1999-11-26 | 2004-02-10 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US6352909B1 (en) * | 2000-01-06 | 2002-03-05 | Silicon Wafer Technologies, Inc. | Process for lift-off of a layer from a substrate |
US6703144B2 (en) * | 2000-01-20 | 2004-03-09 | Amberwave Systems Corporation | Heterointegration of materials using deposition and bonding |
US6344417B1 (en) * | 2000-02-18 | 2002-02-05 | Silicon Wafer Technologies | Method for micro-mechanical structures |
US6709909B2 (en) * | 2000-03-17 | 2004-03-23 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US20020043660A1 (en) * | 2000-06-27 | 2002-04-18 | Shunpei Yamazaki | Semiconductor device and fabrication method therefor |
US6713326B2 (en) * | 2000-08-16 | 2004-03-30 | Masachusetts Institute Of Technology | Process for producing semiconductor article using graded epitaxial growth |
US6524935B1 (en) * | 2000-09-29 | 2003-02-25 | International Business Machines Corporation | Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique |
US20030034529A1 (en) * | 2000-12-04 | 2003-02-20 | Amberwave Systems Corporation | CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
US6677183B2 (en) * | 2001-01-31 | 2004-01-13 | Canon Kabushiki Kaisha | Method of separation of semiconductor device |
US6706614B1 (en) * | 2001-02-28 | 2004-03-16 | Advanced Micro Devices, Inc. | Silicon-on-insulator (SOI) transistor having partial hetero source/drain junctions fabricated with high energy germanium implantation. |
US6677192B1 (en) * | 2001-03-02 | 2004-01-13 | Amberwave Systems Corporation | Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits |
US6703688B1 (en) * | 2001-03-02 | 2004-03-09 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
US6514836B2 (en) * | 2001-06-04 | 2003-02-04 | Rona Elizabeth Belford | Methods of producing strained microelectronic and/or optical integrated and discrete devices |
US6709903B2 (en) * | 2001-06-12 | 2004-03-23 | International Business Machines Corporation | Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing |
US20030013323A1 (en) * | 2001-06-14 | 2003-01-16 | Richard Hammond | Method of selective removal of SiGe alloys |
US20030003679A1 (en) * | 2001-06-29 | 2003-01-02 | Doyle Brian S. | Creation of high mobility channels in thin-body SOI devices |
US20030013305A1 (en) * | 2001-07-12 | 2003-01-16 | Hitachi, Ltd. | Method of producing semiconductor device and semiconductor substrate |
US20030027381A1 (en) * | 2001-08-01 | 2003-02-06 | Advanced Micro Devices, Inc. | XE preamorphizing implantation |
US20030025131A1 (en) * | 2001-08-06 | 2003-02-06 | Massachusetts Institute Of Technology | Formation of planar strained layers |
US20030057439A1 (en) * | 2001-08-09 | 2003-03-27 | Fitzgerald Eugene A. | Dual layer CMOS devices |
US6515335B1 (en) * | 2002-01-04 | 2003-02-04 | International Business Machines Corporation | Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same |
US20040041210A1 (en) * | 2002-04-05 | 2004-03-04 | Chandra Mouli | Semiconductor-on-insulator constructions |
US20040005740A1 (en) * | 2002-06-07 | 2004-01-08 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
US20040031979A1 (en) * | 2002-06-07 | 2004-02-19 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
US6680240B1 (en) * | 2002-06-25 | 2004-01-20 | Advanced Micro Devices, Inc. | Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide |
US20040007715A1 (en) * | 2002-07-09 | 2004-01-15 | Webb Douglas A. | Heterojunction field effect transistors using silicon-germanium and silicon-carbon alloys |
US20040053477A1 (en) * | 2002-07-09 | 2004-03-18 | S.O.I. Tec Silicon On Insulator Technologies S.A. | Process for transferring a layer of strained semiconductor material |
US20040009649A1 (en) * | 2002-07-12 | 2004-01-15 | Kub Francis J. | Wafer bonding of thinned electronic materials and circuits to high performance substrates |
US20040007724A1 (en) * | 2002-07-12 | 2004-01-15 | Anand Murthy | Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby |
US20040012075A1 (en) * | 2002-07-16 | 2004-01-22 | International Business Machines Corporation | Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion |
US20040014276A1 (en) * | 2002-07-16 | 2004-01-22 | Murthy Anand S. | Method of making a semiconductor transistor |
US20040014304A1 (en) * | 2002-07-18 | 2004-01-22 | Micron Technology, Inc. | Stable PD-SOI devices and methods |
US20040012037A1 (en) * | 2002-07-18 | 2004-01-22 | Motorola, Inc. | Hetero-integration of semiconductor materials on silicon |
US20040018699A1 (en) * | 2002-07-24 | 2004-01-29 | International Business Machines Corporation | SOI wafers with 30-100 A buried oxide (box) created by wafer bonding using 30-100 A thin oxide as bonding layer |
US20040031990A1 (en) * | 2002-08-16 | 2004-02-19 | Been-Yih Jin | Semiconductor on insulator apparatus and method |
US20040041174A1 (en) * | 2002-09-02 | 2004-03-04 | Masao Okihara | Strained SOI MOSFET device and method of fabricating same |
US20040048454A1 (en) * | 2002-09-10 | 2004-03-11 | Kiyofumi Sakaguchi | Substrate and manufacturing method therefor |
US20040048091A1 (en) * | 2002-09-11 | 2004-03-11 | Nobuhiko Sato | Substrate and manufacturing method therefor |
US6707106B1 (en) * | 2002-10-18 | 2004-03-16 | Advanced Micro Devices, Inc. | Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer |
US6703648B1 (en) * | 2002-10-29 | 2004-03-09 | Advanced Micro Devices, Inc. | Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication |
Cited By (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040262631A1 (en) * | 1997-06-24 | 2004-12-30 | Massachusetts Institute Of Technology | Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization |
US20030215990A1 (en) * | 2002-03-14 | 2003-11-20 | Eugene Fitzgerald | Methods for fabricating strained layers on semiconductor substrates |
US20050218453A1 (en) * | 2002-06-07 | 2005-10-06 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures with elevated source/drain regions |
US20080128751A1 (en) * | 2002-06-07 | 2008-06-05 | Amberwave Systems Corporation | Methods for forming iii-v semiconductor device structures |
US20050156246A1 (en) * | 2002-06-07 | 2005-07-21 | Amberwave Systems Corporation | Methods of forming strained-semiconductor-on-insulator device structures |
US20050199954A1 (en) * | 2002-06-07 | 2005-09-15 | Amberwave Systems Corporation | Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain |
US20050205934A1 (en) * | 2002-06-07 | 2005-09-22 | Amberwave Systems Corporation | Strained germanium-on-insulator device structures |
US20050212061A1 (en) * | 2002-06-07 | 2005-09-29 | Amberwave Systems Corporation | Methods for forming strained-semiconductor-on-insulator device structures by use of cleave planes |
US20060186510A1 (en) * | 2002-06-07 | 2006-08-24 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator bipolar device structures |
US20060197125A1 (en) * | 2002-06-07 | 2006-09-07 | Amberwave Systems Corporation | Methods for forming double gate strained-semiconductor-on-insulator device structures |
US20050280103A1 (en) * | 2002-06-07 | 2005-12-22 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator finFET device structures |
US8748292B2 (en) | 2002-06-07 | 2014-06-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming strained-semiconductor-on-insulator device structures |
US7838392B2 (en) | 2002-06-07 | 2010-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for forming III-V semiconductor device structures |
US20060197126A1 (en) * | 2002-06-07 | 2006-09-07 | Amberwave Systems Corporation | Methods for forming structures including strained-semiconductor-on-insulator devices |
US20060197123A1 (en) * | 2002-06-07 | 2006-09-07 | Amberwave Systems Corporation | Methods for forming strained-semiconductor-on-insulator bipolar device structures |
US20060088979A1 (en) * | 2003-01-29 | 2006-04-27 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same |
US7232743B2 (en) * | 2003-01-29 | 2007-06-19 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same |
US20050233548A1 (en) * | 2003-07-23 | 2005-10-20 | Kazuhisa Arai | Method for fabricating semiconductor wafer |
US7538010B2 (en) * | 2003-07-24 | 2009-05-26 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating an epitaxially grown layer |
US20090229743A1 (en) * | 2003-07-24 | 2009-09-17 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating an epitaxially grown layer |
US20060118513A1 (en) * | 2003-07-24 | 2006-06-08 | Bruce Faure | Method of fabricating an epitaxially grown layer |
US8216368B2 (en) | 2003-07-24 | 2012-07-10 | Soitec | Method of fabricating an epitaxially grown layer |
US8093138B2 (en) | 2003-07-24 | 2012-01-10 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating an epitaxially grown layer |
US20090321884A1 (en) * | 2003-07-24 | 2009-12-31 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating an epitaxially grown layer |
US20060076559A1 (en) * | 2003-07-24 | 2006-04-13 | Bruce Faure | Method of fabricating an epitaxially grown layer |
US7601217B2 (en) * | 2003-07-24 | 2009-10-13 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating an epitaxially grown layer |
US20060046488A1 (en) * | 2003-09-25 | 2006-03-02 | Ryan Lei | Germanium-on-insulator fabrication utilizing wafer bonding |
US20060049399A1 (en) * | 2003-09-25 | 2006-03-09 | Ryan Lei | Germanium-on-insulator fabrication utilizing wafer bonding |
US20050067377A1 (en) * | 2003-09-25 | 2005-03-31 | Ryan Lei | Germanium-on-insulator fabrication utilizing wafer bonding |
US20050070078A1 (en) * | 2003-09-30 | 2005-03-31 | Nicolas Daval | Indirect bonding with disappearance of bonding layer |
US7078353B2 (en) * | 2003-09-30 | 2006-07-18 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Indirect bonding with disappearance of bonding layer |
US7572331B2 (en) * | 2004-03-01 | 2009-08-11 | S.O.I.Tec Silicon On Insulator Technologies | Method of manufacturing a wafer |
US20070000435A1 (en) * | 2004-03-01 | 2007-01-04 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Method of manufacturing a wafer |
US8183627B2 (en) | 2004-12-01 | 2012-05-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid fin field-effect transistor structures and related methods |
US20060113603A1 (en) * | 2004-12-01 | 2006-06-01 | Amberwave Systems Corporation | Hybrid semiconductor-on-insulator structures and related methods |
US20060113605A1 (en) * | 2004-12-01 | 2006-06-01 | Amberwave Systems Corporation | Hybrid fin field-effect transistor structures and related methods |
US7541105B2 (en) | 2006-09-25 | 2009-06-02 | Seagate Technology Llc | Epitaxial ferroelectric and magnetic recording structures including graded lattice matching layers |
US20080075980A1 (en) * | 2006-09-25 | 2008-03-27 | Seagate Technology Llc | Epitaxial ferroelectric and magnetic recording structures including graded lattice matching layers |
US20110037075A1 (en) * | 2007-06-06 | 2011-02-17 | Chantal Arena | Process for fabricating a structure for epitaxy without an exclusion zone |
US8154022B2 (en) * | 2007-06-06 | 2012-04-10 | Soitec | Process for fabricating a structure for epitaxy without an exclusion zone |
US8841202B2 (en) * | 2009-02-27 | 2014-09-23 | Commissariat A L'energie Atomique | Method of producing a hybrid substrate by partial recrystallization of a mixed layer |
US20100221891A1 (en) * | 2009-02-27 | 2010-09-02 | Franck Fournel | Method of producing a hybrid substrate by partial recrystallization of a mixed layer |
US20120012906A1 (en) * | 2010-07-13 | 2012-01-19 | Tsinghua University | Si-Ge-Si SEMICONDUCTOR STRUCTURE HAVING DOUBLE GRADED JUNCTIONS AND METHOD FOR FORMING THE SAME |
US8889531B2 (en) * | 2010-09-21 | 2014-11-18 | Infineon Technologies Austria Ag | Semiconductor device having two monocrystalline semiconductor regions with a different lattice constant and a strained semiconductor region between |
US20120112242A1 (en) * | 2010-09-21 | 2012-05-10 | Infineon Technologies Austria Ag | Semiconductor body with strained region |
US9245943B2 (en) | 2010-09-21 | 2016-01-26 | Infineon Technologies Austria Ag | Semiconductor body with strained monocrystalline region |
US20140206178A1 (en) * | 2011-07-13 | 2014-07-24 | Yuri Georgievich Shreter | Method of Laser Separation of the Epitaxial Film or of the Epitaxial Film Layer from the Growth Substrate of the Epitaxial Semiconductor Structure (Variations) |
US9337025B2 (en) * | 2011-07-13 | 2016-05-10 | Yury Georgievich Shreter | Method of laser separation of the epitaxial film or of the epitaxial film layer from the growth substrate of the epitaxial semiconductor structure (variations) |
US20160172228A1 (en) * | 2011-07-13 | 2016-06-16 | Yury Georgievich Shreter | Method of laser separation of the epitaxial film or the epitaxial film layer from the growth substrate of the epitaxial semiconductor structure (variations) |
US9966296B2 (en) * | 2011-07-13 | 2018-05-08 | Yury Georgievich Shreter | Method of laser separation of the epitaxial film or the epitaxial film layer from the growth substrate of the epitaxial semiconductor structure (variations) |
US20170288056A1 (en) * | 2016-03-31 | 2017-10-05 | International Business Machines Corporation | Fabrication of vertical fin transistor with multiple threshold voltages |
US11018254B2 (en) * | 2016-03-31 | 2021-05-25 | International Business Machines Corporation | Fabrication of vertical fin transistor with multiple threshold voltages |
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US20030168654A1 (en) | 2003-09-11 |
US20040173791A1 (en) | 2004-09-09 |
US6921914B2 (en) | 2005-07-26 |
US20030155568A1 (en) | 2003-08-21 |
JP2004507084A (en) | 2004-03-04 |
EP1309989A2 (en) | 2003-05-14 |
JP2010016390A (en) | 2010-01-21 |
DE60125952T2 (en) | 2007-08-02 |
US6573126B2 (en) | 2003-06-03 |
US20020072130A1 (en) | 2002-06-13 |
US6737670B2 (en) | 2004-05-18 |
EP1309989B1 (en) | 2007-01-10 |
WO2002015244A2 (en) | 2002-02-21 |
DE60125952D1 (en) | 2007-02-22 |
US6713326B2 (en) | 2004-03-30 |
WO2002015244A3 (en) | 2002-10-31 |
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