US20040106287A1 - Method for making a semiconductor device having a high-k gate dielectric - Google Patents

Method for making a semiconductor device having a high-k gate dielectric Download PDF

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US20040106287A1
US20040106287A1 US10/618,226 US61822603A US2004106287A1 US 20040106287 A1 US20040106287 A1 US 20040106287A1 US 61822603 A US61822603 A US 61822603A US 2004106287 A1 US2004106287 A1 US 2004106287A1
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layer
dielectric layer
gate dielectric
oxide
titanium nitride
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Robert Chau
Reza Arghavani
Mark Doczy
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28238—Making the insulator with sacrificial oxide
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
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    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
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    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02189—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/906—Cleaning of wafer as interim step
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/974—Substrate surface preparation

Definitions

  • the present invention relates to methods for making semiconductor devices, in particular, semiconductor devices that include high-k gate dielectric layers.
  • MOS field-effect transistors with very thin gate dielectrics made from silicon dioxide may experience unacceptable gate leakage currents. Forming the gate dielectric from certain high-k dielectric materials, in place of silicon dioxide, can reduce gate leakage. Such a dielectric may not, however, be compatible with polysilicon—the preferred material for making the device's gate electrode. Placing a thin layer of titanium nitride, which is compatible with many high-k gate dielectrics, between a high-k gate dielectric and a polysilicon-based gate electrode may enable such a dielectric to be used with such a gate electrode. Unfortunately, the presence of such a layer may increase the transistor's threshold voltage, which is undesirable.
  • FIGS. 1 a - 1 d represent cross-sections of structures that may be formed when carrying out an embodiment of the method of the present invention.
  • a method for making a semiconductor device comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. That dielectric layer is modified so that it will be compatible with a gate electrode to be formed on it. A gate electrode is then formed on the dielectric layer.
  • dielectric layer 101 is formed on substrate 100 .
  • Substrate 100 may include isolation regions, p-type wells and n-type wells that have been formed in a bulk silicon or silicon-on-insulator substructure.
  • Substrate 100 may comprise other materials—which may or may not be combined with silicon—such as: germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.
  • germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide such as: germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.
  • Dielectric layer 101 comprises a material that has a dielectric constant that is greater than the dielectric constant of silicon dioxide.
  • Dielectric layer 101 preferably has a dielectric constant that is at least about twice that of silicon dioxide, i.e., a dielectric constant that is greater than about 8.
  • dielectric layer 101 When serving as the gate dielectric for the semiconductor device, dielectric layer 101 is a “high-k gate dielectric.”
  • Some of the materials that may be used to make high-k gate dielectrics include: hafnium oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. Particularly preferred are hafnium oxide, zirconium oxide, titanium oxide, and aluminum oxide.
  • that layer may be made from other materials that serve to reduce gate leakage from the level present in devices that include silicon dioxide gate dielectrics.
  • Dielectric layer 101 may be formed on substrate 100 using a conventional deposition method, e.g., a conventional chemical vapor deposition (“CVD”), low pressure CVD, or physical vapor deposition (“PVD”) process.
  • a conventional atomic layer CVD process is used.
  • a metal oxide precursor e.g., a metal chloride
  • steam may be fed at selected flow rates into a CVD reactor, which is then operated at a selected temperature and pressure to generate an atomically smooth interface between substrate 100 and dielectric layer 101 .
  • the CVD reactor should be operated long enough to form a layer with the desired thickness. In most applications, dielectric layer 101 should be less than about 100 angstroms thick, and more preferably between about 20 angstroms and about 60 angstroms thick.
  • dielectric layer 101 will include undesirable impurities, e.g., hydrogen and/or unreacted metal (represented by dots in FIG. 1 a ), which render that layer incompatible with polysilicon.
  • dielectric layer 101 is modified so that it will be compatible with a gate electrode to be formed on it.
  • FIGS. 1 a - 1 c illustrate steps that may be applied to modify dielectric layer 101 .
  • sacrificial layer 102 is formed on dielectric layer 101 to generate the structure represented by FIG. 1 a .
  • Sacrificial layer 102 preferably is made from a material that may getter impurities from dielectric layer 101 .
  • An example of a suitable material is titanium nitride.
  • Such a titanium nitride layer may be formed on dielectric layer 101 using a conventional CVD or PVD process. In a preferred embodiment, such a process is used to form a titanium nitride layer that is between about 10 angstroms and about 50 angstroms thick.
  • sacrificial layer 102 is formed on dielectric layer 101 , undesirable impurities are transported from dielectric layer 101 to sacrificial layer 102 .
  • impurities may be transported from high-k gate dielectric layer 101 to titanium nitride layer 102 by annealing titanium nitride layer 102 .
  • Titanium nitride layer 102 may be annealed using a rapid thermal anneal process or by heating that layer in a furnace at between about 500° C. and about 1,000° C. for between about 5 minutes and about 20 minutes.
  • FIG. 1 b represents a structure in which undesirable impurities, e.g., hydrogen and unreacted metal (represented by dots in FIG. 1 b ), have been transferred from high-k dielectric layer 101 into titanium nitride layer 102 .
  • FIG. 1 b is not meant to suggest that annealing titanium nitride layer 102 will cause all undesirable impurities, initially present in high-k dielectric layer 101 , to be moved into layer 102 . Rather, the annealing step is performed to cause a sufficient number of those impurities to move from high-k dielectric layer 101 into titanium nitride layer 102 to modify high-k dielectric layer 101 such that it will be compatible with a gate electrode to be formed on that layer.
  • a method that applies an annealing step which does not remove all—or even substantially all—of the undesirable impurities from high-k dielectric layer 101 , may still fall within the spirit and scope of the present invention.
  • sacrificial layer 102 is removed.
  • sacrificial layer 102 is made from titanium nitride and dielectric layer 101 comprises a high-k gate dielectric layer
  • titanium nitride layer 102 may be removed from high-k gate dielectric layer 101 using a conventional wet etch process, which uses a chemistry that is selective for titanium nitride over the material used to form the high-k gate dielectric layer.
  • a gate electrode may be formed on dielectric layer 101 .
  • the gate electrode may be formed by initially depositing polysilicon layer 103 on high-k gate dielectric layer 101 —generating the FIG. 1 c structure.
  • Polysilicon layer 103 may be deposited using conventional methods and preferably is between about 2,000 angstroms and about 4,000 angstroms thick.
  • additional steps that are generally used to complete the gate electrode e.g., forming a silicide (not shown) on the upper part of etched polysilicon structure 104 ) may be applied. As such steps are well known to those skilled in the art, they will not be described in more detail here.
  • a sacrificial titanium nitride layer may enable a high-k gate dielectric to be used with a polysilicon-based gate electrode.
  • a titanium nitride layer may be formed on a high-k gate dielectric layer, annealing and then removing that layer to remove undesirable impurities from the high-k gate dielectric, the embodiment described above enables the resulting device to benefit from the temporary presence of the titanium nitride layer without experiencing the work function shifts that permanent placement of that layer between the high-k gate dielectric and the gate electrode may cause.
  • the present invention is not limited to this particular embodiment, but instead contemplates other processes for modifying dielectric layers to ensure compatibility with gate electrodes.

Abstract

A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a gate electrode to be formed on the dielectric layer, and then a gate electrode is formed on the dielectric layer.

Description

    FIELD OF THE INVENTION
  • The present invention relates to methods for making semiconductor devices, in particular, semiconductor devices that include high-k gate dielectric layers. [0001]
    • BACKGROUND OF THE INVENTION
  • MOS field-effect transistors with very thin gate dielectrics made from silicon dioxide may experience unacceptable gate leakage currents. Forming the gate dielectric from certain high-k dielectric materials, in place of silicon dioxide, can reduce gate leakage. Such a dielectric may not, however, be compatible with polysilicon—the preferred material for making the device's gate electrode. Placing a thin layer of titanium nitride, which is compatible with many high-k gate dielectrics, between a high-k gate dielectric and a polysilicon-based gate electrode may enable such a dielectric to be used with such a gate electrode. Unfortunately, the presence of such a layer may increase the transistor's threshold voltage, which is undesirable. [0002]
  • Accordingly, there is a need for an improved process for making a semiconductor device that includes a high-k gate dielectric. There is a need for such a process in which a polysilicon-based gate electrode is formed on such a gate dielectric to create a functional device—without causing undesirable work function shifts. The method of the present invention provides such a process. [0003]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1[0004] a-1 d represent cross-sections of structures that may be formed when carrying out an embodiment of the method of the present invention.
    • DETAILED DESCRIPTION OF THE PRESENT INVENTION
  • A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. That dielectric layer is modified so that it will be compatible with a gate electrode to be formed on it. A gate electrode is then formed on the dielectric layer. In the following description, a number of details are set forth to provide a thorough understanding of the present invention. It will be apparent to those skilled in the art, however, that the invention may be practiced in many ways other than those expressly described here. The invention is thus not limited by the specific details disclosed below. [0005]
  • In an embodiment of the method of the present invention, as illustrated by FIGS. 1[0006] a-1 d, dielectric layer 101 is formed on substrate 100. Substrate 100 may include isolation regions, p-type wells and n-type wells that have been formed in a bulk silicon or silicon-on-insulator substructure. Substrate 100 may comprise other materials—which may or may not be combined with silicon—such as: germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Although several examples of materials from which substrate 100 may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present invention.
  • [0007] Dielectric layer 101 comprises a material that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. Dielectric layer 101 preferably has a dielectric constant that is at least about twice that of silicon dioxide, i.e., a dielectric constant that is greater than about 8. When serving as the gate dielectric for the semiconductor device, dielectric layer 101 is a “high-k gate dielectric.” Some of the materials that may be used to make high-k gate dielectrics include: hafnium oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. Particularly preferred are hafnium oxide, zirconium oxide, titanium oxide, and aluminum oxide. Although a few examples of materials that may be used to form dielectric layer 101 are described here, that layer may be made from other materials that serve to reduce gate leakage from the level present in devices that include silicon dioxide gate dielectrics.
  • [0008] Dielectric layer 101 may be formed on substrate 100 using a conventional deposition method, e.g., a conventional chemical vapor deposition (“CVD”), low pressure CVD, or physical vapor deposition (“PVD”) process. Preferably, a conventional atomic layer CVD process is used. In such a process, a metal oxide precursor (e.g., a metal chloride) and steam may be fed at selected flow rates into a CVD reactor, which is then operated at a selected temperature and pressure to generate an atomically smooth interface between substrate 100 and dielectric layer 101. The CVD reactor should be operated long enough to form a layer with the desired thickness. In most applications, dielectric layer 101 should be less than about 100 angstroms thick, and more preferably between about 20 angstroms and about 60 angstroms thick.
  • As deposited, [0009] dielectric layer 101 will include undesirable impurities, e.g., hydrogen and/or unreacted metal (represented by dots in FIG. 1a), which render that layer incompatible with polysilicon. In the method of the present invention, dielectric layer 101 is modified so that it will be compatible with a gate electrode to be formed on it. FIGS. 1a-1 c illustrate steps that may be applied to modify dielectric layer 101. First, sacrificial layer 102 is formed on dielectric layer 101 to generate the structure represented by FIG. 1a. Sacrificial layer 102 preferably is made from a material that may getter impurities from dielectric layer 101. An example of a suitable material is titanium nitride. Such a titanium nitride layer may be formed on dielectric layer 101 using a conventional CVD or PVD process. In a preferred embodiment, such a process is used to form a titanium nitride layer that is between about 10 angstroms and about 50 angstroms thick.
  • After [0010] sacrificial layer 102 is formed on dielectric layer 101, undesirable impurities are transported from dielectric layer 101 to sacrificial layer 102. When sacrificial layer 102 is made from titanium nitride and dielectric layer 101 comprises a high-k gate dielectric layer, impurities may be transported from high-k gate dielectric layer 101 to titanium nitride layer 102 by annealing titanium nitride layer 102. Titanium nitride layer 102 may be annealed using a rapid thermal anneal process or by heating that layer in a furnace at between about 500° C. and about 1,000° C. for between about 5 minutes and about 20 minutes.
  • FIG. 1[0011] b represents a structure in which undesirable impurities, e.g., hydrogen and unreacted metal (represented by dots in FIG. 1b), have been transferred from high-k dielectric layer 101 into titanium nitride layer 102. FIG. 1b is not meant to suggest that annealing titanium nitride layer 102 will cause all undesirable impurities, initially present in high-k dielectric layer 101, to be moved into layer 102. Rather, the annealing step is performed to cause a sufficient number of those impurities to move from high-k dielectric layer 101 into titanium nitride layer 102 to modify high-k dielectric layer 101 such that it will be compatible with a gate electrode to be formed on that layer. Thus, a method that applies an annealing step, which does not remove all—or even substantially all—of the undesirable impurities from high-k dielectric layer 101, may still fall within the spirit and scope of the present invention.
  • After the undesirable impurities have been transported from [0012] dielectric layer 101 to sacrificial layer 102, e.g., by annealing the sacrificial layer, sacrificial layer 102 is removed. When sacrificial layer 102 is made from titanium nitride and dielectric layer 101 comprises a high-k gate dielectric layer, titanium nitride layer 102 may be removed from high-k gate dielectric layer 101 using a conventional wet etch process, which uses a chemistry that is selective for titanium nitride over the material used to form the high-k gate dielectric layer.
  • Following the removal of [0013] sacrificial layer 102, a gate electrode may be formed on dielectric layer 101. In a preferred embodiment, the gate electrode may be formed by initially depositing polysilicon layer 103 on high-k gate dielectric layer 101—generating the FIG. 1c structure. Polysilicon layer 103 may be deposited using conventional methods and preferably is between about 2,000 angstroms and about 4,000 angstroms thick. After etching both layers 103 and 101 to form the FIG. 1d structure, using conventional techniques, additional steps that are generally used to complete the gate electrode (e.g., forming a silicide (not shown) on the upper part of etched polysilicon structure 104) may be applied. As such steps are well known to those skilled in the art, they will not be described in more detail here.
  • As described above, a sacrificial titanium nitride layer may enable a high-k gate dielectric to be used with a polysilicon-based gate electrode. By forming a titanium nitride layer on a high-k gate dielectric layer, annealing and then removing that layer to remove undesirable impurities from the high-k gate dielectric, the embodiment described above enables the resulting device to benefit from the temporary presence of the titanium nitride layer without experiencing the work function shifts that permanent placement of that layer between the high-k gate dielectric and the gate electrode may cause. Although the embodiment described above is an example of a process for modifying a dielectric layer to enable it to be compatible with a gate electrode, the present invention is not limited to this particular embodiment, but instead contemplates other processes for modifying dielectric layers to ensure compatibility with gate electrodes. [0014]
  • Although the foregoing description has specified certain steps and materials that may be used in the method of the present invention, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, it is intended that all such modifications, alterations, substitutions and additions be considered to fall within the spirit and scope of the invention as defined by the appended claims. [0015]

Claims (20)

What is claimed is:
1. A method for making a semiconductor device comprising:
forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide;
modifying the dielectric layer so that it will be compatible with a gate electrode to be formed on the dielectric layer; and then
forming a gate electrode on the dielectric layer.
2. The method of claim 1 wherein the dielectric layer is modified by:
forming a sacrificial layer on the dielectric layer;
transporting impurities from the dielectric layer to the sacrificial layer; then
removing the sacrificial layer.
3. The method of claim 2 wherein the dielectric layer is a high-k gate dielectric layer that has a dielectric constant that is greater than about 8.
4. The method of claim 3 wherein the high-k gate dielectric layer is formed by atomic layer chemical vapor deposition, and wherein the high-k gate dielectric layer comprises a material selected from the group consisting of hafnium oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
5. The method of claim 4 wherein the sacrificial layer comprises a titanium nitride layer.
6. The method of claim 5 wherein the titanium nitride layer is annealed to cause the impurities to be transported from the dielectric layer to the titanium nitride layer.
7. The method of claim 6 wherein the gate electrode comprises polysilicon.
8. A method for making a semiconductor device comprising:
forming a high-k gate dielectric layer on a substrate, the high-k gate dielectric layer including impurities;
forming a sacrificial layer on the high-k gate dielectric layer;
transporting the impurities from the high-k gate dielectric layer to the sacrificial layer; then removing the sacrificial layer; and
forming a layer that comprises polysilicon on the high-k gate dielectric layer.
9. The method of claim 8 wherein the sacrificial layer comprises a titanium nitride layer, and wherein the impurities are transported from the high-k gate dielectric layer to the titanium nitride layer by annealing the titanium nitride layer to getter the impurities from the high-k gate dielectric layer.
10. The method of claim 9 wherein the substrate comprises silicon.
11. The method of claim 10 wherein the high-k gate dielectric layer is formed by atomic layer chemical vapor deposition, and is between about 20 angstroms and about 60 angstroms thick.
12. The method of claim 11 wherein the high-k gate dielectric layer comprises a material selected from the group consisting of hafnium oxide, zirconium oxide, titanium oxide, and aluminum oxide.
13. The method of claim 12 wherein the titanium nitride layer is between about 10 angstroms and about 50 angstroms thick.
14. The method of claim 13 wherein the titanium nitride layer is annealed by heating that layer at between about 500° C. and about 1,000° C. for between about 5 minutes and about 20 minutes.
15. The method of claim 14 wherein the titanium nitride layer is removed using a wet etch process that is selective for titanium nitride over the material used to make the high-k dielectric layer.
16. The method of claim 15 wherein the layer that comprises polysilicon is between about 2,000 angstroms and about 4,000 angstroms thick.
17. A method for making a semiconductor device comprising:
forming a high-k gate dielectric layer on a substrate, the high-k gate dielectric layer being less than about 100 angstroms thick and comprising a material selected from the group consisting of hafnium oxide, zirconium oxide, titanium oxide, and aluminum oxide;
forming a titanium nitride layer that is between about 10 angstroms and about 50 angstroms thick on the high-k gate dielectric layer;
annealing the titanium nitride layer at a temperature of between about 500° C. and about 1,000° C. for between about 5 minutes and about 20 minutes; then removing the titanium nitride layer;
forming a layer that comprises polysilicon on the high-k gate dielectric layer; and
etching the polysilicon containing layer and the high-k gate dielectric layer.
18. The method of claim 17 wherein the high-k gate dielectric layer is formed by atomic layer chemical vapor deposition and is between about 20 angstroms and about 60 angstroms thick.
19. The method of claim 18 wherein the titanium nitride layer is removed using a wet etch process that is selective for titanium nitride over the material used to make the high-k dielectric layer.
20. The method of claim 19 wherein the layer that comprises polysilicon is between about 2,000 angstroms and about 4,000 angstroms thick.
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US20060017112A1 (en) * 2004-07-21 2006-01-26 Chih-Hao Wang Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof
US7279756B2 (en) 2004-07-21 2007-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof
US7235847B2 (en) 2004-09-17 2007-06-26 Freescale Semiconductor, Inc. Semiconductor device having a gate with a thin conductive layer
US20070218640A1 (en) * 2004-09-17 2007-09-20 Freescale Semiconductor, Inc. Semiconductor device having a gate with a thin conductive layer
US20070187725A1 (en) * 2004-12-23 2007-08-16 Chih-Hao Wang Method and apparatus for a semiconductor device with a high-k gate dielectric
US7332407B2 (en) 2004-12-23 2008-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for a semiconductor device with a high-k gate dielectric
US20070176227A1 (en) * 2006-01-30 2007-08-02 Chun-Li Liu MOS device with nano-crystal gate structure
US7700438B2 (en) 2006-01-30 2010-04-20 Freescale Semiconductor, Inc. MOS device with nano-crystal gate structure
US20100155825A1 (en) * 2006-01-30 2010-06-24 Freescale Semiconductor, Inc. Transistor devices with nano-crystal gate structures
US7928502B2 (en) 2006-01-30 2011-04-19 Freescale Semiconductor, Inc. Transistor devices with nano-crystal gate structures
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US20030162377A1 (en) 2003-08-28

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