US20040021164A1

US20040021164A1 - DRAM semiconductor device and method for fabricating the same

Info

Publication number: US20040021164A1
Application number: US10/336,525
Authority: US
Inventors: Chul-Sung Kim; Byeong-Chan Lee; Jong-ryeol Yoo; Si-Young Choi; Deok-Hyung Lee
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2002-08-02
Filing date: 2003-01-03
Publication date: 2004-02-05
Also published as: KR100475084B1; KR20040012350A; US20070178642A1; US7579249B2

Abstract

Provided are a DRAM semiconductor device and a method for fabricating the DRAM semiconductor device. The method provides forming a silicon epitaxial layer on a source/drain region of a cell region and a peripheral circuit region using selective epitaxial growth (SEG), thereby forming a raised active region. In addition, in the DRAM semiconductor device, a metal silicide layer and a metal pad are formed on the silicon epitaxial layer in the source/drain region of the cell region. By doing this, the DRAM device is capable of forming a source/drain region as a shallow junction region, reducing the occurrence of leakage current and lowering the contact resistance with the source/drain region.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method for fabricating the same, and more particular to, a Dynamic RAM (DRAM) semiconductor device and a method for fabricating the same.

2. Description of the Related Art

In general, as the integration concentration of DRAM semiconductor devices increases, it is desirable to form source/drain regions as shallow junction regions so as to ensure stability of a transistor. Also, it is required to form contacts having low resistance to source/drain regions in order to achieve high-speed operation of the transistor.

First, a conventional method for fabricating a DRAM semiconductor device having source/drain regions formed as shallow junction regions and low-resistance contacts will be described.

FIGS. 1 through 3 are views for explaining a method for fabricating a DRAM semiconductor device according to the conventional art. More specifically, FIGS. 1 through 3 are views of cell regions of the DRAM semiconductor device.

Referring to FIG. 1, a gate stack pattern 18 on a semiconductor substrate 10 in which a Trench Isolation Region (TIR) and a Active Region (AR) has been determined is formed. A silicon substrate is used for the semiconductor substrate 10. The gate stack pattern 18 is formed by sequentially stacking a gate electrode constructed with a gate dielectric film (not shown), a poly-silicon film 12 and a metal silicide film 14, and a capping film 16. The gate stack pattern 18 functions as a word line.

Next, an n− source/

drain region

20 is formed in the AR of the semiconductor substrate 10 to be aligned with the gate stack pattern 18. The n− source/drain region 20 is formed as a shallow junction region by ion implantation with a shallow implantation depth and a low concentration of impurities by using n-type dopants such as phosphorus (P) or arsenic (As), if the semiconductor substrate 10 is a p-type silicon substrate.

After the formation of the n− source/

drain region

20, a gate spacer 22 is formed on both sidewalls of the gate stack pattern 18. Then an interlayer dielectric film 24 is formed on the semiconductor substrate 10 so as to insulate the gate stack pattern.

Referring to FIG. 2, the interlayer

dielectric film

24 is patterned by photolithography. Then an interlayer dielectric film pattern 24 a having a contact hole 26 exposing the n− source/drain region 20 is formed.

Referring to FIG. 3, a

barrier film

28 formed of Ti/TiN is formed on the wall of the contact hole 26. Then, pads 30 a and 30 b of a tungsten film are formed on the barrier film 28. The pad 30 a is connected to a storage electrode during a subsequent process and the pad 30 b is connected to a bit line during the subsequent process. After that, a DRAM semiconductor device is completed through a general processes such as a bit line forming process and a capacitor forming process or the like.

As described above, in a conventional method for fabricating a DRAM semiconductor device, a titanium silicide film is formed by a reaction of the n− source/drain region with the Ti film constituting the barrier film during a thermal process after the barrier film forming process. The Ti silicide film penetrates into the n− source/drain region so that the n− source/drain region is not able to become a shallow junction region and leakage current is increased during operation of the DRAM semiconductor device.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a DRAM semiconductor device having a source/drain region as a shallow junction region and a contact having a low resistance.

It is another object of the present invention to provide a method for fabricating the DRAM semiconductor device.

In one aspect, the present invention provides a DRAM semiconductor device comprising a gate stack pattern formed on a semiconductor substrate, a source/drain region which is aligned with both sidewalls of the gate stack pattern and formed on the semiconductor substrate, a gate spacer formed on both sidewalls of the gate stack pattern, a silicon epitaxial layer formed on the source/drain region on both sides of the gate spacer, a metal silicide layer formed on the silicon epitaxial layer and a metal pad formed on the metal silicide layer.

Preferably, the source/drain region is an n− source/drain region.

In another aspect, the present invention provides a DRAM semiconductor device comprising a gate stack pattern formed on a cell region and a peripheral circuit region of a semiconductor substrate, a n− source/drain region which is aligned with both sidewalls of the gate stack pattern of the cell region and formed on the semiconductor substrate, a n+ source/drain region and a p+ source/drain region which is aligned with both sidewalls of the gate stack pattern of the peripheral circuit region and formed on the semiconductor substrate, a gate spacer formed on both sidewalls of the gate stack pattern of the cell region and the peripheral circuit region, a silicon epitaxial layer formed on the n− source/drain region, the n+ source/drain region and the p+ source/drain region of a lower portion of both sides of the gate spacer, a metal silicide layer formed on the silicon epitaxial layer of the cell region and the peripheral circuit region, a metal pad formed on the metal silicide layer of the cell region and a metal plug formed on the metal suicide layer of the peripheral circuit region.

Preferably, the metal pad is level with equivalent to or higher than the gate stack pattern. The metal silicide layer is one of a cobalt silicide layer, a titanium silicide layer and a nickel silicide layer. The metal pad and the metal plug are constructed with a tungsten film.

In another aspect, the present invention provides a method for fabricating a DRAM semiconductor device comprising forming a gate stack pattern on a semiconductor substrate, forming a source/drain region on the semiconductor substrate, which is aligned with both sidewalls of the gate stack pattern, forming a silicon epitaxial layer on the source/drain region of both sidewalls of the gate spacer, forming a metal silicide layer on the silicon epitaxial layer and forming a metal pad on the metal silicide layer.

In another aspect, the present invention provides a method for fabricating a DRAM semiconductor device comprising forming a gate stack pattern on a cell region and a peripheral circuit region of a semiconductor substrate, forming a n− source/drain region on the semiconductor substrate of the cell region, to be aligned with both sidewalls of the gate stack pattern of the cell region, and forming a n+ source/drain region and a p+ source/drain region on the semiconductor substrate of the peripheral circuit region, forming a gate spacer on both sidewalls of the gate stack pattern of the cell region and the peripheral circuit region, forming a silicon epitaxial layer on the n− source/drain region, the n+ source/drain region and the p+ source/drain region of a lower portion of both sides of the gate spacer, forming a metal silicide layer on the silicon epitaxial layer of the cell region and the peripheral circuit region, forming a metal pad on the metal silicide layer of the cell region and forming a metal plug on the metal silicide layer of the peripheral circuit region.

Preferably, the metal pad is level with or higher than the gate stack pattern. The metal silicide layer is one of a cobalt silicide layer, a titanium silicide layer and a nickel silicide layer. Preferably, the metal pad and the metal plug are a tungsten film. The source/drain regions are the n− source/drain regions. The silicon epitaxial layer is formed by using selective epitaxial growth.

The DRAM semiconductor device according to the present invention has a raised active region formed on the source/drain region of a cell region and a peripheral circuit region so that the source/drain region can be formed as a shallow junction region and the occurrence of leakage current can be reduced.

In addition to the foregoing, in the DRAM semiconductor device of the present invention, a metal silicide layer and a metal pad are formed on a silicon epitaxial layer in the source/drain region of the cell region and the peripheral circuit region, thereby reducing a contact resistance.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which: [0024]
FIGS. 1 through 3 are views for explaining a conventional method for fabricating a DRAM semiconductor device; and [0025]
FIGS. 4A through 4F and [0026] 5A through 5F are views for explaining a DRAM semiconductor device and a method of fabricating the DRAM semiconductor device according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention now will be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. [0027]
FIGS. 4F and 5F are sectional views of a cell region and a peripheral circuit region of the DRAM semiconductor device according to the present invention. [0028]
Specifically, an n-MOS (Metal Oxide Semiconductor) transistor is formed in the cell region of the DRAM semiconductor device as shown in FIG. 4F. As shown in FIG. 5F, in the other regions excluding the cell region, i.e., the peripheral circuit region of the DRAM semiconductor device. An n-MOS transistor and p-MOS transistor are formed. However, either n-MOS transistors or p-MOS transistors may be formed in the peripheral circuit region of the DRAM semiconductor device, if necessary. [0029]
More specifically, the DRAM semiconductor device according to the present invention includes a [0030] semiconductor substrate 100 having an Active Region (AR) and a Trench Isolation Region (TIR). The semiconductor substrate 100 is a p-type silicon substrate. The TIR is constructed of a trench by etching the semiconductor substrate 100 and a buried oxide film.
A [0031] gate stack pattern 108 is formed on the semiconductor substrate 100 having the AR and the TIR. The gate stack pattern 108 is constructed with a gate dielectric film (not shown), gate electrodes 102 and 104 and a capping film 106. The gate dielectric film is constructed with an oxide film. The gate electrodes 102 and 104 are constructed with a poly-silicon film 102 and a tungsten suicide film 104. The capping film 106 is a nitride film.
As shown in FIG. 4F, on the AR of the cell region of the [0032] semiconductor substrate 100 of the cell region, an n− source/drain region 110 aligned with the gate stack pattern 108 is formed. The n− source/drain region 110 of the cell region is constructed as a shallow junction region. As shown in FIG. 5F, n+ source/drain region 112 and p+ source/drain region 114 aligned with the gate stack pattern 108 on the active region (AR) of the semiconductor substrate 100 of the peripheral circuit region are formed.
A [0033] gate spacer 116 is formed on both sidewalls of the gate stack pattern 108 of the cell region and the peripheral circuit region. The gate spacer 116 is constructed with the nitride film. A silicon epitaxial layer 118 is selectively formed on the n− source/drain region 110, the n+ source/drain region 112 and the p+ source/drain region 114 at both sides of the gate spacer 116 of the cell region and the peripheral circuit region, so as to construct a raised active region.
The [0034] silicon epitaxial layer 118 makes it possible to form a shallow junction and reduces the occurrence of leakage current by preventing damage to the n− source/drain region 110 in a subsequent thermal process. The silicon epitaxial layer 118 of the cell region and the peripheral circuit region prevents the metal silicide layer from penetrating into the n− source/drain region 110, the n+ source/drain region 112 and the p+ source/drain region 114 in a subsequent thermal process, thereby reducing the occurrence of leakage current.
A [0035] metal silicide layer 120 is formed on the silicon epitaxial layer 118 of the cell region and the peripheral circuit region. The metal silicide layer 120 may be a cobalt silicide layer, a titanium silicide layer or a nickel silicide layer. The metal silicide layer 120 lowers a contact resistance when a bit line, a storage electrode of a capacitor and a wiring layer are connected to the n− source/drain region, the n+ source/drain region and the p+ source/drain region, respectively, during a subsequent process.
[0036] Barrier films 124 and 130 formed of a Ti/TiN film are formed on the metal silicide layer 120 of the cell region and the peripheral circuit region, respectively. The metal pads 126 a and 126 b are formed on the barrier film 124 of the cell region. A metal plug 132 is formed on the barrier film 130 of the peripheral circuit region. The metal pad 126 a is connected to the storage electrode of the capacitor. The metal pad 126 b is connected to the bit line. The metal pads 126 a and 126 b and the metal plug 132 are level with or higher than the gate stack pattern 108. The metal pads 126 a and 126 b and the metal plug 132 are constructed with the tungsten film. The metal pads 126 a and 126 b and the metal plug 132 lower a contact resistance when a bit line, a storage electrode of a capacitor and a wiring layer are connected to the n− source/drain region, the n+ source/drain region and the p+ source/drain region, respectively, during a subsequent process. The reference numerals 128 and 128 a of FIGS. 4F and 5F denote an interlayer dielectric film.
Hereinafter, a method for fabricating a DRAM semiconductor device according to the present invention will be described. [0037]
FIGS. 4A through 4F and [0038] 5A through 5F are sectional views for explaining a method of fabricating a DRAM semiconductor device according to the present invention. FIGS. 4A through 4F are views of a method for fabricating a cell region of a DRAM semiconductor device according to the present invention. FIGS. 5A through 5F are views of a method for manufacturing of a peripheral circuit region of a DRAM semiconductor device according to the present invention.
Referring to FIGS. 4A and 5A, the [0039] gate stack pattern 108 is formed on the semiconductor substrate 100 having the AR and the TIR. The silicon substrate is used as the semiconductor substrate 100. The gate stack pattern 108 is constructed with the gate dielectric film (not shown), the gate electrodes 102 and 104 and the capping film 106. The gate dielectric film is an oxide film. The gate electrodes 102 and 104 are formed of a poly-silicon film and a tungsten silicide film. The capping film 106 is an nitride film.
Next, the n− source/[0040] drain region 110 aligned with the gate stack pattern 108 is formed on the AR of the cell region of the semiconductor substrate 100 of the cell region as shown in FIG. 4A. The n− source/drain region 110 is formed as a shallow junction region by an ion implantation with a shallow implantation depth and a low concentration of impurities by using n-type dopants such as phosphorus (P) or arsenic (As), if the semiconductor substrate 100 is a p-type silicon substrate. A concentration of the dopants in the n− source/drain region 110 is adjusted to 1E18/cm³-1E20/cm³.
After that, the n+ source/[0041] drain region 112 and the p+ source/drain region 114 aligned with the gate stack pattern 108 are formed on the active region (AR) of the semiconductor substrate 100 of the peripheral circuit region as shown in FIG. 5A. The n+ source/drain region 112 is formed with n-type dopants such as phosphorus (P) or arsenic (As) if the semiconductor substrate 10 is a p-type silicon substrate. A concentration of the dopants in the n− source/drain region 110 is adjusted to 1E20/cm³-1E22/cm³. The p+ source/drain region 114 is formed by the p-type dopants such as boron if the semiconductor substrate 10 is a p-type silicon substrate. A concentration of the dopants in the p+ source/drain region 114 is adjusted to 1E20/cm³-1E22/cm³.
Then, a [0042] gate spacer 116 is formed on both sidewalls of the gate stack pattern 108 of the cell region and the peripheral circuit region. The gate spacer 116 is formed by forming a nitride film on the whole surface of the semiconductor substrate 100 in which the gate stack pattern 108 is formed, and anisotropically etching the nitride film 100.
Referring FIGS. 4B and 5B, the [0043] silicon epitaxial layer 118 is selectively formed on the n− source/drain region 110 of the cell region, the n+ source/drain region 112 and the p+ source/drain region 114 of the peripheral circuit region by Selective Epitaxial Growth (SEG), so as to construct a raised active region. The silicon epitaxial layer 118 of the cell region makes it possible to form a shallow junction and reduce the occurrence of leakage current by preventing damage to the n− source/drain region 110 in a subsequent thermal process. The silicon epitaxial layer 118 of the cell region and the peripheral circuit region prevents the metal silicide layer from penetrating into the n− source/drain region 110, the n+ source/drain region 112 and the p+ source/drain region 114 in the subsequent thermal process, thereby reducing the occurrence of leakage current.
Referring FIGS. 4C and 5C, the [0044] metal silicide layer 120 is formed on the silicon epitaxial layer 118 of the cell region and the peripheral circuit region. The metal silicide layer 120 may be a cobalt silicide layer, a titanium silicide layer or a nickel silicide layer. The metal silicide layer 120 lowers a contact resistance when the bit line and the storage electrode of the capacitor are connected to the n− source/drain region 110, the n+ source/drain region 112 and the p+ source/drain region 114 in a subsequent process.
The [0045] metal silicide layer 120 is formed by a self-aligned silicide process. In other words, the metal silicide layer 120 is constructed by forming a metal layer on the whole surface of the semiconductor substrate 100 in which the cell region and the peripheral circuit region are formed, applying a thermal process and then a silicidation process. In the silicidation process, the silicon epitaxial layer 118 functions as a protection layer to prevent damage to the n− source/drain region 110, the n+ source/drain region 112 and the p+ source/drain region 114.
Referring to FIGS. 4D and 5D, a first [0046] interlayer dielectric film 122 is formed on the whole surface of the cell region and the peripheral circuit region of the semiconductor substrate in which the gate stack pattern 108 and the metal silicide layer 120 are respectively formed. Then, as illustrated in FIG. 4D, the interlayer dielectric film 122 of the cell region is patterned by photolithography to form the interlayer dielectric film 122 a, which has a contact hole 123 exposing the metal silicide layer 120 of the cell region.
Referring to FIGS. 4E and 5E, a [0047] barrier film 124 formed of Ti/TiN is formed on the whole surface of the cell region and the peripheral circuit region of the semiconductor substrate 100. Then, a metal layer, e.g., a tungsten film, is formed on the whole surface of the cell region of the semiconductor substrate 100 to fill the contact hole 123 and the peripheral circuit region, and metal pads 126 a and 126 b are formed by planarizing the semiconductor substrate 100. A chemical mechanical polishing method or an etch back method is used for the planarization. When performing the planarization, a surface of an upper portion of the gate stack pattern 108 can be used for an etching stop point. The metal pads 126 a and 126 b are level with or higher than the gate stack pattern 108.
The [0048] metal pads 126 a and 126 b lower the contact resistance when the n− source/drain region 110 is connected to the bit line or the storage electrode. The metal pad 126 a is connected to the storage electrode in a subsequent process. The metal pad 126 b is connected to the bit line in the subsequent process.
Referring to FIGS. 4F and 5F, a second [0049] interlayer dielectric film 128 is formed on the whole surface of the semiconductor substrate 100 of the cell region and the peripheral circuit region. Then, the second interlayer dielectric film 128 is patterned to form a second interlayer dielectric film pattern 128 a to expose the metal silicide layer 120 of the peripheral circuit region. After that, a barrier layer 130, e.g., Ti/TiN film, a metal layer, e.g., a tungsten film, are formed on the whole surface of the semiconductor substrate 100 and the metal layer is planarized to from a metal plug 132. When performing the planarization, a surface of an upper portion of the gate stack pattern 108 can be used for an etching rest point. The metal plug 132 is level with the gate stack pattern 108. The metal plug 132 lowers the contact resistance when the n+ source/drain region 112 and the p+ source/drain region 114 are connected to a wiring layer in a subsequent process. After that, the second interlayer dielectric film 128 of the cell region is patterned and, eventually, a DRAM semiconductor device is completed through general processes such as a bit line forming process and a capacitor forming process or the like, in which the metal pads 126 a and 126 b are connected to a bit line or a storage electrode of a capacitor.
As can be seen from the above, the silicon epitaxial layer is formed on a cell region and a source/drain region of a peripheral circuit region using SEG, so as to construct a raised active region. By doing this, it is possible to form a source/drain region as a shallow junction region in a cell region and to reduce the occurrence of leakage current by preventing a metal silicide layer from penetrating into the source/drain region in the cell region and the peripheral circuit region in a subsequent process. [0050]
In the DRAM semiconductor device according to the present invention, a metal silicide layer and a metal pad are formed on a silicon epitaxial layer on the source/drain region of the cell region, and therefore, it is possible to lower a contact resistance between the source/drain region and the bit line or the storage electrode. [0051]
In addition to the foregoing, in the DRAM semiconductor device of the present invention, a metal suicide layer and a metal plug are formed on a silicon epitaxial layer in the source/drain region of the cell region and the peripheral circuit region thereby reducing the contact resistance between the source/drain region and a wiring layer. [0052]
While this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. [0053]

Claims

What is claimed is:

1. A DRAM semiconductor device comprising:

a gate stack pattern formed on a semiconductor substrate:

a source/drain region which is aligned with both sidewalls of the gate stack pattern and formed on the semiconductor substrate;

a gate spacer formed on both sidewalls of the gate stack pattern;

a silicon epitaxial layer formed on the source/drain region on both sides of the gate spacer;

a metal silicide layer formed on the silicon epitaxial layer; and

a metal pad formed on the metal silicide layer.

2. The DRAM semiconductor device of claim 1, wherein the metal pad is level with or higher than the gate stack pattern.

3. The DRAM semiconductor device of claim 1, wherein the metal silicide layer is one of a cobalt silicide layer, a titanium silicide layer and a nickel silicide layer.

4. The DRAM semiconductor device of claim 1, wherein the metal pad is constructed with a tungsten film.

5. The DRAM semiconductor device of claim 1, wherein the source/drain region is an n− source/drain region.

6. A DRAM semiconductor device comprising:

a gate stack pattern formed on a cell region and a peripheral circuit region of a semiconductor substrate;

a n− source/drain region which is aligned with both sidewalls of the gate stack pattern of the cell region and formed on the semiconductor substrate;

a n+ source/drain region and a p+ source/drain region which is aligned with both sidewalls of the gate stack pattern of the peripheral circuit region and formed on the semiconductor substrate;

a gate spacer formed on both sidewalls of the gate stack pattern of the cell region and the peripheral circuit region;

a silicon epitaxial layer formed on the n− source/drain region, the n+ source/drain region and the p+ source/drain region of a lower portion of both sides of the gate spacer;

a metal suicide layer formed on the silicon epitaxial layer of the cell region and the peripheral circuit region;

a metal pad formed on the metal silicide layer of the cell region; and

a metal plug formed on the metal silicide layer of the peripheral circuit region.

7. The DRAM semiconductor device of claim 6, wherein the metal pad is level with equivalent to or higher than the gate stack pattern.

8. The DRAM semiconductor device of claim 6, wherein the metal silicide layer is one of a cobalt silicide layer, a titanium silicide layer and a nickel silicide layer.

9. The DRAM semiconductor device of claim 6, wherein the metal pad and the metal plug are constructed with a tungsten film.

10. A method for fabricating a DRAM semiconductor device, the method comprising:

forming a gate stack pattern on a semiconductor substrate;

forming a source/drain region on the semiconductor substrate, which is aligned with both sidewalls of the gate stack pattern;

forming a silicon epitaxial layer on the source/drain region of both sidewalls of the gate spacer;

forming a metal silicide layer on the silicon epitaxial layer; and

forming a metal pad on the metal silicide layer.

11. The method of claim 10, wherein the metal pad is level with or higher than the gate stack pattern.

12. The method of claim 10, wherein the metal silicide layer is one of a cobalt silicide layer, a titanium silicide layer and a nickel silicide layer.

13. The method of claim 10, wherein the metal pad and the metal plug are constructed with a tungsten film.

14. The method of claim 10, wherein the source/drain region is an n− source/drain region.

15. The method of claim 10, the silicon epitaxial layer is formed by using selective epitaxial growth.

16. A method for fabricating a DRAM semiconductor device, the method comprising:

forming a gate stack pattern on a cell region and a peripheral circuit region of a semiconductor substrate;

forming a n− source/drain region on the semiconductor substrate of the cell region, to be aligned with both sidewalls of the gate stack pattern of the cell region, and forming a n+ source/drain region and a p+ source/drain region on the semiconductor substrate of the peripheral circuit region;

forming a gate spacer on both sidewalls of the gate stack pattern of the cell region and the peripheral circuit region;

forming a silicon epitaxial layer on the n− source/drain region, the n+ source/drain region and the p+ source/drain region of a lower portion of both sides of the gate spacer;

forming a metal silicide layer on the silicon epitaxial layer of the cell region and the peripheral circuit region;

forming a metal pad on the metal silicide layer of the cell region; and

forming a metal plug on the metal silicide layer of the peripheral circuit region.

17. The method of claim 16, wherein the metal pad is level with or higher than the gate stack pattern.

18. The method of claim 16, wherein the metal silicide layer is one of a cobalt silicide layer, a titanium silicide layer and a nickel silicide layer.

19. The method of claim 16, wherein the metal pad and the metal plug are a tungsten film.

20. The method of claim 16, the silicon epitaxial layer is formed by using selective epitaxial growth.