US20030168719A1 - Multi-row leadframe - Google Patents
Multi-row leadframe Download PDFInfo
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- US20030168719A1 US20030168719A1 US10/092,683 US9268302A US2003168719A1 US 20030168719 A1 US20030168719 A1 US 20030168719A1 US 9268302 A US9268302 A US 9268302A US 2003168719 A1 US2003168719 A1 US 2003168719A1
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- terminals
- row
- leadframe
- paddle ring
- paddle
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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Definitions
- FIG. 3 is an enlarged top plan view of the leadframe of FIG. 2;
- FIG. 10 is an enlarged perspective view of the leadframe 62 and the die 70 .
- the leadframe 62 has a first row of terminals 80 and a second row of terminals 82 . Each of the rows of terminals 80 , 82 is connected to pads on the die 70 with wires 84 .
- the leadframe 62 also includes a paddle ring 86 . Prior to singulation, the terminals of the first row of terminals 80 are individually connected to the paddle ring 86 .
- each of the terminals of the second row of terminals 82 is connected to one of the connection bars. For instance, the terminals of the second row of terminals on one side of the die 70 are connected to the connection bar 78 .
- a die 30 is placed in the cavity 28 and on a flag member 46 if the leadframe includes a flag member 46 .
- the die 30 is electrically connected to the leadframe terminals 32 , 34 using a wirebonding process.
- a mold compound 40 is formed over the die 30 and leadframe.
- singulation operations are performed to separate and expose the leadframe terminals 32 , 34 .
Abstract
Description
- The present invention relates to integrated circuits and packaged integrated circuits and, more particularly, to a leadframe for packaged integrated circuits.
- An integrated circuit (IC) die is a small device formed on a semiconductor wafer, such as a silicon wafer. Such a die is typically cut from the wafer and attached to a substrate or base carrier for interconnect redistribution. Bond pads on the die are then electrically connected to the leads on a carrier via wire bonding. The die and wire bonds are encapsulated with a protective material such that a package is formed. The leads encapsulated in the package are redistributed in a network of conductors within the carrier and end in an array of terminal points outside the package. Depending on the package type, these terminal points may be used as-is, such as in a Thin Small Outline Package (TSOP), or further processed, such as by attaching spherical solder balls for a Ball Grid Array (BGA). The terminal points allow the die to be electrically connected with other circuits, such as on a printed circuit board.
- A leadframe is a metal frame, usually copper or nickel alloy, that supports the IC and provides external electrical connections for the packaged chip. A leadframe usually includes a die paddle and lead fingers.
- Referring now to FIG. 1, an enlarged perspective view of a conventional packaged
device 10 is shown. Thedevice 10 includes an integrated circuit or die 12 attached to adie paddle 14 with an adhesive material (not shown). The die 12 is electrically connected to a plurality oflead fingers 16. More particularly, one end of eachlead finger 16 is connected to a bond pad on the die 12 by wire bonds. The other end of eachlead finger 16 is the lead, which allows thedevice 10 to be connected to a substrate or circuit board. Thecircuit 12,paddle 14, and part of thelead fingers 16 are encapsulated, such as with a moldedplastic 18. - The number of input and output (I/O) pins of the packaged
device 10 is limited by I/O pitch and package body size. However, as circuit density increases, it is desirable to provide more I/O pins, but in the same or smaller size package. - The foregoing summary, as well as the following detailed description of preferred embodiments of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there is shown in the drawings embodiments that are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown. In the drawings:
- FIG. 1 is an enlarged perspective view of a conventional packaged semiconductor device;
- FIG. 2 is an enlarged perspective view of a leadframe in accordance with a first embodiment of the present invention;
- FIG. 3 is an enlarged top plan view of the leadframe of FIG. 2;
- FIG. 4 is an enlarged perspective view of a packaged semiconductor device including the leadframe of FIG. 2;
- FIG. 5 is an enlarged perspective view of a bottom side of a packaged semiconductor device in accordance with an embodiment of the present invention;
- FIG. 6 is an enlarged, isometric cross-sectional view taken along line6-6 of the packaged semiconductor device of FIG. 4;
- FIG. 7 is an enlarged, isometric cross-sectional view of a packaged semiconductor device in accordance with a second embodiment of the present invention;
- FIG. 8 is an enlarged perspective view of a bottom side of the packaged semiconductor device of FIG. 7;
- FIG. 9 is an enlarged top plan view of parts of four semiconductor devices connected to a leadframe panel of the present invention prior to singulation; and
- FIG. 10 is an enlarged perspective view of one of the semiconductor devices of FIG. 9 connected to a leadframe of the leadframe panel of FIG. 9.
- The detailed description set forth below in connection with the appended drawings is intended as a description of the presently preferred embodiments of the invention, and is not intended to represent the only forms in which the present invention may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the invention. As will be understood by those of skill in the art, the present invention can be applied to various packages and package types.
- Certain features in the drawings have been enlarged for ease of illustration and the drawings and the elements thereof are not necessarily in proper proportion. Further, the invention is shown embodied in a quad flat no-lead (QFN) type package. However, those of ordinary skill in the art will readily understand the details of the invention and that the invention is applicable to other package types. In the drawings, like numerals are used to indicate like elements throughout.
- In order to provide an integrated circuit device with increased I/O pins, the present invention is a leadframe for a semiconductor device. The leadframe includes a paddle ring having an inner perimeter, an outer perimeter, and a cavity located within the inner perimeter for receiving an integrated circuit die. A first row of terminals generally surrounds the paddle ring outer perimter and a second row of terminals surrounds the first row of terminals. Thus, the leadframe has multiple rows of terminals.
- The present invention also provides a novel semiconductor device including a paddle ring having an inner perimeter, an outer perimeter, and a cavity located within the inner perimeter. A first row of terminals generally surrounds the paddle ring outer perimeter and a second row of terminals surrounds the first row of terminals. An integrated circuit die is located within the cavity and surrounded by the paddle ring. The die includes a plurality of die pads that are electrically connected to respective ones of the terminals of the first and second rows of terminals.
- The present invention further comprises a method of packaging a semiconductor device comprising the steps of:
- forming a leadframe having a paddle ring including an inner perimeter, an outer perimeter and a cavity located within the inner perimeter, a first row of terminals surrounding the paddle ring and individually connected thereto, and a second row of terminals surrounding the first row of terminals, wherein the terminals of the second row of terminals are connected to a connection bar and the connection bar is connected to at least one of the terminals of the first row of terminals or the paddle ring;
- placing an integrated circuit die within the cavity;
- electrically connecting die pads of the integrated circuit die to the terminals of the first and second rows of terminals;
- performing a first singulation operation that separates the terminals of the first row from the paddle ring; and
- performing a second singulation operation that separates the terminals of the second row from the connection bar and separates the connection bar from the connected one of the at least one of the terminals of the first row of terminals and the paddle ring.
- Referring now to FIGS. 2 and 3, a
leadframe 20 in accordance with the present invention is shown. Theleadframe 20 includes apaddle ring 22 having aninner perimeter 24, anouter perimeter 26, and acavity 28 located within theinner perimeter 24. Thecavity 28 is sized and shaped for receiving an integrated circuit die 30 (FIG. 4). Thepaddle ring 22 is generally square shaped, although it could have other shapes depending on the shape of the integratedcircuit die 30. - The
integrated circuit die 30 may be of a type known to those of skill in the art, such as a circuit formed on and cut from a silicon wafer. Thecavity 28 of thepaddle ring 22 is sized and shaped to receive thedie 30. Typical die sizes may range from 4 mm×4 mm to 12 mm×12 mm. The die 30 may have a thickness ranging from about 6 mils to about 21 mils. - The
leadframe 20 also includes a first row ofterminals 32 generally surrounding theouter perimeter 26 of thepaddle ring 22 and a second row ofterminals 34 surrounding the first row ofterminals 32. In FIG. 3, portions of the first and second rows ofterminals terminals paddle ring 22. - In the presently preferred embodiment, the
inner perimeter 24 of thepaddle ring 22 includes a plurality of first spacedprojections 36 that extend from thepaddle ring 22 inwardly. Similarly, theouter perimeter 26 of thepaddle ring 22 includes a plurality of second spaced projections 38 that extend outwardly or towards the first and second rows ofterminals projections 36, 38 increase the mechanical locking between theleadframe 20 and molding compound 40 (FIG. 4). However, it is not a requirement that thepaddle ring 22 have either or both of the spacedprojections 36, 38, and in some designs, thepaddle ring 22 may have only one of the spacedprojections 36, 38. - Referring now to FIG. 4, a chip scale package (CSP) type
plastic IC package 42 is shown. Thepackage 42 includes thepaddle ring 22, the IC die 30, the first and second rows ofterminals mold compound 40, andbond wires 44. Thepaddle ring 22 includes the first and second spaced projections to enhance securing the die and leadframe to themold compound 40. In this example, thepaddle ring 22 is used as a ground and the first and second rows ofterminals paddle member 22, and the remaining die pads are wirebonded to the first and second rows ofterminals package 42 achieves a higher I/O density than similar prior art packages. - Referring now to FIG. 5, a bottom perspective view of an embodiment of a
QFN package 45 is shown. Thepackage 45 has two rows ofterminals paddle member 22 and themold compound 40. In this embodiment, thepaddle member 22 includes aflag member 46 located within thecavity 28. The IC die 30 is attached to theflag member 46 in a known manner, such as with an adhesive material layer or an adhesive tape. Theflag member 46 may be at the same height or planar with thepaddle ring 22 or, as shown in the drawing, the flag member may be stepped down or recessed. It is noted that in this embodiment, thepaddle ring 22 of thepackage 45 only has spaced projections that project inwardly, and does not include outward spaced projections. However, as discussed above, thepackage 45 could be designed to have just outward spaced projections, both outward and inward spaced projections, or no projections at all. - Referring now to FIG. 6, which is side cross-sectional view of the
package 42 of FIG. 4, theflag member 46 is more readily visible. As can be seen, theflag member 46 is integral with thepaddle ring 22. It is also preferred that all of the terminals in the first and second rows ofterminals terminals 34 are exposed at the outer edge of thepackage 42. In order to expose the terminals of the first row ofterminals 32, a groove orchannel 48 is formed in thepackage 42 between thepaddle member 22 and the first row ofterminals 32. Thegroove 48 preferably is formed by a singulation process. That is, thegroove 48 is formed by a depth controlled cut with a saw, such as a saw used for cutting dice from a wafer. The singulation separates the first row ofterminals 32 from thepaddle ring 22 and exposes one vertical side of the first row ofterminals 32 for solder fillet formation. - As can be seen in FIG. 6, the
package 42 is an exposed paddle type package. In exposed paddle (EP) type packages, at least one side of a metal die pad (i.e., the flag member 46) is exposed. - Referring now to FIGS. 7 and 8, a chip scale package (CSP)
type IC package 50 in accordance with a second embodiment of the present invention is shown. Thepackage 50 includes thepaddle member 22, the IC die 30, the first and second rows ofterminals mold compound 40, andbond wires 44. Thepaddle member 22 includes the first and second spaced projections to enhance securing the die and leadframe to themold compound 40. However, as can be seen in FIG. 7, thepackage 50 does not include a flag member, but only thepaddle ring 22. - Referring now to FIG. 9, a top plan view of a portion of a
leadframe panel 60 in accordance with the present invention is shown. More particularly, FIG. 9 shows the intersection of four separate leadframes 62-68 electrically connected to respective die 70-76 with wirebonds, prior to the leadframes and die being separated and packaged. The leadframes 62-68 are interconnected with unit-to-unit connection bars 78 and 79, and the individual terminals of the second row of terminals extend in opposite directions from the connection bars 78 and 79. That is, each of the terminals of the second row of terminals for one of the leadframes is connected to one side of aconnection bar - For example, FIG. 10 is an enlarged perspective view of the
leadframe 62 and thedie 70. Theleadframe 62 has a first row ofterminals 80 and a second row ofterminals 82. Each of the rows ofterminals wires 84. Theleadframe 62 also includes apaddle ring 86. Prior to singulation, the terminals of the first row ofterminals 80 are individually connected to thepaddle ring 86. On the other hand, each of the terminals of the second row ofterminals 82 is connected to one of the connection bars. For instance, the terminals of the second row of terminals on one side of the die 70 are connected to theconnection bar 78. - Referring again to FIG. 9, the connection bars78 and 79 intersect at a point between the four die 70-76. The first (inner) rows of terminals are attached to the connection bars 78, 79 in a manner such as that shown in the drawing. The
leadframe panel 60 is preferably formed from a sheet of conductive metal having a good thermal conductivity, such as copper. Theleadframe panel 60 may be formed by a stamping method, however, for more complex and higher density leadframes, a chemical etching method is preferred. As is understood by those of skill in the art, the etching method uses an artwork mask to define the detailed pattern of the leadframe and then the unmasked portion of the metal is etched away. A plating mask is used to mask out no-plating zones, if any, and then the unmasked portions are plated with metal layers with a plating process. Rinsing and cleaning steps are performed between processes. Such masking, etching, plating, rinsing and cleaning processes are well known to those of skill in the art. - In order to form separate devices, it is preferred to use two saw singulation operations, such as are used to separate dice from a wafer. A first singulation operation in which the depth of the cut is controlled is performed to separate the terminals of the first row from the paddle ring. Then, a second singulation operation is performed to separate the terminals of the second row from the connection bars, which also separates the neighboring devices from each other. The second singulation operation also separates the connection bar from the terminals of the first row of terminals near the intersection of the two connection bars.
- To briefly summarize one method of forming a packaged device, a
die 30 is placed in thecavity 28 and on aflag member 46 if the leadframe includes aflag member 46. Next, thedie 30 is electrically connected to theleadframe terminals mold compound 40 is formed over thedie 30 and leadframe. Finally, singulation operations are performed to separate and expose theleadframe terminals - The description of the preferred embodiments of the present invention have been presented for purposes of illustration and description, but are not intended to be exhaustive or to limit the invention to the forms disclosed. It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. For example, a leadframe having more than two rows of terminals could be formed. In addition, the die and paddle sizes may vary to accommodate the required package design. Further, although the leadframe panel shown in FIG. 9 has the first (inner) row of terminals each individually connected to the paddle ring and the second (outer) row of terminals connected to a connection bar, other ways of making a leadframe having rows of terminals can be made, such as having both the first and second rows of terminals connected to a connection bar and then to the paddle ring only at the corners of the paddle ring. It is understood, therefore, that this invention is not limited to the particular embodiments disclosed, but covers modifications within the spirit and scope of the present invention as defined by the appended claims.
Claims (22)
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/092,683 US6838751B2 (en) | 2002-03-06 | 2002-03-06 | Multi-row leadframe |
JP2003575421A JP2005519485A (en) | 2002-03-06 | 2003-02-19 | Multi-row lead frame |
PCT/US2003/005220 WO2003077315A2 (en) | 2002-03-06 | 2003-02-19 | Multi-row leadframe |
KR1020047013939A KR100930841B1 (en) | 2002-03-06 | 2003-02-19 | Multi-column leadframe |
AU2003213173A AU2003213173A1 (en) | 2002-03-06 | 2003-02-19 | Multi-row leadframe |
CNB038052695A CN100350601C (en) | 2002-03-06 | 2003-02-19 | Multi-row leadframe |
EP03709219A EP1481422A2 (en) | 2002-03-06 | 2003-02-19 | Multi-row leadframe |
TW092104231A TWI237878B (en) | 2002-03-06 | 2003-02-27 | Multi-row leadframe |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/092,683 US6838751B2 (en) | 2002-03-06 | 2002-03-06 | Multi-row leadframe |
Publications (2)
Publication Number | Publication Date |
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US20030168719A1 true US20030168719A1 (en) | 2003-09-11 |
US6838751B2 US6838751B2 (en) | 2005-01-04 |
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Application Number | Title | Priority Date | Filing Date |
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US10/092,683 Expired - Lifetime US6838751B2 (en) | 2002-03-06 | 2002-03-06 | Multi-row leadframe |
Country Status (8)
Country | Link |
---|---|
US (1) | US6838751B2 (en) |
EP (1) | EP1481422A2 (en) |
JP (1) | JP2005519485A (en) |
KR (1) | KR100930841B1 (en) |
CN (1) | CN100350601C (en) |
AU (1) | AU2003213173A1 (en) |
TW (1) | TWI237878B (en) |
WO (1) | WO2003077315A2 (en) |
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Also Published As
Publication number | Publication date |
---|---|
US6838751B2 (en) | 2005-01-04 |
TW200305980A (en) | 2003-11-01 |
KR100930841B1 (en) | 2009-12-10 |
CN1639864A (en) | 2005-07-13 |
TWI237878B (en) | 2005-08-11 |
WO2003077315A3 (en) | 2004-01-08 |
AU2003213173A1 (en) | 2003-09-22 |
CN100350601C (en) | 2007-11-21 |
KR20040097152A (en) | 2004-11-17 |
EP1481422A2 (en) | 2004-12-01 |
WO2003077315A2 (en) | 2003-09-18 |
JP2005519485A (en) | 2005-06-30 |
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