US20030052377A1 - Method of composite gate formation - Google Patents

Method of composite gate formation Download PDF

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US20030052377A1
US20030052377A1 US10/236,841 US23684102A US2003052377A1 US 20030052377 A1 US20030052377 A1 US 20030052377A1 US 23684102 A US23684102 A US 23684102A US 2003052377 A1 US2003052377 A1 US 2003052377A1
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silicon
layer
containing species
exposing
nitrogen
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US10/236,841
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Ronald Weimer
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Micron Technology Inc
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Micron Technology Inc
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Priority to US10/236,841 priority Critical patent/US20030052377A1/en
Publication of US20030052377A1 publication Critical patent/US20030052377A1/en
Priority to US10/931,840 priority patent/US7247920B2/en
Priority to US11/513,659 priority patent/US20060289950A1/en
Priority to US11/513,658 priority patent/US7576398B2/en
Priority to US11/513,663 priority patent/US7323755B2/en
Priority to US11/513,880 priority patent/US7323756B2/en
Abandoned legal-status Critical Current

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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    • H01L21/28229—Making the insulator by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction

Definitions

  • Metal-insulator-silicon (MIS) transistors including metal-oxide-silicon (MOS) transistors, are comprised of doped source and drain regions formed in the surface of a semiconductor substrate, a channel region between the source and drain, and a gate electrode situated over the channel region.
  • the gate electrode is physically and electrically separated from the channel by a thin gate dielectric (oxide) layer, typically silicon dioxide.
  • the gate electrode typically comprises a doped polysilicon material. Diffusion of dopants such as boron from the doped polysilicon gate through the gate oxide layer into the underlying silicon substrate poses serious problems in processing and the functioning of the device.
  • nitrogen has been incorporated into the gate oxide layer.
  • One conventional method of incorporating nitrogen into the oxide layer is by anneal of the oxide layer in nitric oxide (NO), nitrous oxide (N 2 O), ammonia (NH 3 ) or other nitrogen-containing species.
  • thermal nitridation of the gate oxide layer results in nitrogen incorporation at the silicon/oxide interface, which increases the ability of the gate oxide layer to suppress boron penetration but can result in transconductance loss.
  • the invention provides methods for forming a gate electrode.
  • the method comprises exposing a gate oxide (dielectric) layer disposed on a silicon substrate to a silicon-containing species at a low partial pressure of about 10 ⁇ 2 Torr or less to deposit a layer of about 10 to about 20 angstroms silicon; and exposing the silicon layer to a nitrogen-containing species to form a silicon nitride barrier layer.
  • the silicon layer can be thermally annealed in a nitrogen-containing species, preferably at a temperature of about 700° C. to about 900° C.
  • the silicon layer can be exposed to a plasma source of nitrogen.
  • the method can further comprise forming a conductive polysilicon layer comprising a boron dopant over the nitride barrier layer, and additional layers as desired including, for example, a metal silicide layer such as tungsten silicide (WSi X ), a barrier layer such as titanium nitride (TiN), a conductive metal layer such as tungsten (W), and an insulative nitride cap.
  • a metal silicide layer such as tungsten silicide (WSi X )
  • TiN titanium nitride
  • W tungsten
  • insulative nitride cap an insulative nitride cap.
  • FIGS. 2 - 4 are views of the wafer fragment of FIG. 1 at subsequent and sequential processing steps, showing fabrication of a nitride barrier layer in a stacked gate electrode according to an embodiment of the method of the invention.
  • the terms “semiconductive wafer fragment” or “wafer fragment” or “wafer” will be understood to mean any construction comprising semiconductor material, including but not limited to bulk semiconductive materials such as a semiconductor wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials).
  • substrate refers to any supporting structure including, but not limited to, the semiconductive wafer fragments or wafers described above.
  • the gate electrode generally comprises a stack of materials including a gate oxide (dielectric), a conductively doped polysilicon, and can further include a metal silicide layer, a barrier layer, a conductive layer, and an insulative cap.
  • the nitridation of the silicon layer 18 takes place under conditions that are optimal for nitridation of silicon.
  • An example and preferred rapid thermal nitridization includes exposing the silicon layer to ammonia (NH 3 ) or other nitrogen-containing ambient at a temperature of about 700° C. to about 900° C., a pressure of about 1 to about 760 Torr, with a flow rate of about 1100 sccm to about 10,000 sccm, for a duration of about 1 second to about 180 minutes.
  • the partial pressure of the nitrogen-containing ambient can range from a low partial pressure, for example, of about 1 to about 10 Torr, up to full atmospheric pressure to optimize processing as desired.

Abstract

Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing silicon onto an oxide substrate as a thin layer, and then thermally annealing the silicon layer in a nitrogen-containing species or exposing the silicon to a plasma source of nitrogen to nitridize the silicon layer.

Description

    FIELD OF THE INVENTION
  • The present invention relates generally to semiconductor fabrication and, more particularly, to methods of forming nitride barrier layers used in semiconductor devices. [0001]
    • BACKGROUND OF THE INVENTION
  • Metal-insulator-silicon (MIS) transistors, including metal-oxide-silicon (MOS) transistors, are comprised of doped source and drain regions formed in the surface of a semiconductor substrate, a channel region between the source and drain, and a gate electrode situated over the channel region. The gate electrode is physically and electrically separated from the channel by a thin gate dielectric (oxide) layer, typically silicon dioxide. The gate electrode typically comprises a doped polysilicon material. Diffusion of dopants such as boron from the doped polysilicon gate through the gate oxide layer into the underlying silicon substrate poses serious problems in processing and the functioning of the device. [0002]
  • To inhibit boron diffusion, nitrogen has been incorporated into the gate oxide layer. One conventional method of incorporating nitrogen into the oxide layer is by anneal of the oxide layer in nitric oxide (NO), nitrous oxide (N[0003] 2O), ammonia (NH3) or other nitrogen-containing species. However, thermal nitridation of the gate oxide layer results in nitrogen incorporation at the silicon/oxide interface, which increases the ability of the gate oxide layer to suppress boron penetration but can result in transconductance loss.
  • Another method of forming a nitrided gate oxide layer is by remote plasma nitridation by exposing the surface of the oxide layer to a plasma generated species of nitrogen. This results in the polysilicon/oxide interface being nitridized as opposed to the gate oxide/silicon interface, thus avoiding transconductance loss. However, data indicates that the plasma nitridation may not be scaleable below 25 angstroms for integrated circuit (IC) devices with high processing thermal budgets such as DRAMS or flash devices due to the loss of integrity of the gate oxide as well as the loss of transconductance due to the proximity of nitrogen to the gate oxide-silicon interface. [0004]
  • Another conventional method to incorporate nitrogen into the gate oxide layer is to form a composite gate dielectric layer comprising a silicon nitride layer and an oxide layer. An issue with forming such a composite gate oxide is that the interface between the silicon nitride and oxide layers typically requires rigorous post-treatment processing to eliminate potential sources of charge trapping. In addition, composite gate dielectrics that comprise nitride and thermal oxides have limitations due to the total effective oxide thickness that can be achieved due to poor nucleation of nitride on oxide. This requires the formation of a relatively thick nitride layer resulting in an overall effective oxide thickness that is higher than that which is considered as usable. [0005]
  • Thus, a need exists for a nitride barrier layer that avoids such problems. [0006]
    • SUMMARY OF THE INVENTION
  • The present invention provides methods for forming a nitride barrier film layer useful in fabrication of semiconductor devices such as gate structures. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. [0007]
  • In one aspect, the invention provides methods for forming a nitride barrier layer over a dielectric (oxide) substrate. The dielectric layer is exposing to a silicon-containing species under low partial pressure, high vacuum to nucleate the surface of the dielectric layer and deposit a thin layer of silicon, which is then exposed to a nitrogen-containing species to nitridize the silicon and form a silicon nitride barrier layer. The silicon-containing species can be deposited, for example, by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, among other processes. The silicon layer can comprise polysilicon or amorphous silicon. In an embodiment of the method, an oxide layer is irradiated with a silicon-containing species at a low partial pressure of about 10[0008] −2 Torr (10 mTorr) or less to selectively deposit a thin layer of silicon onto the oxide surface, preferably about 10 to about 20 angstroms thick. The silicon layer can then be thermally annealed in a nitrogen-containing species at a preferred temperature of about 700° C. to about 900° C., or exposed to a plasma source of nitrogen to nitridize the silicon. The plasma nitrogen can be produced, for example, by a downstream microwave system, an electron cyclotron residence system, an inductive coupled plasma system, a radio frequency (RF) system, among others.
  • In another aspect, the invention provides methods for forming a semiconductor device. In one embodiment, the method comprises exposing a dielectric layer disposed on a silicon substrate to a silicon-containing species under a low partial pressure of about 10[0009] −2 Torr or less, and a flow rate of less than 100 sccm to deposit a layer of about 10 to about 20 angstroms silicon; and exposing the silicon layer to a nitrogen-containing species to nitridize the silicon and form a silicon nitride barrier layer. The silicon layer can be thermally annealed in a nitrogen-containing species, preferably at a temperature of about 700° C. to about 900° C., or exposed to a plasma source of a nitrogen-containing species.
  • In another aspect, the invention provides methods for forming a gate electrode. In one embodiment, the method comprises exposing a gate oxide (dielectric) layer disposed on a silicon substrate to a silicon-containing species at a low partial pressure of about 10[0010] −2 Torr or less to deposit a layer of about 10 to about 20 angstroms silicon; and exposing the silicon layer to a nitrogen-containing species to form a silicon nitride barrier layer. In one embodiment, the silicon layer can be thermally annealed in a nitrogen-containing species, preferably at a temperature of about 700° C. to about 900° C. In another embodiment, the silicon layer can be exposed to a plasma source of nitrogen. The method can further comprise forming a conductive polysilicon layer comprising a boron dopant over the nitride barrier layer, and additional layers as desired including, for example, a metal silicide layer such as tungsten silicide (WSiX), a barrier layer such as titanium nitride (TiN), a conductive metal layer such as tungsten (W), and an insulative nitride cap. The nitride barrier layer inhibits passage of boron from the conductive polysilicon layer into the gate oxide layer.
  • In another aspect, the invention provides a nitride barrier layer. The barrier layer comprises a nitridized silicon layer of about 10 to about 20 angstroms formed on an oxide layer by irradiating the oxide layer with a silicon-containing species under a low partial pressure of about 10[0011] −2 Torr or less, and nitridizing the silicon layer to silicon nitride by exposure to a nitrogen-containing species. In one embodiment, the nitride barrier layer comprises thermally annealed nitridized silicon having a thickness of about 10 to about 20 angstroms, and disposed adjacent an oxide layer. In another embodiment, the nitride barrier layer comprises a plasma nitrogen annealed silicon layer.
  • In yet another aspect, the invention provides a semiconductor device. The device comprises a semiconductor substrate comprising silicon, an oxide layer disposed adjacent to the semiconductor substrate, and a diffusion barrier layer of about 10 to about 20 angstroms disposed adjacent the oxide layer and comprising a nitridized silicon layer formed by irradiating an oxide layer with a silicon-containing species under low partial pressure of about 10[0012] −2 Torr or less, and nitridizing the silicon to silicon nitride by exposure to a nitrogen-containing species. In one embodiment, the semiconductor device comprises a diffusion barrier layer comprising a thin layer of nitrogen annealed silicon, the silicon being thermally annealed or plasma annealed in a nitrogen-containing species.
  • In a further aspect, the invention provides a gate electrode. The gate electrode comprises a gate oxide layer disposed adjacent to a semiconductor substrate, typically silicon, and a diffusion barrier layer disposed adjacent the gate oxide layer; the diffusion barrier layer having a thickness of about 10 to about 20 angstroms and comprising a nitridized silicon layer formed by irradiating the gate oxide layer with a silicon-containing species under low partial pressure (about 10[0013] −2 Torr or less), and nitridizing the silicon to silicon nitride by exposure to a nitrogen-containing species. In one embodiment, the diffusion barrier layer of the gate electrode comprises silicon thermally annealed in a nitrogen-containing species. In another embodiment, the gate electrode comprises a diffusion barrier comprising a plasma nitrogen annealed silicon.
  • The invention advantageously provides an improved interface between a silicon nitride barrier layer and an underlying dielectric (oxide) layer, having less traps and requiring less post treatment (e.g., oxidation) of the gate dielectric. In addition, the invention achieves a relatively thin nitride layer thus decreasing the effective oxide thickness as compared to conventionally used methods.[0014]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Preferred embodiments of the invention are described below with reference to the following accompanying drawings, which are for illustrative purposes only. Throughout the following views, the reference numerals will be used in the drawings, and the same reference numerals will be used throughout the several views and in the description to indicate same or like parts. [0015]
  • FIG. 1 is a diagrammatic cross-sectional view of a semiconductor wafer fragment at a preliminary step of a processing sequence. [0016]
  • FIGS. [0017] 2-4 are views of the wafer fragment of FIG. 1 at subsequent and sequential processing steps, showing fabrication of a nitride barrier layer in a stacked gate electrode according to an embodiment of the method of the invention.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The invention will be described generally with reference to the drawings for the purpose of illustrating the present preferred embodiments only and not for purposes of limiting the same. The figures illustrate processing steps for use in the fabrication of semiconductor devices in accordance with the present invention. It should be readily apparent that the processing steps are only a portion of the entire fabrication process. [0018]
  • In the current application, the terms “semiconductive wafer fragment” or “wafer fragment” or “wafer” will be understood to mean any construction comprising semiconductor material, including but not limited to bulk semiconductive materials such as a semiconductor wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure including, but not limited to, the semiconductive wafer fragments or wafers described above. [0019]
  • An embodiment of a method of the present invention is described with reference to FIGS. [0020] 1-4, in a method of forming a gate electrode in a stacked configuration. The gate electrode generally comprises a stack of materials including a gate oxide (dielectric), a conductively doped polysilicon, and can further include a metal silicide layer, a barrier layer, a conductive layer, and an insulative cap.
  • While the concepts of the invention are conducive to the fabrication of gate electrodes, the concepts described herein can be applied to other semiconductor devices that would likewise benefit from the fabrication of a nitride barrier film as described herein. Therefore, the depiction of the invention in reference to the manufacture of a stacked gate configuration is not meant to limit the extent to which one skilled in the art might apply the concepts taught herein. [0021]
  • Referring to FIG. 1, a portion of a [0022] semiconductor wafer 10 is shown at a preliminary processing step. The wafer fragment 10 in progress can comprise a semiconductor wafer substrate or the wafer along with various process layers formed thereon, including one or more semiconductor layers or other formations, and active or operable portions of semiconductor devices.
  • The [0023] wafer fragment 10 is shown as comprising a semiconductor substrate 12, an exemplary substrate being a bulk substrate material of semiconductive or semiconductor material, for example, monocrystalline silicon. The substrate 12 is provided with isolation regions 14 formed therein, for example, shallow trench isolation regions. A gate oxide (dielectric) layer 16 overlies the substrate 12. The gate oxide layer 16 can comprise, for example, silicon dioxide (SiO2), tantalum pentoxide (Ta2O5), hafnium dioxide (HfO2), and aluminum trioxide (Al2O3), among others. The gate oxide layer 16 can be formed by conventional methods, and is typically an oxide layer grown directly on the base silicon substrate material 12, but can also be a deposited layer.
  • According to the invention, the [0024] gate oxide layer 14 is irradiated with a silicon-containing species under low partial pressure, high vacuum conditions to deposit (nucleate) a thin layer 18 of silicon onto the surface 16 of the gate oxide layer 14, as shown in FIG. 2. The silicon layer can comprise polysilicon or amorphous silicon. The processing conditions results in a silicon layer 18 that is thinner than can be achieved under standard silicon growth conditions, i.e., a temperature greater than 600° C., and a pressure greater than 100 mTorr, with SiH2, Si2H7, or dichlorosilane (DCS, SiH2Cl2). Preferably, the silicon layer 18 is less than about 30 angstroms, preferably about 10 to about 20 angstroms thick. Exemplary silicon source materials include SiH2Cl2, silicon tetrachloride (SiCl4), and a silicon that contains a hydride such as silane (SiH4), and disilane (Si2H6). The silicon material can be deposited as a layer utilizing any known deposition process including plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), and rapid thermal chemical vapor deposition (RTCVD).
  • Preferably, the silicon material is deposited using a thermal deposition process. Processing conditions include a low partial pressure of about 10[0025] −2 Torr or less, preferably about 10−2 to about 10−7 Torr, preferably about 10−3 to about 10−5 Torr, a temperature of about 500° C. to about 700° C., with a flow rate of the silicon-containing species of less than 100 sccm, preferably about 1 sccm to about 50 sccm, for a duration of about 1 second to about 5 minutes.
  • Referring to FIG. 3, the [0026] silicon layer 18 is then nitridized to convert the silicon to silicon nitride (SiNX) 20 by exposure to a nitrogen-containing gas using conventional methods. Such conventional methods include a rapid thermal nitridization (RTN), and plasma nitridization, among others. Examples of nitrogen-containing gases for use in such methods include nitrogen (N2), ammonia (NH3), nitrogen trifluoride (NF3), nitrogen oxides (NOX), and an N2/He mixture in plasma. The use of a plasma source of nitrogen-containing gas is preferred.
  • The nitridation of the [0027] silicon layer 18 takes place under conditions that are optimal for nitridation of silicon. An example and preferred rapid thermal nitridization includes exposing the silicon layer to ammonia (NH3) or other nitrogen-containing ambient at a temperature of about 700° C. to about 900° C., a pressure of about 1 to about 760 Torr, with a flow rate of about 1100 sccm to about 10,000 sccm, for a duration of about 1 second to about 180 minutes. The partial pressure of the nitrogen-containing ambient can range from a low partial pressure, for example, of about 1 to about 10 Torr, up to full atmospheric pressure to optimize processing as desired.
  • In a plasma nitridization of the [0028] silicon layer 18, the plasma stream can be produced by a variety of plasma sources, such as a downstream microwave system, an electron cyclotron residence (ECR) system, an inductive coupled plasma (ICP) system, a radio frequency (RF) system, among others. Exemplary plasma nitridization processes comprise exposing the wafer 10 to a remote microwave plasma source of nitrogen or an inductive coupled plasma (ICP) at a pressure of about 1 to about 20 Torr. The plasma typically comprises the nitrogen-containing gas, preferably nitrogen (N2) or ammonia (NH3), and an inert gas such as helium or argon to increase the plasma density.
  • The resulting [0029] nitride layer 20 functions as a barrier to inhibit the passage of boron through the gate dielectric layer from an overlying boron-doped gate polysilicon layer into the substrate 12.
  • The structure can then be processed by conventional methods to complete the gate electrode. An example of a gate stack comprises a [0030] gate oxide layer 16, a doped polysilicon layer 22, a barrier layer 24 such as tungsten nitride (WN), a layer 26 of tungsten or other conductive metal, and a nitride cap 28, as shown in FIG. 4. Another example of a gate stack (not shown) comprises a gate oxide, a doped polysilicon, tungsten silicide (WSiX), titanium silicide (TiSiX), cobalt silicide (CoSiX), and a nitride cap. The gate layers can then be patterned and etched utilizing photolithographic processing (i.e., by dry etching) to form a transistor gate stack 30, as shown. Sidewalls 32 are provided adjacent the transistor gate, and can comprise, for example, silicon dioxide or silicon nitride.
  • Thereafter, a dopant implantation, typically with an n-type conductivity-enhancing dopant, can be performed to form the source/drain (S/D) [0031] regions 34 in the silicon substrate 12 proximate the gate 30. The source/drain regions together with the gate form an operative field effect transistor device.
  • In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents. [0032]

Claims (72)

What is claimed is:
1. A method of forming a nitride barrier layer, comprising the steps of:
exposing a dielectric layer to a silicon-containing species under low partial pressure to deposit a layer of silicon thereon; and
exposing the silicon layer to a nitrogen-containing species to form a silicon nitride barrier layer.
2. The method of claim 1, wherein the dielectric layer is exposed to the silicon-containing species at a partial pressure of about 10−2 Torr or less.
3. The method of claim 1, wherein the dielectric layer is exposed to the silicon-containing species at pressure of about 10−2 to about 10−7 Torr.
4. The method of claim 2, wherein the dielectric layer is exposed to the silicon-containing species at a temperature of about 500° C. to about 700° C.
5. A method of forming a nitride barrier layer, comprising the steps of:
irradiating a dielectric layer with a silicon-containing species under low partial pressure to nucleate the dielectric layer with a layer of silicon; and
exposing the silicon layer to a nitrogen-containing species to form a silicon nitride barrier layer.
6. The method of claim 5, wherein the silicon layer has a thickness of about 10 to about 30 angstroms.
7. A method of forming a nitride barrier layer, comprising the steps of:
exposing a dielectric layer to a silicon-containing species under low partial pressure to deposit a layer of about 10 to about 30 angstroms silicon thereon; and
nitridizing the silicon layer in a nitrogen-containing species to form a silicon nitride barrier layer.
8. A method of forming a nitride barrier layer, comprising the steps of:
exposing a surface of a dielectric layer to a silicon-containing species at a low partial pressure to nucleate the surface of the dielectric layer with a layer of silicon; and
exposing the silicon layer to a nitrogen-containing species to form a silicon nitride barrier layer.
9. A method of forming a nitride barrier layer, comprising the steps of:
exposing a dielectric layer to a silicon-containing species at a partial pressure of about 10−2 Torr or less to deposit a layer of about 10 to about 30 angstroms silicon thereon; and
nitridizing the silicon layer to form a silicon nitride barrier layer.
10. The method of claim 9, wherein the dielectric layer is exposed to the silicon-containing species at a temperature of about 500° C. to about 700° C.
11. The method of claim 9, wherein the silicon-containing species is selected from the group consisting of dichlorosilane, silicon tetrachloride, silane, and disilane.
12. The method of claim 9, wherein the step of exposing the dielectric layer to the silicon-containing species is by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, or rapid thermal chemical vapor deposition.
13. The method of claim 9, wherein the silicon-containing species is deposited by rapid thermal chemical vapor deposition at about 500° C. to about 700° C.
14. The method of claim 9, wherein the dielectric layer comprises silicon dioxide.
15. The method of claim 9, wherein the dielectric layer comprises a dielectric material selected from the group consisting of tantalum pentoxide, hafnium dioxide, and aluminum trioxide.
16. A method of forming a nitride barrier layer, comprising the steps of:
exposing a dielectric layer to a silicon-containing species at a partial pressure of about 10−2 to about 10−7 to nucleate the dielectric layer with a layer of silicon; and
exposing the silicon layer to a nitrogen-containing species to form a silicon nitride barrier layer.
17. A method of forming a nitride barrier layer, comprising the steps of:
exposing a dielectric layer to a silicon-containing species at a partial pressure of about 10−2 to about 10−7, a temperature of about 500° C. to about 700° C., and a duration of about 1 second to about 5 minutes, to nucleate the dielectric layer with a layer of silicon; and
exposing the silicon layer to a nitrogen-containing species to form a silicon nitride barrier layer.
18. A method of forming a nitride barrier layer, comprising the steps of:
depositing a silicon layer onto a dielectric layer by exposing the dielectric layer to a silicon-containing species under low partial pressure; and
thermally annealing the silicon layer in a nitrogen-containing species.
19. A method of forming a nitride barrier layer, comprising the steps of:
depositing a silicon layer onto a dielectric layer by exposing the dielectric layer to a silicon-containing species under low partial pressure; and
exposing the silicon layer to a nitrogen-containing species at a temperature of about 700° C. to about 900° C. to nitridize the silicon layer.
20. A method of forming a nitride barrier layer, comprising the steps of:
depositing a silicon layer onto a dielectric layer by exposing the dielectric layer to a silicon-containing species under low partial pressure; and exposing the silicon layer to a nitrogen-containing species at a temperature of about 700° C. to about 900° C., a pressure of about 1 to about 760 Torr, and a flow rate of about 100 to about 10,000 sccm, for about 1 second to about 180 minutes to nitridize the silicon layer.
21. The method of claim 20, wherein the nitrogen-containing species is selected from the group consisting of nitrogen, ammonia, nitrogen trifluoride, nitrogen oxide, and a nitrogenhelium mixture.
22. The method of claim 21, wherein the silicon layer is exposed to a plasma source of nitrogen.
23. A method of forming a nitride barrier layer, comprising the steps of:
depositing a silicon layer onto a dielectric layer by exposing the dielectric layer to a silicon-containing species under low partial pressure; and
exposing the silicon layer to a plasma source of a nitrogen-containing species to nitridize the silicon layer.
24. The method of claim 23, wherein the plasma source of the nitrogen-containing species is produced by a downstream microwave system, an electron cyclotron residence system, an inductive coupled plasma system, or a radio frequency system.
25. A method of forming a nitride barrier layer, comprising the steps of:
depositing a silicon layer onto a dielectric layer by exposing the dielectric layer to a silicon-containing species under low partial pressure; and
exposing the silicon layer to a remote microwave plasma source of a nitrogen-containing species at a pressure of about 1 to about 20 Torr to nitridize the silicon layer.
26. A method of forming a nitride barrier layer, comprising the steps of:
depositing a silicon layer onto a dielectric layer by exposing the dielectric layer to a silicon-containing species under low partial pressure; and exposing the silicon layer to a remote microwave plasma source of a nitrogen-containing species at a pressure of about 1 to about 20 Torr, and a temperature of about 700° C. to about 900° C. to nitridize the silicon layer.
27. A method of forming a nitride barrier layer, comprising the steps of:
depositing a silicon layer onto a dielectric layer by exposing the dielectric layer to a silicon-containing species under low partial pressure; and
exposing the silicon layer to an inductive coupled plasma source of a nitrogen-containing species at a pressure of about 1 to about 20 Torr to nitridize the silicon layer.
28. A method of forming a semiconductor device, comprising the steps of:
irradiating a dielectric layer disposed on a silicon substrate with a silicon-containing species under low partial pressure to nucleate the dielectric layer with a layer of silicon; and
nitridizing the silicon layer.
29. The method of claim 28, wherein the step of irradiating the dielectric layer with the silicon-containing species is at a partial pressure about 10−2 Torr or less.
30. The method of claim 29, wherein the step of irradiating the dielectric layer is at a partial pressure of about 10−2 to about 10−7 Torr.
31. The method of claim 29, wherein the silicon-containing species is selected from the group consisting of dichlorosilane, silicon tetrachloride, silane, and disilane.
32. The method of claim 28, wherein the step of irradiating the dielectric layer with the silicon-containing species is by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, or rapid thermal chemical vapor deposition.
33. The method of claim 28, wherein the step of irradiating the dielectric layer with the silicon-containing species is by rapid thermal chemical vapor deposition at a temperature of about 500° C. to about 700° C.
34. The method of claim 28, wherein the dielectric layer comprises silicon dioxide.
35. The method of claim 28, wherein the dielectric layer comprises a dielectric material selected from the group consisting of tantalum pentoxide, hafnium dioxide, and aluminum trioxide.
36. A method of forming a semiconductor device, comprising the steps of:
exposing a dielectric layer disposed on a silicon substrate to a silicon-containing species at a partial pressure of about 1 Torr or less to nucleate the dielectric layer with a layer of silicon; and
nitridizing the silicon layer in a nitrogen-containing species.
37. A method of forming a semiconductor device, comprising the steps of:
exposing an oxide layer disposed on a silicon substrate to a silicon-containing species at a partial pressure of about 10−2 Torr or less to nucleate the dielectric layer with a layer of silicon; and
thermally annealing the silicon layer in a nitrogen-containing gas.
38. A method of forming a semiconductor device, comprising the steps of:
exposing an oxide layer disposed on a silicon substrate to a silicon-containing species at a partial pressure of about 10−2 Torr or less to nucleate the dielectric layer with a layer of silicon; and
exposing the silicon layer to a nitrogen-containing species at a temperature of about 700° C. to about 900° C. to nitridize the silicon layer.
39. A method of forming a semiconductor device, comprising the steps of:
depositing a silicon layer onto a dielectric layer by exposing the dielectric layer to a silicon-containing species under low partial pressure to nucleate the dielectric layer with a layer of silicon; and
exposing the silicon layer to a plasma source of a nitrogen-containing species to nitridize the silicon layer.
40. The method of claim 39, wherein the plasma source of the nitrogen-containing species is produced by a downstream microwave system, an electron cyclotron residence system, an inductive coupled plasma system, or a radio frequency system.
41. A method of forming a semiconductor device, comprising the steps of:
depositing a silicon layer onto a dielectric layer by exposing the dielectric layer to a silicon-containing species under low a partial pressure of about 1 Torr or less to nucleate the dielectric layer with a layer of silicon; and
exposing the silicon layer to a remote microwave plasma source of a nitrogen-containing species at a pressure of about 1 to about 20 Torr to nitridize the silicon layer.
42. A method of forming a gate electrode, comprising the steps of:
exposing a gate oxide layer disposed on a silicon substrate to a silicon-containing species at a partial pressure of about 10−2 Torr or less to nucleate the dielectric layer with a layer silicon; and
exposing the silicon layer to a nitrogen-containing species to form a silicon nitride barrier layer.
43. A method of forming a gate electrode, comprising the steps of:
exposing a gate oxide layer disposed on a silicon substrate to a silicon-containing species at a partial pressure of about 10−2 to about 10−7 to nucleate the dielectric layer with a layer of silicon; and
exposing the silicon layer to a nitrogen-containing species to form a silicon nitride barrier layer.
44. A method of forming a gate electrode, comprising the steps of:
exposing a gate oxide layer disposed on a silicon substrate to a silicon-containing species at a partial pressure of about 10−2 to about 10−7, a temperature of about 500° C. to about 700° C., and a duration of about 1 second to about 5 minutes, to nucleate the dielectric layer with a layer of silicon and exposing the silicon layer to a nitrogen-containing species to form a silicon nitride barrier layer.
45. A method of forming a gate electrode, comprising the steps of:
depositing a silicon layer onto a gate oxide layer disposed on a silicon substrate by exposing the gate oxide layer to a silicon-containing species at a partial pressure of about 10−2 Torr or less; and
thermally annealing the silicon layer in a nitrogen-containing species.
46. A method of forming a gate electrode, comprising the steps of:
depositing a silicon layer onto a gate oxide layer disposed on a silicon substrate by exposing the gate oxide layer to a silicon-containing species at a partial pressure of about 10−2 Torr or less; and
exposing the silicon layer to a nitrogen-containing species at a temperature of about 700° C. to about 900° C. to nitridize the silicon layer to a silicon nitride layer.
47. A method of forming a gate electrode, comprising the steps of:
depositing a silicon layer onto a gate oxide layer disposed on a silicon substrate by exposing the dielectric layer to a silicon-containing species under low partial pressure; and
exposing the silicon layer to a nitrogen-containing species at a temperature of about 700° C. to about 900° C., a pressure of about 1 to about 760 Torr, a flow rate of about 100 to about 10,000 sccm, for about 1 second to about 180 minutes to nitridize the silicon layer.
48. The method of claim 47, wherein the nitrogen-containing species is selected from the group consisting of nitrogen, ammonia, nitrogen trifluoride, nitrogen oxide, and a mixture of nitrogen and helium.
49. A method of forming a gate electrode, comprising the steps of:
depositing a silicon layer onto a gate oxide layer disposed on a silicon substrate by exposing the dielectric layer to a silicon-containing species at a partial pressure of about 10−2 Torr or less; and
exposing the silicon layer to a plasma source of a nitrogen-containing species to nitridize the silicon layer.
50. The method of claim 49, wherein the plasma source of the nitrogen-containing species is produced by a downstream microwave system, an electron cyclotron residence system, an inductive coupled plasma system, or a radio frequency system.
51. A method of forming a gate electrode, comprising the steps of:
depositing a silicon layer onto a gate oxide layer disposed on a silicon substrate by exposing the dielectric layer to a silicon-containing species at a partial pressure of about 10−2 Torr or less; and
exposing the silicon layer to a remote microwave plasma source of a nitrogen-containing species at a temperature of about 700° C. to about 900° C., and a pressure of about 1 to about 20 Torr to nitridize the silicon layer.
52. A method of forming a gate electrode, comprising the steps of:
depositing a silicon layer onto a gate oxide layer disposed on a silicon substrate by exposing the dielectric layer to a silicon-containing species at a partial pressure of about 10−2 Torr or less; and
exposing the silicon layer to an inductive coupled plasma source of a nitrogen-containing species at a pressure of about 1 to about 20 Torr to nitridize the silicon layer.
53. A method of forming a gate electrode, comprising the steps of:
exposing a gate oxide layer disposed on a silicon substrate to a silicon-containing species at a partial pressure of about 10−2 to about 10−7 to nucleate the dielectric layer with a layer of silicon;
nitridizing the silicon layer in a nitrogen-containing species to form a silicon nitride barrier layer; and
forming a conductive polysilicon layer comprising a conductivity enhancing dopant over the nitride barrier layer; wherein the nitride barrier layer inhibits passage of the dopant from the conductive polysilicon layer therethrough.
54. The method of claim 53, wherein the polysilicon layer comprises a boron dopant.
55. The method of claim 53, further comprising:
forming an insulative nitride cap over the conductive polysilicon layer; and
patterning the layers to form a gate stack.
56. The method of claim 53, further comprising:
forming a barrier layer over the doped polysilicon layer;
forming a conductive metal layer over the barrier layer;
forming an insulative nitride cap over the conductive metal layer; and
patterning the layers to form a gate stack.
57. The method of claim 53, further comprising:
forming a metal silicide layer over the doped polysilicon layer;
forming an insulative nitride cap over the metal silicide layer; and
patterning the layers to form a gate stack.
58. A nitride barrier layer, comprising:
a nitridized silicon layer of less than about 30 angstroms disposed on an oxide layer, and formed by irradiation of the oxide layer with a silicon-containing species under low partial pressure in the presence of a nitrogen-containing species.
59. A nitride barrier layer, comprising: a nitridized silicon layer having a thickness of less than about 30 angstroms, and disposed adjacent an oxide layer.
60. A nitride barrier layer, comprising: an annealed nitridized silicon layer having a thickness of less than about 30 angstroms, and disposed adjacent an oxide layer.
61. The barrier layer of claim 60, wherein the barrier layer is thermally annealed.
62. The barrier layer of claim 60, wherein the barrier layer is plasma annealed.
63. A semiconductor device comprising:
a semiconductor substrate comprising silicon;
an oxide layer disposed adjacent to the semiconductor substrate; and
a diffusion barrier layer disposed adjacent the oxide layer; the diffusion barrier layer having a thickness of less than about 30 angstroms, and comprising a nitridized silicon layer formed by irradiation of an oxide layer with a silicon-containing species under low partial pressure in the presence of a nitrogen-containing species,
64. A semiconductor device comprising:
a semiconductor substrate comprising silicon;
an oxide layer disposed adjacent to the semiconductor substrate; and
a diffusion barrier layer disposed adjacent the oxide layer, and comprising nitridized silicon having a thickness of about 10 to about 20 angstroms.
65. A semiconductor device comprising:
a semiconductor substrate comprising silicon;
an oxide layer disposed adjacent to the semiconductor substrate; and
a diffusion barrier layer disposed adjacent the oxide layer, and comprising nitrogen annealed silicon and having a thickness of about 10 to about 20 angstroms.
66. The device of claim 65, wherein the diffusion barrier layer comprises plasma annealed silicon.
67. The device of claim 65, wherein the diffusion barrier layer comprises thermally annealed silicon.
68. A gate electrode, comprising:
a gate oxide layer disposed adjacent to a semiconductor substrate; and
a diffusion barrier layer disposed adjacent the gate oxide layer; the diffusion barrier layer having a thickness of about 10 to about 20 angstroms and comprising a nitridized silicon layer deposited by irradiating an oxide layer with a silicon-containing species under low partial pressure, and nitridizing the silicon layer by exposure to a nitrogen-containing species.
69. A gate electrode, comprising:
a gate oxide layer disposed adjacent to a semiconductor substrate; and
a diffusion barrier layer disposed adjacent the oxide layer, and comprising a nitridized silicon layer having a thickness of about 10 to about 20 angstroms.
70. A gate electrode, comprising:
a gate oxide layer disposed adjacent to a semiconductor substrate; and
a diffusion barrier layer disposed adjacent the oxide layer, and comprising nitrogen annealed silicon and having a thickness of about 10 to about 20 angstroms.
71. The electrode of claim 70, wherein the diffusion barrier layer comprises plasma annealed silicon.
72. The electrode of claim 70, wherein the diffusion barrier layer comprises thermally annealed silicon.
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030124783A1 (en) * 2001-12-28 2003-07-03 Rotondaro Antonio L. P. System for creating ultra-shallow dopant profiles
US20040115894A1 (en) * 2002-12-12 2004-06-17 Park Sang Wook Method of manufacturing a semiconductor device
US6767847B1 (en) * 2002-07-02 2004-07-27 Taiwan Semiconductor Manufacturing Company Method of forming a silicon nitride-silicon dioxide gate stack
WO2005027210A1 (en) * 2003-09-04 2005-03-24 Advanced Micro Devices, Inc Memory cell structure having nitride layer with reduced charge loss and method for fabricating same
US20070018220A1 (en) * 2005-07-15 2007-01-25 Lee Chang-Won Semiconductor device, gate electrode and method of fabricating the same
US20070052054A1 (en) * 2005-08-24 2007-03-08 Micron Technology, Inc. CMOS imager with nitrided gate oxide and method of fabrication
US20080173927A1 (en) * 2007-01-22 2008-07-24 Kiwamu Sakuma Semiconductor device and method for manufacturing the same
US20080305647A1 (en) * 2005-09-29 2008-12-11 Kabushiki Kaisha Toshiba Method for Manufacturing a Semiconductor Device
US20110256691A1 (en) * 2007-12-21 2011-10-20 Kartik Ramaswamy Removal of surface dopants from a substrate

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3781666B2 (en) * 2001-11-29 2006-05-31 エルピーダメモリ株式会社 Method for forming gate electrode and gate electrode structure
KR100486248B1 (en) * 2002-07-09 2005-05-03 삼성전자주식회사 Method of fabricating semiconductor device including silicon oxide layer
US20040071878A1 (en) * 2002-08-15 2004-04-15 Interuniversitair Microelektronica Centrum (Imec Vzw) Surface preparation using plasma for ALD Films
US7166896B2 (en) * 2002-08-26 2007-01-23 Micron Technology, Inc. Cross diffusion barrier layer in polysilicon
US6967154B2 (en) * 2002-08-26 2005-11-22 Micron Technology, Inc. Enhanced atomic layer deposition
JP2004095918A (en) * 2002-08-30 2004-03-25 Fasl Japan Ltd Semiconductor memory device and its manufacturing method
US7141511B2 (en) * 2004-04-27 2006-11-28 Micron Technology Inc. Method and apparatus for fabricating a memory device with a dielectric etch stop layer
US9236383B2 (en) * 2004-04-27 2016-01-12 Micron Technology, Inc. Method and apparatus for fabricating a memory device with a dielectric etch stop layer
KR100871006B1 (en) * 2004-07-30 2008-11-27 어플라이드 머티어리얼스, 인코포레이티드 Thin tungsten silicide layer deposition and gate metal integration
US7087531B1 (en) * 2005-01-17 2006-08-08 International Business Machines Corporation Shallow trench isolation formation
US8334220B2 (en) * 2007-03-21 2012-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of selectively forming a silicon nitride layer
US8337950B2 (en) * 2007-06-19 2012-12-25 Applied Materials, Inc. Method for depositing boron-rich films for lithographic mask applications
KR20100042644A (en) * 2007-07-13 2010-04-26 어플라이드 머티어리얼스, 인코포레이티드 Boron derived materials deposition method
US8148269B2 (en) * 2008-04-04 2012-04-03 Applied Materials, Inc. Boron nitride and boron-nitride derived materials deposition method
KR20090126520A (en) * 2008-06-04 2009-12-09 삼성전자주식회사 Method of fabricating semiconductor device and semiconductor device produced by the same
GB0901589D0 (en) * 2009-01-30 2009-03-11 Omar Ralph M Improvements relating to multifunction authentication systems
US8895352B2 (en) * 2009-06-02 2014-11-25 International Business Machines Corporation Method to improve nucleation of materials on graphene and carbon nanotubes
US9388494B2 (en) * 2012-06-25 2016-07-12 Novellus Systems, Inc. Suppression of parasitic deposition in a substrate processing system by suppressing precursor flow and plasma outside of substrate region
CN103578998B (en) * 2012-07-30 2016-06-08 上海华虹宏力半导体制造有限公司 Prevent the method that in PMOS device technique, grid polycrystalline silicon exhausts
CN103681341B (en) * 2012-09-21 2016-04-13 上海华虹宏力半导体制造有限公司 Suppress the method for PMOS device threshold voltage shift
CN106062970B (en) 2013-03-11 2018-05-08 英特尔公司 The low-voltage avalanche photodide with re-entrant angle mirror for silicon-based photonics integration circuit
CN110047832B (en) 2018-01-16 2021-11-02 联华电子股份有限公司 Semiconductor memory device and method of manufacturing the same

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5138401A (en) * 1987-08-24 1992-08-11 Semiconductor Energy Laboratory Co., Ltd. Electronic devices utilizing superconducting materials
US5563093A (en) * 1993-01-28 1996-10-08 Kawasaki Steel Corporation Method of manufacturing fet semiconductor devices with polysilicon gate having large grain sizes
US5634974A (en) * 1995-11-03 1997-06-03 Micron Technologies, Inc. Method for forming hemispherical grained silicon
US5923999A (en) * 1996-10-29 1999-07-13 International Business Machines Corporation Method of controlling dopant diffusion and metal contamination in thin polycide gate conductor of mosfet device
US6005807A (en) * 1998-09-16 1999-12-21 Winbond Electronics Corp. Method and apparatus for self-aligned memory cells and array using source side injection
US6087229A (en) * 1998-03-09 2000-07-11 Lsi Logic Corporation Composite semiconductor gate dielectrics
US6127287A (en) * 1996-05-30 2000-10-03 Micron Technology, Inc. Silicon nitride deposition method for use in forming a memory cell dielectric
US6203613B1 (en) * 1999-10-19 2001-03-20 International Business Machines Corporation Atomic layer deposition with nitrate containing precursors
US6228779B1 (en) * 1998-11-06 2001-05-08 Novellus Systems, Inc. Ultra thin oxynitride and nitride/oxide stacked gate dielectrics fabricated by high pressure technology
US6245689B1 (en) * 1996-09-05 2001-06-12 Advanced Micro Devices, Inc. Process for reliable ultrathin oxynitride formation
US6291868B1 (en) * 1998-02-26 2001-09-18 Micron Technology, Inc. Forming a conductive structure in a semiconductor device
US6297095B1 (en) * 2000-06-16 2001-10-02 Motorola, Inc. Memory device that includes passivated nanoclusters and method for manufacture
US6323114B1 (en) * 1998-11-24 2001-11-27 Texas Instruments Incorporated Stacked/composite gate dielectric which incorporates nitrogen at an interface
US6410968B1 (en) * 2000-08-31 2002-06-25 Micron Technology, Inc. Semiconductor device with barrier layer
US6531364B1 (en) * 1998-08-05 2003-03-11 Advanced Micro Devices, Inc. Advanced fabrication technique to form ultra thin gate dielectric using a sacrificial polysilicon seed layer
US6544908B1 (en) * 2000-08-30 2003-04-08 Micron Technology, Inc. Ammonia gas passivation on nitride encapsulated devices
US6559007B1 (en) * 2000-04-06 2003-05-06 Micron Technology, Inc. Method for forming flash memory device having a tunnel dielectric comprising nitrided oxide
US6998303B2 (en) * 2002-08-08 2006-02-14 Fujitsu Limited Manufacture method for semiconductor device with patterned film of ZrO2 or the like

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258333A (en) * 1992-08-18 1993-11-02 Intel Corporation Composite dielectric for a semiconductor device and method of fabrication
US5837598A (en) * 1997-03-13 1998-11-17 Lsi Logic Corporation Diffusion barrier for polysilicon gate electrode of MOS device in integrated circuit structure, and method of making same
KR100486248B1 (en) * 2002-07-09 2005-05-03 삼성전자주식회사 Method of fabricating semiconductor device including silicon oxide layer
US20080268634A1 (en) * 2007-04-24 2008-10-30 Yang Haining S Dopant diffusion barrier layer to prevent out diffusion

Patent Citations (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5138401A (en) * 1987-08-24 1992-08-11 Semiconductor Energy Laboratory Co., Ltd. Electronic devices utilizing superconducting materials
US5563093A (en) * 1993-01-28 1996-10-08 Kawasaki Steel Corporation Method of manufacturing fet semiconductor devices with polysilicon gate having large grain sizes
US5634974A (en) * 1995-11-03 1997-06-03 Micron Technologies, Inc. Method for forming hemispherical grained silicon
US5759262A (en) * 1995-11-03 1998-06-02 Micron Technology, Inc. Method of forming hemispherical grained silicon
US6127287A (en) * 1996-05-30 2000-10-03 Micron Technology, Inc. Silicon nitride deposition method for use in forming a memory cell dielectric
US6204206B1 (en) * 1996-05-30 2001-03-20 Micron Technology, Inc. Silicon nitride deposition method
US6245689B1 (en) * 1996-09-05 2001-06-12 Advanced Micro Devices, Inc. Process for reliable ultrathin oxynitride formation
US5923999A (en) * 1996-10-29 1999-07-13 International Business Machines Corporation Method of controlling dopant diffusion and metal contamination in thin polycide gate conductor of mosfet device
US6596595B1 (en) * 1998-02-26 2003-07-22 Micron Technology, Inc. Forming a conductive structure in a semiconductor device
US6362086B2 (en) * 1998-02-26 2002-03-26 Micron Technology, Inc. Forming a conductive structure in a semiconductor device
US6291868B1 (en) * 1998-02-26 2001-09-18 Micron Technology, Inc. Forming a conductive structure in a semiconductor device
US6087229A (en) * 1998-03-09 2000-07-11 Lsi Logic Corporation Composite semiconductor gate dielectrics
US6531364B1 (en) * 1998-08-05 2003-03-11 Advanced Micro Devices, Inc. Advanced fabrication technique to form ultra thin gate dielectric using a sacrificial polysilicon seed layer
US6005807A (en) * 1998-09-16 1999-12-21 Winbond Electronics Corp. Method and apparatus for self-aligned memory cells and array using source side injection
US6228779B1 (en) * 1998-11-06 2001-05-08 Novellus Systems, Inc. Ultra thin oxynitride and nitride/oxide stacked gate dielectrics fabricated by high pressure technology
US6323114B1 (en) * 1998-11-24 2001-11-27 Texas Instruments Incorporated Stacked/composite gate dielectric which incorporates nitrogen at an interface
US6203613B1 (en) * 1999-10-19 2001-03-20 International Business Machines Corporation Atomic layer deposition with nitrate containing precursors
US6559007B1 (en) * 2000-04-06 2003-05-06 Micron Technology, Inc. Method for forming flash memory device having a tunnel dielectric comprising nitrided oxide
US6815805B2 (en) * 2000-04-06 2004-11-09 Micron Technology, Inc. Method of fabricating an integrated circuit with a dielectric layer exposed to a hydrogen-bearing nitrogen source
US6297095B1 (en) * 2000-06-16 2001-10-02 Motorola, Inc. Memory device that includes passivated nanoclusters and method for manufacture
US6544908B1 (en) * 2000-08-30 2003-04-08 Micron Technology, Inc. Ammonia gas passivation on nitride encapsulated devices
US6410968B1 (en) * 2000-08-31 2002-06-25 Micron Technology, Inc. Semiconductor device with barrier layer
US6475883B2 (en) * 2000-08-31 2002-11-05 Micron Technology, Inc. Method for forming a barrier layer
US6998303B2 (en) * 2002-08-08 2006-02-14 Fujitsu Limited Manufacture method for semiconductor device with patterned film of ZrO2 or the like

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030124783A1 (en) * 2001-12-28 2003-07-03 Rotondaro Antonio L. P. System for creating ultra-shallow dopant profiles
US6767847B1 (en) * 2002-07-02 2004-07-27 Taiwan Semiconductor Manufacturing Company Method of forming a silicon nitride-silicon dioxide gate stack
US20040115894A1 (en) * 2002-12-12 2004-06-17 Park Sang Wook Method of manufacturing a semiconductor device
US6893981B2 (en) * 2002-12-12 2005-05-17 Hynix Semiconductor Inc. Method of manufacturing a semiconductor device by RTA process in nitrogen atmosphere
KR101217260B1 (en) 2003-09-04 2012-12-31 어드밴스드 마이크로 디바이시즈, 인코포레이티드 Method for fabricating a memory cell structure having nitride layer with reduced charge loss
WO2005027210A1 (en) * 2003-09-04 2005-03-24 Advanced Micro Devices, Inc Memory cell structure having nitride layer with reduced charge loss and method for fabricating same
GB2420226A (en) * 2003-09-04 2006-05-17 Advanced Micro Devices Inc Memory cell structure having nitride layer with reduced charge loss and method for fabricating same
GB2420226B (en) * 2003-09-04 2007-01-17 Advanced Micro Devices Inc Memory cell structure having nitride layer with reduced charge loss and method for fabricating same
US20070018220A1 (en) * 2005-07-15 2007-01-25 Lee Chang-Won Semiconductor device, gate electrode and method of fabricating the same
US20070052054A1 (en) * 2005-08-24 2007-03-08 Micron Technology, Inc. CMOS imager with nitrided gate oxide and method of fabrication
US7728330B2 (en) 2005-08-24 2010-06-01 Aptina Imaging Corporation CMOS imager with nitrided gate oxide and method of fabrication
US20080305647A1 (en) * 2005-09-29 2008-12-11 Kabushiki Kaisha Toshiba Method for Manufacturing a Semiconductor Device
US7772129B2 (en) * 2005-09-29 2010-08-10 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device
US20110003481A1 (en) * 2005-09-29 2011-01-06 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device
US8557717B2 (en) * 2005-09-29 2013-10-15 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device
US7749919B2 (en) * 2007-01-22 2010-07-06 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20080173927A1 (en) * 2007-01-22 2008-07-24 Kiwamu Sakuma Semiconductor device and method for manufacturing the same
US20110256691A1 (en) * 2007-12-21 2011-10-20 Kartik Ramaswamy Removal of surface dopants from a substrate

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US20050026348A1 (en) 2005-02-03
US7576398B2 (en) 2009-08-18

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