US20030029715A1 - An Apparatus For Annealing Substrates In Physical Vapor Deposition Systems - Google Patents

An Apparatus For Annealing Substrates In Physical Vapor Deposition Systems Download PDF

Info

Publication number
US20030029715A1
US20030029715A1 US09/916,234 US91623401A US2003029715A1 US 20030029715 A1 US20030029715 A1 US 20030029715A1 US 91623401 A US91623401 A US 91623401A US 2003029715 A1 US2003029715 A1 US 2003029715A1
Authority
US
United States
Prior art keywords
substrate
chamber
annealing
temperature
disposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US09/916,234
Inventor
Sang-Ho Yu
Yonghwa Cha
Ki Yoon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US09/916,234 priority Critical patent/US20030029715A1/en
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Assigned to APPLIED MATERIALS, INC. reassignment APPLIED MATERIALS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YOON, KI HWAN, CHA, YONGHWA CHRIS, YU, SANG-HO
Priority to US10/044,412 priority patent/US6740585B2/en
Priority to PCT/US2002/023578 priority patent/WO2003080887A2/en
Priority to JP2003578610A priority patent/JP2006500472A/en
Priority to JP2003533324A priority patent/JP2005504885A/en
Priority to PCT/US2002/023581 priority patent/WO2003030224A2/en
Publication of US20030029715A1 publication Critical patent/US20030029715A1/en
Priority to US10/845,970 priority patent/US20040211665A1/en
Priority to US11/456,073 priority patent/US7416979B2/en
Priority to US11/733,929 priority patent/US8110489B2/en
Priority to US12/111,923 priority patent/US20090004850A1/en
Priority to US12/111,930 priority patent/US20080268635A1/en
Priority to US12/171,132 priority patent/US7611990B2/en
Priority to US12/201,976 priority patent/US9051641B2/en
Priority to US12/969,445 priority patent/US8187970B2/en
Priority to US13/452,237 priority patent/US8815724B2/en
Priority to US13/456,904 priority patent/US8563424B2/en
Priority to US14/717,375 priority patent/US9209074B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/56Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
    • C23C14/564Means for minimising impurities in the coating chamber such as dust, moisture, residual gases
    • C23C14/566Means for minimising impurities in the coating chamber such as dust, moisture, residual gases using a load-lock chamber
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/54Apparatus specially adapted for continuous coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846Layer combinations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855After-treatment introducing at least one additional element into the layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864Thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD

Definitions

  • the present invention relates to the fabrication of semiconductor devices and to the deposition and annealing of materials on a semiconductor substrate.
  • ULSI circuits include metal oxide semiconductor (MOS) devices, such as complementary metal oxide semiconductor (CMOS) field effect transistors (FETs).
  • MOS metal oxide semiconductor
  • CMOS complementary metal oxide semiconductor
  • FETs field effect transistors
  • the transistors can include semiconductor gates disposed between source and drain regions.
  • MOS devices using polysilicon gate electrodes, it has become the practice to provide a metal silicide layer over the polysilicon gate electrode, and over the source and drain regions of the silicon substrate, to facilitate lower resistance and improve device performance by electrically connecting the source and drain regions to metal interconnects.
  • CMOS processing technology One important processing technique currently used in CMOS processing technology is the Self-Aligned Silicidation (salicide) of refractory metals such as titanium and cobalt.
  • siicide refractory metals
  • refractory metals such as titanium and cobalt.
  • Co cobalt
  • the source and drain and polysilicon gate resistances are reduced by forming a high conductivity overlayer and the contact resistance is reduced by increasing the effective contact area of the source and drain with subsequently formed metal interconnects.
  • Salicide processing technology seeks to exploit the principle that a refractory metal such as cobalt deposited on a patterned silicon substrate will selectively react with exposed silicon under specific processing conditions, and will not react with silicon oxide material.
  • a layer of cobalt is sputtered onto silicon, typically patterned on a substrate surface, and then subjected to a thermal annealing process to form cobalt silicide (CoSi 2 ).
  • Unreacted cobalt such as cobalt deposited outside the patterned silicon or on a protective layer of silicon oxide, can thereafter be selectively etched away.
  • the selective reaction of cobalt silicide will result in maskless, self-aligned formation of a low-resistivity refractory metal silicide in source, drain, and polysilicon gate regions formed on the substrate surface and in interconnecting conductors of the semiconductor device.
  • further processing of the substrate may occur, such as additional thermal annealing, which may be used to further reduce the sheet resistance of the silicide material.
  • Oxide formation on the surface of the substrate can result in increasing the resistance of silicide layers as well reducing the reliability of the overall circuit.
  • oxidation of the deposited cobalt material may result in cobalt agglomeration and irregular growth of the silicide layer.
  • the agglomeration and irregular growth of the cobalt layer may result in device malformation, such as source and drain electrodes having different thicknesses and surface areas.
  • excess cobalt silicide growth on substrate surface may form conductive paths between devices, which may result in short circuits and device failure.
  • One solution to limiting cobalt and silicon contamination is to sputter a capping film of titanium or titanium nitride on the cobalt and silicon film prior to transferring the substrate between chambers.
  • the capping film is then removed after annealing the substrate and prior to further processing of the substrate.
  • titanium nitride deposition and removal processes increase the number of processing steps required for silicide formation, thereby reducing process efficiency, increasing processing complexity, and reducing substrate through-put.
  • Embodiments of the invention described herein generally provide methods and apparatus for forming a metal suicide layer using a deposition and annealing process.
  • a system for processing a substrate including a load lock chamber, an intermediate substrate transfer region connected to the load lock chamber, the intermediate substrate transfer region comprising a first substrate transfer chamber and a second substrate transfer chamber, wherein the first substrate transfer chamber is coupled to the load lock chamber and the second substrate transfer chamber is coupled to the first substrate transfer chamber, a physical vapor deposition (PVD) processing chamber disposed on the first substrate transfer chamber and an annealing chamber disposed on the second substrate transfer chamber.
  • PVD physical vapor deposition
  • a method for forming a silicide layer on a substrate including positioning a substrate having silicon material disposed thereon on a substrate support disposed in a deposition chamber having a metal target disposed therein, applying a current to the substrate support to heat the substrate to a first temperature, introducing an inert gas into the deposition chamber, generating a plasma by applying a bias between a metal target and the substrate support in the inert gas environment to sputter material from the metal target, depositing the sputtered material on at least the silicon material, providing a backside gas between the substrate pedestal and the substrate, and annealing the substrate in situ at a second temperature greater than the first temperature to form a metal silicide layer.
  • a method for processing a substrate including introducing a substrate having silicon material disposed thereon into a load lock, transferring the substrate to a first transfer chamber having a physical vapor deposition processing chamber disposed thereon, the first transfer chamber is connected to the loadlock and the depositing chamber has a metal target and heating pedestal disposed therein, positioning the substrate into the physical vapor deposition chamber, depositing a metal layer on the silicon material, annealing the substrate prior to transferring the substrate to a second transfer chamber having an annealing chamber disposed thereon, wherein the second transfer chamber is connected to the first transfer chamber, and annealing the substrate in the annealing chamber to form a metal silicide layer.
  • FIG. 1 is schematic top view of one embodiment of an integrated multi-chamber apparatus suitable for depositing a conformal PVD layer on a semiconductor substrate and suitable for annealing the deposited layer;
  • FIG. 2 is schematic top view of another embodiment of an integrated multi-chamber apparatus suitable for depositing a conformal PVD layer on a semiconductor substrate and suitable for annealing the deposited layer
  • FIG. 3 is a cross-sectional view of one embodiment of a sputtering chamber included within the invention.
  • FIG. 4 is an expanded view of FIG. 3 including upper area of the shields near the target;
  • FIG. 5 is a plan view of one embodiment of a ring collimator
  • FIG. 6 is a partial plan view of one embodiment of a honeycomb collimator
  • FIG. 7A is a cross-sectional view of one embodiment of a pedestal for annealing a substrate
  • FIG. 7B is a cross-sectional view of another embodiment of a pedestal for annealing a substrate.
  • FIG. 8 is a simplified sectional view of a silicide material used as a contact with a transistor.
  • Embodiments of the invention described herein provide methods and apparatus for forming a metal silicide layer in a deposition chamber or substrate processing system.
  • PVD physical vapor deposition
  • One embodiment described below in reference to a physical vapor deposition (PVD) process is provided to illustrate the invention, and should not be construed or interpreted as limiting the scope of the invention. Aspects of the invention may be used to advantage in other processes, such as chemical vapor deposition, in which an anneal is desired for forming metal silicide layers.
  • FIG. 1 is schematic top view of one embodiment of an integrated multi-chamber substrate processing system suitable for performing at least one embodiment the metal deposition and annealing processes described herein.
  • the deposition and annealing processes may be performed in a multi-chamber processing system or cluster tool having a PVD chamber disposed thereon.
  • One processing platform that may be used to advantage is an EnduraTM processing platform commercially available from Applied Materials, Inc., located in Santa Clara, Calif.
  • the processing platform 35 typically includes a cluster of process chambers including two transfer chambers 48 , 50 and at least one long throw physical vapor deposition (PVD) chamber 36 , additional processing chambers 38 and 40 , and an annealing chamber 41 .
  • the annealing chambers 41 and the PVD chambers 36 are disposed in separate transfer chambers, which are operated at different vacuum pressures.
  • Chambers 38 and 40 may include PVD chambers or chemical vapor deposition (CVD) chambers for depositing other materials as desired by the operator.
  • Rapid thermal annealing (RTA) chambers that can anneal substrates at vacuum pressures may be used for the annealing chamber 41 on transfer chamber 48 or 50 based upon the configuration desired by the operator.
  • the processing platform 35 may further comprise one or more pre-clean chambers 42 , such as PreClean II chambers available from Applied Materials, for removing contaminants, two degas chambers 44 , and two load lock chambers 46 .
  • the processing platform 35 typically includes transfer robots 49 , 51 , disposed in transfer chambers 48 , 50 respectfully, and two cooldown or pre-heating chambers 52 separating the transfer chambers 48 , 50 .
  • the processing platform 35 is automated by programming a microprocessor controller 54 .
  • RTA chambers (not shown) may also be disposed on the first transfer chamber 48 of the processing platform 35 to provide post deposition annealing processes prior to substrate removal from the platform 35 .
  • a plurality of vacuum pumps are disposed in fluid communication with each transfer chamber and each of the processing chambers to independently regulate pressures in the respective chambers.
  • the pumps may establish a vacuum gradient of increasing pressure across the apparatus from the load lock chamber to the processing chambers.
  • FIG. 2 is a schematic top view of another embodiment of an integrated multi-chamber substrate processing system suitable for performing at least one embodiment the metal deposition and annealing processes described herein.
  • two PVD deposition chamber are disposed on the first transfer chamber 48 with two degas chambers 44 , and two load lock chambers 46 .
  • One of the PVD deposition chambers may be substitute with a vacuum annealing chamber or a pre-clean chamber 42 , such as the PreClean II chamber.
  • Two annealing chambers 41 are disposed on the second transfer chamber 50 .
  • the operating pressure of the first transfer chamber 48 is generally lower than that for the second transfer chamber 50 since high vacuum PVD processes are performed on the first transfer chamber 48 and high pressure processes, such as atmosphere annealing processes, are performed on the second transfer chamber 50 .
  • FIG. 3 illustrates one embodiment of a long throw physical vapor deposition chamber.
  • suitable long throw PVD chambers are ALPS plusTM and SIPTM PVD processing chambers, both commercially available from Applied Materials, Inc., Santa Clara, Calif.
  • the long throw PVD chamber 36 contains a sputtering source, such as a target 142 , and a substrate support pedestal 152 for receiving a semiconductor substrate 154 thereon and located within a grounded enclosure wall 150 , which may be a chamber wall as shown or a grounded shield.
  • a sputtering source such as a target 142
  • a substrate support pedestal 152 for receiving a semiconductor substrate 154 thereon and located within a grounded enclosure wall 150 , which may be a chamber wall as shown or a grounded shield.
  • the chamber 36 includes a target 142 supported on and sealed by O-rings to a grounded conductive aluminum adapter 144 through a dielectric isolator 146 .
  • the target 142 may be a bonded composite of a metallic cobalt surface layer and a backing plate of a more workable metal.
  • the target 142 comprises the material to be deposited on the substrate surface during sputtering.
  • the target may include, for example, materials including cobalt, titanium, tantalum, tungsten, molybdenum, platinum, nickel, iron, niobium, palladium, and combinations thereof, which are used in forming metal silicide layers.
  • targets comprising elemental cobalt, nickel cobalt alloys, or nickel iron alloys may be used as the target 142 .
  • a controllable DC power source 148 applies a negative voltage or bias to the target 142 , typically between about between about 0 V and about 2400 V to the target 142 to excite the gas into a plasma state.
  • the adapter 144 in turn is sealed and grounded to an aluminum chamber sidewall 150 . Ions from the plasma bombard the target 142 to sputter atoms and larger particles onto the substrate 154 disposed below. While, the power supplied is expressed in voltage, power may also be expressed as kilowatts or a power density (W/cm 2 ). The amount of power supplied to the chamber may be varied depending upon the amount of sputtering and the size of the substrate size being processed.
  • a pedestal 152 supports a substrate 154 to be sputter coated in planar opposition to the principal face of the target 142 .
  • the substrate support pedestal 152 has a planar substrate receiving surface disposed generally parallel to the sputtering surface of the target 142 .
  • the substrate 154 is positioned on the substrate support pedestal 152 and plasma is generated in the chamber 36 .
  • a long throw distance of at least about 90 mm separates the target 142 and the substrate.
  • the substrate support pedestal 152 and the target 142 may be separated by a distance between about 100 mm and about 300 mm for a 200 mm substrate.
  • the substrate support pedestal 152 and the target 142 may be separated by a distance between about 150 mm and about 400 mm for a 300 mm substrate. Any separation between the substrate and target that is greater than 50% of the substrate diameter is considered a long throw processing chamber.
  • a RF power supply 156 in some applications is connected to the pedestal electrode 152 in order to induce a negative DC self-bias on the substrate 154 , but in other applications the pedestal 152 is grounded or left electrically floating.
  • the D.C. power supply 148 or another power supply may be used to apply a negative bias, for example, between about 0 V and about 500 V, to the substrate support pedestal 152 .
  • the pedestal 152 is vertically movable through a bellows 158 connected to a lower chamber wall 160 to allow the substrate 154 to be transferred onto the pedestal 152 through an load lock valve (not shown) in the lower portion of the chamber and thereafter raised to a deposition position.
  • Processing working gas is supplied from a gas source 162 through a mass flow controller 164 into the lower part of the chamber.
  • a vacuum pumping system 166 connected through a pumping port 168 in the lower chamber is capable of maintaining the chamber at a base pressure of less than 10 ⁇ 6 Torr, but the processing pressure within the chamber is typically maintained at between 0.2 and 2 milliTorr, preferably less than 1 milliTorr, for cobalt sputtering.
  • the processing gas includes non-reactive or inert species such as argon (Ar), xenon (Xe), helium (He), or combinations thereof.
  • a rotatable magnetron 170 is positioned in back of the target 142 and includes a plurality of horseshoe magnets 172 supported by a base plate 174 connected to a rotation shaft 176 coincident with the central axis of the chamber 140 and the substrate 154 .
  • the horseshoe magnets 172 are arranged in closed pattern typically having a kidney shape. They produce a magnetic field within the chamber, generally parallel and close to the front face of the target 142 to trap electrons and thereby increase the local plasma density, which in turn increases the sputtering rate.
  • the magnets 172 are rotated so as to more uniformly sputter the target 142 and coat the substrate 154 .
  • the chamber 36 of the invention includes a grounded bottom shield 180 having, as is more clearly illustrated in the exploded cross-sectional view of FIG. 4, an upper flange 182 supported on and electrically connected to a ledge 184 of the adapter 144 .
  • a dark space shield 186 is supported on the flange 182 of the bottom shield 180 , and screws (not shown) recessed in the upper surface of the dark space shield 186 fix it and the flange 182 to the adapter ledge 184 having tapped holes receiving the screws.
  • This metallic threaded connection grounds the two shields 180 , 186 to the adapter 144 .
  • Both shields 180 , 186 are typically formed from hard, non-magnetic stainless steel.
  • the dark space shield 186 has an upper portion that closely fits an annular side recess of the target 142 with a narrow gap 188 between the dark space shield 186 and the target 142 which is sufficiently narrow to prevent the plasma to penetrate, hence protecting the ceramic isolator 146 from being sputter coated with a metal layer, which would electrically short the target 142 .
  • the dark space shield 186 also includes a downwardly projecting tip 190 , which prevents the interface between the bottom shield 180 and dark space shield 186 from becoming bonded by sputter deposited metal.
  • the bottom shield 180 extends downwardly in a upper generally tubular portion 194 of a first diameter and a lower generally tubular portion 196 of a smaller second diameter to extend generally along the walls of the adapter 144 and the chamber body 150 to below the top surface of the pedestal 152 . It also has a bowl-shaped bottom including a radially extending bottom portion 198 and an upwardly extending inner portion 100 just outside of the pedestal 152 .
  • a cover ring 102 rests on the top of the upwardly extending inner portion 100 of the bottom shield 180 when the pedestal 152 is in its lower, loading position but rests on the outer periphery of the pedestal 152 when it is in its upper, deposition position to protect the pedestal 152 from sputter deposition.
  • An additional deposition ring (not shown) may be used to shield the periphery of the substrate 154 from deposition.
  • the chamber 36 may also be adapted to provide a more directional sputtering of material onto a substrate.
  • directional sputtering may be achieved by positioning a collimator 110 positioned between the target 142 and the substrate support pedestal 152 to provide a more uniform and symmetrical flux of deposition material on the substrate 154 .
  • a metallic ring collimator 110 rests on the ledge portion 106 of the lower shield, thereby grounding the collimator 110 .
  • the ring collimator 110 includes, as better illustrated in the plan view of FIG. 5, three concentric tubular sections 112 , 114 , 116 linked by cross struts 118 , 120 .
  • the outer tubular section 116 rests on the ledge portion 106 of the lower shield 180 .
  • the use of the lower shield 180 to support the collimator 110 simplifies the design and maintenance of the chamber.
  • At least the two inner tubular sections 112 , 114 are sufficiently high to define high aspect-ratio apertures that partially collimate the sputtered particles.
  • the upper surface of the collimator 110 acts as a ground plane in opposition to the biased target 142 , particularly keeping plasma electrons away from the substrate 154 .
  • FIG. 6 Another type of collimator usable with the invention is a honeycomb collimator 124 , partially illustrated in the plan view of FIG. 6 having a mesh structure with hexagonal walls 126 separating hexagonal apertures 128 in a close-packed arrangement.
  • An advantage of the honeycomb collimator 124 is, if desired, the thickness of the collimator 124 can be varied from the center to the periphery of the collimator, usually in a convex shape, so that the apertures 128 have aspect ratios that are likewise varying across the collimator 124 .
  • the collimator may have one or more convex sides. This allows the sputter flux density to be tailored across the substrate, permitting increased uniformity of deposition. Collimators that may be used in the PVD chamber are described in U.S. Pat. No. 5,650,052, issued Jul. 22, 1997, which is hereby incorporated by reference herein to the extent not inconsistent with aspects of the invention and claims described herein.
  • embodiments of the substrate support pedestal 152 may be heated by resistive heaters electrically coupled to a power source and may be cooled by a thermal medium passing through fluid conductors connected fluid source, i.e., a liquid heat exchanger.
  • a thermal medium passing through fluid conductors connected fluid source i.e., a liquid heat exchanger.
  • Embodiments of the substrate support pedestal 152 are described below, and are provided for illustrative purposes and should not be construed or interpreted as limiting the scope of the invention.
  • FIG. 7A One embodiment of a substrate support pedestal 152 is shown in FIG. 7A.
  • the substrate support pedestal 152 is suitable for use in a high temperature high vacuum annealing process.
  • the substrate support pedestal 152 includes a heating portion 210 disposed on a base 240 coupled to a shaft 245 .
  • the heating portion 210 generally includes heating elements 250 disposed in a thermally conducting material 220 and a substrate support surface 275 .
  • the thermally conducting material 220 may be any material that has sufficient thermal conductance at operating temperatures for efficient heat transfer between the heating elements 250 and a substrate support surface 275 .
  • An example of the conducting material is steel.
  • the substrate support surface 275 may include a dielectric material and typically includes a substantially planar receiving surface for a substrate 280 disposed thereon.
  • the heating elements 250 may be resistive heating elements, such as electrically conducting wires having leads embedded within the conducting material 220 , and are provided to complete an electrical circuit by which electricity is passed through the conducting material 220 .
  • An example of a heating element 250 includes a discrete heating coil disposed in the thermally conducting material 220 . Electrical wires connect a voltage source (not shown) to the ends of the electrically resistive heating coil to provide energy sufficient to heat the coil.
  • the coil may take any shape that covers the area of the substrate support pedestal 152 . More than one coil may be used to provide additional heating capability, if needed.
  • the body provides support for the heating portion and includes fluid channels 290 disposed therein.
  • the fluid channels 290 are generally coupled to a surface of the heating portion 210 and may provide for either heating or cooling of the substrate support pedestal 152 .
  • the combination of heating elements 250 and fluid channels 290 generally achieve temperature control of the surface of the substrate support pedestal 152 .
  • the fluid channels 290 may include a concentric ring or series of rings, or other desired configuration, having fluid inlets and outlets for circulating a liquid from a remotely located source (not shown).
  • the fluid channels 290 are connected to the fluid source 294 by fluid passage 292 formed in the shaft 245 of substrate support pedestal 152 .
  • the heating elements 250 can heat the substrate on the substrate support pedestal up to about 900° C. and the fluid channels may cool the substrate to a temperature of about 0° C.
  • the combination of heating elements 250 and the fluid channels 290 are generally used to control the temperature of a substrate 280 between about 10° C. and about 900° C., subject to properties of materials used in substrate support pedestal 152 and the process parameters used for processing a substrate in the chamber 36 .
  • Temperature sensors 260 may be attached to or embedded in the substrate support pedestal 152 , such as adjacent the heating portion 210 , to monitor temperature in a conventional manner. For example, measured temperature may be used in a feedback loop to control electric current applied to the resistive heaters from a power supply, such that substrate temperature can be maintained or controlled at a desired temperature or within a desired temperature range.
  • a control unit (not shown) may be used to receive a signal from temperature sensor and control the heat power supply or a fluid source in response.
  • the power supply and the fluid supply of the heating and cooling components are generally located external of the chamber 36 .
  • each of the resistive heaters communicate via voltage sources by wires disposed through utility passages (not shown) formed in the base 240 and shaft 245 of the substrate support pedestal 152 and are coupled to utility sources, such as power, located externally to the chamber 36 .
  • the utility passages, including the fluid passage 294 are disposed axially along the base 240 and shaft 245 of the substrate support pedestal 152 .
  • a protective, flexible sheath 295 is disposed around the shaft 245 and extends from the substrate support pedestal 152 to the chamber wall (not shown) to prevent contamination between the substrate support pedestal 152 and the inside of the chamber.
  • the substrate support pedestal 152 may further contain gas channels (not shown) fluidly connecting with the substrate receiving surface 275 of the heating portion 210 to a source of backside gas (not shown).
  • the fluid channels 270 define a backside gas passage control passage of a heat transfer gas or masking gas between the heating portion and the substrate 280 .
  • a support pedestal disposed in the chamber may include an electrostatic chuck for supporting a substrate during deposition.
  • electrostatic chucks include MCATM Electrostatic E-chuck or Pyrolytic Boron Nitride Electrostatic E-Chuck, both available from Applied Materials, Inc., of Santa Clara, Calif.
  • FIG. 7B illustrates another embodiment of the substrate support pedestal 152 having an electrostatic chuck 210 mounted to or forming the heating portion of the substrate support pedestal 152 .
  • the electrostatic chuck 210 includes an electrode 230 and a substrate receiving surface 275 coated with a dielectric material 235 . Electrically conducting wires (not shown) couple the electrodes 230 to a voltage source (not shown).
  • a substrate 280 may be placed in contact with the dielectric material 235 , and a direct current voltage is placed on the electrode 230 to create the electrostatic attractive force to grip the substrate.
  • the electrodes 230 are disposed in the thermally conducting material 220 in a spaced relationship with the heating elements 250 disposed therein.
  • the heating elements 250 are generally disposed in a vertically spaced and parallel manner from the electrodes 230 in the thermally conducting material 220 .
  • the electrodes are disposed between the heating elements and the substrate receiving surface 275 though other configurations may be used.
  • Fluid channels 290 disposed on a bottom portion of the electrostatic chuck 210 may also be used to achieve temperature control of the substrate support pedestal 152 and are connected to the fluid source by fluid passage 292 formed in the substrate support pedestal base 240 .
  • Temperature sensors 260 are attached to or embedded in the electrostatic chuck 210 to monitor temperature.
  • the electrostatic chuck 210 may further contain channels 270 formed in the substrate support pedestal 152 fluidly connecting with the substrate receiving surface 275 of the electrostatic chuck 210 to a source of backside gas (not shown).
  • the fluid channels 270 define a backside gas passage control passage of a heat transfer gas or masking gas between the electrostatic chuck 210 and the substrate 280 .
  • the embodiments of the substrate support pedestals 152 described above may be used to form a high vacuum anneal chamber.
  • the high vacuum anneal chamber may include substrate support pedestals 152 disposed in a PVD chamber, such as the long throw chamber 36 described herein, with a blank target disposed therein or without a target and without bias coupled to either the target or substrate support pedestal.
  • a substrate is disposed on the substrate support pedestal, and the substrate is heated, with or without the presence of a backside gas, by the heating elements 250 to the desired processing temperature, processed for sufficient time to anneal the substrate for the desired anneal results, and then removed from the chamber.
  • substrate support pedestal 152 may be used to anneal the substrate
  • commercially available anneal chambers such as rapid thermal anneal (RTA) chambers may also be used to anneal the substrate to form the silicide films.
  • RTA rapid thermal anneal
  • the invention contemplates utilizing a variety of thermal anneal chamber designs, including hot plate designs and heated lamp designs, to enhance the electroplating results.
  • One particular thermal anneal chamber useful for the present invention is the WxZTM chamber available from Applied materials, Inc., located in Santa Clara, Calif.
  • One particular hot plate thermal anneal chamber useful for the present invention is the RTP XEplus Centura® thermal processing chamber available from Applied Materials, Inc., located in Santa Clara, Calif.
  • One particular lamp anneal chamber is the RadianceTM thermal processing chamber available from Applied Materials, Inc., located in Santa Clara, Calif.
  • Anneal chambers capable of operating at vacuum pressures may be disposed on the PVD transfer chamber 50 , to allow post deposition annealing without breaking vacuum.
  • Anneal chamber that are capable of operating at near atmosphere pressures may be disposed on the first transfer chamber 48 .
  • PVD deposition chambers with cobalt targets are disposed on the first transfer chamber 48 and the anneal chambers 41 that are capable of operating at near atmosphere pressures may be disposed on the second transfer chamber 50 .
  • the deposition and annealing step used in forming a metal silicide layer may be formed in situ, such as in a deposition chamber or in a processing system without breaking vacuum.
  • In situ is broadly defined herein as performing two or more processes in the same chamber or in the same processing system without breaking vacuum.
  • in situ annealing may be performed in the same processing chamber as the metal deposition.
  • in situ annealing may be performed in a chamber adjacent to the deposition chamber, both of which are coupled to a transfer chamber, and the vacuum on the transfer chamber is not broken during processing.
  • in situ annealing may be performed on the same processing system at separate processing pressures, such as processing a substrate in processing chambers and annealing chambers disposed on the first and second transfer chambers 48 , 50 , respectfully, in system 35 without breaking the vacuum on the system 35 or tranfer of th substrate to another processing system.
  • the invention contemplates the use of other materials, including titanium, tantalum, tungsten, molybdenum, platinum, nickel, iron, niobium, palladium, and combinations thereof, to form the metal silicide material as described herein.
  • a metal layer may be deposited on a silicon substrate disposed in chamber 36 and annealed on the substrate pedestal 152 to form the metal silicide layer without breaking vacuum.
  • Metal for forming the metal silicide layer is deposited using the PVD chamber 36 described above.
  • the target 142 of material, such as cobalt, to be deposited is disposed in the upper portion of the chamber 36 .
  • a substrate 154 is provided to the chamber 36 and disposed on the substrate support pedestal 152 .
  • the substrate 154 includes silicon material disposed thereon and is generally patterned to define features into which metal silicide films will be formed.
  • a processing gas is introduced into the chamber 38 at a flow rate of between about 5 sccm and about 30 sccm.
  • the chamber pressure is maintained below about 5 milliTorr to promote deposition of conformal PVD metal layers.
  • a chamber pressure between about 0.2 milliTorr and about 2 milliTorr may be used during deposition. More preferably, a chamber pressure between about 0.2 milliTorr and about 1.0 milliTorr has been observed to be sufficient for sputtering cobalt onto a substrate.
  • a plasma is generated by applying a power level to the target 142 between about 0 volts (V) and about 2400 V.
  • a power level is delivered to the target 142 at between about 0 V and about 1000 V to sputter material on a 200 mm substrate.
  • a power level between about 0 V and about 500 V may be applied to the substrate support pedestal 152 to improve directionality of the sputtered material to the substrate surface.
  • the substrate is maintained at a temperature between about 10° C. and about 500° C. during the deposition process.
  • An example of a deposition process includes introducing an inert gas, such as argon, into the chamber at a flow rate between about 5 sccm and about 30 sccm, maintaining a chamber pressure between about 0.2 milliTorr and about 1.0 milliTorr, applying a negative bias of between about 0 volts and about 1000 volts to the target 142 to excite the gas into a plasma state, maintaining the substrate at a temperature between about 10° C. and about 500° C., preferably about 50° C. and about 300° C., and most preferably, between about 50° C. and about 100° C.
  • an inert gas such as argon
  • Cobalt may be deposited on the silicon material at a rate between about 300 ⁇ /min and about 2000 ⁇ /min using this process.
  • the cobalt and silicon layer is then annealed in situ at a temperature between about 300° C. and about 900° C. for between about 10 seconds and about 600 seconds to form the metal silicide layer.
  • the annealing process may be performed under an inert gas environment in the deposition chamber by first introducing an inert gas into the chamber at a flow rate between about 0 sccm (Le., no backside gas) and about 15 sccm, maintaining a chamber pressure between of about 2 milliTorr or less, heating the substrate to a temperature between about 300° C. and about 900° C. for between about 5 seconds and about 600 seconds to form the metal silicide layer.
  • the metal may be deposited at substrate temperature of 200° C. or less, and then rapidly annealed on the substrate support pedestal 152 at temperatures of about 400° C. or greater by introducing a backside gas flow.
  • An example of a deposition process includes introducing an inert gas, such as argon, into the chamber at a flow rate between about 5 sccm and about 30 sccm, maintaining a chamber pressure between about 0.2 milliTorr and about 1.0 milliTorr, applying a negative bias of between about 0 volts and about 1000 volts to the target 142 to excite the gas into a plasma state, maintaining the substrate at a temperature of about 200° C., and spacing the target between about 100 mm and about 300 mm from the substrate surface for a 200 mm substrate.
  • an inert gas such as argon
  • the substrate temperature may be maintained at about 200° C. by heating the substrate in the absence of a backside gas at a heating level that would normally heat the substrate to temperatures of 400° C. or greater. This reduced temperature control is achieved by inefficient heat transfer between the pedestal surface and the backside of the substrate at vacuum pressures. Cobalt may be deposited on the silicon material at a rate between about 300 ⁇ /min and about 2000 ⁇ /min using this process.
  • the annealing process can then be performed in the deposition chamber by ending the plasma and applying a backside gas to the substrate support to enhance heating of the substrate to a temperature between about 400° C. and 600° C. at the same heating levels used for the deposition process.
  • the annealing process is performed at a temperature between about 400° C. and about 600° C. for between about 5 seconds and about 300 seconds.
  • the substrate is annealed in the deposition chamber at 500° C. for between about 60 seconds and 120 seconds.
  • the metal layer may be physical vapor deposited on a silicon substrate in chamber 36 , annealed for a first temperature for a first period of time, transferred to a second chamber, for example chamber 41 , in the system 35 , and annealed at a second temperature for a second period of time to form the metal suicide layer without breaking vacuum.
  • the physical vapor deposition of the metal is performed as described above at a temperature of about 200° C. or less, preferably between about 0° C. and about 100° C.
  • the first step of the two step in situ annealing process described above may be performed under an inert gas environment in the deposition chamber by first introducing an inert gas into the chamber at a flow rate between about 0 sccm and about 15 sccm, maintaining a chamber pressure between about 0 milliTorr and about 2 milliTorr, heating the substrate to a temperature between about 400° C. and about 600° C. for between about 5 seconds and about 300 seconds.
  • the substrate is annealed in the deposition chamber at 500° C. for between about 60 seconds and 120 seconds.
  • the substrate is then removed from the deposition chamber and transferred to a vacuum anneal chamber disposed on the same transfer chamber, such as transfer chamber 48 described above in FIG. 2.
  • the high vacuum anneal chamber may include a PVD chamber having a blank target and substrate support pedestal 152 described above or a commercial high vacuum anneal pedestal, such as the High Temperature High Uniformity, HTHUTM substrate support commercially available from Applied Materials Inc., of Santa Clara Calif.
  • the second annealing step may then be performed by maintaining a chamber pressure between about 0 milliTorr and about 2 milliTorr and heating the substrate to a temperature between about 600° C. and about 900° C. for a period of time between about 5 seconds and about 300 seconds to form the metal silicide layer.
  • the substrate is annealed in the anneal chamber at 800° C. for between about 60 seconds and 120 seconds.
  • the metal layer is deposited according to the process described herein at about 200° C. or less, preferably between about 0° C. and about 100° C., in the deposition chamber.
  • the substrate is then annealed in the deposition chamber according to the anneal process described above.
  • the substrate may then be transferred to a RTA chamber disposed on transfer chamber 50 in FIG. 2 for a second anneal process.
  • Annealing in an RTA anneal chamber may be performed by introducing a process gas including nitrogen (N 2 ), argon (Ar), helium (He), and combinations thereof, with less than about 4% hydrogen (H 2 ), at a process gas flow rate greater than 20 liters/min to control the oxygen content to less than 100 ppm, maintaining a chamber pressure of about ambient, and heating the substrate to a temperature between about 600° C. and about 900° C. for between about 5 seconds and about 300 seconds to form the metal silicide layer.
  • the substrate is annealed in the RTA anneal chamber at 800° C. for about 30 seconds.
  • the metal layer may be deposited on a silicon substrate in chamber 36 , transferred to a first anneal chamber, such as a vacuum anneal chamber disposed on the same transfer chamber 48 on the system 35 , annealed for a first temperature for a first period of time, transferred to a second anneal chamber, for example chamber 41 , in the system 35 , and annealed at a second temperature for a second period of time to form the metal suicide layer without breaking vacuum.
  • a first anneal chamber such as a vacuum anneal chamber disposed on the same transfer chamber 48 on the system 35
  • annealed for a first temperature for a first period of time transferred to a second anneal chamber, for example chamber 41 , in the system 35 , and annealed at a second temperature for a second period of time to form the metal suicide layer without breaking vacuum.
  • the metal deposition is performed in the deposition chamber according to the process described above at a substrate temperature of about 200° C. or less, preferably between about 0° C. and about 100° C.
  • the first step of this embodiment of the annealing process may be performed in situ in a first high vacuum anneal chamber disposed on a processing system by introducing an inert gas into the anneal chamber at a flow rate between about 0 sccm and about 15 sccm, maintaining a chamber pressure between about 0 milliTorr and about 2 milliTorr, heating the substrate to a temperature between about 400° C. and about 600° C. for between about 5 seconds and about 300 seconds.
  • the substrate is annealed in the deposition chamber at 500° C. for between about 60 seconds and 120 seconds.
  • the first annealing step is believed to form an oxygen resistant film such as CoSi.
  • the substrate may be annealed in situ by transfer to a second high vacuum annealing chamber in the processing system.
  • the second annealing step may then be performed by maintaining a chamber pressure of about 2 milliTorr or less and heating the substrate to a temperature between about 600° C. and about 900° C. for a period of time between about 5 seconds and about 300 seconds to form the metal silicide layer.
  • the substrate is annealed in the anneal chamber at 800° C. for between about 60 seconds and 120 seconds.
  • the substrate may be transferred to a second annealing chamber located outside the transfer chamber or processing system, such as an atmosphere pressure RTA chamber.
  • Annealing in an RTA anneal chamber may be performed by introducing a process gas including nitrogen (N 2 ), argon (Ar), helium (He), and combinations thereof, with less than about 4% hydrogen (H 2 ), at a process gas flow rate greater than 20 liters/min to control the oxygen content to less than 100 ppm, maintaining a chamber pressure of about ambient, and heating the substrate to a temperature between about 400° C. and about 900° C. for between about 5 seconds and about 300 seconds to form the metal suicide layer.
  • the substrate is annealed in the RTA anneal chamber at 800° C. for about 30 seconds.
  • the metal may be deposited at a high deposition temperature.
  • An example of a deposition process includes introducing an inert gas, such as argon, into the chamber at a flow rate between about 5 sccm and about 30 sccm, maintaining a chamber pressure between about 0.2 milliTorr and about 1.0 milliTorr, applying a negative bias of between about 0 volts and about 1000 volts to the target 142 to excite the gas into a plasma state, maintaining the substrate at about an annealing temperature, Le., between about 400° C. and about 600° C. by applying a backside gas, and spacing the target between about 100 mm and about 300 mm from the substrate surface for a 200 mm substrate.
  • the temperature may be maintained at about 200° C. by heating the substrate in the absence of a backside gas.
  • Cobalt may be deposited on the silicon material at a rate between about 300 ⁇ /min and about 2000 ⁇ /min using this process.
  • the annealing process can then be performed in the deposition chamber by ending the plasma and heating of the substrate to a temperature between about 400° C. and 600° C. at the same heating levels used for the deposition process.
  • the annealing process is performed at a temperature between about 400° C. and about 600° C. for between about 5 seconds and about 300 seconds.
  • the substrate is annealed in the deposition chamber at 500° C. for between about 60 seconds and 120 seconds.
  • the second annealing step may then be formed in an annealing chamber without breaking vacuum or in an annealing chamber located on a separate transfer chamber or processing system.
  • the second annealing step includes heating the substrate to a temperature between about 600° C. and about 900° C. for a period of time between about 5 seconds and about 300 seconds to form the metal silicide layer.
  • the substrate is annealed at 800° C. for between about 60 seconds and 120 seconds.
  • the metal silicide material including suicides of cobalt, titanium, tantalum, tungsten, molybdenum, platinum, nickel, iron, niobium, palladium, and combinations thereof, may be used in the formation of a MOS device shown in FIG. 8.
  • N+ source and drain regions 402 and 404 are formed in a P type silicon substrate 400 adjacent field oxide portions 406 .
  • a gate oxide layer 408 and a polysilicon gate electrode 410 are formed over silicon substrate 400 in between source and drain regions 402 and 404 with oxide spacers 412 formed on the sidewalls of polysilicon gate electrode 410 .
  • a cobalt layer is deposited over the MOS structure, and in particular over the exposed silicon surfaces of source and drain regions 402 and 404 and the exposed top surface of polysilicon gate electrode 410 by the process described herein.
  • the cobalt material is deposited to a thickness of at about 1000 ⁇ or less to provide a sufficient amount of cobalt for the subsequent reaction with the underlying silicon at 402 and 404 .
  • Cobalt may be deposited to a thickness between about 50 ⁇ and about 500 ⁇ on the silicon material.
  • the cobalt layer is then annealed in situ as described herein to form cobalt silicide.

Abstract

Methods and apparatus are provided for annealing of materials deposited in a processing chamber to form silicide layers. In one aspect, a method is provided for treating a substrate surface including positioning a substrate having silicon material disposed thereon on a substrate support in a chamber, forming a metal layer on at least the silicon material, and annealing the substrate in situ to form a metal silicide layer. In another aspect, the method is performed in an apparatus including a load lock chamber, an intermediate substrate transfer region connected to the load lock chamber, the intermediate substrate transfer region comprising a first substrate transfer chamber and a second substrate transfer chamber, a physical vapor deposition processing chamber disposed on the first substrate transfer chamber and an annealing chamber disposed on the second substrate transfer chamber.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to the fabrication of semiconductor devices and to the deposition and annealing of materials on a semiconductor substrate. [0002]
  • 2. Description of the Related Art [0003]
  • Recent improvements in circuitry of ultra-large scale integration (ULSI) on semiconductor substrates indicate that future generations of semiconductor devices will require sub-quarter micron multi-level metallization. The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die. [0004]
  • ULSI circuits include metal oxide semiconductor (MOS) devices, such as complementary metal oxide semiconductor (CMOS) field effect transistors (FETs). The transistors can include semiconductor gates disposed between source and drain regions. In the formation of integrated circuit structures, and particularly in the formation of MOS devices using polysilicon gate electrodes, it has become the practice to provide a metal silicide layer over the polysilicon gate electrode, and over the source and drain regions of the silicon substrate, to facilitate lower resistance and improve device performance by electrically connecting the source and drain regions to metal interconnects. [0005]
  • One important processing technique currently used in CMOS processing technology is the Self-Aligned Silicidation (salicide) of refractory metals such as titanium and cobalt. In a salicide process using cobalt (Co), for example, the source and drain and polysilicon gate resistances are reduced by forming a high conductivity overlayer and the contact resistance is reduced by increasing the effective contact area of the source and drain with subsequently formed metal interconnects. Salicide processing technology seeks to exploit the principle that a refractory metal such as cobalt deposited on a patterned silicon substrate will selectively react with exposed silicon under specific processing conditions, and will not react with silicon oxide material. [0006]
  • For example, a layer of cobalt is sputtered onto silicon, typically patterned on a substrate surface, and then subjected to a thermal annealing process to form cobalt silicide (CoSi[0007] 2). Unreacted cobalt, such as cobalt deposited outside the patterned silicon or on a protective layer of silicon oxide, can thereafter be selectively etched away. The selective reaction of cobalt silicide will result in maskless, self-aligned formation of a low-resistivity refractory metal silicide in source, drain, and polysilicon gate regions formed on the substrate surface and in interconnecting conductors of the semiconductor device. After the etch process, further processing of the substrate may occur, such as additional thermal annealing, which may be used to further reduce the sheet resistance of the silicide material.
  • However, it has been difficult in integrating cobalt silicide processes into conventional manufacturing equipment. Current processing systems performing cobalt silicide processes require transfer of the substrate between separate chambers for the deposition and annealing process steps. Transfer between chambers may expose the substrate to contamination and potential oxidation of silicon or cobalt deposited on the substrate surface [0008]
  • Oxide formation on the surface of the substrate can result in increasing the resistance of silicide layers as well reducing the reliability of the overall circuit. For example, oxidation of the deposited cobalt material may result in cobalt agglomeration and irregular growth of the silicide layer. The agglomeration and irregular growth of the cobalt layer may result in device malformation, such as source and drain electrodes having different thicknesses and surface areas. Additionally, excess cobalt silicide growth on substrate surface may form conductive paths between devices, which may result in short circuits and device failure. [0009]
  • One solution to limiting cobalt and silicon contamination is to sputter a capping film of titanium or titanium nitride on the cobalt and silicon film prior to transferring the substrate between chambers. The capping film is then removed after annealing the substrate and prior to further processing of the substrate. However, the addition of titanium nitride deposition and removal processes increase the number of processing steps required for silicide formation, thereby reducing process efficiency, increasing processing complexity, and reducing substrate through-put. [0010]
  • Therefore, there is a need for a method and apparatus for forming suicide materials on a substrate while reducing processing complexity and improving processing efficiency and throughput. [0011]
  • SUMMARY OF THE INVENTION
  • Embodiments of the invention described herein generally provide methods and apparatus for forming a metal suicide layer using a deposition and annealing process. In one aspect, a system is provided for processing a substrate including a load lock chamber, an intermediate substrate transfer region connected to the load lock chamber, the intermediate substrate transfer region comprising a first substrate transfer chamber and a second substrate transfer chamber, wherein the first substrate transfer chamber is coupled to the load lock chamber and the second substrate transfer chamber is coupled to the first substrate transfer chamber, a physical vapor deposition (PVD) processing chamber disposed on the first substrate transfer chamber and an annealing chamber disposed on the second substrate transfer chamber. [0012]
  • In another aspect, a method is provided for forming a silicide layer on a substrate including positioning a substrate having silicon material disposed thereon on a substrate support disposed in a deposition chamber having a metal target disposed therein, applying a current to the substrate support to heat the substrate to a first temperature, introducing an inert gas into the deposition chamber, generating a plasma by applying a bias between a metal target and the substrate support in the inert gas environment to sputter material from the metal target, depositing the sputtered material on at least the silicon material, providing a backside gas between the substrate pedestal and the substrate, and annealing the substrate in situ at a second temperature greater than the first temperature to form a metal silicide layer. [0013]
  • In another aspect, a method is provided for processing a substrate including introducing a substrate having silicon material disposed thereon into a load lock, transferring the substrate to a first transfer chamber having a physical vapor deposition processing chamber disposed thereon, the first transfer chamber is connected to the loadlock and the depositing chamber has a metal target and heating pedestal disposed therein, positioning the substrate into the physical vapor deposition chamber, depositing a metal layer on the silicon material, annealing the substrate prior to transferring the substrate to a second transfer chamber having an annealing chamber disposed thereon, wherein the second transfer chamber is connected to the first transfer chamber, and annealing the substrate in the annealing chamber to form a metal silicide layer.[0014]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • So that the manner in which the above recited aspects of the invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings. [0015]
  • It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. [0016]
  • FIG. 1 is schematic top view of one embodiment of an integrated multi-chamber apparatus suitable for depositing a conformal PVD layer on a semiconductor substrate and suitable for annealing the deposited layer; [0017]
  • FIG. 2 is schematic top view of another embodiment of an integrated multi-chamber apparatus suitable for depositing a conformal PVD layer on a semiconductor substrate and suitable for annealing the deposited layer [0018]
  • FIG. 3 is a cross-sectional view of one embodiment of a sputtering chamber included within the invention; [0019]
  • FIG. 4 is an expanded view of FIG. 3 including upper area of the shields near the target; [0020]
  • FIG. 5 is a plan view of one embodiment of a ring collimator; [0021]
  • FIG. 6 is a partial plan view of one embodiment of a honeycomb collimator; [0022]
  • FIG. 7A is a cross-sectional view of one embodiment of a pedestal for annealing a substrate; [0023]
  • FIG. 7B is a cross-sectional view of another embodiment of a pedestal for annealing a substrate; and [0024]
  • FIG. 8 is a simplified sectional view of a silicide material used as a contact with a transistor.[0025]
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Embodiments of the invention described herein provide methods and apparatus for forming a metal silicide layer in a deposition chamber or substrate processing system. One embodiment described below in reference to a physical vapor deposition (PVD) process is provided to illustrate the invention, and should not be construed or interpreted as limiting the scope of the invention. Aspects of the invention may be used to advantage in other processes, such as chemical vapor deposition, in which an anneal is desired for forming metal silicide layers. [0026]
  • FIG. 1 is schematic top view of one embodiment of an integrated multi-chamber substrate processing system suitable for performing at least one embodiment the metal deposition and annealing processes described herein. The deposition and annealing processes may be performed in a multi-chamber processing system or cluster tool having a PVD chamber disposed thereon. One processing platform that may be used to advantage is an Endura™ processing platform commercially available from Applied Materials, Inc., located in Santa Clara, Calif. [0027]
  • The [0028] processing platform 35 typically includes a cluster of process chambers including two transfer chambers 48, 50 and at least one long throw physical vapor deposition (PVD) chamber 36, additional processing chambers 38 and 40, and an annealing chamber 41. Generally, the annealing chambers 41 and the PVD chambers 36 are disposed in separate transfer chambers, which are operated at different vacuum pressures. Chambers 38 and 40 may include PVD chambers or chemical vapor deposition (CVD) chambers for depositing other materials as desired by the operator. Rapid thermal annealing (RTA) chambers that can anneal substrates at vacuum pressures may be used for the annealing chamber 41 on transfer chamber 48 or 50 based upon the configuration desired by the operator.
  • The [0029] processing platform 35 may further comprise one or more pre-clean chambers 42, such as PreClean II chambers available from Applied Materials, for removing contaminants, two degas chambers 44, and two load lock chambers 46. The processing platform 35 typically includes transfer robots 49, 51, disposed in transfer chambers 48, 50 respectfully, and two cooldown or pre-heating chambers 52 separating the transfer chambers 48, 50. The processing platform 35 is automated by programming a microprocessor controller 54. RTA chambers (not shown) may also be disposed on the first transfer chamber 48 of the processing platform 35 to provide post deposition annealing processes prior to substrate removal from the platform 35. While not shown, a plurality of vacuum pumps are disposed in fluid communication with each transfer chamber and each of the processing chambers to independently regulate pressures in the respective chambers. The pumps may establish a vacuum gradient of increasing pressure across the apparatus from the load lock chamber to the processing chambers.
  • FIG. 2 is a schematic top view of another embodiment of an integrated multi-chamber substrate processing system suitable for performing at least one embodiment the metal deposition and annealing processes described herein. In this embodiment, two PVD deposition chamber are disposed on the [0030] first transfer chamber 48 with two degas chambers 44, and two load lock chambers 46. One of the PVD deposition chambers may be substitute with a vacuum annealing chamber or a pre-clean chamber 42, such as the PreClean II chamber. Two annealing chambers 41, are disposed on the second transfer chamber 50. The operating pressure of the first transfer chamber 48 is generally lower than that for the second transfer chamber 50 since high vacuum PVD processes are performed on the first transfer chamber 48 and high pressure processes, such as atmosphere annealing processes, are performed on the second transfer chamber 50.
  • FIG. 3 illustrates one embodiment of a long throw physical vapor deposition chamber. Example of suitable long throw PVD chambers are ALPS plus™ and SIP™ PVD processing chambers, both commercially available from Applied Materials, Inc., Santa Clara, Calif. [0031]
  • Generally, the long [0032] throw PVD chamber 36 contains a sputtering source, such as a target 142, and a substrate support pedestal 152 for receiving a semiconductor substrate 154 thereon and located within a grounded enclosure wall 150, which may be a chamber wall as shown or a grounded shield.
  • The [0033] chamber 36 includes a target 142 supported on and sealed by O-rings to a grounded conductive aluminum adapter 144 through a dielectric isolator 146. The target 142 may be a bonded composite of a metallic cobalt surface layer and a backing plate of a more workable metal. The target 142 comprises the material to be deposited on the substrate surface during sputtering. The target may include, for example, materials including cobalt, titanium, tantalum, tungsten, molybdenum, platinum, nickel, iron, niobium, palladium, and combinations thereof, which are used in forming metal silicide layers. For example, targets comprising elemental cobalt, nickel cobalt alloys, or nickel iron alloys may be used as the target 142.
  • A controllable [0034] DC power source 148 applies a negative voltage or bias to the target 142, typically between about between about 0 V and about 2400 V to the target 142 to excite the gas into a plasma state. The adapter 144 in turn is sealed and grounded to an aluminum chamber sidewall 150. Ions from the plasma bombard the target 142 to sputter atoms and larger particles onto the substrate 154 disposed below. While, the power supplied is expressed in voltage, power may also be expressed as kilowatts or a power density (W/cm2). The amount of power supplied to the chamber may be varied depending upon the amount of sputtering and the size of the substrate size being processed.
  • A [0035] pedestal 152 supports a substrate 154 to be sputter coated in planar opposition to the principal face of the target 142. The substrate support pedestal 152 has a planar substrate receiving surface disposed generally parallel to the sputtering surface of the target 142. In operation, the substrate 154 is positioned on the substrate support pedestal 152 and plasma is generated in the chamber 36. A long throw distance of at least about 90 mm separates the target 142 and the substrate. The substrate support pedestal 152 and the target 142 may be separated by a distance between about 100 mm and about 300 mm for a 200 mm substrate. The substrate support pedestal 152 and the target 142 may be separated by a distance between about 150 mm and about 400 mm for a 300 mm substrate. Any separation between the substrate and target that is greater than 50% of the substrate diameter is considered a long throw processing chamber.
  • A [0036] RF power supply 156 in some applications is connected to the pedestal electrode 152 in order to induce a negative DC self-bias on the substrate 154, but in other applications the pedestal 152 is grounded or left electrically floating. The D.C. power supply 148 or another power supply may be used to apply a negative bias, for example, between about 0 V and about 500 V, to the substrate support pedestal 152. The pedestal 152 is vertically movable through a bellows 158 connected to a lower chamber wall 160 to allow the substrate 154 to be transferred onto the pedestal 152 through an load lock valve (not shown) in the lower portion of the chamber and thereafter raised to a deposition position.
  • Processing working gas is supplied from a [0037] gas source 162 through a mass flow controller 164 into the lower part of the chamber. A vacuum pumping system 166 connected through a pumping port 168 in the lower chamber is capable of maintaining the chamber at a base pressure of less than 10−6 Torr, but the processing pressure within the chamber is typically maintained at between 0.2 and 2 milliTorr, preferably less than 1 milliTorr, for cobalt sputtering. The processing gas includes non-reactive or inert species such as argon (Ar), xenon (Xe), helium (He), or combinations thereof.
  • A [0038] rotatable magnetron 170 is positioned in back of the target 142 and includes a plurality of horseshoe magnets 172 supported by a base plate 174 connected to a rotation shaft 176 coincident with the central axis of the chamber 140 and the substrate 154. The horseshoe magnets 172 are arranged in closed pattern typically having a kidney shape. They produce a magnetic field within the chamber, generally parallel and close to the front face of the target 142 to trap electrons and thereby increase the local plasma density, which in turn increases the sputtering rate. The magnets 172 are rotated so as to more uniformly sputter the target 142 and coat the substrate 154.
  • The [0039] chamber 36 of the invention includes a grounded bottom shield 180 having, as is more clearly illustrated in the exploded cross-sectional view of FIG. 4, an upper flange 182 supported on and electrically connected to a ledge 184 of the adapter 144. A dark space shield 186 is supported on the flange 182 of the bottom shield 180, and screws (not shown) recessed in the upper surface of the dark space shield 186 fix it and the flange 182 to the adapter ledge 184 having tapped holes receiving the screws. This metallic threaded connection grounds the two shields 180, 186 to the adapter 144. Both shields 180, 186 are typically formed from hard, non-magnetic stainless steel. The dark space shield 186 has an upper portion that closely fits an annular side recess of the target 142 with a narrow gap 188 between the dark space shield 186 and the target 142 which is sufficiently narrow to prevent the plasma to penetrate, hence protecting the ceramic isolator 146 from being sputter coated with a metal layer, which would electrically short the target 142. The dark space shield 186 also includes a downwardly projecting tip 190, which prevents the interface between the bottom shield 180 and dark space shield 186 from becoming bonded by sputter deposited metal.
  • Returning to the overall view of FIG. 3, the [0040] bottom shield 180 extends downwardly in a upper generally tubular portion 194 of a first diameter and a lower generally tubular portion 196 of a smaller second diameter to extend generally along the walls of the adapter 144 and the chamber body 150 to below the top surface of the pedestal 152. It also has a bowl-shaped bottom including a radially extending bottom portion 198 and an upwardly extending inner portion 100 just outside of the pedestal 152. A cover ring 102 rests on the top of the upwardly extending inner portion 100 of the bottom shield 180 when the pedestal 152 is in its lower, loading position but rests on the outer periphery of the pedestal 152 when it is in its upper, deposition position to protect the pedestal 152 from sputter deposition. An additional deposition ring (not shown) may be used to shield the periphery of the substrate 154 from deposition.
  • The [0041] chamber 36 may also be adapted to provide a more directional sputtering of material onto a substrate. In one aspect, directional sputtering may be achieved by positioning a collimator 110 positioned between the target 142 and the substrate support pedestal 152 to provide a more uniform and symmetrical flux of deposition material on the substrate 154.
  • A [0042] metallic ring collimator 110 rests on the ledge portion 106 of the lower shield, thereby grounding the collimator 110. The ring collimator 110 includes, as better illustrated in the plan view of FIG. 5, three concentric tubular sections 112, 114, 116 linked by cross struts 118, 120. The outer tubular section 116 rests on the ledge portion 106 of the lower shield 180. The use of the lower shield 180 to support the collimator 110 simplifies the design and maintenance of the chamber. At least the two inner tubular sections 112, 114 are sufficiently high to define high aspect-ratio apertures that partially collimate the sputtered particles. Further, the upper surface of the collimator 110 acts as a ground plane in opposition to the biased target 142, particularly keeping plasma electrons away from the substrate 154.
  • Another type of collimator usable with the invention is a [0043] honeycomb collimator 124, partially illustrated in the plan view of FIG. 6 having a mesh structure with hexagonal walls 126 separating hexagonal apertures 128 in a close-packed arrangement. An advantage of the honeycomb collimator 124 is, if desired, the thickness of the collimator 124 can be varied from the center to the periphery of the collimator, usually in a convex shape, so that the apertures 128 have aspect ratios that are likewise varying across the collimator 124. The collimator may have one or more convex sides. This allows the sputter flux density to be tailored across the substrate, permitting increased uniformity of deposition. Collimators that may be used in the PVD chamber are described in U.S. Pat. No. 5,650,052, issued Jul. 22, 1997, which is hereby incorporated by reference herein to the extent not inconsistent with aspects of the invention and claims described herein.
  • Referring to FIGS. 7A and 7B, embodiments of the [0044] substrate support pedestal 152 may be heated by resistive heaters electrically coupled to a power source and may be cooled by a thermal medium passing through fluid conductors connected fluid source, i.e., a liquid heat exchanger. Embodiments of the substrate support pedestal 152 are described below, and are provided for illustrative purposes and should not be construed or interpreted as limiting the scope of the invention.
  • One embodiment of a [0045] substrate support pedestal 152 is shown in FIG. 7A. The substrate support pedestal 152 is suitable for use in a high temperature high vacuum annealing process. Generally, the substrate support pedestal 152 includes a heating portion 210 disposed on a base 240 coupled to a shaft 245.
  • The [0046] heating portion 210 generally includes heating elements 250 disposed in a thermally conducting material 220 and a substrate support surface 275. The thermally conducting material 220 may be any material that has sufficient thermal conductance at operating temperatures for efficient heat transfer between the heating elements 250 and a substrate support surface 275. An example of the conducting material is steel. The substrate support surface 275 may include a dielectric material and typically includes a substantially planar receiving surface for a substrate 280 disposed thereon.
  • The [0047] heating elements 250 may be resistive heating elements, such as electrically conducting wires having leads embedded within the conducting material 220, and are provided to complete an electrical circuit by which electricity is passed through the conducting material 220. An example of a heating element 250 includes a discrete heating coil disposed in the thermally conducting material 220. Electrical wires connect a voltage source (not shown) to the ends of the electrically resistive heating coil to provide energy sufficient to heat the coil. The coil may take any shape that covers the area of the substrate support pedestal 152. More than one coil may be used to provide additional heating capability, if needed.
  • The body provides support for the heating portion and includes [0048] fluid channels 290 disposed therein. The fluid channels 290 are generally coupled to a surface of the heating portion 210 and may provide for either heating or cooling of the substrate support pedestal 152. The combination of heating elements 250 and fluid channels 290 generally achieve temperature control of the surface of the substrate support pedestal 152.
  • The [0049] fluid channels 290 may include a concentric ring or series of rings, or other desired configuration, having fluid inlets and outlets for circulating a liquid from a remotely located source (not shown). The fluid channels 290 are connected to the fluid source 294 by fluid passage 292 formed in the shaft 245 of substrate support pedestal 152.
  • The [0050] heating elements 250 can heat the substrate on the substrate support pedestal up to about 900° C. and the fluid channels may cool the substrate to a temperature of about 0° C. The combination of heating elements 250 and the fluid channels 290 are generally used to control the temperature of a substrate 280 between about 10° C. and about 900° C., subject to properties of materials used in substrate support pedestal 152 and the process parameters used for processing a substrate in the chamber 36.
  • [0051] Temperature sensors 260, such as a thermocouple, may be attached to or embedded in the substrate support pedestal 152, such as adjacent the heating portion 210, to monitor temperature in a conventional manner. For example, measured temperature may be used in a feedback loop to control electric current applied to the resistive heaters from a power supply, such that substrate temperature can be maintained or controlled at a desired temperature or within a desired temperature range. A control unit (not shown) may be used to receive a signal from temperature sensor and control the heat power supply or a fluid source in response.
  • The power supply and the fluid supply of the heating and cooling components are generally located external of the [0052] chamber 36. For example, each of the resistive heaters communicate via voltage sources by wires disposed through utility passages (not shown) formed in the base 240 and shaft 245 of the substrate support pedestal 152 and are coupled to utility sources, such as power, located externally to the chamber 36. The utility passages, including the fluid passage 294, are disposed axially along the base 240 and shaft 245 of the substrate support pedestal 152. A protective, flexible sheath 295 is disposed around the shaft 245 and extends from the substrate support pedestal 152 to the chamber wall (not shown) to prevent contamination between the substrate support pedestal 152 and the inside of the chamber.
  • The [0053] substrate support pedestal 152 may further contain gas channels (not shown) fluidly connecting with the substrate receiving surface 275 of the heating portion 210 to a source of backside gas (not shown). The fluid channels 270 define a backside gas passage control passage of a heat transfer gas or masking gas between the heating portion and the substrate 280.
  • A support pedestal disposed in the chamber may include an electrostatic chuck for supporting a substrate during deposition. Examples of suitable electrostatic chucks that may be used for the support pedestal include MCA™ Electrostatic E-chuck or Pyrolytic Boron Nitride Electrostatic E-Chuck, both available from Applied Materials, Inc., of Santa Clara, Calif. [0054]
  • FIG. 7B illustrates another embodiment of the [0055] substrate support pedestal 152 having an electrostatic chuck 210 mounted to or forming the heating portion of the substrate support pedestal 152. The electrostatic chuck 210 includes an electrode 230 and a substrate receiving surface 275 coated with a dielectric material 235. Electrically conducting wires (not shown) couple the electrodes 230 to a voltage source (not shown). A substrate 280 may be placed in contact with the dielectric material 235, and a direct current voltage is placed on the electrode 230 to create the electrostatic attractive force to grip the substrate.
  • Generally, the [0056] electrodes 230 are disposed in the thermally conducting material 220 in a spaced relationship with the heating elements 250 disposed therein. The heating elements 250 are generally disposed in a vertically spaced and parallel manner from the electrodes 230 in the thermally conducting material 220. Typically, the electrodes are disposed between the heating elements and the substrate receiving surface 275 though other configurations may be used. Fluid channels 290 disposed on a bottom portion of the electrostatic chuck 210 may also be used to achieve temperature control of the substrate support pedestal 152 and are connected to the fluid source by fluid passage 292 formed in the substrate support pedestal base 240. Temperature sensors 260 are attached to or embedded in the electrostatic chuck 210 to monitor temperature.
  • The [0057] electrostatic chuck 210 may further contain channels 270 formed in the substrate support pedestal 152 fluidly connecting with the substrate receiving surface 275 of the electrostatic chuck 210 to a source of backside gas (not shown). The fluid channels 270 define a backside gas passage control passage of a heat transfer gas or masking gas between the electrostatic chuck 210 and the substrate 280.
  • The embodiments of the substrate support pedestals [0058] 152 described above may be used to form a high vacuum anneal chamber. The high vacuum anneal chamber may include substrate support pedestals 152 disposed in a PVD chamber, such as the long throw chamber 36 described herein, with a blank target disposed therein or without a target and without bias coupled to either the target or substrate support pedestal. In operation, a substrate is disposed on the substrate support pedestal, and the substrate is heated, with or without the presence of a backside gas, by the heating elements 250 to the desired processing temperature, processed for sufficient time to anneal the substrate for the desired anneal results, and then removed from the chamber.
  • While the embodiments of [0059] substrate support pedestal 152 described herein may be used to anneal the substrate, commercially available anneal chambers, such as rapid thermal anneal (RTA) chambers may also be used to anneal the substrate to form the silicide films. The invention contemplates utilizing a variety of thermal anneal chamber designs, including hot plate designs and heated lamp designs, to enhance the electroplating results. One particular thermal anneal chamber useful for the present invention is the WxZ™ chamber available from Applied materials, Inc., located in Santa Clara, Calif. One particular hot plate thermal anneal chamber useful for the present invention is the RTP XEplus Centura® thermal processing chamber available from Applied Materials, Inc., located in Santa Clara, Calif. One particular lamp anneal chamber is the Radiance™ thermal processing chamber available from Applied Materials, Inc., located in Santa Clara, Calif.
  • Anneal chambers capable of operating at vacuum pressures may be disposed on the [0060] PVD transfer chamber 50, to allow post deposition annealing without breaking vacuum. Anneal chamber that are capable of operating at near atmosphere pressures may be disposed on the first transfer chamber 48. In the embodiment shown in FIG. 3, PVD deposition chambers with cobalt targets are disposed on the first transfer chamber 48 and the anneal chambers 41 that are capable of operating at near atmosphere pressures may be disposed on the second transfer chamber 50.
  • Metal Silicide Process [0061]
  • The deposition and annealing step used in forming a metal silicide layer may be formed in situ, such as in a deposition chamber or in a processing system without breaking vacuum. In situ is broadly defined herein as performing two or more processes in the same chamber or in the same processing system without breaking vacuum. For example, in situ annealing may be performed in the same processing chamber as the metal deposition. [0062]
  • In another example, in situ annealing may performed in a chamber adjacent to the deposition chamber, both of which are coupled to a transfer chamber, and the vacuum on the transfer chamber is not broken during processing. In a further example, in situ annealing may be performed on the same processing system at separate processing pressures, such as processing a substrate in processing chambers and annealing chambers disposed on the first and [0063] second transfer chambers 48, 50, respectfully, in system 35 without breaking the vacuum on the system 35 or tranfer of th substrate to another processing system.
  • While the following material describes the deposition of a cobalt film, the invention contemplates the use of other materials, including titanium, tantalum, tungsten, molybdenum, platinum, nickel, iron, niobium, palladium, and combinations thereof, to form the metal silicide material as described herein. [0064]
  • Metal Deposition [0065]
  • In one embodiment, a metal layer may be deposited on a silicon substrate disposed in [0066] chamber 36 and annealed on the substrate pedestal 152 to form the metal silicide layer without breaking vacuum. Metal for forming the metal silicide layer is deposited using the PVD chamber 36 described above. The target 142 of material, such as cobalt, to be deposited is disposed in the upper portion of the chamber 36. A substrate 154 is provided to the chamber 36 and disposed on the substrate support pedestal 152. The substrate 154 includes silicon material disposed thereon and is generally patterned to define features into which metal silicide films will be formed.
  • A processing gas is introduced into the [0067] chamber 38 at a flow rate of between about 5 sccm and about 30 sccm. The chamber pressure is maintained below about 5 milliTorr to promote deposition of conformal PVD metal layers. Preferably, a chamber pressure between about 0.2 milliTorr and about 2 milliTorr may be used during deposition. More preferably, a chamber pressure between about 0.2 milliTorr and about 1.0 milliTorr has been observed to be sufficient for sputtering cobalt onto a substrate.
  • A plasma is generated by applying a power level to the [0068] target 142 between about 0 volts (V) and about 2400 V. For example, a power level is delivered to the target 142 at between about 0 V and about 1000 V to sputter material on a 200 mm substrate. A power level between about 0 V and about 500 V may be applied to the substrate support pedestal 152 to improve directionality of the sputtered material to the substrate surface. The substrate is maintained at a temperature between about 10° C. and about 500° C. during the deposition process.
  • An example of a deposition process includes introducing an inert gas, such as argon, into the chamber at a flow rate between about 5 sccm and about 30 sccm, maintaining a chamber pressure between about 0.2 milliTorr and about 1.0 milliTorr, applying a negative bias of between about 0 volts and about 1000 volts to the [0069] target 142 to excite the gas into a plasma state, maintaining the substrate at a temperature between about 10° C. and about 500° C., preferably about 50° C. and about 300° C., and most preferably, between about 50° C. and about 100° C. during the sputtering process, and spacing the target between about 100 mm and about 300 mm from the substrate surface for a 200 mm substrate. Cobalt may be deposited on the silicon material at a rate between about 300 Å/min and about 2000 Å/min using this process.
  • General In-Situ Annealing Process [0070]
  • The cobalt and silicon layer is then annealed in situ at a temperature between about 300° C. and about 900° C. for between about 10 seconds and about 600 seconds to form the metal silicide layer. The annealing process may be performed under an inert gas environment in the deposition chamber by first introducing an inert gas into the chamber at a flow rate between about 0 sccm (Le., no backside gas) and about 15 sccm, maintaining a chamber pressure between of about 2 milliTorr or less, heating the substrate to a temperature between about 300° C. and about 900° C. for between about 5 seconds and about 600 seconds to form the metal silicide layer. [0071]
  • Deposition and Annealing Process with Backside Gases in the Deposition Chamber. [0072]
  • The metal may be deposited at substrate temperature of 200° C. or less, and then rapidly annealed on the [0073] substrate support pedestal 152 at temperatures of about 400° C. or greater by introducing a backside gas flow. An example of a deposition process includes introducing an inert gas, such as argon, into the chamber at a flow rate between about 5 sccm and about 30 sccm, maintaining a chamber pressure between about 0.2 milliTorr and about 1.0 milliTorr, applying a negative bias of between about 0 volts and about 1000 volts to the target 142 to excite the gas into a plasma state, maintaining the substrate at a temperature of about 200° C., and spacing the target between about 100 mm and about 300 mm from the substrate surface for a 200 mm substrate.
  • The substrate temperature may be maintained at about 200° C. by heating the substrate in the absence of a backside gas at a heating level that would normally heat the substrate to temperatures of 400° C. or greater. This reduced temperature control is achieved by inefficient heat transfer between the pedestal surface and the backside of the substrate at vacuum pressures. Cobalt may be deposited on the silicon material at a rate between about 300 Å/min and about 2000 Å/min using this process. [0074]
  • The annealing process can then be performed in the deposition chamber by ending the plasma and applying a backside gas to the substrate support to enhance heating of the substrate to a temperature between about 400° C. and 600° C. at the same heating levels used for the deposition process. The annealing process is performed at a temperature between about 400° C. and about 600° C. for between about 5 seconds and about 300 seconds. Preferably, the substrate is annealed in the deposition chamber at 500° C. for between about 60 seconds and 120 seconds. [0075]
  • Low Temperature Deposition and Two-Step In-Situ Annealing Process in Two Chambers [0076]
  • In another embodiment, the metal layer may be physical vapor deposited on a silicon substrate in [0077] chamber 36, annealed for a first temperature for a first period of time, transferred to a second chamber, for example chamber 41, in the system 35, and annealed at a second temperature for a second period of time to form the metal suicide layer without breaking vacuum.
  • The physical vapor deposition of the metal is performed as described above at a temperature of about 200° C. or less, preferably between about 0° C. and about 100° C. The first step of the two step in situ annealing process described above may be performed under an inert gas environment in the deposition chamber by first introducing an inert gas into the chamber at a flow rate between about 0 sccm and about 15 sccm, maintaining a chamber pressure between about 0 milliTorr and about 2 milliTorr, heating the substrate to a temperature between about 400° C. and about 600° C. for between about 5 seconds and about 300 seconds. Preferably, the substrate is annealed in the deposition chamber at 500° C. for between about 60 seconds and 120 seconds. [0078]
  • The substrate is then removed from the deposition chamber and transferred to a vacuum anneal chamber disposed on the same transfer chamber, such as [0079] transfer chamber 48 described above in FIG. 2. The high vacuum anneal chamber may include a PVD chamber having a blank target and substrate support pedestal 152 described above or a commercial high vacuum anneal pedestal, such as the High Temperature High Uniformity, HTHU™ substrate support commercially available from Applied Materials Inc., of Santa Clara Calif.
  • The second annealing step may then be performed by maintaining a chamber pressure between about 0 milliTorr and about 2 milliTorr and heating the substrate to a temperature between about 600° C. and about 900° C. for a period of time between about 5 seconds and about 300 seconds to form the metal silicide layer. Preferably, the substrate is annealed in the anneal chamber at 800° C. for between about 60 seconds and 120 seconds. [0080]
  • Low Temperature Deposition and Two-Step Anneal Process in Two Chambers [0081]
  • In an alternative embodiment of the two chamber deposition and anneal process, the metal layer is deposited according to the process described herein at about 200° C. or less, preferably between about 0° C. and about 100° C., in the deposition chamber. The substrate is then annealed in the deposition chamber according to the anneal process described above. The substrate may then be transferred to a RTA chamber disposed on [0082] transfer chamber 50 in FIG. 2 for a second anneal process.
  • Annealing in an RTA anneal chamber may be performed by introducing a process gas including nitrogen (N[0083] 2), argon (Ar), helium (He), and combinations thereof, with less than about 4% hydrogen (H2), at a process gas flow rate greater than 20 liters/min to control the oxygen content to less than 100 ppm, maintaining a chamber pressure of about ambient, and heating the substrate to a temperature between about 600° C. and about 900° C. for between about 5 seconds and about 300 seconds to form the metal silicide layer. Preferably, the substrate is annealed in the RTA anneal chamber at 800° C. for about 30 seconds.
  • Low Temperature Deposition and Two-Step Annealing Process in Three Chambers. [0084]
  • In another embodiment, the metal layer may be deposited on a silicon substrate in [0085] chamber 36, transferred to a first anneal chamber, such as a vacuum anneal chamber disposed on the same transfer chamber 48 on the system 35, annealed for a first temperature for a first period of time, transferred to a second anneal chamber, for example chamber 41, in the system 35, and annealed at a second temperature for a second period of time to form the metal suicide layer without breaking vacuum.
  • The metal deposition is performed in the deposition chamber according to the process described above at a substrate temperature of about 200° C. or less, preferably between about 0° C. and about 100° C. The first step of this embodiment of the annealing process may be performed in situ in a first high vacuum anneal chamber disposed on a processing system by introducing an inert gas into the anneal chamber at a flow rate between about 0 sccm and about 15 sccm, maintaining a chamber pressure between about 0 milliTorr and about 2 milliTorr, heating the substrate to a temperature between about 400° C. and about 600° C. for between about 5 seconds and about 300 seconds. Preferably, the substrate is annealed in the deposition chamber at 500° C. for between about 60 seconds and 120 seconds. The first annealing step is believed to form an oxygen resistant film such as CoSi. [0086]
  • The substrate may be annealed in situ by transfer to a second high vacuum annealing chamber in the processing system. The second annealing step may then be performed by maintaining a chamber pressure of about 2 milliTorr or less and heating the substrate to a temperature between about 600° C. and about 900° C. for a period of time between about 5 seconds and about 300 seconds to form the metal silicide layer. Preferably, the substrate is annealed in the anneal chamber at 800° C. for between about 60 seconds and 120 seconds. [0087]
  • Alternatively, the substrate may be transferred to a second annealing chamber located outside the transfer chamber or processing system, such as an atmosphere pressure RTA chamber. Annealing in an RTA anneal chamber may be performed by introducing a process gas including nitrogen (N[0088] 2), argon (Ar), helium (He), and combinations thereof, with less than about 4% hydrogen (H2), at a process gas flow rate greater than 20 liters/min to control the oxygen content to less than 100 ppm, maintaining a chamber pressure of about ambient, and heating the substrate to a temperature between about 400° C. and about 900° C. for between about 5 seconds and about 300 seconds to form the metal suicide layer. Preferably, the substrate is annealed in the RTA anneal chamber at 800° C. for about 30 seconds.
  • High Temperature Deposition and Annealing Process. [0089]
  • The metal may be deposited at a high deposition temperature. An example of a deposition process includes introducing an inert gas, such as argon, into the chamber at a flow rate between about 5 sccm and about 30 sccm, maintaining a chamber pressure between about 0.2 milliTorr and about 1.0 milliTorr, applying a negative bias of between about 0 volts and about 1000 volts to the [0090] target 142 to excite the gas into a plasma state, maintaining the substrate at about an annealing temperature, Le., between about 400° C. and about 600° C. by applying a backside gas, and spacing the target between about 100 mm and about 300 mm from the substrate surface for a 200 mm substrate. The temperature may be maintained at about 200° C. by heating the substrate in the absence of a backside gas. Cobalt may be deposited on the silicon material at a rate between about 300 Å/min and about 2000 Å/min using this process.
  • The annealing process can then be performed in the deposition chamber by ending the plasma and heating of the substrate to a temperature between about 400° C. and 600° C. at the same heating levels used for the deposition process. The annealing process is performed at a temperature between about 400° C. and about 600° C. for between about 5 seconds and about 300 seconds. Preferably, the substrate is annealed in the deposition chamber at 500° C. for between about 60 seconds and 120 seconds. [0091]
  • The second annealing step may then be formed in an annealing chamber without breaking vacuum or in an annealing chamber located on a separate transfer chamber or processing system. The second annealing step includes heating the substrate to a temperature between about 600° C. and about 900° C. for a period of time between about 5 seconds and about 300 seconds to form the metal silicide layer. Preferably, the substrate is annealed at 800° C. for between about 60 seconds and 120 seconds. [0092]
  • The metal silicide material, including suicides of cobalt, titanium, tantalum, tungsten, molybdenum, platinum, nickel, iron, niobium, palladium, and combinations thereof, may be used in the formation of a MOS device shown in FIG. 8. In the illustrated MOS structure, N+ source and drain [0093] regions 402 and 404 are formed in a P type silicon substrate 400 adjacent field oxide portions 406. A gate oxide layer 408 and a polysilicon gate electrode 410 are formed over silicon substrate 400 in between source and drain regions 402 and 404 with oxide spacers 412 formed on the sidewalls of polysilicon gate electrode 410.
  • A cobalt layer is deposited over the MOS structure, and in particular over the exposed silicon surfaces of source and drain [0094] regions 402 and 404 and the exposed top surface of polysilicon gate electrode 410 by the process described herein. The cobalt material is deposited to a thickness of at about 1000 Å or less to provide a sufficient amount of cobalt for the subsequent reaction with the underlying silicon at 402 and 404. Cobalt may be deposited to a thickness between about 50 Å and about 500 Å on the silicon material. The cobalt layer is then annealed in situ as described herein to form cobalt silicide.
  • The unreacted cobalt is removed from the substrate surface and the cobalt [0095]

Claims (36)

1. A system for processing a substrate, comprising:
a load lock chamber;
an intermediate substrate transfer region connected to the load lock chamber, the intermediate substrate transfer region comprising a first substrate transfer chamber and a second substrate transfer chamber, wherein the first substrate transfer chamber is coupled to the load lock chamber and the second substrate transfer chamber is coupled to the first substrate transfer chamber;
a physical vapor deposition (PVD) processing chamber disposed on the first substrate transfer chamber; and
an annealing chamber disposed on the second substrate transfer chamber.
2. The apparatus of claim 1, further comprising plurality of vacuum pumps communicating with the intermediate substrate transfer region and each of the processing chambers, wherein the plurality of pumps establish a vacuum gradient of increasing pressure across the apparatus from the load lock chamber to the processing chambers.
3. The apparatus of claim 1, wherein the second transfer chamber has a higher chamber pressure than the first substrate transfer chamber.
4. The apparatus of claim 1, wherein the PVD processing chamber has an annealing pedestal disposed therein.
5. The apparatus of claim 1, wherein the PVD processing chamber has a target of material selected from the group of cobalt, titanium, tantalum, tungsten, molybdenum, platinum, nickel, iron, niobium, palladium, and combinations thereof.
6. The apparatus of claim 1, wherein the PVD processing chamber comprises a cobalt target and an annealing pedestal disposed therein.
7. The apparatus of claim 1, wherein the annealing chamber comprises a rapid thermal annealing chamber.
8. The apparatus of claim 1, further comprising a chemical vapor deposition chamber disposed on the first substrate transfer chamber, the second substrate transfer chamber, or combinations thereof.
9. The apparatus of claim 1, wherein the apparatus comprises two PVD processing chambers comprising a cobalt target and an annealing pedestal disposed therein are disposed on the first transfer region and two annealing processing chambers are disposed on the second transfer chamber, wherein the second transfer chamber has a higher operating temperature than the first transfer chamber.
10. The apparatus of claim 1, wherein the physical vapor deposition (PVD) processing chamber comprises:
a chamber enclosing a sputtering source;
a substrate support member disposed generally parallel to the sputtering surface of the sputtering source, the substrate support member comprising:
a generally planar substrate receiving surface configured to receive a substrate thereon;
an electrically resistive heating element disposed in the substrate support member; and
a fluid channel connected to a fluid supply and regulated by a controller; and
a collimator mounted between the sputtering source and the substrate support member.
11. The apparatus of claim 10, wherein the substrate support member comprises:
an electrostatic chuck having an electrode, an electrical insulator having a generally planar substrate receiving surface disposed on the electrode and configured to receive a substrate thereon;
an electrically resistive heating element disposed in the electrostatic chuck; and
a fluid channel connected to a fluid supply and regulated by a controller.
12. The apparatus of claim 10, further comprising an electrically conductive lead for coupling the electrically resistive heating elements to a voltage source.
13. The apparatus of claim 12, further comprising at least one temperature sensor connected to the substrate support member.
14. The apparatus of claim 12, further comprising a source of gas connected to a channel disposed in the support pedestal, the channel connecting the source of gas to the planar substrate receiving surface.
15. The apparatus of claim 11, wherein the collimator has upper and lower surfaces and at least one of the surfaces being a convex surface.
16. A method for forming a silicide layer on a substrate, comprising:
positioning a substrate having silicon material disposed thereon on a substrate support disposed in a deposition chamber having a metal target disposed therein;
applying a current to the substrate support to heat the substrate to a first temperature;
introducing an inert gas into the deposition chamber;
generating a plasma by applying a bias between a metal target and the substrate support in the inert gas environment to sputter material from the metal target;
depositing the sputtered material on at least the silicon material;
providing a backside gas between the substrate pedestal and the substrate; and
annealing the substrate in situ at a second temperature greater than the first temperature to form a metal silicide layer.
17. The method of claim 16, wherein the substrate is positioned between about 90 mm and about 400 mm from the target.
18. The method of claim 16, wherein the metal material is selected from the group of cobalt, titanium, tantalum, tungsten, molybdenum, platinum, nickel, iron, niobium, palladium, and combinations thereof.
19. The method of claim 16, further comprising collimating the sputtered material.
20. The method of claim 16, wherein the first temperature is about 200° C. or less.
21. The method of claim 16, wherein annealing the substrate in situ at a second temperature comprises annealing the substrate at a temperature between about 300° C. and about 900° C. on the substrate support.
22. The method of claim 21, wherein the substrate is annealed for between about 10 seconds and about 600 seconds.
23. The method of claim 22, wherein annealing the substrate in situ comprises annealing the substrate at a second temperature for a first period of time in the deposition chamber, transferring the substrate to an annealing chamber, and annealing the substrate at a third temperature greater than the second temperature for a second period of time without breaking vacuum in a processing system.
24. The method of claim 23, wherein the second temperature is between about 300° C. and about 500° C. and the third temperature is between about 400° C. and about 900° C.
25. The method of claim 23, wherein the first period of time is between about 5 second and about 300 seconds and the second period of time is between about 5 seconds and about 300 seconds.
26. The method of claim 23, wherein annealing the substrate in situ comprises annealing the substrate at a second temperature higher than the first temperature in a first annealing chamber, transferring the substrate to a second annealing chamber, and then annealing the substrate at a third temperature higher than the second temperature for the second period of time without breaking vacuum in a processing system.
27. The method of claim 23, wherein the substrate surface is treated by annealing the substrate in the deposition chamber at a first temperature for a first period of time, transferring the substrate to the thermal annealing chamber, and annealing the substrate at a second temperature for a second period of time without breaking vacuum in the processing system.
28. A method of processing a substrate, comprising:
introducing a substrate having silicon material disposed thereon into a load lock;
transferring the substrate to a first transfer chamber in vacuum tight communication with the loadlock;
positioning the substrate on a heating pedestal in a physical vapor deposition chamber in vacuum tight communication with the first transfer chamber;
depositing a metal layer on the silicon material;
annealing the substrate prior to transferring the substrate to a second transfer chamber having an annealing chamber disposed thereon, wherein the second transfer chamber is in vacuum tight communication with the first transfer chamber; and
annealing the substrate in the annealing chamber to form a metal silicide layer.
29. The method of claim 28, wherein annealing the substrate prior to transferring the substrate comprises annealing the substrate in the physical vapor deposition processing chamber.
30. The method of claim 28, further comprising a vacuum annealing chamber in vacuum tight communication with the first transfer chamber.
31. The method of claim 30, wherein annealing the substrate in the annealing chamber comprises annealing the substrate in the vacuum annealing chamber.
32. The method of claim 28, wherein annealing the substrate comprises annealing the substrate at a temperature between about 300° C. and about 900° C. without breaking vacuum.
33. The method of claim 28, wherein depositing a metal layer comprises sputtering the metal target at a substrate temperature of about 200° C. or less.
34. The method of claim 28, wherein the second transfer chamber has a higher chamber pressure than the first substrate transfer chamber.
35. The method of claim 28, wherein the metal target comprises a material selected from the group of cobalt, titanium, tantalum, tungsten, molybdenum, platinum, nickel, iron, niobium, palladium, and combinations thereof.
36. The apparatus of claim 28, wherein the physical vapor deposition processing chamber comprises a cobalt target and an annealing pedestal disposed therein.
US09/916,234 2001-07-25 2001-07-25 An Apparatus For Annealing Substrates In Physical Vapor Deposition Systems Abandoned US20030029715A1 (en)

Priority Applications (17)

Application Number Priority Date Filing Date Title
US09/916,234 US20030029715A1 (en) 2001-07-25 2001-07-25 An Apparatus For Annealing Substrates In Physical Vapor Deposition Systems
US10/044,412 US6740585B2 (en) 2001-07-25 2002-01-09 Barrier formation using novel sputter deposition method with PVD, CVD, or ALD
PCT/US2002/023578 WO2003080887A2 (en) 2001-07-25 2002-07-25 Methods and apparatus for annealing in physical vapor deposition systems
JP2003578610A JP2006500472A (en) 2001-07-25 2002-07-25 Annealing method and apparatus in physical vapor deposition system
JP2003533324A JP2005504885A (en) 2001-07-25 2002-07-25 Barrier formation using a novel sputter deposition method
PCT/US2002/023581 WO2003030224A2 (en) 2001-07-25 2002-07-25 Barrier formation using novel sputter-deposition method
US10/845,970 US20040211665A1 (en) 2001-07-25 2004-05-14 Barrier formation using novel sputter-deposition method
US11/456,073 US7416979B2 (en) 2001-07-25 2006-07-06 Deposition methods for barrier and tungsten materials
US11/733,929 US8110489B2 (en) 2001-07-25 2007-04-11 Process for forming cobalt-containing materials
US12/111,923 US20090004850A1 (en) 2001-07-25 2008-04-29 Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US12/111,930 US20080268635A1 (en) 2001-07-25 2008-04-29 Process for forming cobalt and cobalt silicide materials in copper contact applications
US12/171,132 US7611990B2 (en) 2001-07-25 2008-07-10 Deposition methods for barrier and tungsten materials
US12/201,976 US9051641B2 (en) 2001-07-25 2008-08-29 Cobalt deposition on barrier surfaces
US12/969,445 US8187970B2 (en) 2001-07-25 2010-12-15 Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US13/452,237 US8815724B2 (en) 2001-07-25 2012-04-20 Process for forming cobalt-containing materials
US13/456,904 US8563424B2 (en) 2001-07-25 2012-04-26 Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US14/717,375 US9209074B2 (en) 2001-07-25 2015-05-20 Cobalt deposition on barrier surfaces

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/916,234 US20030029715A1 (en) 2001-07-25 2001-07-25 An Apparatus For Annealing Substrates In Physical Vapor Deposition Systems

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/044,412 Continuation-In-Part US6740585B2 (en) 2001-07-25 2002-01-09 Barrier formation using novel sputter deposition method with PVD, CVD, or ALD

Publications (1)

Publication Number Publication Date
US20030029715A1 true US20030029715A1 (en) 2003-02-13

Family

ID=25436918

Family Applications (3)

Application Number Title Priority Date Filing Date
US09/916,234 Abandoned US20030029715A1 (en) 2001-07-25 2001-07-25 An Apparatus For Annealing Substrates In Physical Vapor Deposition Systems
US10/044,412 Expired - Lifetime US6740585B2 (en) 2001-07-25 2002-01-09 Barrier formation using novel sputter deposition method with PVD, CVD, or ALD
US12/171,132 Expired - Fee Related US7611990B2 (en) 2001-07-25 2008-07-10 Deposition methods for barrier and tungsten materials

Family Applications After (2)

Application Number Title Priority Date Filing Date
US10/044,412 Expired - Lifetime US6740585B2 (en) 2001-07-25 2002-01-09 Barrier formation using novel sputter deposition method with PVD, CVD, or ALD
US12/171,132 Expired - Fee Related US7611990B2 (en) 2001-07-25 2008-07-10 Deposition methods for barrier and tungsten materials

Country Status (3)

Country Link
US (3) US20030029715A1 (en)
JP (1) JP2006500472A (en)
WO (1) WO2003080887A2 (en)

Cited By (211)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030235973A1 (en) * 2002-06-21 2003-12-25 Jiong-Ping Lu Nickel SALICIDE process technology for CMOS devices
US20040092123A1 (en) * 2002-10-17 2004-05-13 Fujitsu Limited Method of manufacturing semiconductor device having silicide layer
US20040161917A1 (en) * 2001-11-20 2004-08-19 Kazuya Hizawa Method for fabricating a semiconductor device having a metallic silicide layer
US20050092598A1 (en) * 2003-11-05 2005-05-05 Industrial Technology Research Institute Sputtering process with temperature control for salicide application
US20050173068A1 (en) * 2001-10-26 2005-08-11 Ling Chen Gas delivery apparatus and method for atomic layer deposition
US20050252449A1 (en) * 2004-05-12 2005-11-17 Nguyen Son T Control of gas flow and delivery to suppress the formation of particles in an MOCVD/ALD system
US20060019494A1 (en) * 2002-03-04 2006-01-26 Wei Cao Sequential deposition of tantalum nitride using a tantalum-containing precursor and a nitrogen-containing precursor
US20060063380A1 (en) * 2004-08-09 2006-03-23 Sug-Woo Jung Salicide process and method of fabricating semiconductor device using the same
US20060153995A1 (en) * 2004-05-21 2006-07-13 Applied Materials, Inc. Method for fabricating a dielectric stack
US20070119370A1 (en) * 2005-11-04 2007-05-31 Paul Ma Apparatus and process for plasma-enhanced atomic layer deposition
US20070151514A1 (en) * 2002-11-14 2007-07-05 Ling Chen Apparatus and method for hybrid chemical processing
US20070190780A1 (en) * 2003-06-18 2007-08-16 Applied Materials, Inc. Atomic layer deposition of barrier materials
US20070202254A1 (en) * 2001-07-25 2007-08-30 Seshadri Ganguli Process for forming cobalt-containing materials
US20070218688A1 (en) * 2000-06-28 2007-09-20 Ming Xi Method for depositing tungsten-containing layers by vapor deposition techniques
US20070252299A1 (en) * 2006-04-27 2007-11-01 Applied Materials, Inc. Synchronization of precursor pulsing and wafer rotation
US20070259110A1 (en) * 2006-05-05 2007-11-08 Applied Materials, Inc. Plasma, uv and ion/neutral assisted ald or cvd in a batch tool
US20070283886A1 (en) * 2001-09-26 2007-12-13 Hua Chung Apparatus for integration of barrier layer and seed layer
US20080006523A1 (en) * 2006-06-26 2008-01-10 Akihiro Hosokawa Cooled pvd shield
US20080044595A1 (en) * 2005-07-19 2008-02-21 Randhir Thakur Method for semiconductor processing
US20080076246A1 (en) * 2006-09-25 2008-03-27 Peterson Brennan L Through contact layer opening silicide and barrier layer formation
US20080085611A1 (en) * 2006-10-09 2008-04-10 Amit Khandelwal Deposition and densification process for titanium nitride barrier layers
US20080135914A1 (en) * 2006-06-30 2008-06-12 Krishna Nety M Nanocrystal formation
US20080206987A1 (en) * 2007-01-29 2008-08-28 Gelatos Avgerinos V Process for tungsten nitride deposition by a temperature controlled lid assembly
US20080268636A1 (en) * 2001-07-25 2008-10-30 Ki Hwan Yoon Deposition methods for barrier and tungsten materials
US20080280438A1 (en) * 2000-06-28 2008-11-13 Ken Kaung Lai Methods for depositing tungsten layers employing atomic layer deposition techniques
US20080305629A1 (en) * 2002-02-26 2008-12-11 Shulin Wang Tungsten nitride atomic layer deposition processes
US20080317954A1 (en) * 2001-07-13 2008-12-25 Xinliang Lu Pulsed deposition process for tungsten nucleation
US20090004850A1 (en) * 2001-07-25 2009-01-01 Seshadri Ganguli Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US20090053426A1 (en) * 2001-07-25 2009-02-26 Jiang Lu Cobalt deposition on barrier surfaces
US20090053893A1 (en) * 2005-01-19 2009-02-26 Amit Khandelwal Atomic layer deposition of tungsten materials
US20090081868A1 (en) * 2007-09-25 2009-03-26 Applied Materials, Inc. Vapor deposition processes for tantalum carbide nitride materials
US20090078916A1 (en) * 2007-09-25 2009-03-26 Applied Materials, Inc. Tantalum carbide nitride materials by vapor deposition processes
US20090087585A1 (en) * 2007-09-28 2009-04-02 Wei Ti Lee Deposition processes for titanium nitride barrier and aluminum
US20090087983A1 (en) * 2007-09-28 2009-04-02 Applied Materials, Inc. Aluminum contact integration on cobalt silicide junction
US20090111280A1 (en) * 2004-02-26 2009-04-30 Applied Materials, Inc. Method for removing oxides
US20090142474A1 (en) * 2004-12-10 2009-06-04 Srinivas Gandikota Ruthenium as an underlayer for tungsten film deposition
US20090156004A1 (en) * 2000-06-28 2009-06-18 Moris Kori Method for forming tungsten materials during vapor deposition processes
US20090269507A1 (en) * 2008-04-29 2009-10-29 Sang-Ho Yu Selective cobalt deposition on copper surfaces
US20100062614A1 (en) * 2008-09-08 2010-03-11 Ma Paul F In-situ chamber treatment and deposition process
US7732327B2 (en) 2000-06-28 2010-06-08 Applied Materials, Inc. Vapor deposition of tungsten materials
US7749815B2 (en) 2001-07-16 2010-07-06 Applied Materials, Inc. Methods for depositing tungsten after surface treatment
US20100218785A1 (en) * 2009-02-27 2010-09-02 Applied Materials, Inc. In situ plasma clean for removal of residue from pedestal surface without breaking vacuum
US20100304027A1 (en) * 2009-05-27 2010-12-02 Applied Materials, Inc. Substrate processing system and methods thereof
US7867914B2 (en) 2002-04-16 2011-01-11 Applied Materials, Inc. System and method for forming an integrated barrier layer
US7892602B2 (en) 2001-12-07 2011-02-22 Applied Materials, Inc. Cyclical deposition of refractory metal silicon nitride
US20110124192A1 (en) * 2006-04-11 2011-05-26 Seshadri Ganguli Process for forming cobalt-containing materials
US8679983B2 (en) 2011-09-01 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and nitrogen
US8679982B2 (en) 2011-08-26 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and oxygen
US8765574B2 (en) 2012-11-09 2014-07-01 Applied Materials, Inc. Dry etch process
US8771539B2 (en) 2011-02-22 2014-07-08 Applied Materials, Inc. Remotely-excited fluorine and water vapor etch
US8801952B1 (en) 2013-03-07 2014-08-12 Applied Materials, Inc. Conformal oxide dry etch
US8808563B2 (en) 2011-10-07 2014-08-19 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
TWI462228B (en) * 2006-06-15 2014-11-21 Advanced Micro Devices Inc Low contact resistance cmos circuits and methods for their fabrication
US8895449B1 (en) 2013-05-16 2014-11-25 Applied Materials, Inc. Delicate dry clean
US8921234B2 (en) 2012-12-21 2014-12-30 Applied Materials, Inc. Selective titanium nitride etching
US8927390B2 (en) 2011-09-26 2015-01-06 Applied Materials, Inc. Intrench profile
US8951429B1 (en) 2013-10-29 2015-02-10 Applied Materials, Inc. Tungsten oxide processing
US8956980B1 (en) 2013-09-16 2015-02-17 Applied Materials, Inc. Selective etch of silicon nitride
US8969212B2 (en) 2012-11-20 2015-03-03 Applied Materials, Inc. Dry-etch selectivity
US8975152B2 (en) 2011-11-08 2015-03-10 Applied Materials, Inc. Methods of reducing substrate dislocation during gapfill processing
US8980763B2 (en) 2012-11-30 2015-03-17 Applied Materials, Inc. Dry-etch for selective tungsten removal
US8999856B2 (en) 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
US9023734B2 (en) 2012-09-18 2015-05-05 Applied Materials, Inc. Radical-component oxide etch
US9023732B2 (en) 2013-03-15 2015-05-05 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9034770B2 (en) 2012-09-17 2015-05-19 Applied Materials, Inc. Differential silicon oxide etch
US9040422B2 (en) 2013-03-05 2015-05-26 Applied Materials, Inc. Selective titanium nitride removal
US9064815B2 (en) 2011-03-14 2015-06-23 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US9064816B2 (en) 2012-11-30 2015-06-23 Applied Materials, Inc. Dry-etch for selective oxidation removal
US9111877B2 (en) 2012-12-18 2015-08-18 Applied Materials, Inc. Non-local plasma oxide etch
US9117855B2 (en) 2013-12-04 2015-08-25 Applied Materials, Inc. Polarity control for remote plasma
US9114438B2 (en) 2013-05-21 2015-08-25 Applied Materials, Inc. Copper residue chamber clean
US9136273B1 (en) 2014-03-21 2015-09-15 Applied Materials, Inc. Flash gate air gap
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US9159606B1 (en) 2014-07-31 2015-10-13 Applied Materials, Inc. Metal air gap
US9165786B1 (en) 2014-08-05 2015-10-20 Applied Materials, Inc. Integrated oxide and nitride recess for better channel contact in 3D architectures
US9190293B2 (en) 2013-12-18 2015-11-17 Applied Materials, Inc. Even tungsten etch for high aspect ratio trenches
US9236266B2 (en) 2011-08-01 2016-01-12 Applied Materials, Inc. Dry-etch for silicon-and-carbon-containing films
US9236265B2 (en) 2013-11-04 2016-01-12 Applied Materials, Inc. Silicon germanium processing
US9245762B2 (en) 2013-12-02 2016-01-26 Applied Materials, Inc. Procedure for etch rate consistency
US9263278B2 (en) 2013-12-17 2016-02-16 Applied Materials, Inc. Dopant etch selectivity control
US9269590B2 (en) 2014-04-07 2016-02-23 Applied Materials, Inc. Spacer formation
US9287134B2 (en) 2014-01-17 2016-03-15 Applied Materials, Inc. Titanium oxide etch
US9287095B2 (en) 2013-12-17 2016-03-15 Applied Materials, Inc. Semiconductor system assemblies and methods of operation
US9293568B2 (en) 2014-01-27 2016-03-22 Applied Materials, Inc. Method of fin patterning
US9299575B2 (en) 2014-03-17 2016-03-29 Applied Materials, Inc. Gas-phase tungsten etch
US9299583B1 (en) 2014-12-05 2016-03-29 Applied Materials, Inc. Aluminum oxide selective etch
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9299538B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US9343272B1 (en) 2015-01-08 2016-05-17 Applied Materials, Inc. Self-aligned process
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US9355862B2 (en) 2014-09-24 2016-05-31 Applied Materials, Inc. Fluorine-based hardmask removal
US9355856B2 (en) 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch
WO2016085805A1 (en) * 2014-11-26 2016-06-02 Applied Materials, Inc. Collimator for use in substrate processing chambers
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9368364B2 (en) 2014-09-24 2016-06-14 Applied Materials, Inc. Silicon etch process with tunable selectivity to SiO2 and other materials
US9373522B1 (en) 2015-01-22 2016-06-21 Applied Mateials, Inc. Titanium nitride removal
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9418890B2 (en) 2008-09-08 2016-08-16 Applied Materials, Inc. Method for tuning a deposition rate during an atomic layer deposition process
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9449846B2 (en) 2015-01-28 2016-09-20 Applied Materials, Inc. Vertical gate separation
US9472417B2 (en) 2013-11-12 2016-10-18 Applied Materials, Inc. Plasma-free metal etch
US9478432B2 (en) 2014-09-25 2016-10-25 Applied Materials, Inc. Silicon oxide selective removal
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9502258B2 (en) 2014-12-23 2016-11-22 Applied Materials, Inc. Anisotropic gap etch
US9499898B2 (en) 2014-03-03 2016-11-22 Applied Materials, Inc. Layered thin film heater and method of fabrication
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9721789B1 (en) 2016-10-04 2017-08-01 Applied Materials, Inc. Saving ion-damaged spacers
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9768034B1 (en) 2016-11-11 2017-09-19 Applied Materials, Inc. Removal methods for high aspect ratio structures
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US9847289B2 (en) 2014-05-30 2017-12-19 Applied Materials, Inc. Protective via cap for improved interconnect performance
US9865484B1 (en) 2016-06-29 2018-01-09 Applied Materials, Inc. Selective etch using material modification and RF pulsing
US9881805B2 (en) 2015-03-02 2018-01-30 Applied Materials, Inc. Silicon selective removal
US9885117B2 (en) 2014-03-31 2018-02-06 Applied Materials, Inc. Conditioned semiconductor system parts
US9892890B2 (en) 2012-04-26 2018-02-13 Intevac, Inc. Narrow source for physical vapor deposition processing
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal
US9960024B2 (en) 2015-10-27 2018-05-01 Applied Materials, Inc. Biasable flux optimizer / collimator for PVD sputter chamber
WO2018094022A1 (en) * 2016-11-18 2018-05-24 Applied Materials, Inc. Collimator for use in a physical vapor deposition chamber
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10043684B1 (en) 2017-02-06 2018-08-07 Applied Materials, Inc. Self-limiting atomic thermal etching systems and methods
US10049891B1 (en) 2017-05-31 2018-08-14 Applied Materials, Inc. Selective in situ cobalt residue removal
US10062585B2 (en) 2016-10-04 2018-08-28 Applied Materials, Inc. Oxygen compatible plasma source
US10062587B2 (en) 2012-07-18 2018-08-28 Applied Materials, Inc. Pedestal with multi-zone temperature control and multiple purge capabilities
US10062575B2 (en) 2016-09-09 2018-08-28 Applied Materials, Inc. Poly directional etch by oxidation
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US10128086B1 (en) 2017-10-24 2018-11-13 Applied Materials, Inc. Silicon pretreatment for nitride removal
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10170282B2 (en) 2013-03-08 2019-01-01 Applied Materials, Inc. Insulated semiconductor faceplate designs
US10170336B1 (en) 2017-08-04 2019-01-01 Applied Materials, Inc. Methods for anisotropic control of selective silicon removal
US10224210B2 (en) 2014-12-09 2019-03-05 Applied Materials, Inc. Plasma processing system with direct outlet toroidal plasma source
US10242908B2 (en) 2016-11-14 2019-03-26 Applied Materials, Inc. Airgap formation with damage-free copper
US10256112B1 (en) 2017-12-08 2019-04-09 Applied Materials, Inc. Selective tungsten removal
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US10283321B2 (en) 2011-01-18 2019-05-07 Applied Materials, Inc. Semiconductor processing system and methods using capacitively coupled plasma
US10283324B1 (en) 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10354889B2 (en) 2017-07-17 2019-07-16 Applied Materials, Inc. Non-halogen etching of silicon-containing materials
USD858468S1 (en) * 2018-03-16 2019-09-03 Applied Materials, Inc. Collimator for a physical vapor deposition chamber
US10403507B2 (en) 2017-02-03 2019-09-03 Applied Materials, Inc. Shaped etch profile with oxidation
USD859333S1 (en) * 2018-03-16 2019-09-10 Applied Materials, Inc. Collimator for a physical vapor deposition chamber
US10431429B2 (en) 2017-02-03 2019-10-01 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10468267B2 (en) 2017-05-31 2019-11-05 Applied Materials, Inc. Water-free etching methods
US10490418B2 (en) 2014-10-14 2019-11-26 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US10490406B2 (en) 2018-04-10 2019-11-26 Appled Materials, Inc. Systems and methods for material breakthrough
US10497573B2 (en) 2018-03-13 2019-12-03 Applied Materials, Inc. Selective atomic layer etching of semiconductor materials
US10504754B2 (en) 2016-05-19 2019-12-10 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US10522371B2 (en) 2016-05-19 2019-12-31 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US10541184B2 (en) 2017-07-11 2020-01-21 Applied Materials, Inc. Optical emission spectroscopic techniques for monitoring etching
US10546729B2 (en) 2016-10-04 2020-01-28 Applied Materials, Inc. Dual-channel showerhead with improved profile
US10566206B2 (en) 2016-12-27 2020-02-18 Applied Materials, Inc. Systems and methods for anisotropic material breakthrough
US10573527B2 (en) 2018-04-06 2020-02-25 Applied Materials, Inc. Gas-phase selective etching systems and methods
US10573496B2 (en) 2014-12-09 2020-02-25 Applied Materials, Inc. Direct outlet toroidal plasma source
US10593560B2 (en) 2018-03-01 2020-03-17 Applied Materials, Inc. Magnetic induction plasma source for semiconductor processes and equipment
US10593523B2 (en) 2014-10-14 2020-03-17 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US10615047B2 (en) 2018-02-28 2020-04-07 Applied Materials, Inc. Systems and methods to form airgaps
US10629473B2 (en) 2016-09-09 2020-04-21 Applied Materials, Inc. Footing removal for nitride spacer
CN111133558A (en) * 2017-09-21 2020-05-08 应用材料公司 Method and apparatus for filling substrate features with cobalt
US10672642B2 (en) 2018-07-24 2020-06-02 Applied Materials, Inc. Systems and methods for pedestal configuration
US10679870B2 (en) 2018-02-15 2020-06-09 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
US10699879B2 (en) 2018-04-17 2020-06-30 Applied Materials, Inc. Two piece electrode assembly with gap for plasma control
US10727080B2 (en) 2017-07-07 2020-07-28 Applied Materials, Inc. Tantalum-containing material removal
US10755941B2 (en) 2018-07-06 2020-08-25 Applied Materials, Inc. Self-limiting selective etching systems and methods
CN111719132A (en) * 2020-06-29 2020-09-29 东部超导科技(苏州)有限公司 Multi-channel winding device integrating film coating and heat treatment of superconducting strip
US10796918B2 (en) 2010-10-25 2020-10-06 Stmicroelectronics S.R.L. Integrated circuits with backside metalization and production method thereof
US10854426B2 (en) 2018-01-08 2020-12-01 Applied Materials, Inc. Metal recess for semiconductor structures
US10872778B2 (en) 2018-07-06 2020-12-22 Applied Materials, Inc. Systems and methods utilizing solid-phase etchants
US10886137B2 (en) 2018-04-30 2021-01-05 Applied Materials, Inc. Selective nitride removal
US10892198B2 (en) 2018-09-14 2021-01-12 Applied Materials, Inc. Systems and methods for improved performance in semiconductor processing
US10903054B2 (en) 2017-12-19 2021-01-26 Applied Materials, Inc. Multi-zone gas distribution systems and methods
US10920320B2 (en) 2017-06-16 2021-02-16 Applied Materials, Inc. Plasma health determination in semiconductor substrate processing reactors
US10920319B2 (en) 2019-01-11 2021-02-16 Applied Materials, Inc. Ceramic showerheads with conductive electrodes
US10943834B2 (en) 2017-03-13 2021-03-09 Applied Materials, Inc. Replacement contact process
US10964512B2 (en) 2018-02-15 2021-03-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus and methods
US11049755B2 (en) 2018-09-14 2021-06-29 Applied Materials, Inc. Semiconductor substrate supports with embedded RF shield
US11062887B2 (en) 2018-09-17 2021-07-13 Applied Materials, Inc. High temperature RF heater pedestals
US11121002B2 (en) 2018-10-24 2021-09-14 Applied Materials, Inc. Systems and methods for etching metals and metal derivatives
USD937329S1 (en) 2020-03-23 2021-11-30 Applied Materials, Inc. Sputter target for a physical vapor deposition chamber
US11239061B2 (en) 2014-11-26 2022-02-01 Applied Materials, Inc. Methods and systems to enhance process uniformity
US11257693B2 (en) 2015-01-09 2022-02-22 Applied Materials, Inc. Methods and systems to improve pedestal temperature control
US11276590B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US11276559B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US11328909B2 (en) 2017-12-22 2022-05-10 Applied Materials, Inc. Chamber conditioning and removal processes
US11417534B2 (en) 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
US11437242B2 (en) 2018-11-27 2022-09-06 Applied Materials, Inc. Selective removal of silicon-containing materials
US11594428B2 (en) 2015-02-03 2023-02-28 Applied Materials, Inc. Low temperature chuck for plasma processing systems
US11682560B2 (en) 2018-10-11 2023-06-20 Applied Materials, Inc. Systems and methods for hafnium-containing film removal
US11721527B2 (en) 2019-01-07 2023-08-08 Applied Materials, Inc. Processing chamber mixing systems
USD997111S1 (en) 2021-12-15 2023-08-29 Applied Materials, Inc. Collimator for use in a physical vapor deposition (PVD) chamber
USD998575S1 (en) 2020-04-07 2023-09-12 Applied Materials, Inc. Collimator for use in a physical vapor deposition (PVD) chamber
USD1009816S1 (en) 2021-08-29 2024-01-02 Applied Materials, Inc. Collimator for a physical vapor deposition chamber
US11959167B2 (en) 2022-06-07 2024-04-16 Applied Materials, Inc. Selective cobalt deposition on copper surfaces

Families Citing this family (198)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6974766B1 (en) 1998-10-01 2005-12-13 Applied Materials, Inc. In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application
US7589017B2 (en) * 2001-05-22 2009-09-15 Novellus Systems, Inc. Methods for growing low-resistivity tungsten film
US7005372B2 (en) * 2003-01-21 2006-02-28 Novellus Systems, Inc. Deposition of tungsten nitride
US9076843B2 (en) 2001-05-22 2015-07-07 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US7141494B2 (en) * 2001-05-22 2006-11-28 Novellus Systems, Inc. Method for reducing tungsten film roughness and improving step coverage
US7955972B2 (en) * 2001-05-22 2011-06-07 Novellus Systems, Inc. Methods for growing low-resistivity tungsten for high aspect ratio and small features
US7262125B2 (en) * 2001-05-22 2007-08-28 Novellus Systems, Inc. Method of forming low-resistivity tungsten interconnects
US7469558B2 (en) * 2001-07-10 2008-12-30 Springworks, Llc As-deposited planar optical waveguides with low scattering loss and methods for their manufacture
JP2005518088A (en) 2001-07-16 2005-06-16 アプライド マテリアルズ インコーポレイテッド Formation of tungsten composite film
US20030036242A1 (en) * 2001-08-16 2003-02-20 Haining Yang Methods of forming metal-comprising materials and capacitor electrodes; and capacitor constructions
US7404877B2 (en) * 2001-11-09 2008-07-29 Springworks, Llc Low temperature zirconia based thermal barrier layer by PVD
US7378356B2 (en) * 2002-03-16 2008-05-27 Springworks, Llc Biased pulse DC reactive sputtering of oxide films
US6884327B2 (en) * 2002-03-16 2005-04-26 Tao Pan Mode size converter for a planar waveguide
US20030175142A1 (en) * 2002-03-16 2003-09-18 Vassiliki Milonopoulou Rare-earth pre-alloyed PVD targets for dielectric planar applications
US6743721B2 (en) * 2002-06-10 2004-06-01 United Microelectronics Corp. Method and system for making cobalt silicide
US8021778B2 (en) * 2002-08-09 2011-09-20 Infinite Power Solutions, Inc. Electrochemical apparatus with barrier layer protected substrate
US8394522B2 (en) * 2002-08-09 2013-03-12 Infinite Power Solutions, Inc. Robust metal film encapsulation
US8236443B2 (en) * 2002-08-09 2012-08-07 Infinite Power Solutions, Inc. Metal film encapsulation
US9793523B2 (en) 2002-08-09 2017-10-17 Sapurast Research Llc Electrochemical apparatus with barrier layer protected substrate
US8445130B2 (en) * 2002-08-09 2013-05-21 Infinite Power Solutions, Inc. Hybrid thin-film battery
US20070264564A1 (en) 2006-03-16 2007-11-15 Infinite Power Solutions, Inc. Thin film battery on an integrated circuit or circuit board and method thereof
US8431264B2 (en) * 2002-08-09 2013-04-30 Infinite Power Solutions, Inc. Hybrid thin-film battery
US8404376B2 (en) 2002-08-09 2013-03-26 Infinite Power Solutions, Inc. Metal film encapsulation
WO2004021532A1 (en) * 2002-08-27 2004-03-11 Symmorphix, Inc. Optically coupling into highly uniform waveguides
US7147759B2 (en) * 2002-09-30 2006-12-12 Zond, Inc. High-power pulsed magnetron sputtering
US6896773B2 (en) * 2002-11-14 2005-05-24 Zond, Inc. High deposition rate sputtering
US7262133B2 (en) * 2003-01-07 2007-08-28 Applied Materials, Inc. Enhancement of copper line reliability using thin ALD tan film to cap the copper line
US20040214417A1 (en) * 2003-03-11 2004-10-28 Paul Rich Methods of forming tungsten or tungsten containing films
KR100576363B1 (en) * 2003-05-30 2006-05-03 삼성전자주식회사 In-situ chemical vapor deposition metallization process and chemical vapor deposition apparatus used therein
US6844258B1 (en) 2003-05-09 2005-01-18 Novellus Systems, Inc. Selective refractory metal and nitride capping
US7675174B2 (en) * 2003-05-13 2010-03-09 Stmicroelectronics, Inc. Method and structure of a thick metal layer using multiple deposition chambers
US8728285B2 (en) * 2003-05-23 2014-05-20 Demaray, Llc Transparent conductive oxides
US7238628B2 (en) * 2003-05-23 2007-07-03 Symmorphix, Inc. Energy conversion and storage films and devices by physical vapor deposition of titanium and titanium oxides and sub-oxides
KR100680944B1 (en) * 2003-05-27 2007-02-08 주식회사 하이닉스반도체 Method of manufacturing semicondutor device
US20040238876A1 (en) * 2003-05-29 2004-12-02 Sunpil Youn Semiconductor structure having low resistance and method of manufacturing same
KR100560666B1 (en) * 2003-07-07 2006-03-16 삼성전자주식회사 Metal layer deposition system for semiconductor device fabrication and method of operating the same
US7754604B2 (en) * 2003-08-26 2010-07-13 Novellus Systems, Inc. Reducing silicon attack and improving resistivity of tungsten nitride film
US7312163B2 (en) * 2003-09-24 2007-12-25 Micron Technology, Inc. Atomic layer deposition methods, and methods of forming materials over semiconductor substrates
US20050239287A1 (en) * 2003-10-03 2005-10-27 Mei-Yun Wang Silicide formation using a metal-organic chemical vapor deposited capping layer
US9771648B2 (en) 2004-08-13 2017-09-26 Zond, Inc. Method of ionized physical vapor deposition sputter coating high aspect-ratio structures
KR100555541B1 (en) * 2003-12-23 2006-03-03 삼성전자주식회사 Forming method for cobalt silicide layer and manufacturing method for semiconductor device using the forming method
US7071102B2 (en) * 2004-01-06 2006-07-04 Macronix International Co., Ltd. Method of forming a metal silicide layer on non-planar-topography polysilicon
US9123508B2 (en) * 2004-02-22 2015-09-01 Zond, Llc Apparatus and method for sputtering hard coatings
US7780793B2 (en) * 2004-02-26 2010-08-24 Applied Materials, Inc. Passivation layer formation by plasma clean process to reduce native oxide growth
US20060051966A1 (en) * 2004-02-26 2006-03-09 Applied Materials, Inc. In-situ chamber clean process to remove by-product deposits from chemical vapor etch chamber
KR100564617B1 (en) * 2004-03-05 2006-03-28 삼성전자주식회사 Forming method for metal salicide layer and manufacturing method for semiconductor device using the forming method
JP4390616B2 (en) * 2004-04-27 2009-12-24 Necエレクトロニクス株式会社 Cleaning liquid and method for manufacturing semiconductor device
US7268065B2 (en) * 2004-06-18 2007-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing metal-silicide features
DE602005016933D1 (en) * 2004-06-28 2009-11-12 Cambridge Nanotech Inc ATOMIC SEPARATION SYSTEM AND METHOD
KR101050863B1 (en) * 2004-06-30 2011-07-20 매그나칩 반도체 유한회사 Method of forming diffusion barrier in semiconductor device
KR100587686B1 (en) * 2004-07-15 2006-06-08 삼성전자주식회사 Method for forming TiN and method for manufacturing capacitor used the same
US7368368B2 (en) * 2004-08-18 2008-05-06 Cree, Inc. Multi-chamber MOCVD growth apparatus for high performance/high throughput
TW200633216A (en) * 2004-10-05 2006-09-16 St Microelectronics Crolles 2 Gate structure and manufacturing method
TWI331634B (en) * 2004-12-08 2010-10-11 Infinite Power Solutions Inc Deposition of licoo2
US7959769B2 (en) * 2004-12-08 2011-06-14 Infinite Power Solutions, Inc. Deposition of LiCoO2
US20060130971A1 (en) * 2004-12-21 2006-06-22 Applied Materials, Inc. Apparatus for generating plasma by RF power
US20060251801A1 (en) * 2005-03-18 2006-11-09 Weidman Timothy W In-situ silicidation metallization process
JP2006261608A (en) * 2005-03-18 2006-09-28 Canon Inc Device manufacturing apparatus and controlling method
US7794574B2 (en) * 2005-04-14 2010-09-14 Tango Systems, Inc. Top shield for sputtering system
US7785455B2 (en) * 2005-04-14 2010-08-31 Tango Systems, Inc. Cross-contaminant shield in sputtering system
US7192878B2 (en) * 2005-05-09 2007-03-20 United Microelectronics Corp. Method for removing post-etch residue from wafer surface
US7588669B2 (en) * 2005-07-20 2009-09-15 Ascentool, Inc. Single-process-chamber deposition system
US7432184B2 (en) * 2005-08-26 2008-10-07 Applied Materials, Inc. Integrated PVD system using designated PVD chambers
US7534080B2 (en) * 2005-08-26 2009-05-19 Ascentool, Inc. Vacuum processing and transfer system
US20070078398A1 (en) * 2005-08-27 2007-04-05 Dextradeur Alan J Multi-branched anti-reflux valve
US7838133B2 (en) * 2005-09-02 2010-11-23 Springworks, Llc Deposition of perovskite and other compound ceramic films for dielectric applications
US20070059878A1 (en) * 2005-09-14 2007-03-15 Yu-Lan Chang Salicide process
CN100431105C (en) * 2005-09-22 2008-11-05 联华电子股份有限公司 Self-aligning metal silicide technology
US20070087573A1 (en) * 2005-10-19 2007-04-19 Yi-Yiing Chiang Pre-treatment method for physical vapor deposition of metal layer and method of forming metal silicide layer
US20070108041A1 (en) * 2005-11-11 2007-05-17 Guo George X Magnetron source having increased usage life
US7638022B2 (en) * 2006-02-27 2009-12-29 Ascentool, Inc Magnetron source for deposition on large substrates
JP4782037B2 (en) * 2006-03-03 2011-09-28 キヤノンアネルバ株式会社 Magnetoresistive element manufacturing method and manufacturing apparatus
US20070259111A1 (en) * 2006-05-05 2007-11-08 Singh Kaushal K Method and apparatus for photo-excitation of chemicals for atomic layer deposition of dielectric film
CN101140871B (en) * 2006-09-04 2010-11-10 中芯国际集成电路制造(上海)有限公司 Preparation method of metallic silicide in semiconductor device
US7485572B2 (en) * 2006-09-25 2009-02-03 International Business Machines Corporation Method for improved formation of cobalt silicide contacts in semiconductor devices
EP2067163A4 (en) * 2006-09-29 2009-12-02 Infinite Power Solutions Inc Masking of and material constraint for depositing battery layers on flexible substrates
US8197781B2 (en) * 2006-11-07 2012-06-12 Infinite Power Solutions, Inc. Sputtering target of Li3PO4 and method for producing same
US8236152B2 (en) * 2006-11-24 2012-08-07 Ascentool International Ltd. Deposition system
US20080121620A1 (en) * 2006-11-24 2008-05-29 Guo G X Processing chamber
US7837790B2 (en) * 2006-12-01 2010-11-23 Applied Materials, Inc. Formation and treatment of epitaxial layer containing silicon and carbon
US8791018B2 (en) 2006-12-19 2014-07-29 Spansion Llc Method of depositing copper using physical vapor deposition
US20080170959A1 (en) * 2007-01-11 2008-07-17 Heraeus Incorporated Full density Co-W magnetic sputter targets
ITMI20070446A1 (en) * 2007-03-06 2008-09-07 St Microelectronics Srl PROCESS PERFABRICATING INTEGRATED CIRCUITS FORMED ON A SEMINCONDUCTOR SUBSTRATE AND INCLUDING TUNGSTEN LAYERS
DE102007015503B4 (en) * 2007-03-30 2013-03-21 Globalfoundries Inc. Method and system for controlling chemical mechanical polishing by taking into account zone specific substrate data
US8152975B2 (en) * 2007-03-30 2012-04-10 Ascentool International Deposition system with improved material utilization
KR101136477B1 (en) * 2007-04-06 2012-04-23 고쿠리츠 다이가쿠 호진 도호쿠 다이가쿠 Magnetron sputtering appartus
US8082741B2 (en) * 2007-05-15 2011-12-27 Brooks Automation, Inc. Integral facet cryopump, water vapor pump, or high vacuum pump
WO2008149446A1 (en) * 2007-06-07 2008-12-11 Canon Anelva Corporation Semiconductor production apparatus and process
EP2006411A1 (en) * 2007-06-19 2008-12-24 Applied Materials, Inc. Evaporation apparatus having a rotatable evaporation unit receptacle
KR100890047B1 (en) * 2007-06-28 2009-03-25 주식회사 하이닉스반도체 Method for fabricating interconnection in semicondutor device
US7655567B1 (en) 2007-07-24 2010-02-02 Novellus Systems, Inc. Methods for improving uniformity and resistivity of thin tungsten films
US8049178B2 (en) * 2007-08-30 2011-11-01 Washington State University Research Foundation Semiconductive materials and associated uses thereof
KR101334221B1 (en) * 2007-09-03 2013-11-29 주식회사 원익아이피에스 Method of manufacturing multi-level metal thin film and apparatus for manufacturing the same
US7772114B2 (en) 2007-12-05 2010-08-10 Novellus Systems, Inc. Method for improving uniformity and adhesion of low resistivity tungsten film
US8053365B2 (en) * 2007-12-21 2011-11-08 Novellus Systems, Inc. Methods for forming all tungsten contacts and lines
KR20150128817A (en) * 2007-12-21 2015-11-18 사푸라스트 리써치 엘엘씨 Method for sputter targets for electrolyte films
US8268488B2 (en) 2007-12-21 2012-09-18 Infinite Power Solutions, Inc. Thin film electrolyte for thin film batteries
JP5705549B2 (en) 2008-01-11 2015-04-22 インフィニット パワー ソリューションズ, インコーポレイテッド Thin film encapsulation for thin film batteries and other devices
US8062977B1 (en) 2008-01-31 2011-11-22 Novellus Systems, Inc. Ternary tungsten-containing resistive thin films
US7618893B2 (en) * 2008-03-04 2009-11-17 Applied Materials, Inc. Methods of forming a layer for barrier applications in an interconnect structure
CN101983469B (en) * 2008-04-02 2014-06-04 无穷动力解决方案股份有限公司 Passive over/under voltage control and protection for energy storage devices associated with energy harvesting
US8058170B2 (en) * 2008-06-12 2011-11-15 Novellus Systems, Inc. Method for depositing thin tungsten film with low resistivity and robust micro-adhesion characteristics
KR20160145849A (en) * 2008-06-17 2016-12-20 어플라이드 머티어리얼스, 인코포레이티드 Apparatus and method for uniform deposition
US20100012481A1 (en) * 2008-07-21 2010-01-21 Guo G X Deposition system having improved material utilization
US8500962B2 (en) 2008-07-21 2013-08-06 Ascentool Inc Deposition system and methods having improved material utilization
WO2010019577A1 (en) 2008-08-11 2010-02-18 Infinite Power Solutions, Inc. Energy device with integral collector surface for electromagnetic energy harvesting and method thereof
US8551885B2 (en) * 2008-08-29 2013-10-08 Novellus Systems, Inc. Method for reducing tungsten roughness and improving reflectivity
WO2010027112A1 (en) * 2008-09-04 2010-03-11 Integrated Process Systems Ltd Method of manufacturing multi-level metal thin film and apparatus for manufacturing the same
JP5650646B2 (en) * 2008-09-12 2015-01-07 インフィニット パワー ソリューションズ, インコーポレイテッド Energy device with integral conductive surface for data communication via electromagnetic energy and method for data communication via electromagnetic energy
US20100075499A1 (en) * 2008-09-19 2010-03-25 Olsen Christopher S Method and apparatus for metal silicide formation
US8508193B2 (en) * 2008-10-08 2013-08-13 Infinite Power Solutions, Inc. Environmentally-powered wireless sensor module
US20100183825A1 (en) * 2008-12-31 2010-07-22 Cambridge Nanotech Inc. Plasma atomic layer deposition system and method
US20100267230A1 (en) 2009-04-16 2010-10-21 Anand Chandrashekar Method for forming tungsten contacts and interconnects with small critical dimensions
US9159571B2 (en) 2009-04-16 2015-10-13 Lam Research Corporation Tungsten deposition process using germanium-containing reducing agent
EP2433330A4 (en) * 2009-05-20 2016-12-07 Sapurast Res Llc Method of integrating electrochemical devices into and onto fixtures
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US9653353B2 (en) 2009-08-04 2017-05-16 Novellus Systems, Inc. Tungsten feature fill
KR101792287B1 (en) * 2009-09-01 2017-10-31 사푸라스트 리써치 엘엘씨 Printed circuit board with integrated thin film battery
US8207062B2 (en) * 2009-09-09 2012-06-26 Novellus Systems, Inc. Method for improving adhesion of low resistivity tungsten/tungsten nitride layers
US8227344B2 (en) * 2010-02-26 2012-07-24 Tokyo Electron Limited Hybrid in-situ dry cleaning of oxidized surface layers
US8709948B2 (en) 2010-03-12 2014-04-29 Novellus Systems, Inc. Tungsten barrier and seed for copper filled TSV
DE102010028458A1 (en) * 2010-04-30 2011-11-03 Globalfoundries Dresden Module One Llc & Co. Kg Semiconductor device having contact elements and Metallsilizidgebieten, which are made in a common process sequence
KR101930561B1 (en) 2010-06-07 2018-12-18 사푸라스트 리써치 엘엘씨 Rechargeable high-density electrochemical device
US8492899B2 (en) 2010-10-14 2013-07-23 International Business Machines Corporation Method to electrodeposit nickel on silicon for forming controllable nickel silicide
JP5725454B2 (en) * 2011-03-25 2015-05-27 株式会社アルバック NiSi film forming method, silicide film forming method, silicide annealing metal film forming method, vacuum processing apparatus, and film forming apparatus
US8831180B2 (en) * 2011-08-04 2014-09-09 General Electric Company Apparatus for scatter reduction for CT imaging and method of fabricating same
US9034760B2 (en) 2012-06-29 2015-05-19 Novellus Systems, Inc. Methods of forming tensile tungsten films and compressive tungsten films
US8975184B2 (en) 2012-07-27 2015-03-10 Novellus Systems, Inc. Methods of improving tungsten contact resistance in small critical dimension features
US20140065819A1 (en) * 2012-09-03 2014-03-06 Intermolecular, Inc. Methods and Systems for Low Resistance Contact Formation
US20140065799A1 (en) * 2012-09-03 2014-03-06 Intermolecular, Inc. Methods and Systems for Low Resistance Contact Formation
US8853080B2 (en) 2012-09-09 2014-10-07 Novellus Systems, Inc. Method for depositing tungsten film with low roughness and low resistivity
US20140134838A1 (en) * 2012-11-09 2014-05-15 Primestar Solar, Inc. Methods of annealing a conductive transparent oxide film layer for use in a thin film photovoltaic device
US8729702B1 (en) * 2012-11-20 2014-05-20 Stmicroelectronics, Inc. Copper seed layer for an interconnect structure having a doping concentration level gradient
TWI689004B (en) 2012-11-26 2020-03-21 美商應用材料股份有限公司 Stiction-free drying process with contaminant removal for high-aspect-ratio semiconductor device structures
US8859417B2 (en) 2013-01-03 2014-10-14 Globalfoundries Inc. Gate electrode(s) and contact structure(s), and methods of fabrication thereof
US20150376776A1 (en) * 2013-02-14 2015-12-31 Veeco Instruments, Inc. Variable-temperature material growth stages and thin film growth
US9230835B2 (en) * 2013-03-15 2016-01-05 Applied Materials, Inc. Integrated platform for fabricating n-type metal oxide semiconductor (NMOS) devices
US9153486B2 (en) 2013-04-12 2015-10-06 Lam Research Corporation CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications
US20150099358A1 (en) * 2013-10-07 2015-04-09 Win Semiconductors Corp. Method for forming through wafer vias in semiconductor devices
US20150118833A1 (en) * 2013-10-24 2015-04-30 Applied Materials, Inc. Method of making source/drain contacts by sputtering a doped target
US9305839B2 (en) 2013-12-19 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Curing photo resist for improving etching selectivity
US9589808B2 (en) 2013-12-19 2017-03-07 Lam Research Corporation Method for depositing extremely low resistivity tungsten
US9899234B2 (en) * 2014-06-30 2018-02-20 Lam Research Corporation Liner and barrier applications for subtractive metal integration
CN105448644B (en) * 2014-06-30 2019-07-02 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
WO2016007874A1 (en) * 2014-07-11 2016-01-14 Applied Materials, Inc. Supercritical carbon dioxide process for low-k thin films
US9994956B2 (en) 2014-08-11 2018-06-12 University Of Kansas Apparatus for in situ deposition of multilayer structures via atomic layer deposition and ultra-high vacuum physical or chemical vapor deposition
US9412619B2 (en) * 2014-08-12 2016-08-09 Applied Materials, Inc. Method of outgassing a mask material deposited over a workpiece in a process tool
JP6364295B2 (en) * 2014-09-22 2018-07-25 ルネサスエレクトロニクス株式会社 Semiconductor device manufacturing method and sputtering apparatus
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US9953984B2 (en) 2015-02-11 2018-04-24 Lam Research Corporation Tungsten for wordline applications
US9613818B2 (en) 2015-05-27 2017-04-04 Lam Research Corporation Deposition of low fluorine tungsten by sequential CVD process
US9978605B2 (en) 2015-05-27 2018-05-22 Lam Research Corporation Method of forming low resistivity fluorine free tungsten film without nucleation
US9754824B2 (en) 2015-05-27 2017-09-05 Lam Research Corporation Tungsten films having low fluorine content
JP6556945B2 (en) 2015-10-04 2019-08-07 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated Substrate support and baffle equipment
WO2017062136A1 (en) 2015-10-04 2017-04-13 Applied Materials, Inc. Reduced volume processing chamber
JP6644881B2 (en) 2015-10-04 2020-02-12 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated Drying process for high aspect ratio features
KR102062873B1 (en) * 2015-10-04 2020-01-06 어플라이드 머티어리얼스, 인코포레이티드 Small thermal mass pressurized chamber
CN107026113B (en) * 2016-02-02 2020-03-31 中芯国际集成电路制造(上海)有限公司 Method and system for manufacturing semiconductor device
JP6088083B1 (en) * 2016-03-14 2017-03-01 株式会社東芝 Processing device and collimator
US10224224B2 (en) * 2017-03-10 2019-03-05 Micromaterials, LLC High pressure wafer processing systems and related methods
US10563304B2 (en) 2017-04-07 2020-02-18 Applied Materials, Inc. Methods and apparatus for dynamically treating atomic layer deposition films in physical vapor deposition chambers
US10453678B2 (en) * 2017-04-13 2019-10-22 Applied Materials, Inc. Method and apparatus for deposition of low-k films
US10622214B2 (en) 2017-05-25 2020-04-14 Applied Materials, Inc. Tungsten defluorination by high pressure treatment
GB201709446D0 (en) * 2017-06-14 2017-07-26 Semblant Ltd Plasma processing apparatus
US10199267B2 (en) 2017-06-30 2019-02-05 Lam Research Corporation Tungsten nitride barrier layer deposition
US10593871B2 (en) 2017-07-10 2020-03-17 University Of Kansas Atomic layer deposition of ultrathin tunnel barriers
KR20200032756A (en) 2017-08-14 2020-03-26 램 리써치 코포레이션 Metal filling process for 3D vertical NAND wordlines
CN111095513B (en) 2017-08-18 2023-10-31 应用材料公司 High-pressure high-temperature annealing chamber
US10276411B2 (en) 2017-08-18 2019-04-30 Applied Materials, Inc. High pressure and high temperature anneal chamber
CN111095524B (en) 2017-09-12 2023-10-03 应用材料公司 Apparatus and method for fabricating semiconductor structures using protective barrier layers
EP4321649A2 (en) 2017-11-11 2024-02-14 Micromaterials LLC Gas delivery system for high pressure processing chamber
JP2021503714A (en) 2017-11-17 2021-02-12 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated Capacitor system for high pressure processing system
KR20230079236A (en) 2018-03-09 2023-06-05 어플라이드 머티어리얼스, 인코포레이티드 High pressure annealing process for metal containing materials
US11028480B2 (en) 2018-03-19 2021-06-08 Applied Materials, Inc. Methods of protecting metallic components against corrosion using chromium-containing thin films
US10975464B2 (en) 2018-04-09 2021-04-13 International Business Machines Corporation Hard mask films with graded vertical concentration formed using reactive sputtering in a radio frequency deposition chamber
US11015252B2 (en) 2018-04-27 2021-05-25 Applied Materials, Inc. Protection of components from corrosion
US11549175B2 (en) 2018-05-03 2023-01-10 Lam Research Corporation Method of depositing tungsten and other metals in 3D NAND structures
US10950429B2 (en) 2018-05-08 2021-03-16 Applied Materials, Inc. Methods of forming amorphous carbon hard mask layers and hard mask layers formed therefrom
CN112204169A (en) * 2018-05-16 2021-01-08 应用材料公司 Atomic layer self-aligned substrate processing and integrated tool set
US11081358B2 (en) * 2018-07-05 2021-08-03 Applied Materials, Inc. Silicide film nucleation
US10748783B2 (en) 2018-07-25 2020-08-18 Applied Materials, Inc. Gas delivery module
US10675581B2 (en) 2018-08-06 2020-06-09 Applied Materials, Inc. Gas abatement apparatus
WO2020033629A1 (en) * 2018-08-10 2020-02-13 Applied Materials, Inc. Methods and apparatus for producing semiconductor liners
US11009339B2 (en) 2018-08-23 2021-05-18 Applied Materials, Inc. Measurement of thickness of thermal barrier coatings using 3D imaging and surface subtraction methods for objects with complex geometries
CN110890275B (en) * 2018-09-07 2022-04-12 长鑫存储技术有限公司 Metal silicide forming method
KR20210077779A (en) 2018-11-16 2021-06-25 어플라이드 머티어리얼스, 인코포레이티드 Film Deposition Using Enhanced Diffusion Process
US10636705B1 (en) 2018-11-29 2020-04-28 Applied Materials, Inc. High pressure annealing of metal gate structures
WO2020117462A1 (en) 2018-12-07 2020-06-11 Applied Materials, Inc. Semiconductor processing system
EP3959356A4 (en) 2019-04-26 2023-01-18 Applied Materials, Inc. Methods of protecting aerospace components against corrosion and oxidation
US11794382B2 (en) 2019-05-16 2023-10-24 Applied Materials, Inc. Methods for depositing anti-coking protective coatings on aerospace components
US11697879B2 (en) 2019-06-14 2023-07-11 Applied Materials, Inc. Methods for depositing sacrificial coatings on aerospace components
US11466364B2 (en) 2019-09-06 2022-10-11 Applied Materials, Inc. Methods for forming protective coatings containing crystallized aluminum oxide
US11901222B2 (en) 2020-02-17 2024-02-13 Applied Materials, Inc. Multi-step process for flowable gap-fill film
US11519066B2 (en) 2020-05-21 2022-12-06 Applied Materials, Inc. Nitride protective coatings on aerospace components and methods for making the same
CN115734826A (en) 2020-07-03 2023-03-03 应用材料公司 Method for refurbishing aircraft components
CN111816551A (en) * 2020-09-09 2020-10-23 南京晶驱集成电路有限公司 Manufacturing method and manufacturing system of semiconductor layer
US20220081759A1 (en) * 2020-09-17 2022-03-17 Taiwan Semiconductor Manufacturing Co., Ltd. Apparatus and method for manufacturing metal gate structures
US11515200B2 (en) * 2020-12-03 2022-11-29 Applied Materials, Inc. Selective tungsten deposition within trench structures

Family Cites Families (179)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6482262B1 (en) * 1959-10-10 2002-11-19 Asm Microchemistry Oy Deposition of transition metal carbides
SE393967B (en) 1974-11-29 1977-05-31 Sateko Oy PROCEDURE AND PERFORMANCE OF LAYING BETWEEN THE STORAGE IN A LABOR PACKAGE
FI57975C (en) 1979-02-28 1980-11-10 Lohja Ab Oy OVER ANCHORING VIDEO UPDATE FOR AVAILABILITY
US4389973A (en) 1980-03-18 1983-06-28 Oy Lohja Ab Apparatus for performing growth of compound thin films
US4415275A (en) 1981-12-21 1983-11-15 Dietrich David E Swirl mixing device
FI64878C (en) 1982-05-10 1984-01-10 Lohja Ab Oy KOMBINATIONSFILM FOER ISYNNERHET TUNNFILMELEKTROLUMINENSSTRUKTURER
US4500409A (en) 1983-07-19 1985-02-19 Varian Associates, Inc. Magnetron sputter coating source for both magnetic and non magnetic target materials
GB2162207B (en) 1984-07-26 1989-05-10 Japan Res Dev Corp Semiconductor crystal growth apparatus
US5294286A (en) 1984-07-26 1994-03-15 Research Development Corporation Of Japan Process for forming a thin film of silicon
US5096364A (en) * 1986-04-28 1992-03-17 Varian Associates, Inc. Wafer arm handler mechanism
US4761269A (en) 1986-06-12 1988-08-02 Crystal Specialties, Inc. Apparatus for depositing material on a substrate
JPH0639357B2 (en) 1986-09-08 1994-05-25 新技術開発事業団 Method for growing element semiconductor single crystal thin film
US5227335A (en) 1986-11-10 1993-07-13 At&T Bell Laboratories Tungsten metallization
US4951601A (en) * 1986-12-19 1990-08-28 Applied Materials, Inc. Multi-chamber integrated process system
JP2555045B2 (en) 1987-01-19 1996-11-20 株式会社日立製作所 Thin film forming method and apparatus
DE3721637A1 (en) 1987-06-30 1989-01-12 Aixtron Gmbh GAS INLET FOR A MULTIPLE DIFFERENT REACTION GAS IN REACTION VESSELS
US4824544A (en) 1987-10-29 1989-04-25 International Business Machines Corporation Large area cathode lift-off sputter deposition device
DE3743938C2 (en) 1987-12-23 1995-08-31 Cs Halbleiter Solartech Process for atomic layer epitaxy growth of a III / V compound semiconductor thin film
FR2628985B1 (en) 1988-03-22 1990-12-28 Labo Electronique Physique EPITAXY REACTOR WITH WALL PROTECTION
US5261959A (en) 1988-05-26 1993-11-16 General Electric Company Diamond crystal growth apparatus
JPH0666287B2 (en) 1988-07-25 1994-08-24 富士通株式会社 Method for manufacturing semiconductor device
JPH0824191B2 (en) 1989-03-17 1996-03-06 富士通株式会社 Thin film transistor
US5186718A (en) * 1989-05-19 1993-02-16 Applied Materials, Inc. Staged-vacuum wafer processing system and method
US5028565A (en) 1989-08-25 1991-07-02 Applied Materials, Inc. Process for CVD deposition of tungsten layer on semiconductor wafer
DE69014027T2 (en) 1989-08-30 1995-06-01 Nec Corp Thin film capacitors and their manufacturing processes.
EP0440377B1 (en) 1990-01-29 1998-03-18 Varian Associates, Inc. Collimated deposition apparatus and method
US5320728A (en) 1990-03-30 1994-06-14 Applied Materials, Inc. Planar magnetron sputtering source producing improved coating thickness uniformity, step coverage and step coverage uniformity
US5242566A (en) 1990-04-23 1993-09-07 Applied Materials, Inc. Planar magnetron sputtering source enabling a controlled sputtering profile out to the target perimeter
US5225366A (en) 1990-06-22 1993-07-06 The United States Of America As Represented By The Secretary Of The Navy Apparatus for and a method of growing thin films of elemental semiconductors
US5252807A (en) 1990-07-02 1993-10-12 George Chizinsky Heated plate rapid thermal processor
US5483919A (en) 1990-08-31 1996-01-16 Nippon Telegraph And Telephone Corporation Atomic layer epitaxy method and apparatus
US5286296A (en) 1991-01-10 1994-02-15 Sony Corporation Multi-chamber wafer process equipment having plural, physically communicating transfer means
US5178681A (en) 1991-01-29 1993-01-12 Applied Materials, Inc. Suspension system for semiconductor reactors
US5173327A (en) 1991-06-18 1992-12-22 Micron Technology, Inc. LPCVD process for depositing titanium films for semiconductor devices
US5480818A (en) 1992-02-10 1996-01-02 Fujitsu Limited Method for forming a film and method for manufacturing a thin film transistor
US5660744A (en) 1992-03-26 1997-08-26 Kabushiki Kaisha Toshiba Plasma generating apparatus and surface processing apparatus
US5306666A (en) 1992-07-24 1994-04-26 Nippon Steel Corporation Process for forming a thin metal film by chemical vapor deposition
US5338362A (en) 1992-08-29 1994-08-16 Tokyo Electron Limited Apparatus for processing semiconductor wafer comprising continuously rotating wafer table and plural chamber compartments
US5607009A (en) 1993-01-28 1997-03-04 Applied Materials, Inc. Method of heating and cooling large area substrates and apparatus therefor
US5335138A (en) 1993-02-12 1994-08-02 Micron Semiconductor, Inc. High dielectric constant capacitor and method of manufacture
JP3265042B2 (en) 1993-03-18 2002-03-11 東京エレクトロン株式会社 Film formation method
US5443647A (en) 1993-04-28 1995-08-22 The United States Of America As Represented By The Secretary Of The Army Method and apparatus for depositing a refractory thin film by chemical vapor deposition
TW271490B (en) 1993-05-05 1996-03-01 Varian Associates
US5526244A (en) 1993-05-24 1996-06-11 Bishop; Vernon R. Overhead luminaire
KR960005377Y1 (en) 1993-06-24 1996-06-28 현대전자산업 주식회사 Sputtering apparatus for semiconductor device manufacture
US6171922B1 (en) 1993-09-01 2001-01-09 National Semiconductor Corporation SiCr thin film resistors having improved temperature coefficients of resistance and sheet resistance
DE69403768T2 (en) 1993-12-28 1997-11-13 Tokyo Electron Ltd Dipole ring magnet for magnetron sputtering or magnetron etching
US5666247A (en) 1994-02-04 1997-09-09 Seagate Technology, Inc. No-field, low power FeMn deposition giving high exchange films
KR970009828B1 (en) 1994-02-23 1997-06-18 Sansung Electronics Co Ltd Fabrication method of collimator
JP3181171B2 (en) 1994-05-20 2001-07-03 シャープ株式会社 Vapor phase growth apparatus and vapor phase growth method
US5796116A (en) 1994-07-27 1998-08-18 Sharp Kabushiki Kaisha Thin-film semiconductor device including a semiconductor film with high field-effect mobility
US5504041A (en) 1994-08-01 1996-04-02 Texas Instruments Incorporated Conductive exotic-nitride barrier layer for high-dielectric-constant materials
JPH0860355A (en) 1994-08-23 1996-03-05 Tel Varian Ltd Treating device
JP2655094B2 (en) 1994-08-30 1997-09-17 日本電気株式会社 Electron gun deposition equipment
US5616218A (en) 1994-09-12 1997-04-01 Matereials Research Corporation Modification and selection of the magnetic properties of magnetic recording media through selective control of the crystal texture of the recording layer
US5945008A (en) 1994-09-29 1999-08-31 Sony Corporation Method and apparatus for plasma control
JP2671835B2 (en) 1994-10-20 1997-11-05 日本電気株式会社 Sputtering apparatus and method for manufacturing semiconductor device using the apparatus
FI97730C (en) 1994-11-28 1997-02-10 Mikrokemia Oy Equipment for the production of thin films
FI97731C (en) 1994-11-28 1997-02-10 Mikrokemia Oy Method and apparatus for making thin films
FI100409B (en) 1994-11-28 1997-11-28 Asm Int Method and apparatus for making thin films
US5527438A (en) 1994-12-16 1996-06-18 Applied Materials, Inc. Cylindrical sputtering shield
JPH08186085A (en) 1994-12-28 1996-07-16 Nec Corp Manufacture of semiconductor device
US5663088A (en) 1995-05-19 1997-09-02 Micron Technology, Inc. Method of forming a Ta2 O5 dielectric layer with amorphous diffusion barrier layer and method of forming a capacitor having a Ta2 O5 dielectric layer and amorphous diffusion barrier layer
US5632873A (en) 1995-05-22 1997-05-27 Stevens; Joseph J. Two piece anti-stick clamp ring
US5780361A (en) 1995-06-23 1998-07-14 Nec Corporation Salicide process for selectively forming a monocobalt disilicide film on a silicon region
CA2225681C (en) 1995-06-28 2001-09-11 Bell Communications Research, Inc. Barrier layer for ferroelectric capacitor integrated on silicon
KR0167248B1 (en) 1995-07-24 1999-02-01 문정환 Heat treatment of substrate
US5589039A (en) 1995-07-28 1996-12-31 Sony Corporation In-plane parallel bias magnetic field generator for sputter coating magnetic materials onto substrates
US6238533B1 (en) 1995-08-07 2001-05-29 Applied Materials, Inc. Integrated PVD system for aluminum hole filling using ionized metal adhesion layer
US5804488A (en) 1995-08-24 1998-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a tungsten silicide capacitor having a high breakdown voltage
US5650052A (en) 1995-10-04 1997-07-22 Edelstein; Sergio Variable cell size collimator
US6084302A (en) 1995-12-26 2000-07-04 Micron Technologies, Inc. Barrier layer cladding around copper interconnect lines
JPH09316643A (en) 1996-02-15 1997-12-09 Mitsubishi Materials Corp Sticking preventing parts for physical vapor deposition system
EP0799903A3 (en) * 1996-04-05 1999-11-17 Applied Materials, Inc. Methods of sputtering a metal onto a substrate and semiconductor processing apparatus
US6313035B1 (en) * 1996-05-31 2001-11-06 Micron Technology, Inc. Chemical vapor deposition using organometallic precursors
US6342277B1 (en) * 1996-08-16 2002-01-29 Licensee For Microelectronics: Asm America, Inc. Sequential chemical vapor deposition
US5736021A (en) 1996-07-10 1998-04-07 Applied Materials, Inc. Electrically floating shield in a plasma reactor
US5916365A (en) 1996-08-16 1999-06-29 Sherman; Arthur Sequential chemical vapor deposition
TW351825B (en) 1996-09-12 1999-02-01 Tokyo Electron Ltd Plasma process device
US5835677A (en) 1996-10-03 1998-11-10 Emcore Corporation Liquid vaporizer system and method
US5923056A (en) 1996-10-10 1999-07-13 Lucent Technologies Inc. Electronic components with doped metal oxide dielectric materials and a process for making electronic components with doped metal oxide dielectric materials
US6071572A (en) 1996-10-15 2000-06-06 Applied Materials, Inc. Forming tin thin films using remote activated specie generation
US6224312B1 (en) * 1996-11-18 2001-05-01 Applied Materials, Inc. Optimal trajectory robot motion
US5886864A (en) * 1996-12-02 1999-03-23 Applied Materials, Inc. Substrate support member for uniform heating of a substrate
US5807792A (en) 1996-12-18 1998-09-15 Siemens Aktiengesellschaft Uniform distribution of reactants in a device layer
JP4142753B2 (en) 1996-12-26 2008-09-03 株式会社東芝 Sputtering target, sputtering apparatus, semiconductor device and manufacturing method thereof
US6335280B1 (en) * 1997-01-13 2002-01-01 Asm America, Inc. Tungsten silicide deposition process
US6221766B1 (en) 1997-01-24 2001-04-24 Steag Rtp Systems, Inc. Method and apparatus for processing refractory metals on semiconductor substrates
US5879459A (en) 1997-08-29 1999-03-09 Genus, Inc. Vertically-stacked process reactor and cluster tool system for atomic layer deposition
US6174377B1 (en) * 1997-03-03 2001-01-16 Genus, Inc. Processing chamber for atomic layer deposition processes
US5936831A (en) 1997-03-06 1999-08-10 Lucent Technologies Inc. Thin film tantalum oxide capacitors and resulting product
US5902129A (en) 1997-04-07 1999-05-11 Lsi Logic Corporation Process for forming improved cobalt silicide layer on integrated circuit structure using two capping layers
JPH10306377A (en) 1997-05-02 1998-11-17 Tokyo Electron Ltd Method for supplying minute amount of gas and device therefor
US6692617B1 (en) * 1997-05-08 2004-02-17 Applied Materials, Inc. Sustained self-sputtering reactor having an increased density plasma
US6156382A (en) 1997-05-16 2000-12-05 Applied Materials, Inc. Chemical vapor deposition process for depositing tungsten
JPH111770A (en) 1997-06-06 1999-01-06 Anelva Corp Sputtering apparatus and sputtering method
US6162715A (en) 1997-06-30 2000-12-19 Applied Materials, Inc. Method of forming gate electrode connection structure by in situ chemical vapor deposition of tungsten and tungsten nitride
KR100385946B1 (en) * 1999-12-08 2003-06-02 삼성전자주식회사 Method for forming a metal layer by an atomic layer deposition and a semiconductor device with the metal layer as a barrier metal layer, an upper electrode, or a lower electrode of capacitor
KR100269306B1 (en) 1997-07-31 2000-10-16 윤종용 Integrate circuit device having buffer layer containing metal oxide stabilized by low temperature treatment and fabricating method thereof
US5879523A (en) 1997-09-29 1999-03-09 Applied Materials, Inc. Ceramic coated metallic insulator particularly useful in a plasma sputter reactor
US6348376B2 (en) * 1997-09-29 2002-02-19 Samsung Electronics Co., Ltd. Method of forming metal nitride film by chemical vapor deposition and method of forming metal contact and capacitor of semiconductor device using the same
US6071055A (en) 1997-09-30 2000-06-06 Applied Materials, Inc. Front end vacuum processing environment
KR100274603B1 (en) 1997-10-01 2001-01-15 윤종용 Method and apparatus for fabricating semiconductor device
US6235634B1 (en) * 1997-10-08 2001-05-22 Applied Komatsu Technology, Inc. Modular substrate processing system
JPH11195621A (en) * 1997-11-05 1999-07-21 Tokyo Electron Ltd Barrier metal, its formation, gate electrode, and its formation
US6179983B1 (en) 1997-11-13 2001-01-30 Novellus Systems, Inc. Method and apparatus for treating surface including virtual anode
US5972430A (en) 1997-11-26 1999-10-26 Advanced Technology Materials, Inc. Digital chemical vapor deposition (CVD) method for forming a multi-component oxide layer
US6099904A (en) 1997-12-02 2000-08-08 Applied Materials, Inc. Low resistivity W using B2 H6 nucleation step
KR100269328B1 (en) * 1997-12-31 2000-10-16 윤종용 Method for forming conductive layer using atomic layer deposition process
US6015917A (en) 1998-01-23 2000-01-18 Advanced Technology Materials, Inc. Tantalum amide precursors for deposition of tantalum nitride on a substrate
US6074922A (en) 1998-03-13 2000-06-13 Taiwan Semiconductor Manufacturing Company Enhanced structure for salicide MOSFET
KR100267885B1 (en) * 1998-05-18 2000-11-01 서성기 Deposition apparatus
JP3375302B2 (en) * 1998-07-29 2003-02-10 東京エレクトロン株式会社 Magnetron plasma processing apparatus and processing method
GB2340845B (en) 1998-08-19 2001-01-31 Kobe Steel Ltd Magnetron sputtering apparatus
US6132575A (en) 1998-09-28 2000-10-17 Alcatel Magnetron reactor for providing a high density, inductively coupled plasma source for sputtering metal and dielectric films
US6251759B1 (en) 1998-10-03 2001-06-26 Applied Materials, Inc. Method and apparatus for depositing material upon a semiconductor wafer using a transition chamber of a multiple chamber semiconductor wafer processing system
JP2000195821A (en) * 1998-12-24 2000-07-14 Nec Corp Manufacture of semiconductor and semiconductor device
US6165807A (en) 1999-01-25 2000-12-26 Taiwan Smiconductor Manufacturing Company Method for forming junction leakage monitor for mosfets with silicide contacts
US6225176B1 (en) 1999-02-22 2001-05-01 Advanced Micro Devices, Inc. Step drain and source junction formation
KR100347379B1 (en) 1999-05-01 2002-08-07 주식회사 피케이엘 Atomic layer deposition apparatus for depositing multi substrate
US6124158A (en) 1999-06-08 2000-09-26 Lucent Technologies Inc. Method of reducing carbon contamination of a thin dielectric film by using gaseous organic precursors, inert gas, and ozone to react with carbon contaminants
US6524952B1 (en) * 1999-06-25 2003-02-25 Applied Materials, Inc. Method of forming a titanium silicide layer on a substrate
US6984415B2 (en) * 1999-08-20 2006-01-10 International Business Machines Corporation Delivery systems for gases for gases via the sublimation of solid precursors
US6511539B1 (en) * 1999-09-08 2003-01-28 Asm America, Inc. Apparatus and method for growth of a thin film
WO2001038486A2 (en) * 1999-11-22 2001-05-31 Human Genome Sciences, Inc. Kunitz-type protease inhibitor polynucleotides, polypeptides, and antibodies
KR100705926B1 (en) * 1999-12-22 2007-04-11 주식회사 하이닉스반도체 Method of manufacturing a capacitor in a semiconductor device
EP1266054B1 (en) * 2000-03-07 2006-12-20 Asm International N.V. Graded thin films
US6482733B2 (en) * 2000-05-15 2002-11-19 Asm Microchemistry Oy Protective layers prior to alternating layer deposition
TW508658B (en) * 2000-05-15 2002-11-01 Asm Microchemistry Oy Process for producing integrated circuits
KR100427423B1 (en) * 2000-05-25 2004-04-13 가부시키가이샤 고베 세이코쇼 Inner tube for cvd apparatus
WO2001099166A1 (en) * 2000-06-08 2001-12-27 Genitech Inc. Thin film forming method
KR100387255B1 (en) * 2000-06-20 2003-06-11 주식회사 하이닉스반도체 Method of forming a metal wiring in a semiconductor device
KR100332314B1 (en) * 2000-06-24 2002-04-12 서성기 Reactor for depositing thin film on wafer
US6620723B1 (en) * 2000-06-27 2003-09-16 Applied Materials, Inc. Formation of boride barrier layers using chemisorption techniques
US7405158B2 (en) * 2000-06-28 2008-07-29 Applied Materials, Inc. Methods for depositing tungsten layers employing atomic layer deposition techniques
US6551929B1 (en) * 2000-06-28 2003-04-22 Applied Materials, Inc. Bifurcated deposition process for depositing refractory metal layers employing atomic layer deposition and chemical vapor deposition techniques
US6936538B2 (en) * 2001-07-16 2005-08-30 Applied Materials, Inc. Method and apparatus for depositing tungsten after surface treatment to improve film characteristics
KR100444149B1 (en) * 2000-07-22 2004-08-09 주식회사 아이피에스 ALD thin film depositin equipment cleaning method
KR100396879B1 (en) * 2000-08-11 2003-09-02 삼성전자주식회사 Semiconductor memory device having capacitor encapsulated by multi-layer which includes double layeres being made of same material and method of manufacturing thereof
US6346477B1 (en) * 2001-01-09 2002-02-12 Research Foundation Of Suny - New York Method of interlayer mediated epitaxy of cobalt silicide from low temperature chemical vapor deposition of cobalt
US6951804B2 (en) * 2001-02-02 2005-10-04 Applied Materials, Inc. Formation of a tantalum-nitride layer
US6878206B2 (en) * 2001-07-16 2005-04-12 Applied Materials, Inc. Lid assembly for a processing system to facilitate sequential deposition techniques
US7141494B2 (en) * 2001-05-22 2006-11-28 Novellus Systems, Inc. Method for reducing tungsten film roughness and improving step coverage
US7005372B2 (en) * 2003-01-21 2006-02-28 Novellus Systems, Inc. Deposition of tungsten nitride
US6828218B2 (en) * 2001-05-31 2004-12-07 Samsung Electronics Co., Ltd. Method of forming a thin film using atomic layer deposition
JP4680429B2 (en) * 2001-06-26 2011-05-11 Okiセミコンダクタ株式会社 High speed reading control method in text-to-speech converter
US20070009658A1 (en) * 2001-07-13 2007-01-11 Yoo Jong H Pulse nucleation enhanced nucleation technique for improved step coverage and better gap fill for WCVD process
JP2005518088A (en) * 2001-07-16 2005-06-16 アプライド マテリアルズ インコーポレイテッド Formation of tungsten composite film
US20030017697A1 (en) * 2001-07-19 2003-01-23 Kyung-In Choi Methods of forming metal layers using metallic precursors
US20030015421A1 (en) * 2001-07-20 2003-01-23 Applied Materials, Inc. Collimated sputtering of cobalt
SG126681A1 (en) * 2001-07-25 2006-11-29 Inst Data Storage Oblique deposition apparatus
WO2003030224A2 (en) * 2001-07-25 2003-04-10 Applied Materials, Inc. Barrier formation using novel sputter-deposition method
US20030029715A1 (en) * 2001-07-25 2003-02-13 Applied Materials, Inc. An Apparatus For Annealing Substrates In Physical Vapor Deposition Systems
US20090004850A1 (en) * 2001-07-25 2009-01-01 Seshadri Ganguli Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US6548906B2 (en) * 2001-08-22 2003-04-15 Agere Systems Inc. Method for reducing a metal seam in an interconnect structure and a device manufactured thereby
TW589684B (en) * 2001-10-10 2004-06-01 Applied Materials Inc Method for depositing refractory metal layers employing sequential deposition techniques
US6916398B2 (en) * 2001-10-26 2005-07-12 Applied Materials, Inc. Gas delivery apparatus and method for atomic layer deposition
US6998014B2 (en) * 2002-01-26 2006-02-14 Applied Materials, Inc. Apparatus and method for plasma assisted deposition
US6833161B2 (en) * 2002-02-26 2004-12-21 Applied Materials, Inc. Cyclical deposition of tungsten nitride for metal oxide gate electrode
US6846516B2 (en) * 2002-04-08 2005-01-25 Applied Materials, Inc. Multiple precursor cyclical deposition system
US7279432B2 (en) * 2002-04-16 2007-10-09 Applied Materials, Inc. System and method for forming an integrated barrier layer
US7005697B2 (en) * 2002-06-21 2006-02-28 Micron Technology, Inc. Method of forming a non-volatile electron storage memory and the resulting device
KR100476926B1 (en) * 2002-07-02 2005-03-17 삼성전자주식회사 Method for forming dual gate of semiconductor device
US6838125B2 (en) * 2002-07-10 2005-01-04 Applied Materials, Inc. Method of film deposition using activated precursor gases
US20040013803A1 (en) * 2002-07-16 2004-01-22 Applied Materials, Inc. Formation of titanium nitride films using a cyclical deposition process
US7186385B2 (en) * 2002-07-17 2007-03-06 Applied Materials, Inc. Apparatus for providing gas to a processing chamber
US6955211B2 (en) * 2002-07-17 2005-10-18 Applied Materials, Inc. Method and apparatus for gas temperature control in a semiconductor processing system
US7066194B2 (en) * 2002-07-19 2006-06-27 Applied Materials, Inc. Valve design and configuration for fast delivery system
KR100468852B1 (en) * 2002-07-20 2005-01-29 삼성전자주식회사 Manufacturing method of Capacitor Structure
US6772072B2 (en) * 2002-07-22 2004-08-03 Applied Materials, Inc. Method and apparatus for monitoring solid precursor delivery
US7300038B2 (en) * 2002-07-23 2007-11-27 Advanced Technology Materials, Inc. Method and apparatus to help promote contact of gas with vaporized material
US6921062B2 (en) * 2002-07-23 2005-07-26 Advanced Technology Materials, Inc. Vaporizer delivery ampoule
US6915592B2 (en) * 2002-07-29 2005-07-12 Applied Materials, Inc. Method and apparatus for generating gas to a processing chamber
KR100542736B1 (en) * 2002-08-17 2006-01-11 삼성전자주식회사 Method of forming oxide layer using atomic layer deposition method and method of forming capacitor of semiconductor device using the same
US7262133B2 (en) * 2003-01-07 2007-08-28 Applied Materials, Inc. Enhancement of copper line reliability using thin ALD tan film to cap the copper line
KR20060079144A (en) * 2003-06-18 2006-07-05 어플라이드 머티어리얼스, 인코포레이티드 Atomic layer deposition of barrier materials
US20060033678A1 (en) * 2004-01-26 2006-02-16 Applied Materials, Inc. Integrated electroless deposition system
KR100871006B1 (en) * 2004-07-30 2008-11-27 어플라이드 머티어리얼스, 인코포레이티드 Thin tungsten silicide layer deposition and gate metal integration
US20070020890A1 (en) * 2005-07-19 2007-01-25 Applied Materials, Inc. Method and apparatus for semiconductor processing

Cited By (333)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070218688A1 (en) * 2000-06-28 2007-09-20 Ming Xi Method for depositing tungsten-containing layers by vapor deposition techniques
US20090156004A1 (en) * 2000-06-28 2009-06-18 Moris Kori Method for forming tungsten materials during vapor deposition processes
US20100093170A1 (en) * 2000-06-28 2010-04-15 Applied Materials, Inc. Method for forming tungsten materials during vapor deposition processes
US7709385B2 (en) 2000-06-28 2010-05-04 Applied Materials, Inc. Method for depositing tungsten-containing layers by vapor deposition techniques
US7732327B2 (en) 2000-06-28 2010-06-08 Applied Materials, Inc. Vapor deposition of tungsten materials
US7745333B2 (en) 2000-06-28 2010-06-29 Applied Materials, Inc. Methods for depositing tungsten layers employing atomic layer deposition techniques
US20080280438A1 (en) * 2000-06-28 2008-11-13 Ken Kaung Lai Methods for depositing tungsten layers employing atomic layer deposition techniques
US7846840B2 (en) 2000-06-28 2010-12-07 Applied Materials, Inc. Method for forming tungsten materials during vapor deposition processes
US7674715B2 (en) 2000-06-28 2010-03-09 Applied Materials, Inc. Method for forming tungsten materials during vapor deposition processes
US7695563B2 (en) 2001-07-13 2010-04-13 Applied Materials, Inc. Pulsed deposition process for tungsten nucleation
US20080317954A1 (en) * 2001-07-13 2008-12-25 Xinliang Lu Pulsed deposition process for tungsten nucleation
US7749815B2 (en) 2001-07-16 2010-07-06 Applied Materials, Inc. Methods for depositing tungsten after surface treatment
US20110086509A1 (en) * 2001-07-25 2011-04-14 Seshadri Ganguli Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US20090053426A1 (en) * 2001-07-25 2009-02-26 Jiang Lu Cobalt deposition on barrier surfaces
US8187970B2 (en) 2001-07-25 2012-05-29 Applied Materials, Inc. Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US8563424B2 (en) 2001-07-25 2013-10-22 Applied Materials, Inc. Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US20090004850A1 (en) * 2001-07-25 2009-01-01 Seshadri Ganguli Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US20070202254A1 (en) * 2001-07-25 2007-08-30 Seshadri Ganguli Process for forming cobalt-containing materials
US9209074B2 (en) 2001-07-25 2015-12-08 Applied Materials, Inc. Cobalt deposition on barrier surfaces
US8110489B2 (en) 2001-07-25 2012-02-07 Applied Materials, Inc. Process for forming cobalt-containing materials
US8815724B2 (en) 2001-07-25 2014-08-26 Applied Materials, Inc. Process for forming cobalt-containing materials
US9051641B2 (en) 2001-07-25 2015-06-09 Applied Materials, Inc. Cobalt deposition on barrier surfaces
US20080268636A1 (en) * 2001-07-25 2008-10-30 Ki Hwan Yoon Deposition methods for barrier and tungsten materials
US20070283886A1 (en) * 2001-09-26 2007-12-13 Hua Chung Apparatus for integration of barrier layer and seed layer
US7780788B2 (en) 2001-10-26 2010-08-24 Applied Materials, Inc. Gas delivery apparatus for atomic layer deposition
US20050173068A1 (en) * 2001-10-26 2005-08-11 Ling Chen Gas delivery apparatus and method for atomic layer deposition
US8668776B2 (en) 2001-10-26 2014-03-11 Applied Materials, Inc. Gas delivery apparatus and method for atomic layer deposition
US20100247767A1 (en) * 2001-10-26 2010-09-30 Ling Chen Gas delivery apparatus and method for atomic layer deposition
US7202151B2 (en) * 2001-11-20 2007-04-10 Oki Electric Industry Co., Ltd. Method for fabricating a semiconductor device having a metallic silicide layer
US20040161917A1 (en) * 2001-11-20 2004-08-19 Kazuya Hizawa Method for fabricating a semiconductor device having a metallic silicide layer
US7892602B2 (en) 2001-12-07 2011-02-22 Applied Materials, Inc. Cyclical deposition of refractory metal silicon nitride
US20080305629A1 (en) * 2002-02-26 2008-12-11 Shulin Wang Tungsten nitride atomic layer deposition processes
US7745329B2 (en) 2002-02-26 2010-06-29 Applied Materials, Inc. Tungsten nitride atomic layer deposition processes
US20110070730A1 (en) * 2002-03-04 2011-03-24 Wei Cao Sequential deposition of tantalum nitride using a tantalum-containing precursor and a nitrogen-containing precursor
US20060019494A1 (en) * 2002-03-04 2006-01-26 Wei Cao Sequential deposition of tantalum nitride using a tantalum-containing precursor and a nitrogen-containing precursor
US7867896B2 (en) 2002-03-04 2011-01-11 Applied Materials, Inc. Sequential deposition of tantalum nitride using a tantalum-containing precursor and a nitrogen-containing precursor
US7867914B2 (en) 2002-04-16 2011-01-11 Applied Materials, Inc. System and method for forming an integrated barrier layer
US20030235973A1 (en) * 2002-06-21 2003-12-25 Jiong-Ping Lu Nickel SALICIDE process technology for CMOS devices
US7011734B2 (en) * 2002-10-17 2006-03-14 Fujitsu Limited Method of manufacturing semiconductor device having silicide layer
US20040092123A1 (en) * 2002-10-17 2004-05-13 Fujitsu Limited Method of manufacturing semiconductor device having silicide layer
US20070151514A1 (en) * 2002-11-14 2007-07-05 Ling Chen Apparatus and method for hybrid chemical processing
US20070190780A1 (en) * 2003-06-18 2007-08-16 Applied Materials, Inc. Atomic layer deposition of barrier materials
US20050092598A1 (en) * 2003-11-05 2005-05-05 Industrial Technology Research Institute Sputtering process with temperature control for salicide application
US20090111280A1 (en) * 2004-02-26 2009-04-30 Applied Materials, Inc. Method for removing oxides
US8846163B2 (en) 2004-02-26 2014-09-30 Applied Materials, Inc. Method for removing oxides
US8282992B2 (en) 2004-05-12 2012-10-09 Applied Materials, Inc. Methods for atomic layer deposition of hafnium-containing high-K dielectric materials
US20050252449A1 (en) * 2004-05-12 2005-11-17 Nguyen Son T Control of gas flow and delivery to suppress the formation of particles in an MOCVD/ALD system
US7794544B2 (en) 2004-05-12 2010-09-14 Applied Materials, Inc. Control of gas flow and delivery to suppress the formation of particles in an MOCVD/ALD system
US8343279B2 (en) 2004-05-12 2013-01-01 Applied Materials, Inc. Apparatuses for atomic layer deposition
US20080044569A1 (en) * 2004-05-12 2008-02-21 Myo Nyi O Methods for atomic layer deposition of hafnium-containing high-k dielectric materials
US20060153995A1 (en) * 2004-05-21 2006-07-13 Applied Materials, Inc. Method for fabricating a dielectric stack
US7569483B2 (en) * 2004-08-09 2009-08-04 Samsung Electronics Co., Ltd. Methods of forming metal silicide layers by annealing metal layers using inert heat transferring gases established in a convection apparatus
US20060063380A1 (en) * 2004-08-09 2006-03-23 Sug-Woo Jung Salicide process and method of fabricating semiconductor device using the same
US20090142474A1 (en) * 2004-12-10 2009-06-04 Srinivas Gandikota Ruthenium as an underlayer for tungsten film deposition
US7691442B2 (en) 2004-12-10 2010-04-06 Applied Materials, Inc. Ruthenium or cobalt as an underlayer for tungsten film deposition
US7964505B2 (en) 2005-01-19 2011-06-21 Applied Materials, Inc. Atomic layer deposition of tungsten materials
US20090053893A1 (en) * 2005-01-19 2009-02-26 Amit Khandelwal Atomic layer deposition of tungsten materials
US20080044595A1 (en) * 2005-07-19 2008-02-21 Randhir Thakur Method for semiconductor processing
US20070119370A1 (en) * 2005-11-04 2007-05-31 Paul Ma Apparatus and process for plasma-enhanced atomic layer deposition
US7850779B2 (en) 2005-11-04 2010-12-14 Applied Materisals, Inc. Apparatus and process for plasma-enhanced atomic layer deposition
US20070128863A1 (en) * 2005-11-04 2007-06-07 Paul Ma Apparatus and process for plasma-enhanced atomic layer deposition
US20070128862A1 (en) * 2005-11-04 2007-06-07 Paul Ma Apparatus and process for plasma-enhanced atomic layer deposition
US9032906B2 (en) 2005-11-04 2015-05-19 Applied Materials, Inc. Apparatus and process for plasma-enhanced atomic layer deposition
US7682946B2 (en) 2005-11-04 2010-03-23 Applied Materials, Inc. Apparatus and process for plasma-enhanced atomic layer deposition
US20070119371A1 (en) * 2005-11-04 2007-05-31 Paul Ma Apparatus and process for plasma-enhanced atomic layer deposition
US20110124192A1 (en) * 2006-04-11 2011-05-26 Seshadri Ganguli Process for forming cobalt-containing materials
US20070252299A1 (en) * 2006-04-27 2007-11-01 Applied Materials, Inc. Synchronization of precursor pulsing and wafer rotation
US7798096B2 (en) 2006-05-05 2010-09-21 Applied Materials, Inc. Plasma, UV and ion/neutral assisted ALD or CVD in a batch tool
US20070259110A1 (en) * 2006-05-05 2007-11-08 Applied Materials, Inc. Plasma, uv and ion/neutral assisted ald or cvd in a batch tool
TWI462228B (en) * 2006-06-15 2014-11-21 Advanced Micro Devices Inc Low contact resistance cmos circuits and methods for their fabrication
US20080006523A1 (en) * 2006-06-26 2008-01-10 Akihiro Hosokawa Cooled pvd shield
US9222165B2 (en) * 2006-06-26 2015-12-29 Applied Materials, Inc. Cooled PVD shield
US20120111273A1 (en) * 2006-06-26 2012-05-10 Akihiro Hosokawa Cooled pvd shield
US20080135914A1 (en) * 2006-06-30 2008-06-12 Krishna Nety M Nanocrystal formation
US20080076246A1 (en) * 2006-09-25 2008-03-27 Peterson Brennan L Through contact layer opening silicide and barrier layer formation
US20080085611A1 (en) * 2006-10-09 2008-04-10 Amit Khandelwal Deposition and densification process for titanium nitride barrier layers
US20090280640A1 (en) * 2006-10-09 2009-11-12 Applied Materials Incorporated Deposition and densification process for titanium nitride barrier layers
US7838441B2 (en) 2006-10-09 2010-11-23 Applied Materials, Inc. Deposition and densification process for titanium nitride barrier layers
US20080206987A1 (en) * 2007-01-29 2008-08-28 Gelatos Avgerinos V Process for tungsten nitride deposition by a temperature controlled lid assembly
US20090078916A1 (en) * 2007-09-25 2009-03-26 Applied Materials, Inc. Tantalum carbide nitride materials by vapor deposition processes
US20090081868A1 (en) * 2007-09-25 2009-03-26 Applied Materials, Inc. Vapor deposition processes for tantalum carbide nitride materials
US7678298B2 (en) 2007-09-25 2010-03-16 Applied Materials, Inc. Tantalum carbide nitride materials by vapor deposition processes
US7824743B2 (en) 2007-09-28 2010-11-02 Applied Materials, Inc. Deposition processes for titanium nitride barrier and aluminum
US20090087585A1 (en) * 2007-09-28 2009-04-02 Wei Ti Lee Deposition processes for titanium nitride barrier and aluminum
US7867900B2 (en) 2007-09-28 2011-01-11 Applied Materials, Inc. Aluminum contact integration on cobalt silicide junction
US20090087983A1 (en) * 2007-09-28 2009-04-02 Applied Materials, Inc. Aluminum contact integration on cobalt silicide junction
US11384429B2 (en) 2008-04-29 2022-07-12 Applied Materials, Inc. Selective cobalt deposition on copper surfaces
US20090269507A1 (en) * 2008-04-29 2009-10-29 Sang-Ho Yu Selective cobalt deposition on copper surfaces
US8491967B2 (en) 2008-09-08 2013-07-23 Applied Materials, Inc. In-situ chamber treatment and deposition process
US9418890B2 (en) 2008-09-08 2016-08-16 Applied Materials, Inc. Method for tuning a deposition rate during an atomic layer deposition process
US20100062614A1 (en) * 2008-09-08 2010-03-11 Ma Paul F In-situ chamber treatment and deposition process
US20100218785A1 (en) * 2009-02-27 2010-09-02 Applied Materials, Inc. In situ plasma clean for removal of residue from pedestal surface without breaking vacuum
US8900471B2 (en) 2009-02-27 2014-12-02 Applied Materials, Inc. In situ plasma clean for removal of residue from pedestal surface without breaking vacuum
US9818585B2 (en) 2009-02-27 2017-11-14 Applied Materials, Inc. In situ plasma clean for removal of residue from pedestal surface without breaking vacuum
US20100304027A1 (en) * 2009-05-27 2010-12-02 Applied Materials, Inc. Substrate processing system and methods thereof
US9754800B2 (en) 2010-05-27 2017-09-05 Applied Materials, Inc. Selective etch for silicon films
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US10796918B2 (en) 2010-10-25 2020-10-06 Stmicroelectronics S.R.L. Integrated circuits with backside metalization and production method thereof
US10283321B2 (en) 2011-01-18 2019-05-07 Applied Materials, Inc. Semiconductor processing system and methods using capacitively coupled plasma
US8771539B2 (en) 2011-02-22 2014-07-08 Applied Materials, Inc. Remotely-excited fluorine and water vapor etch
US8999856B2 (en) 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
US10062578B2 (en) 2011-03-14 2018-08-28 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US9064815B2 (en) 2011-03-14 2015-06-23 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US9842744B2 (en) 2011-03-14 2017-12-12 Applied Materials, Inc. Methods for etch of SiN films
US9236266B2 (en) 2011-08-01 2016-01-12 Applied Materials, Inc. Dry-etch for silicon-and-carbon-containing films
US8679982B2 (en) 2011-08-26 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and oxygen
US8679983B2 (en) 2011-09-01 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and nitrogen
US9012302B2 (en) 2011-09-26 2015-04-21 Applied Materials, Inc. Intrench profile
US8927390B2 (en) 2011-09-26 2015-01-06 Applied Materials, Inc. Intrench profile
US8808563B2 (en) 2011-10-07 2014-08-19 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US9418858B2 (en) 2011-10-07 2016-08-16 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US8975152B2 (en) 2011-11-08 2015-03-10 Applied Materials, Inc. Methods of reducing substrate dislocation during gapfill processing
US9892890B2 (en) 2012-04-26 2018-02-13 Intevac, Inc. Narrow source for physical vapor deposition processing
US10062587B2 (en) 2012-07-18 2018-08-28 Applied Materials, Inc. Pedestal with multi-zone temperature control and multiple purge capabilities
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US10032606B2 (en) 2012-08-02 2018-07-24 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9887096B2 (en) 2012-09-17 2018-02-06 Applied Materials, Inc. Differential silicon oxide etch
US9034770B2 (en) 2012-09-17 2015-05-19 Applied Materials, Inc. Differential silicon oxide etch
US9437451B2 (en) 2012-09-18 2016-09-06 Applied Materials, Inc. Radical-component oxide etch
US9023734B2 (en) 2012-09-18 2015-05-05 Applied Materials, Inc. Radical-component oxide etch
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US9978564B2 (en) 2012-09-21 2018-05-22 Applied Materials, Inc. Chemical control features in wafer process equipment
US11264213B2 (en) 2012-09-21 2022-03-01 Applied Materials, Inc. Chemical control features in wafer process equipment
US10354843B2 (en) 2012-09-21 2019-07-16 Applied Materials, Inc. Chemical control features in wafer process equipment
US8765574B2 (en) 2012-11-09 2014-07-01 Applied Materials, Inc. Dry etch process
US9384997B2 (en) 2012-11-20 2016-07-05 Applied Materials, Inc. Dry-etch selectivity
US8969212B2 (en) 2012-11-20 2015-03-03 Applied Materials, Inc. Dry-etch selectivity
US9412608B2 (en) 2012-11-30 2016-08-09 Applied Materials, Inc. Dry-etch for selective tungsten removal
US9064816B2 (en) 2012-11-30 2015-06-23 Applied Materials, Inc. Dry-etch for selective oxidation removal
US8980763B2 (en) 2012-11-30 2015-03-17 Applied Materials, Inc. Dry-etch for selective tungsten removal
US9355863B2 (en) 2012-12-18 2016-05-31 Applied Materials, Inc. Non-local plasma oxide etch
US9111877B2 (en) 2012-12-18 2015-08-18 Applied Materials, Inc. Non-local plasma oxide etch
US8921234B2 (en) 2012-12-21 2014-12-30 Applied Materials, Inc. Selective titanium nitride etching
US9449845B2 (en) 2012-12-21 2016-09-20 Applied Materials, Inc. Selective titanium nitride etching
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US11024486B2 (en) 2013-02-08 2021-06-01 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US10424485B2 (en) 2013-03-01 2019-09-24 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9040422B2 (en) 2013-03-05 2015-05-26 Applied Materials, Inc. Selective titanium nitride removal
US9607856B2 (en) 2013-03-05 2017-03-28 Applied Materials, Inc. Selective titanium nitride removal
US9093390B2 (en) 2013-03-07 2015-07-28 Applied Materials, Inc. Conformal oxide dry etch
US8801952B1 (en) 2013-03-07 2014-08-12 Applied Materials, Inc. Conformal oxide dry etch
US10170282B2 (en) 2013-03-08 2019-01-01 Applied Materials, Inc. Insulated semiconductor faceplate designs
US9184055B2 (en) 2013-03-15 2015-11-10 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9991134B2 (en) 2013-03-15 2018-06-05 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9153442B2 (en) 2013-03-15 2015-10-06 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9449850B2 (en) 2013-03-15 2016-09-20 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9023732B2 (en) 2013-03-15 2015-05-05 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9704723B2 (en) 2013-03-15 2017-07-11 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9659792B2 (en) 2013-03-15 2017-05-23 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9093371B2 (en) 2013-03-15 2015-07-28 Applied Materials, Inc. Processing systems and methods for halide scavenging
US8895449B1 (en) 2013-05-16 2014-11-25 Applied Materials, Inc. Delicate dry clean
US9114438B2 (en) 2013-05-21 2015-08-25 Applied Materials, Inc. Copper residue chamber clean
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US9209012B2 (en) 2013-09-16 2015-12-08 Applied Materials, Inc. Selective etch of silicon nitride
US8956980B1 (en) 2013-09-16 2015-02-17 Applied Materials, Inc. Selective etch of silicon nitride
US8951429B1 (en) 2013-10-29 2015-02-10 Applied Materials, Inc. Tungsten oxide processing
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9236265B2 (en) 2013-11-04 2016-01-12 Applied Materials, Inc. Silicon germanium processing
US9520303B2 (en) 2013-11-12 2016-12-13 Applied Materials, Inc. Aluminum selective etch
US9472417B2 (en) 2013-11-12 2016-10-18 Applied Materials, Inc. Plasma-free metal etch
US9711366B2 (en) 2013-11-12 2017-07-18 Applied Materials, Inc. Selective etch for metal-containing materials
US9472412B2 (en) 2013-12-02 2016-10-18 Applied Materials, Inc. Procedure for etch rate consistency
US9245762B2 (en) 2013-12-02 2016-01-26 Applied Materials, Inc. Procedure for etch rate consistency
US9117855B2 (en) 2013-12-04 2015-08-25 Applied Materials, Inc. Polarity control for remote plasma
US9287095B2 (en) 2013-12-17 2016-03-15 Applied Materials, Inc. Semiconductor system assemblies and methods of operation
US9263278B2 (en) 2013-12-17 2016-02-16 Applied Materials, Inc. Dopant etch selectivity control
US9190293B2 (en) 2013-12-18 2015-11-17 Applied Materials, Inc. Even tungsten etch for high aspect ratio trenches
US9287134B2 (en) 2014-01-17 2016-03-15 Applied Materials, Inc. Titanium oxide etch
US9293568B2 (en) 2014-01-27 2016-03-22 Applied Materials, Inc. Method of fin patterning
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9499898B2 (en) 2014-03-03 2016-11-22 Applied Materials, Inc. Layered thin film heater and method of fabrication
US9299575B2 (en) 2014-03-17 2016-03-29 Applied Materials, Inc. Gas-phase tungsten etch
US9564296B2 (en) 2014-03-20 2017-02-07 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9837249B2 (en) 2014-03-20 2017-12-05 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9299538B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9136273B1 (en) 2014-03-21 2015-09-15 Applied Materials, Inc. Flash gate air gap
US9885117B2 (en) 2014-03-31 2018-02-06 Applied Materials, Inc. Conditioned semiconductor system parts
US9903020B2 (en) 2014-03-31 2018-02-27 Applied Materials, Inc. Generation of compact alumina passivation layers on aluminum plasma equipment components
US9269590B2 (en) 2014-04-07 2016-02-23 Applied Materials, Inc. Spacer formation
US10465294B2 (en) 2014-05-28 2019-11-05 Applied Materials, Inc. Oxide and metal removal
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9847289B2 (en) 2014-05-30 2017-12-19 Applied Materials, Inc. Protective via cap for improved interconnect performance
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9159606B1 (en) 2014-07-31 2015-10-13 Applied Materials, Inc. Metal air gap
US9773695B2 (en) 2014-07-31 2017-09-26 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9165786B1 (en) 2014-08-05 2015-10-20 Applied Materials, Inc. Integrated oxide and nitride recess for better channel contact in 3D architectures
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9355856B2 (en) 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch
US9355862B2 (en) 2014-09-24 2016-05-31 Applied Materials, Inc. Fluorine-based hardmask removal
US9478434B2 (en) 2014-09-24 2016-10-25 Applied Materials, Inc. Chlorine-based hardmask removal
US9368364B2 (en) 2014-09-24 2016-06-14 Applied Materials, Inc. Silicon etch process with tunable selectivity to SiO2 and other materials
US9837284B2 (en) 2014-09-25 2017-12-05 Applied Materials, Inc. Oxide etch selectivity enhancement
US9478432B2 (en) 2014-09-25 2016-10-25 Applied Materials, Inc. Silicon oxide selective removal
US9613822B2 (en) 2014-09-25 2017-04-04 Applied Materials, Inc. Oxide etch selectivity enhancement
US10707061B2 (en) 2014-10-14 2020-07-07 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US10796922B2 (en) 2014-10-14 2020-10-06 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US10490418B2 (en) 2014-10-14 2019-11-26 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US10593523B2 (en) 2014-10-14 2020-03-17 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US9543126B2 (en) 2014-11-26 2017-01-10 Applied Materials, Inc. Collimator for use in substrate processing chambers
CN109338293A (en) * 2014-11-26 2019-02-15 应用材料公司 The collimator used in substrate processing chamber
WO2016085805A1 (en) * 2014-11-26 2016-06-02 Applied Materials, Inc. Collimator for use in substrate processing chambers
US11239061B2 (en) 2014-11-26 2022-02-01 Applied Materials, Inc. Methods and systems to enhance process uniformity
CN107002220A (en) * 2014-11-26 2017-08-01 应用材料公司 The collimater used in substrate processing chamber
US11637002B2 (en) 2014-11-26 2023-04-25 Applied Materials, Inc. Methods and systems to enhance process uniformity
US9299583B1 (en) 2014-12-05 2016-03-29 Applied Materials, Inc. Aluminum oxide selective etch
US10224210B2 (en) 2014-12-09 2019-03-05 Applied Materials, Inc. Plasma processing system with direct outlet toroidal plasma source
US10573496B2 (en) 2014-12-09 2020-02-25 Applied Materials, Inc. Direct outlet toroidal plasma source
US9502258B2 (en) 2014-12-23 2016-11-22 Applied Materials, Inc. Anisotropic gap etch
US9343272B1 (en) 2015-01-08 2016-05-17 Applied Materials, Inc. Self-aligned process
US11257693B2 (en) 2015-01-09 2022-02-22 Applied Materials, Inc. Methods and systems to improve pedestal temperature control
US9373522B1 (en) 2015-01-22 2016-06-21 Applied Mateials, Inc. Titanium nitride removal
US9449846B2 (en) 2015-01-28 2016-09-20 Applied Materials, Inc. Vertical gate separation
US11594428B2 (en) 2015-02-03 2023-02-28 Applied Materials, Inc. Low temperature chuck for plasma processing systems
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US10468285B2 (en) 2015-02-03 2019-11-05 Applied Materials, Inc. High temperature chuck for plasma processing systems
US9881805B2 (en) 2015-03-02 2018-01-30 Applied Materials, Inc. Silicon selective removal
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US10147620B2 (en) 2015-08-06 2018-12-04 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US10468276B2 (en) 2015-08-06 2019-11-05 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US10607867B2 (en) 2015-08-06 2020-03-31 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US11158527B2 (en) 2015-08-06 2021-10-26 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10424463B2 (en) 2015-08-07 2019-09-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10424464B2 (en) 2015-08-07 2019-09-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US11476093B2 (en) 2015-08-27 2022-10-18 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US9960024B2 (en) 2015-10-27 2018-05-01 Applied Materials, Inc. Biasable flux optimizer / collimator for PVD sputter chamber
US11309169B2 (en) 2015-10-27 2022-04-19 Applied Materials, Inc. Biasable flux optimizer / collimator for PVD sputter chamber
US10347474B2 (en) 2015-10-27 2019-07-09 Applied Materials, Inc. Biasable flux optimizer / collimator for PVD sputter chamber
US10727033B2 (en) 2015-10-27 2020-07-28 Applied Materials, Inc. Biasable flux optimizer / collimator for PVD sputter chamber
US11735441B2 (en) 2016-05-19 2023-08-22 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10522371B2 (en) 2016-05-19 2019-12-31 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10504754B2 (en) 2016-05-19 2019-12-10 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US9865484B1 (en) 2016-06-29 2018-01-09 Applied Materials, Inc. Selective etch using material modification and RF pulsing
US10629473B2 (en) 2016-09-09 2020-04-21 Applied Materials, Inc. Footing removal for nitride spacer
US10062575B2 (en) 2016-09-09 2018-08-28 Applied Materials, Inc. Poly directional etch by oxidation
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US10062585B2 (en) 2016-10-04 2018-08-28 Applied Materials, Inc. Oxygen compatible plasma source
US9721789B1 (en) 2016-10-04 2017-08-01 Applied Materials, Inc. Saving ion-damaged spacers
US10546729B2 (en) 2016-10-04 2020-01-28 Applied Materials, Inc. Dual-channel showerhead with improved profile
US10541113B2 (en) 2016-10-04 2020-01-21 Applied Materials, Inc. Chamber with flow-through source
US11049698B2 (en) 2016-10-04 2021-06-29 Applied Materials, Inc. Dual-channel showerhead with improved profile
US10224180B2 (en) 2016-10-04 2019-03-05 Applied Materials, Inc. Chamber with flow-through source
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US10319603B2 (en) 2016-10-07 2019-06-11 Applied Materials, Inc. Selective SiN lateral recess
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal
US9768034B1 (en) 2016-11-11 2017-09-19 Applied Materials, Inc. Removal methods for high aspect ratio structures
US10770346B2 (en) 2016-11-11 2020-09-08 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10186428B2 (en) 2016-11-11 2019-01-22 Applied Materials, Inc. Removal methods for high aspect ratio structures
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10600639B2 (en) 2016-11-14 2020-03-24 Applied Materials, Inc. SiN spacer profile patterning
US10242908B2 (en) 2016-11-14 2019-03-26 Applied Materials, Inc. Airgap formation with damage-free copper
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
WO2018094022A1 (en) * 2016-11-18 2018-05-24 Applied Materials, Inc. Collimator for use in a physical vapor deposition chamber
US10697057B2 (en) 2016-11-18 2020-06-30 Applied Materials, Inc. Collimator for use in a physical vapor deposition chamber
US10566206B2 (en) 2016-12-27 2020-02-18 Applied Materials, Inc. Systems and methods for anisotropic material breakthrough
US10903052B2 (en) 2017-02-03 2021-01-26 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10431429B2 (en) 2017-02-03 2019-10-01 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10403507B2 (en) 2017-02-03 2019-09-03 Applied Materials, Inc. Shaped etch profile with oxidation
US10043684B1 (en) 2017-02-06 2018-08-07 Applied Materials, Inc. Self-limiting atomic thermal etching systems and methods
US10529737B2 (en) 2017-02-08 2020-01-07 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10325923B2 (en) 2017-02-08 2019-06-18 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10943834B2 (en) 2017-03-13 2021-03-09 Applied Materials, Inc. Replacement contact process
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US11361939B2 (en) 2017-05-17 2022-06-14 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US11276590B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US11276559B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US11915950B2 (en) 2017-05-17 2024-02-27 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US10049891B1 (en) 2017-05-31 2018-08-14 Applied Materials, Inc. Selective in situ cobalt residue removal
US10468267B2 (en) 2017-05-31 2019-11-05 Applied Materials, Inc. Water-free etching methods
US10497579B2 (en) 2017-05-31 2019-12-03 Applied Materials, Inc. Water-free etching methods
US10920320B2 (en) 2017-06-16 2021-02-16 Applied Materials, Inc. Plasma health determination in semiconductor substrate processing reactors
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US10727080B2 (en) 2017-07-07 2020-07-28 Applied Materials, Inc. Tantalum-containing material removal
US10541184B2 (en) 2017-07-11 2020-01-21 Applied Materials, Inc. Optical emission spectroscopic techniques for monitoring etching
US10354889B2 (en) 2017-07-17 2019-07-16 Applied Materials, Inc. Non-halogen etching of silicon-containing materials
US10170336B1 (en) 2017-08-04 2019-01-01 Applied Materials, Inc. Methods for anisotropic control of selective silicon removal
US10593553B2 (en) 2017-08-04 2020-03-17 Applied Materials, Inc. Germanium etching systems and methods
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US11101136B2 (en) 2017-08-07 2021-08-24 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
CN111133558A (en) * 2017-09-21 2020-05-08 应用材料公司 Method and apparatus for filling substrate features with cobalt
US10128086B1 (en) 2017-10-24 2018-11-13 Applied Materials, Inc. Silicon pretreatment for nitride removal
US10283324B1 (en) 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10256112B1 (en) 2017-12-08 2019-04-09 Applied Materials, Inc. Selective tungsten removal
US10903054B2 (en) 2017-12-19 2021-01-26 Applied Materials, Inc. Multi-zone gas distribution systems and methods
US11328909B2 (en) 2017-12-22 2022-05-10 Applied Materials, Inc. Chamber conditioning and removal processes
US10861676B2 (en) 2018-01-08 2020-12-08 Applied Materials, Inc. Metal recess for semiconductor structures
US10854426B2 (en) 2018-01-08 2020-12-01 Applied Materials, Inc. Metal recess for semiconductor structures
US10964512B2 (en) 2018-02-15 2021-03-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus and methods
US10699921B2 (en) 2018-02-15 2020-06-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
US10679870B2 (en) 2018-02-15 2020-06-09 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
US10615047B2 (en) 2018-02-28 2020-04-07 Applied Materials, Inc. Systems and methods to form airgaps
US10593560B2 (en) 2018-03-01 2020-03-17 Applied Materials, Inc. Magnetic induction plasma source for semiconductor processes and equipment
US11004689B2 (en) 2018-03-12 2021-05-11 Applied Materials, Inc. Thermal silicon etch
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10497573B2 (en) 2018-03-13 2019-12-03 Applied Materials, Inc. Selective atomic layer etching of semiconductor materials
USD859333S1 (en) * 2018-03-16 2019-09-10 Applied Materials, Inc. Collimator for a physical vapor deposition chamber
USD858468S1 (en) * 2018-03-16 2019-09-03 Applied Materials, Inc. Collimator for a physical vapor deposition chamber
US10573527B2 (en) 2018-04-06 2020-02-25 Applied Materials, Inc. Gas-phase selective etching systems and methods
US10490406B2 (en) 2018-04-10 2019-11-26 Appled Materials, Inc. Systems and methods for material breakthrough
US10699879B2 (en) 2018-04-17 2020-06-30 Applied Materials, Inc. Two piece electrode assembly with gap for plasma control
US10886137B2 (en) 2018-04-30 2021-01-05 Applied Materials, Inc. Selective nitride removal
US10755941B2 (en) 2018-07-06 2020-08-25 Applied Materials, Inc. Self-limiting selective etching systems and methods
US10872778B2 (en) 2018-07-06 2020-12-22 Applied Materials, Inc. Systems and methods utilizing solid-phase etchants
US10672642B2 (en) 2018-07-24 2020-06-02 Applied Materials, Inc. Systems and methods for pedestal configuration
US10892198B2 (en) 2018-09-14 2021-01-12 Applied Materials, Inc. Systems and methods for improved performance in semiconductor processing
US11049755B2 (en) 2018-09-14 2021-06-29 Applied Materials, Inc. Semiconductor substrate supports with embedded RF shield
US11062887B2 (en) 2018-09-17 2021-07-13 Applied Materials, Inc. High temperature RF heater pedestals
US11417534B2 (en) 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
US11682560B2 (en) 2018-10-11 2023-06-20 Applied Materials, Inc. Systems and methods for hafnium-containing film removal
US11121002B2 (en) 2018-10-24 2021-09-14 Applied Materials, Inc. Systems and methods for etching metals and metal derivatives
US11437242B2 (en) 2018-11-27 2022-09-06 Applied Materials, Inc. Selective removal of silicon-containing materials
US11721527B2 (en) 2019-01-07 2023-08-08 Applied Materials, Inc. Processing chamber mixing systems
US10920319B2 (en) 2019-01-11 2021-02-16 Applied Materials, Inc. Ceramic showerheads with conductive electrodes
USD937329S1 (en) 2020-03-23 2021-11-30 Applied Materials, Inc. Sputter target for a physical vapor deposition chamber
USD998575S1 (en) 2020-04-07 2023-09-12 Applied Materials, Inc. Collimator for use in a physical vapor deposition (PVD) chamber
CN111719132A (en) * 2020-06-29 2020-09-29 东部超导科技(苏州)有限公司 Multi-channel winding device integrating film coating and heat treatment of superconducting strip
USD1009816S1 (en) 2021-08-29 2024-01-02 Applied Materials, Inc. Collimator for a physical vapor deposition chamber
USD997111S1 (en) 2021-12-15 2023-08-29 Applied Materials, Inc. Collimator for use in a physical vapor deposition (PVD) chamber
US11959167B2 (en) 2022-06-07 2024-04-16 Applied Materials, Inc. Selective cobalt deposition on copper surfaces

Also Published As

Publication number Publication date
WO2003080887A2 (en) 2003-10-02
JP2006500472A (en) 2006-01-05
US20080268636A1 (en) 2008-10-30
US6740585B2 (en) 2004-05-25
WO2003080887A3 (en) 2004-08-26
US7611990B2 (en) 2009-11-03
US20030022487A1 (en) 2003-01-30

Similar Documents

Publication Publication Date Title
US20030029715A1 (en) An Apparatus For Annealing Substrates In Physical Vapor Deposition Systems
US7416979B2 (en) Deposition methods for barrier and tungsten materials
JP6867429B2 (en) Method of forming a metal-silicon compound layer and a metal-silicon compound layer formed from the method
US6562715B1 (en) Barrier layer structure for copper metallization and method of forming the structure
JP4970679B2 (en) Plasma reaction chamber component with improved temperature uniformity and processing method using the same
US7026238B2 (en) Reliability barrier integration for Cu application
KR101031617B1 (en) Aluminum sputtering while biasing wafer
TWI602263B (en) Cu wiring formation method and memory medium
JP2001220667A (en) Method and device for forming sputtered dope-finished seed layer
US20090242385A1 (en) Method of depositing metal-containing films by inductively coupled physical vapor deposition
KR20010029929A (en) Continuous, non-agglomerated adhesion of a seed layer to a barrier layer
US20020132473A1 (en) Integrated barrier layer structure for copper contact level metallization
US6528180B1 (en) Liner materials
US6579783B2 (en) Method for high temperature metal deposition for reducing lateral silicidation
TWI723465B (en) Method of forming nickel silicide materials
TW201703148A (en) METHOD FOR FORMING Cu WIRING AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
US20050189075A1 (en) Pre-clean chamber with wafer heating apparatus and method of use
WO2021133635A1 (en) Methods and apparatus for depositing aluminum by physical vapor deposition (pvd) with controlled cooling
US5873983A (en) Method for minimizing substrate to clamp sticking during thermal processing of thermally flowable layers
EP0570069A2 (en) Semiconductor device with a semiconductor body of which a surface is provided with a conductor pattern formed in a layer package comprising a TiW layer and an Al layer

Legal Events

Date Code Title Description
AS Assignment

Owner name: APPLIED MATERIALS, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YU, SANG-HO;CHA, YONGHWA CHRIS;YOON, KI HWAN;REEL/FRAME:012430/0026;SIGNING DATES FROM 20010904 TO 20010917

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION