US20030011080A1 - Method of fabricating sio2 spacers and annealing caps - Google Patents

Method of fabricating sio2 spacers and annealing caps Download PDF

Info

Publication number
US20030011080A1
US20030011080A1 US09/902,830 US90283001A US2003011080A1 US 20030011080 A1 US20030011080 A1 US 20030011080A1 US 90283001 A US90283001 A US 90283001A US 2003011080 A1 US2003011080 A1 US 2003011080A1
Authority
US
United States
Prior art keywords
divot
oxide film
cmos device
gate stack
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/902,830
Other versions
US6512266B1 (en
Inventor
Sadanand Deshpande
Bruce Doris
Rajarao Jammy
William Ma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Auriga Innovations Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US09/902,830 priority Critical patent/US6512266B1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JAMMY, RAJARAO, DORIS, BRUCE B., MA. WILLIAM H., DESHPANDE, SADANAND V.
Publication of US20030011080A1 publication Critical patent/US20030011080A1/en
Application granted granted Critical
Publication of US6512266B1 publication Critical patent/US6512266B1/en
Assigned to GLOBALFOUNDRIES U.S. 2 LLC reassignment GLOBALFOUNDRIES U.S. 2 LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES U.S. 2 LLC, GLOBALFOUNDRIES U.S. INC.
Assigned to AURIGA INNOVATIONS, INC. reassignment AURIGA INNOVATIONS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES INC.
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Definitions

  • the present invention relates to complementary metal oxide semiconductor (CMOS) devices, and more particularly to metal oxide semiconductor field effect transistors (MOSFETs) that include an oxide spacer to reduce parasitic capacitance and an annealing cap that prevents dopant loss in the gate material during an activation-annealing step.
  • CMOS complementary metal oxide semiconductor
  • MOSFETs metal oxide semiconductor field effect transistors
  • the present invention also provides methods of manufacturing the CMOS devices of the present invention.
  • SiN spacers are typically used to implant source/drain extensions (SDE) and halos for CMOS devices.
  • SDE source/drain extensions
  • the use of SiO 2 spacers is advantageous compared to SiN spacers because the lower dielectric constant of SiO 2 reduces the parasitic capacitance between the gate and S/D regions.
  • Annealing caps are used to protect the patterned gate stack, source/drain (S/D) and SDE regions from dopant loss during activation annealing.
  • the utilization of a deposited oxide material as the annealing cap is advantageous since low energy implantation can be performed through the bare Si substrate. After the implant, a low temperature SiO 2 film may be deposited over the entire wafer to prevent dopant loss during annealing.
  • the SiO 2 cap also serves as an etch stop for the thicker SiN spacer formation used to implant the S/D regions. As in the case of the thin SiO 2 spacer, the SiO 2 annealing cap reduces the parasitic capacitance between the gate and S/D regions. Simulations have shown that switching from a nitride annealing cap to an oxide annealing cap improves the ring oscillation delay by as much as 5%.
  • a major problem of integrating thin SiO 2 spacers and/or SiO 2 annealing caps into prior art processes is that any SiO 2 that is exposed during the pre-silicide cleaning or other process steps may be excessively etched.
  • any SiO 2 that is exposed during the pre-silicide cleaning or other process steps may be excessively etched.
  • excessive etching may cause the entire SiO 2 spacer to be removed thus leaving Si substrate area exposed. This leads to gate to substrate shorting by silicide bridging.
  • the SiO 2 annealing cap if the etching is excessive then the thick SiN spacers are undercut and may become completely detached rendering the device inoperable. This leads to silicide bridging since the spacers are present to prevent this from occurring.
  • One object of the present invention is to provide a method of forming a CMOS device in which a thin SiO 2 spacer and/or annealing cap is employed.
  • Another object of the present invention is to provide a method of forming a CMOS device in which the thin SiO 2 spacer and/or annealing cap is not aggressively attacked during the silicide pre-cleaning step or other process.
  • the divot fill process provides a means for protecting the exposed surfaces of the thin SiO 2 spacer and/or annealing cap such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning or other process steps.
  • a first method of the present invention which forms an SiO 2 annealing cap, comprises the steps of:
  • the oxide film remaining in the structure after the recessing step is in the shape of the letter “L”.
  • the oxide film remaining in the structure after recessing is present on portions of the vertical sidewalls of the patterned gate stack region as well as on a portion of the semiconductor substrate.
  • the first method of the present invention provides a CMOS device which comprises:
  • a semiconductor structure having at least one patterned gate stack region formed thereon, said patterned gate stack region having vertical sidewalls;
  • thick spacers formed on said oxide film, wherein said thick spacers extend beyond edges of said oxide film such that a divot region is present between at least said thick spacers and a top surface of said patterned gate stack region;
  • a second method of the present invention which forms a thin SiO 2 spacer and/or annealing cap comprises the steps of:
  • the second method of the present invention provides a CMOS device which comprises:
  • said patterned gate stack region having vertical sidewalls
  • thick spacers formed on said oxide film and said semiconductor substrate, wherein said thick spacers extend beyond edges of said oxide film such that a divot region is present between at least said thick spacers and a top surface of said patterned gate stack region;
  • FIGS 1 A- 1 F are pictorial representations (through cross-sectional views) illustrating the inventive CMOS device through various processing steps employed in the first method of the present invention.
  • FIGS. 2 A- 2 G are pictorial representations (through cross-sectional views) illustrating the inventive CMOS device through various processing steps employed in a second method of the present invention.
  • FIGS. 1 A- 1 F illustrate a first method of the present invention wherein an SiO 2 annealing cap is formed.
  • FIG 1 A illustrates an initial structure that is employed in the present invention.
  • the initial structure shown in FIG. 1A comprises semiconductor substrate 10 , patterned gate dielectric 12 formed on a portion of semiconductor substrate 10 , and patterned gate stack 14 formed atop patterned gate dielectric 12 .
  • patterned gate dielectric 12 formed on a portion of semiconductor substrate 10
  • patterned gate stack 14 formed atop patterned gate dielectric 12 .
  • the drawings depict the presence of only one patterned gate region (i.e., patterned gate dielectric and patterned gate stack) on the semiconductor substrate, the present invention works in cases wherein a plurality of patterned gate regions are present on the semiconductor substrate.
  • semiconductor substrate 10 is comprised of a semiconductor material including, but not limited to: Si, Ge, SiGe, GaAs, InAs, InP and all other III/V semiconductor compounds.
  • semiconductor substrate 10 may also include a layered substrate comprising the same or different semiconductor material, e.g., Si/Si or Si/SiGe, as well as a silicon-on-insulator (SOI) substrate.
  • the substrate may be of the n- or p-type depending on the desired device to be fabricated.
  • semiconductor substrate 10 may contain active device regions, wiring regions, isolation regions or other like regions that are typically present in CMOS-containing devices. For clarity, these regions are not shown in the drawings, but are nevertheless meant to be included within region 10 .
  • semiconductor substrate 10 is comprised of Si.
  • a layer of gate dielectric material such as an oxide, nitride, oxynitride or any combination and multilayer thereof is then formed on a surface of semiconductor substrate 10 utilizing a conventional process well known in the art.
  • the layer of gate dielectric material may be formed utilizing a conventional deposition process such as chemical vapor deposition (CVD), plasma-assisted CVD, evaporation or chemical solution deposition, or alternatively, the gate dielectric material may be formed by a thermal growing process such as oxidation, nitridation or oxynitridation. It is noted that the gate dielectric material will be subsequently patterned and etched into patterned gate dielectric 12 shown in FIG. 1A.
  • the thickness of the layer of gate dielectric material is not critical to the present invention, but typically, the gate dielectric material has a thickness of from about 1 to about 20 nm after deposition, with a thickness of from about 1.5 to about 10 nm being more highly preferred.
  • the gate dielectric material employed in the present invention may be a conventional dielectric material such as SiO 2 or Si 3 N 4 , or alternatively, high-k dielectrics such as oxides of Ta, Zr, Al or combinations thereof may be employed.
  • gate dielectric 12 is comprised of an oxide such as SiO 2 , ZrO 2 , Ta 2 O 5 or Al 2 O 3 .
  • gate stack 14 which includes at least a gate material is formed on the gate dielectric material.
  • gate material denotes a conductive material, a material that can be made conductive via a subsequent process such as ion implantation, or any combination thereof.
  • Suitable gate materials include, but are not limited to: polysilicon, amorphous silicon, elemental metals that are conductive such as W, Pt, Pd, Ru, Rh and Ir, alloys of these elemental metals, silicide or nitrides of these elemental metals and combinations thereof, e.g., a gate stack including a layer of polysilicon and a layer of conductive metal.
  • a highly preferred gate material employed in the present invention is a gate material that is comprised of polysilicon or amorphous silicon.
  • the gate material is formed on the surface of the gate dielectric material utilizing a conventional deposition process including, but not limited to: CVD, plasma-assisted CVD, evaporation, plating or chemical solution deposition.
  • a conventional silicide process may be used in forming the silicide layer.
  • One such silicide process that can be used in the present invention includes the steps of: first forming an elemental metal on the gate dielectric material, annealing the layers so as to form a metal silicide layer therefrom, and removing any unreacted elemental metal utilizing a conventional wet etch process that has a high selectivity for removing elemental metal as compared to silicide.
  • the polysilicon layer may be formed utilizing an in-situ doping deposition process or by a conventional deposition process followed by ion implantation. Note that the ion implantation step may be formed immediately after deposition of the polysilicon layer, or in a later step of the present invention, i.e., after patterning of the gate stack.
  • an optional diffusion barrier (not shown in the drawings) may be formed between each layer of the gate stack.
  • the optional diffusion barrier which is formed utilizing a conventional deposition process such as CVD or plasma-assisted CVD, is comprised of a material such as SiN, TaN, TaSiN, WN, TiN, and other like materials which can prevent diffusion of a conductive material therethrough.
  • the gate stack and the gate dielectric are then patterned utilizing conventional processing steps well known in the art which are capable of forming the patterned structure shown in FIG. 1A. Specifically, the structure shown in FIG 1 A is formed by lithography and etching.
  • the lithography step includes the following: applying a photoresist (not shown in the drawings) to the top surface of the gate stack, exposing the photoresist to a pattern of radiation and developing the pattern utilizing a conventional resist developer solution.
  • Etching is performed utilizing a conventional dry etching process such as reactive-ion etching, plasma etching, ion beam etching, laser ablation or a combination thereof.
  • the etching step may remove portions of the gate stack and the underlying gate dielectric material that are not protected by the patterned photoresist in a single step, or alternatively, multiple etching steps may be performed wherein the exposed portions of the gate stack is first removed stopping on a surface of the gate dielectric material, and thereafter the exposed portions of the gate dielectric are removed stopping on the surface of semiconductor substrate 10 .
  • the patterned photoresist is removed utilizing a conventional stripping process well known in the art providing the structure shown, for example, in FIG 1 A.
  • source/drain extension and halo implants may be performed. Note in FIG. 1A, region 18 denotes the source/drain extension regions and region 20 denotes the halo implant region. In other embodiment of the present invention, the source/drain extension and halo implant implants may be formed after the structure shown in FIG. 1B is formed.
  • the deep source/drain diffusion regions (labeled as 16 in FIG. 1C) are formed utilizing conventional processes (i.e., ion implantation and annealing) anytime after the structure shown in FIG 1 C is formed, i.e., after thick spacers 24 are formed in the structure.
  • the structure illustrated in FIG. 1A is subjected to a conventional reoxidation process prior to proceeding to the next step of the present invention.
  • FIG. 1B illustrates the structure after oxide film 22 is formed over the patterned gate stack structure of FIG. 1A.
  • the oxide film which is the annealing cap or thin inner spacer of the inventive structure, is formed utilizing any conformal deposition process that is capable of depositing a film that follows the contour of the structure shown in FIG. 1A. Specifically, CVD, plasma-assisted CVD, evaporation or chemical solution deposition may be employed in forming oxide film 22 on the structure.
  • fluorine or nitrogen-containing dopants may be incorporated (via ion implantation or another conventional process) into oxide film 22 so as to alter the dielectric constant of oxide film 22 .
  • a highly preferred oxide film employed in the present invention is a film that is comprised of SiO 2 , which may or may not be doped with fluorine or nitrogen.
  • oxide film 22 is not critical to the present invention, but typically oxide film 22 has a thickness of from about 2 ⁇ to about 40 nm, with a thickness of from about 5 to about 10 nm being more highly preferred.
  • an annealing step may be performed to activate the dopants, if implanted, and to possibly heal the implant damage.
  • the activation-annealing step is conducted utilizing conditions well known in the art. For example, activation annealing at a temperature of about 900° C. or greater for a time period of about 30 seconds or less may be employed at this point of the present invention. Additionally, the various implants steps mentioned hereinabove may also be performed at this point of the present invention.
  • thick spacers 24 which may include a single spacer material or a combination of spacer materials, are formed on the oxide film that abuts the patterned gate stack so as to provide the structure shown in FIG 1 C.
  • the thick spacers are formed of a dielectric material other than an oxide.
  • the thick spacers are comprised of a nitride, an oxynitride or combinations and multilayers thereof.
  • the thick spacers are formed by a conventional deposition process such as CVD or plasma-assisted CVD, followed by etching.
  • the spacer materials may be deposited sequentially followed by a single etching step, or alternatively, one spacer material is first deposited and etched, and thereafter a second spacer material is deposited and etched. This combination of spacer material deposition and etching may be repeated any number of times.
  • the etching step used in forming thick spacers 24 is a highly anisotropic etching process which is capable of removing the spacer material from atop the oxide layer that lays above the patterned gate stack.
  • thick spacers is used herein to denote spacers that have a thickness of from about 2 to about 100 nm, with a thickness of from about 20 to about 80 nm being more highly preferred.
  • the deep source/drain diffusion regions may be formed by utilizing conventional ion implantation and annealing processes well known in the art.
  • the structure shown in FIG. 1C is then subjected to an etching step wherein oxide film 22 is recessed below the uppermost horizontal edge of thick spacers 24 providing the structure shown, for example, in FIG 1 D.
  • an etching step is employed in the present invention so as to provide divot regions 26 which exist between the thick spacers 24 and patterned gate stack 14 .
  • the recessing process may be conducted laterally providing divot region 26 between the thick spacers and semiconductor substrate 10 . Note this recessing step converts oxide film 22 into an L-shaped structures 23 .
  • the etching process used in forming divots 26 in the structure includes a wet chemical etch process or a dry chemical etch process.
  • a chemical etchant such as HF that has a high selectivity for removing portions of the oxide film as compared with either the thick spacer material, the patterned gate stack and the semiconductor substrate is employed.
  • the dry etching process includes any dry etch process which is also capable of selectively removing portions of the oxide film as compared with either the thick spacer material, the patterned gate stack and the semiconductor substrate is employed.
  • divot fill material 28 is formed by a conformal deposition process such as CVD or plasma-assisted CVD so as to provide the structure shown, for example, in FIG. 1E.
  • the divot fill material includes a dielectric material other than an oxide, e.g., nitride, or oxynitride, that is not capable of being removed by a subsequent silicide precleaning or other processes which follow the processing steps of the present invention.
  • the thickness of the divot fill material is not critical to the present invention, but typically the thickness of the divot fill material is from about 4 to about 80 nm with a thickness of from about 10 to about 20 nm being more highly preferred.
  • the divot fill material is next etched back by utilizing a spacer type etching process or a combination of isotropic and anisotropic etches that removes the divot fill material from horizontal surfaces and possibly removes some of the divot fill material from the vertical surfaces so that the divot fill material is left completely or partially covering the recessed oxide film (both on the vertical and lateral portions).
  • the etch back step results in the formation of the structure shown in FIG 1 F.
  • the silicidation process is performed after the structure illustrated in FIG IF is formed. Specifically, the silicidation process includes the steps of forming a refractory metal such as Co, Ni or Ti on the surface of semiconductor substrate 10 , annealing the refractory metal under conditions that are capable of converting the refractory metal layer into a metal silicide layer, and, if needed, removing any non-reactant refractory metal from the structure.
  • a refractory metal such as Co, Ni or Ti
  • the present invention also contemplates other well known CMOS processing steps that are typically employed in the prior art.
  • the present invention also contemplates forming a metal contact to the metal silicide layer, and connecting the metal contact to an external contact.
  • FIGS. 2 A- 2 G illustrate a second method of the present invention wherein an “I” shaped oxide film is employed as an extension and halo spacer.
  • FIG. 2A shows an initial structure that is employed in the second method of the present application.
  • the initial structure includes semiconductor substrate 10 , patterned gate dielectric 12 formed on a portion of semiconductor substrate 10 , and patterned gate stack 14 formed atop patterned gate dielectric 12 .
  • FIG. 2A Note that the initial structure shown in FIG. 2A is identical to the one shown in FIG. 1A therefore no further details concerning the initial structure is needed herein. That is, the detailed description concerning the various elements of the structure shown in FIG. 2A as well as the processing steps used in forming the same are identical to that previously described in connection with FIG. 1A; therefore the above description regarding FIG. 1A is incorporated herein by reference.
  • various ion implantation steps may be performed to implant source/drain extension regions and halo implant regions into the semiconductor substrate. Note that these implant regions are shown in FIG. 2A.
  • the various implant steps may be postponed until after the structures shown in FIGS. 2B or 2 C have been formed.
  • the deep source/drain diffusion regions are again formed anytime after spacers 24 are present on the structure, i.e., after the formation of the structure shown in FIG. 2D.
  • FIG. 2B shows the structure that is obtained after oxide film 22 is formed over the patterned gate region as well as the exposed surface of semiconductor substrate 10 .
  • oxide film 22 may include dopant ions such as nitrogen or fluorine incorporated therein via ion implantation so as to provide an oxide layer that has a modified dielectric constant.
  • oxide film 22 is comprised of SiO 2 , which may or may not include dopant ions incorporated therein.
  • oxide film 22 is formed by a conventional deposition processes such as CVD and plasma-assisted CVD which are capable of forming a conformal oxide film on the structure.
  • the thickness of oxide film 22 is not critical to the present invention, but typically oxide film 22 has a thickness of from about 2 to about 30 nm, with a thickness of from about 5 to about 15 nm being more highly preferred.
  • a spacer etch step is performed so as to provide the structure shown in FIG. 2C.
  • the spacer etch forms “I” shaped oxide film 25 on the structure.
  • a spacer etching step is performed so as to convert oxide film 22 into “I” shaped spacers 25 which are present on at least a portion of the vertical sidewalls of the patterned gate stack. Note that in FIG. 2C, the I-shaped oxide spacers are not present on the upper portion of the patterned gate stack.
  • the I-shaped oxide spacers are formed by utilizing an etching process that is highly anisotropic so that the dielectric film is removed from all horizontal surfaces, but still remains on substantially all the vertical surfaces.
  • a conventional reactive ion etching process or any other like dry etching process may be utilized in etching oxide film 22 into I-shaped oxide spacers 25 .
  • thick spacers 24 which may be comprised of a single spacer material or a combination of spacer materials, are formed on the structure such that the structure shown in FIG. 2D is formed.
  • the thick spacers are comprised of a dielectric material, such as a nitride, or an oxynitride, which is different from I-shaped oxide spacers 25 .
  • the thin spacers are comprised of SiO 2
  • the thick spacers are formed of a nitride (e.g., Si 3 N 4 ) or oxynitride (e.g., SiON).
  • thick spacers 24 are formed utilizing the processing steps mentioned hereinabove, e.g., deposition and etching.
  • deep source/drain diffusion regions 16 may be formed in the substrate (for either NFET, PFET or both) utilizing conventional ion implantation and annealing processes well known to those skilled in the art.
  • FIG. 2E shows the structure wherein I-shaped oxide spacers 25 are recessed to a level below that of the thick spacers so as to form divot region 26 in the structure.
  • the oxide spacer recessing step may be carried out by a wet chemical etching process which includes the use of a chemical etch such as HF that has a high selectivity for recessing oxide spacer 25 as compared with thick spacer 24 . Note that the I-shaped spacers are recessed below the top most edge of the thick spacers.
  • the recess may also be achieved by utilizing a dry etching process that is capable of etching oxide spacer 25 but is selective to the gate stack material, the thick spacers and the semiconductor substrate.
  • FIG. 2F shows the structure that is obtained after divot fill material 28 is formed on all exposed surfaces of the structure.
  • the divot fill material includes the same material as mentioned previously in respect to the first method of the present invention and it is formed utilizing one of the above mentioned processing steps.
  • FIG. 2G shows the structure that is obtained after the divot fill material has been subjected to the above-mentioned etch back process.
  • the etch back process may include a spacer type etching process or a combination of isotropic etching and anisotropic etching that removes some of the material from the vertical surfaces so that the divot fill material is left completely or partially covering oxide spacers 25 .
  • the silicidation process is performed after the structure illustrated in FIG. 2G is formed. Specifically, the silicidation process includes the steps of forming a refractory metal such as Co, Ni or Ti on the surface of semiconductor substrate 10 , annealing the refractory metal under conditions that are capable of converting the refractory metal layer into a metal silicide layer, and, if needed, removing any non-reactant refractory metal from the structure.
  • a refractory metal such as Co, Ni or Ti
  • the present invention also contemplates other well known complementary oxide semiconductor (CMOS) processing steps that are typically employed in the prior art.
  • CMOS complementary oxide semiconductor
  • the present invention also contemplates forming a metal contact to the metal silicide layer, and connecting the metal contact to an external contact.

Abstract

Divot fill methods of incorporating thin SiO2 spacer and/or annealing caps into a complementary metal oxide semiconductor (CMOS) processing flow are provided. In accordance with the present invention, the divot fill processes provide a means for protecting the exposed surfaces of the thin SiO2 spacer and/or annealing cap such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning step. CMOS devices including thin SiO2 spacer and/or annealing caps whose surfaces are protected such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning or other process steps are also provided.

Description

    FIELD OF THE INVENTION
  • The present invention relates to complementary metal oxide semiconductor (CMOS) devices, and more particularly to metal oxide semiconductor field effect transistors (MOSFETs) that include an oxide spacer to reduce parasitic capacitance and an annealing cap that prevents dopant loss in the gate material during an activation-annealing step. The present invention also provides methods of manufacturing the CMOS devices of the present invention. [0001]
  • BACKGROUND OF THE INVENTION
  • In the semiconductor industry thin, SiN spacers are typically used to implant source/drain extensions (SDE) and halos for CMOS devices. The use of SiO[0002] 2 spacers is advantageous compared to SiN spacers because the lower dielectric constant of SiO2 reduces the parasitic capacitance between the gate and S/D regions.
  • Annealing caps are used to protect the patterned gate stack, source/drain (S/D) and SDE regions from dopant loss during activation annealing. The utilization of a deposited oxide material as the annealing cap is advantageous since low energy implantation can be performed through the bare Si substrate. After the implant, a low temperature SiO[0003] 2 film may be deposited over the entire wafer to prevent dopant loss during annealing. The SiO2 cap also serves as an etch stop for the thicker SiN spacer formation used to implant the S/D regions. As in the case of the thin SiO2 spacer, the SiO2 annealing cap reduces the parasitic capacitance between the gate and S/D regions. Simulations have shown that switching from a nitride annealing cap to an oxide annealing cap improves the ring oscillation delay by as much as 5%.
  • A major problem of integrating thin SiO[0004] 2 spacers and/or SiO2 annealing caps into prior art processes is that any SiO2 that is exposed during the pre-silicide cleaning or other process steps may be excessively etched. In the case of the thin SiO2 spacer, excessive etching may cause the entire SiO2 spacer to be removed thus leaving Si substrate area exposed. This leads to gate to substrate shorting by silicide bridging. In the case of the SiO2 annealing cap, if the etching is excessive then the thick SiN spacers are undercut and may become completely detached rendering the device inoperable. This leads to silicide bridging since the spacers are present to prevent this from occurring.
  • In view of the above, there is a continued need for developing a new and improved method wherein thin SiO[0005] 2 spacers and/or annealing caps can be integrated into a CMOS processing flow without exhibiting any of the problems mentioned hereinabove.
  • SUMMARY OF THE INVENTION
  • One object of the present invention is to provide a method of forming a CMOS device in which a thin SiO[0006] 2 spacer and/or annealing cap is employed.
  • Another object of the present invention is to provide a method of forming a CMOS device in which the thin SiO[0007] 2 spacer and/or annealing cap is not aggressively attacked during the silicide pre-cleaning step or other process.
  • These and other objects and advantages are achieved in the present invention by utilizing a divot fill process which overcomes the above-mentioned drawbacks in the prior art. In accordance with the present invention, the divot fill process provides a means for protecting the exposed surfaces of the thin SiO[0008] 2 spacer and/or annealing cap such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning or other process steps.
  • Specifically, a first method of the present invention, which forms an SiO[0009] 2 annealing cap, comprises the steps of:
  • (a) forming an oxide film on vertical and horizontal surfaces of a semiconductor structure, said semiconductor structure comprises at least a semiconductor substrate having at least one patterned gate stack region formed thereon; [0010]
  • (b) forming thick spacers on portions of said oxide film that are adjoining said at least one patterned gate stack region, said thick spacers being composed of a dielectric material other than an oxide; [0011]
  • (c) recessing said oxide film so as to form at least a divot region between said thick spacers and a top surface of said patterned gate stack region; and [0012]
  • (d) forming a divot fill material in said divot region, said divot fill material being composed of a dielectric material other than an oxide. [0013]
  • Note that in the first method of the present invention, the oxide film remaining in the structure after the recessing step is in the shape of the letter “L”. Hence, the oxide film remaining in the structure after recessing is present on portions of the vertical sidewalls of the patterned gate stack region as well as on a portion of the semiconductor substrate. [0014]
  • The first method of the present invention provides a CMOS device which comprises: [0015]
  • a semiconductor structure having at least one patterned gate stack region formed thereon, said patterned gate stack region having vertical sidewalls; [0016]
  • an oxide film formed on portions of said vertical sidewalls of said at least one patterned gate stack region as well as portions of said semiconductor substrate; [0017]
  • thick spacers formed on said oxide film, wherein said thick spacers extend beyond edges of said oxide film such that a divot region is present between at least said thick spacers and a top surface of said patterned gate stack region; and [0018]
  • a divot fill material present in said divot region. [0019]
  • A second method of the present invention, which forms a thin SiO[0020] 2 spacer and/or annealing cap comprises the steps of:
  • (a) forming an oxide film on vertical and horizontal surfaces of a semiconductor structure, said semiconductor structure comprises at least a semiconductor substrate having at least one patterned gate stack region formed thereon; [0021]
  • (b) etching said oxide film so as to remove said oxide fill from said horizontal surfaces of said structure; [0022]
  • (c) forming thick spacers on portions of said oxide film that are adjoining said at least one patterned gate stack region, said thick spacers being composed of a dielectric material other than an oxide; [0023]
  • (d) recessing said oxide film so as to form at least a divot region between said thick spacers and a top surface of said patterned gate stack region; and [0024]
  • (e) forming a divot fill material in said divot region, said divot fill material being composed of a dielectric material other than an oxide. [0025]
  • The second method of the present invention provides a CMOS device which comprises: [0026]
  • a semiconductor structure having at least one patterned gate stack region formed thereon, [0027]
  • said patterned gate stack region having vertical sidewalls; [0028]
  • an oxide film formed on portions of said vertical sidewalls of said at least one patterned gate stack region; [0029]
  • thick spacers formed on said oxide film and said semiconductor substrate, wherein said thick spacers extend beyond edges of said oxide film such that a divot region is present between at least said thick spacers and a top surface of said patterned gate stack region; and [0030]
  • a divot fill material present in said divot region.[0031]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS [0032] 1A-1F are pictorial representations (through cross-sectional views) illustrating the inventive CMOS device through various processing steps employed in the first method of the present invention.
  • FIGS. [0033] 2A-2G are pictorial representations (through cross-sectional views) illustrating the inventive CMOS device through various processing steps employed in a second method of the present invention.
  • DETAILED DESCRIPTION OF THE INVENTION
  • The present invention, which relates to CMOS devices containing oxide spacers and/or annealing caps and methods of fabricating the same, will now be described in more detail by referring to the drawings that accompany the present application. It is noted that in the accompanying drawings, like and/or corresponding elements are referred to by like reference numerals. [0034]
  • Reference is first made to the embodiment depicted in FIGS. [0035] 1A-1F which illustrate a first method of the present invention wherein an SiO2 annealing cap is formed. Specifically, FIG 1A illustrates an initial structure that is employed in the present invention. The initial structure shown in FIG. 1A comprises semiconductor substrate 10, patterned gate dielectric 12 formed on a portion of semiconductor substrate 10, and patterned gate stack 14 formed atop patterned gate dielectric 12. It is noted that although the drawings depict the presence of only one patterned gate region (i.e., patterned gate dielectric and patterned gate stack) on the semiconductor substrate, the present invention works in cases wherein a plurality of patterned gate regions are present on the semiconductor substrate.
  • The structure shown in FIG. 1A is comprised of conventional materials well known in the art and the illustrated structure is fabricated utilizing processing steps that are also well known in the art. For example, [0036] semiconductor substrate 10 is comprised of a semiconductor material including, but not limited to: Si, Ge, SiGe, GaAs, InAs, InP and all other III/V semiconductor compounds. Semiconductor substrate 10 may also include a layered substrate comprising the same or different semiconductor material, e.g., Si/Si or Si/SiGe, as well as a silicon-on-insulator (SOI) substrate. The substrate may be of the n- or p-type depending on the desired device to be fabricated.
  • Additionally, [0037] semiconductor substrate 10 may contain active device regions, wiring regions, isolation regions or other like regions that are typically present in CMOS-containing devices. For clarity, these regions are not shown in the drawings, but are nevertheless meant to be included within region 10. In one highly preferred embodiment of the present invention, semiconductor substrate 10 is comprised of Si.
  • Next, a layer of gate dielectric material such as an oxide, nitride, oxynitride or any combination and multilayer thereof is then formed on a surface of [0038] semiconductor substrate 10 utilizing a conventional process well known in the art. For example, the layer of gate dielectric material may be formed utilizing a conventional deposition process such as chemical vapor deposition (CVD), plasma-assisted CVD, evaporation or chemical solution deposition, or alternatively, the gate dielectric material may be formed by a thermal growing process such as oxidation, nitridation or oxynitridation. It is noted that the gate dielectric material will be subsequently patterned and etched into patterned gate dielectric 12 shown in FIG. 1A.
  • The thickness of the layer of gate dielectric material is not critical to the present invention, but typically, the gate dielectric material has a thickness of from about 1 to about 20 nm after deposition, with a thickness of from about 1.5 to about 10 nm being more highly preferred. It is noted that the gate dielectric material employed in the present invention may be a conventional dielectric material such as SiO[0039] 2 or Si3N4, or alternatively, high-k dielectrics such as oxides of Ta, Zr, Al or combinations thereof may be employed. In one highly preferred embodiment of the present invention, gate dielectric 12 is comprised of an oxide such as SiO2, ZrO2, Ta2O5 or Al2O3.
  • After forming the gate dielectric material on the surface of [0040] semiconductor substrate 10, gate stack 14 which includes at least a gate material is formed on the gate dielectric material. The term “gate material” as used herein denotes a conductive material, a material that can be made conductive via a subsequent process such as ion implantation, or any combination thereof. Illustrative examples of suitable gate materials include, but are not limited to: polysilicon, amorphous silicon, elemental metals that are conductive such as W, Pt, Pd, Ru, Rh and Ir, alloys of these elemental metals, silicide or nitrides of these elemental metals and combinations thereof, e.g., a gate stack including a layer of polysilicon and a layer of conductive metal. A highly preferred gate material employed in the present invention is a gate material that is comprised of polysilicon or amorphous silicon.
  • The gate material is formed on the surface of the gate dielectric material utilizing a conventional deposition process including, but not limited to: CVD, plasma-assisted CVD, evaporation, plating or chemical solution deposition. When metal suicides are employed, a conventional silicide process may be used in forming the silicide layer. One such silicide process that can be used in the present invention includes the steps of: first forming an elemental metal on the gate dielectric material, annealing the layers so as to form a metal silicide layer therefrom, and removing any unreacted elemental metal utilizing a conventional wet etch process that has a high selectivity for removing elemental metal as compared to silicide. [0041]
  • When polysilicon is employed as the gate material, the polysilicon layer may be formed utilizing an in-situ doping deposition process or by a conventional deposition process followed by ion implantation. Note that the ion implantation step may be formed immediately after deposition of the polysilicon layer, or in a later step of the present invention, i.e., after patterning of the gate stack. [0042]
  • It is noted that in embodiments wherein a gate stack including a layer of polysilicon and a layer of conductive elemental metal is employed, an optional diffusion barrier (not shown in the drawings) may be formed between each layer of the gate stack. The optional diffusion barrier, which is formed utilizing a conventional deposition process such as CVD or plasma-assisted CVD, is comprised of a material such as SiN, TaN, TaSiN, WN, TiN, and other like materials which can prevent diffusion of a conductive material therethrough. [0043]
  • After forming the gate stack on the gate dielectric material, the gate stack and the gate dielectric are then patterned utilizing conventional processing steps well known in the art which are capable of forming the patterned structure shown in FIG. 1A. Specifically, the structure shown in FIG [0044] 1A is formed by lithography and etching.
  • The lithography step includes the following: applying a photoresist (not shown in the drawings) to the top surface of the gate stack, exposing the photoresist to a pattern of radiation and developing the pattern utilizing a conventional resist developer solution. [0045]
  • Etching is performed utilizing a conventional dry etching process such as reactive-ion etching, plasma etching, ion beam etching, laser ablation or a combination thereof. The etching step may remove portions of the gate stack and the underlying gate dielectric material that are not protected by the patterned photoresist in a single step, or alternatively, multiple etching steps may be performed wherein the exposed portions of the gate stack is first removed stopping on a surface of the gate dielectric material, and thereafter the exposed portions of the gate dielectric are removed stopping on the surface of [0046] semiconductor substrate 10. Following the etching process, the patterned photoresist is removed utilizing a conventional stripping process well known in the art providing the structure shown, for example, in FIG 1A.
  • At this point of the present invention, source/drain extension and halo implants may be performed. Note in FIG. 1A, [0047] region 18 denotes the source/drain extension regions and region 20 denotes the halo implant region. In other embodiment of the present invention, the source/drain extension and halo implant implants may be formed after the structure shown in FIG. 1B is formed.
  • Note that the deep source/drain diffusion regions (labeled as [0048] 16 in FIG. 1C) are formed utilizing conventional processes (i.e., ion implantation and annealing) anytime after the structure shown in FIG 1C is formed, i.e., after thick spacers 24 are formed in the structure.
  • In another embodiment of the present invention, the structure illustrated in FIG. 1A is subjected to a conventional reoxidation process prior to proceeding to the next step of the present invention. [0049]
  • FIG. 1B illustrates the structure after [0050] oxide film 22 is formed over the patterned gate stack structure of FIG. 1A. The oxide film, which is the annealing cap or thin inner spacer of the inventive structure, is formed utilizing any conformal deposition process that is capable of depositing a film that follows the contour of the structure shown in FIG. 1A. Specifically, CVD, plasma-assisted CVD, evaporation or chemical solution deposition may be employed in forming oxide film 22 on the structure.
  • In one embodiment of the present invention, fluorine or nitrogen-containing dopants may be incorporated (via ion implantation or another conventional process) into [0051] oxide film 22 so as to alter the dielectric constant of oxide film 22. A highly preferred oxide film employed in the present invention is a film that is comprised of SiO2, which may or may not be doped with fluorine or nitrogen.
  • The thickness of [0052] oxide film 22 is not critical to the present invention, but typically oxide film 22 has a thickness of from about 2 Å to about 40 nm, with a thickness of from about 5 to about 10 nm being more highly preferred.
  • At this point of the present invention, an annealing step may be performed to activate the dopants, if implanted, and to possibly heal the implant damage. The activation-annealing step is conducted utilizing conditions well known in the art. For example, activation annealing at a temperature of about 900° C. or greater for a time period of about 30 seconds or less may be employed at this point of the present invention. Additionally, the various implants steps mentioned hereinabove may also be performed at this point of the present invention. [0053]
  • Next, [0054] thick spacers 24, which may include a single spacer material or a combination of spacer materials, are formed on the oxide film that abuts the patterned gate stack so as to provide the structure shown in FIG 1C. The thick spacers are formed of a dielectric material other than an oxide. Specifically, the thick spacers are comprised of a nitride, an oxynitride or combinations and multilayers thereof.
  • The thick spacers are formed by a conventional deposition process such as CVD or plasma-assisted CVD, followed by etching. When the thick spacers are comprised of a combination of spacer materials, the spacer materials may be deposited sequentially followed by a single etching step, or alternatively, one spacer material is first deposited and etched, and thereafter a second spacer material is deposited and etched. This combination of spacer material deposition and etching may be repeated any number of times. The etching step used in forming [0055] thick spacers 24 is a highly anisotropic etching process which is capable of removing the spacer material from atop the oxide layer that lays above the patterned gate stack.
  • The term “thick spacers” is used herein to denote spacers that have a thickness of from about 2 to about 100 nm, with a thickness of from about 20 to about 80 nm being more highly preferred. [0056]
  • As stated above, and at this point of the present invention, the deep source/drain diffusion regions, may be formed by utilizing conventional ion implantation and annealing processes well known in the art. [0057]
  • After forming [0058] thick spacers 24, the structure shown in FIG. 1C is then subjected to an etching step wherein oxide film 22 is recessed below the uppermost horizontal edge of thick spacers 24 providing the structure shown, for example, in FIG 1D. Specifically, an etching step is employed in the present invention so as to provide divot regions 26 which exist between the thick spacers 24 and patterned gate stack 14. Optionally, the recessing process may be conducted laterally providing divot region 26 between the thick spacers and semiconductor substrate 10. Note this recessing step converts oxide film 22 into an L-shaped structures 23.
  • The etching process used in forming [0059] divots 26 in the structure includes a wet chemical etch process or a dry chemical etch process. When wet etching is employed in the present invention in forming divots 26, a chemical etchant such as HF that has a high selectivity for removing portions of the oxide film as compared with either the thick spacer material, the patterned gate stack and the semiconductor substrate is employed.
  • When dry etching is employed in forming the divots, the dry etching process includes any dry etch process which is also capable of selectively removing portions of the oxide film as compared with either the thick spacer material, the patterned gate stack and the semiconductor substrate is employed. [0060]
  • After recessing the oxide film, divot fill [0061] material 28 is formed by a conformal deposition process such as CVD or plasma-assisted CVD so as to provide the structure shown, for example, in FIG. 1E. The divot fill material includes a dielectric material other than an oxide, e.g., nitride, or oxynitride, that is not capable of being removed by a subsequent silicide precleaning or other processes which follow the processing steps of the present invention.
  • The thickness of the divot fill material is not critical to the present invention, but typically the thickness of the divot fill material is from about 4 to about 80 nm with a thickness of from about 10 to about 20 nm being more highly preferred. [0062]
  • The divot fill material is next etched back by utilizing a spacer type etching process or a combination of isotropic and anisotropic etches that removes the divot fill material from horizontal surfaces and possibly removes some of the divot fill material from the vertical surfaces so that the divot fill material is left completely or partially covering the recessed oxide film (both on the vertical and lateral portions). The etch back step results in the formation of the structure shown in FIG [0063] 1F.
  • The silicidation process is performed after the structure illustrated in FIG IF is formed. Specifically, the silicidation process includes the steps of forming a refractory metal such as Co, Ni or Ti on the surface of [0064] semiconductor substrate 10, annealing the refractory metal under conditions that are capable of converting the refractory metal layer into a metal silicide layer, and, if needed, removing any non-reactant refractory metal from the structure.
  • In addition to silicidation, the present invention also contemplates other well known CMOS processing steps that are typically employed in the prior art. For example, the present invention also contemplates forming a metal contact to the metal silicide layer, and connecting the metal contact to an external contact. [0065]
  • Reference will now be made to FIGS. [0066] 2A-2G which illustrate a second method of the present invention wherein an “I” shaped oxide film is employed as an extension and halo spacer. Specifically, FIG. 2A shows an initial structure that is employed in the second method of the present application. The initial structure includes semiconductor substrate 10, patterned gate dielectric 12 formed on a portion of semiconductor substrate 10, and patterned gate stack 14 formed atop patterned gate dielectric 12.
  • Note that the initial structure shown in FIG. 2A is identical to the one shown in FIG. 1A therefore no further details concerning the initial structure is needed herein. That is, the detailed description concerning the various elements of the structure shown in FIG. 2A as well as the processing steps used in forming the same are identical to that previously described in connection with FIG. 1A; therefore the above description regarding FIG. 1A is incorporated herein by reference. [0067]
  • After forming the initial structure shown in FIG. 2A, various ion implantation steps may be performed to implant source/drain extension regions and halo implant regions into the semiconductor substrate. Note that these implant regions are shown in FIG. 2A. Alternatively, the various implant steps may be postponed until after the structures shown in FIGS. 2B or [0068] 2C have been formed. The deep source/drain diffusion regions are again formed anytime after spacers 24 are present on the structure, i.e., after the formation of the structure shown in FIG. 2D.
  • FIG. 2B shows the structure that is obtained after [0069] oxide film 22 is formed over the patterned gate region as well as the exposed surface of semiconductor substrate 10. In some embodiments of the present invention, oxide film 22 may include dopant ions such as nitrogen or fluorine incorporated therein via ion implantation so as to provide an oxide layer that has a modified dielectric constant. In a highly preferred embodiment of the present invention, oxide film 22 is comprised of SiO2, which may or may not include dopant ions incorporated therein.
  • As mentioned previously herein, [0070] oxide film 22 is formed by a conventional deposition processes such as CVD and plasma-assisted CVD which are capable of forming a conformal oxide film on the structure. The thickness of oxide film 22 is not critical to the present invention, but typically oxide film 22 has a thickness of from about 2 to about 30 nm, with a thickness of from about 5 to about 15 nm being more highly preferred.
  • Following formation of the oxide film on the structure, a spacer etch step is performed so as to provide the structure shown in FIG. 2C. Note that the spacer etch forms “I” shaped [0071] oxide film 25 on the structure. Specifically, a spacer etching step is performed so as to convert oxide film 22 into “I” shaped spacers 25 which are present on at least a portion of the vertical sidewalls of the patterned gate stack. Note that in FIG. 2C, the I-shaped oxide spacers are not present on the upper portion of the patterned gate stack.
  • In accordance with the present invention, the I-shaped oxide spacers are formed by utilizing an etching process that is highly anisotropic so that the dielectric film is removed from all horizontal surfaces, but still remains on substantially all the vertical surfaces. A conventional reactive ion etching process or any other like dry etching process may be utilized in [0072] etching oxide film 22 into I-shaped oxide spacers 25.
  • Next, [0073] thick spacers 24, which may be comprised of a single spacer material or a combination of spacer materials, are formed on the structure such that the structure shown in FIG. 2D is formed. The thick spacers are comprised of a dielectric material, such as a nitride, or an oxynitride, which is different from I-shaped oxide spacers 25. For example, when the thin spacers are comprised of SiO2, then the thick spacers are formed of a nitride (e.g., Si3N4) or oxynitride (e.g., SiON). Note that thick spacers 24 are formed utilizing the processing steps mentioned hereinabove, e.g., deposition and etching.
  • At this point of the present invention, deep source/[0074] drain diffusion regions 16 may be formed in the substrate (for either NFET, PFET or both) utilizing conventional ion implantation and annealing processes well known to those skilled in the art.
  • FIG. 2E shows the structure wherein I-shaped [0075] oxide spacers 25 are recessed to a level below that of the thick spacers so as to form divot region 26 in the structure. The oxide spacer recessing step may be carried out by a wet chemical etching process which includes the use of a chemical etch such as HF that has a high selectivity for recessing oxide spacer 25 as compared with thick spacer 24. Note that the I-shaped spacers are recessed below the top most edge of the thick spacers.
  • The recess may also be achieved by utilizing a dry etching process that is capable of etching [0076] oxide spacer 25 but is selective to the gate stack material, the thick spacers and the semiconductor substrate.
  • FIG. 2F shows the structure that is obtained after divot fill [0077] material 28 is formed on all exposed surfaces of the structure. The divot fill material includes the same material as mentioned previously in respect to the first method of the present invention and it is formed utilizing one of the above mentioned processing steps.
  • FIG. 2G shows the structure that is obtained after the divot fill material has been subjected to the above-mentioned etch back process. Specifically, the etch back process may include a spacer type etching process or a combination of isotropic etching and anisotropic etching that removes some of the material from the vertical surfaces so that the divot fill material is left completely or partially covering [0078] oxide spacers 25.
  • The silicidation process is performed after the structure illustrated in FIG. 2G is formed. Specifically, the silicidation process includes the steps of forming a refractory metal such as Co, Ni or Ti on the surface of [0079] semiconductor substrate 10, annealing the refractory metal under conditions that are capable of converting the refractory metal layer into a metal silicide layer, and, if needed, removing any non-reactant refractory metal from the structure.
  • In addition to silicidation, the present invention also contemplates other well known complementary oxide semiconductor (CMOS) processing steps that are typically employed in the prior art. For example, the present invention also contemplates forming a metal contact to the metal silicide layer, and connecting the metal contact to an external contact. [0080]
  • While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims. [0081]

Claims (57)

Having thus described our invention in detail, what we claim as new and desire to secure by the letters PATENT is:
1. A method of forming a complementary metal oxide semiconductor device comprising the steps of:
(a) forming an oxide film on vertical and horizontal surfaces of a semiconductor structure, said semiconductor structure comprises at least a semiconductor substrate having at least one patterned gate stack region formed thereon;
(b) forming thick spacers on portions of said oxide film that are adjoining said at least one patterned gate stack region, said thick spacers being composed of a dielectric material other than an oxide;
(c) recessing said oxide film so as to form at least a divot region between said thick spacers and a top surface of said patterned gate stack region; and
(d) forming a divot fill material in said divot region, said divot fill material being composed of a dielectric material other than an oxide.
2. The method of claim 1 wherein said oxide film is formed by a conformal deposition process that follows the contour of said semiconductor structure.
3. The method of claim 2 wherein said conformal deposition process comprises chemical vapor deposition, plasma-assisted chemical vapor deposition, evaporation or chemical solution deposition.
4. The method of claim 1 wherein said patterned gate stack region is formed by lithography and etching.
5. The method of claim 1 wherein said thick spacers are formed by deposition and etching.
6. The method of claim 5 wherein said etching comprises an anisotropic etching process.
7. The method of claim 1 wherein step (c) converts said oxide film into L-shaped spacers.
8. The method of claim 1 wherein step (c) comprises a chemical wet etch process.
9. The method of claim 8 wherein said chemical wet etch process comprises the use of as a chemical etchant.
10. The method of claim 1 wherein step (c) comprises a dry etching process selected from the group consisting of reactive-ion etching, plasma etching, ion beam etching and laser ablation.
11. The method of claim 1 wherein step (d) comprises deposition of a conformal layer of said divot fill material and etching back said conformal layer.
12. The method of claim 11 wherein said deposition comprises chemical vapor deposition or plasma-assisted chemical vapor deposition.
13. The method of claim 11 wherein said etching back comprises a spacer etching process or a combination of isotropic and anisotropic etching.
14. The method of claim 1 wherein said divot fill material is formed completely with said divot region.
15. The method of claim 1 wherein said divot film material is form partially within said divot region.
16. A complementary metal oxide semiconductor (CMOS) device comprising:
a semiconductor structure having at least one patterned gate stack region formed thereon,
said patterned gate stack region having vertical sidewalls;
an oxide film formed on portions of said vertical sidewalls of said at least one patterned gate stack region as well as portions of said semiconductor substrate;
thick spacers formed on said oxide film, wherein said thick spacers extend beyond edges of said oxide film such that a divot region is present between at least said thick spacers and a top surface of said patterned gate stack region; and
a divot fill material present in said divot region.
17. The CMOS device of claim 16 wherein said semiconductor substrate comprises Si, Ge, SiGe, GaAs, InAs, InP, Si/Si, Si/SiGe or silicon-on-insulators.
18. The CMOS device of claim 16 wherein said semiconductor substrate comprises Si.
19. The CMOS device of claim 16 wherein said patterned gate stack region comprises a patterned gate dielectric material and a patterned gate stack.
20. The CMOS device of claim 19 wherein said patterned gate dielectric is comprised of an oxide, a nitride, an oxynitride or any combination and multilayer thereof.
21. The CMOS device of claim 19 wherein said patterned gate dielectric is comprised of an oxide selected from the group consisting of SiO2, ZrO2, Ta2O5 and Al2O3.
22. The CMOS device of claim 19 wherein said gate stack includes at least a gate material.
23. The CMOS device of claim 22 wherein said gate material is selected from the group consisting of polysilicon, amorphous silicon, elemental metals that are conductive, alloys of elemental metals that are conductive, silicides or nitrides of elemental metals that are conductive and any combination thereof.
24. The CMOS device of claim 22 wherein said gate material is comprised of silicon or amorphous silicon.
25. The CMOS device of claim 16 wherein said oxide film is comprised of SiO2.
26. The CMOS device of claim 16 wherein said oxide film is an L-shaped spacer.
27. The CMOS device of claim 16 wherein said thick spacers are comprised of a nitride, an oxynitride or any combinations or multilayers thereof.
28. The CMOS device of claim 16 wherein said divot fill material is comprised of a nitride or an oxynitride.
29. A method of forming a CMOS device comprising the steps of:
(a) forming an oxide film on vertical and horizontal surfaces of a semiconductor structure, said semiconductor structure comprises at least a semiconductor substrate having at least one patterned gate stack region formed thereon;
(b) etching said oxide film so as to remove said oxide fill from said horizontal surfaces of said structure;
(c) forming thick spacers on portions of said oxide film that are adjoining said at least one patterned gate stack region, said thick spacers being composed of a dielectric material other than an oxide;
(d) recessing said oxide film so as to form at least a divot region between said thick spacers and a top surface of said patterned gate stack region; and
(e) filling said divot region with a divot fill material, said divot fill material being composed of a dielectric material other than an oxide.
30. The method of claim 29 wherein said oxide film is formed by a conformal deposition process that follows the contour of said semiconductor structure.
31. The method of claim 30 wherein said conformal deposition process comprises chemical vapor deposition, plasma-assisted chemical vapor deposition, evaporation or chemical solution deposition.
32. The method of claim 29 wherein said patterned gate stack region is formed by lithography and etching.
33. The method of claim 29 wherein step (b) includes a spacer etching process.
34. The method of claim 29 wherein step (b) forms I-shaped oxide spacers on said vertical surfaces of said structure.
35. The method of claim 29 wherein said thick spacers are formed by deposition and etching.
36. The method of claim 35 wherein said etching comprises an anisotropic etching process.
37. The method of claim 29 wherein step (d) comprises a chemical wet etch process.
38. The method of claim 37 wherein said chemical wet etch process comprises the use of HF as a chemical etchant.
39. The method of claim 29 wherein step (d) comprises a dry etching process selected from the group consisting of reactive-ion etching, plasma etching, ion beam etching and laser ablation.
40. The method of claim 29 wherein step (e) comprises deposition of a conformal layer of said divot fill material and etching back said conformal layer.
41. The method of claim 40 wherein said deposition comprises chemical vapor deposition or plasma-assisted chemical vapor deposition.
42. The method of claim 40 wherein said etching back comprises a spacer etching process or a combination of isotropic and anisotropic etching.
43. The method of claim 29 wherein said divot fill material is formed completely with said divot region.
44. The method of claim 29 wherein said divot film material is form partially within said divot region.
45. A CMOS device comprising:
a semiconductor structure having at least one patterned gate stack region formed thereon,
said patterned gate stack region having vertical sidewalls;
an oxide film formed on portions of said vertical sidewalls of said at least one patterned gate stack region;
thick spacers formed on said oxide film and said semiconductor substrate, wherein said
thick spacers extend beyond edges of said oxide film such that a divot region is present between at least said thick spacers and a top surface of said patterned gate stack region; and
a divot fill material present in said divot region.
46. The CMOS device of claim 45 wherein said semiconductor substrate comprises Si, Ge, SiGe, GaAs, InAs, InP, Si/Si, Si/SiGe or silicon-on-insulators.
47. The CMOS device of claim 45 wherein said semiconductor substrate comprises Si.
48. The CMOS device of claim 45 wherein said patterned gate stack region comprises a patterned gate dielectric material and a patterned gate stack.
49. The CMOS device of claim 48 wherein said patterned gate dielectric is comprised of an oxide, a nitride, an oxynitride or any combination and multilayer thereof.
50. The CMOS device of claim 48 wherein said patterned gate dielectric is comprised of an oxide selected from the group consisting of SiO2, ZrO2, Ta2O5 and Al2O3.
51. The CMOS device of claim 48 wherein said gate stack includes at least a gate material.
52. The CMOS device of claim 51 wherein said gate material is selected from the group consisting of polysilicon, amorphous silicon, elemental metals that are conductive, alloys of elemental metals that are conductive, suicides or nitrides of elemental metals that are conductive and any combination thereof.
53. The CMOS device of claim 51 wherein said gate material is comprised of silicon or amorphous silicon.
54. The CMOS device of claim 45 wherein said oxide film is comprised of SiO2.
55. The CMOS device of claim 45 wherein said oxide film is an I-shaped spacer.
56. The CMOS device of claim 45 wherein said thick spacers are comprised of a nitride, an oxynitride or any combinations or multilayers thereof.
57. The CMOS device of claim 45 wherein said divot fill material is comprised of a nitride or an oxynitride.
US09/902,830 2001-07-11 2001-07-11 Method of fabricating SiO2 spacers and annealing caps Expired - Lifetime US6512266B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/902,830 US6512266B1 (en) 2001-07-11 2001-07-11 Method of fabricating SiO2 spacers and annealing caps

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/902,830 US6512266B1 (en) 2001-07-11 2001-07-11 Method of fabricating SiO2 spacers and annealing caps

Publications (2)

Publication Number Publication Date
US20030011080A1 true US20030011080A1 (en) 2003-01-16
US6512266B1 US6512266B1 (en) 2003-01-28

Family

ID=25416463

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/902,830 Expired - Lifetime US6512266B1 (en) 2001-07-11 2001-07-11 Method of fabricating SiO2 spacers and annealing caps

Country Status (1)

Country Link
US (1) US6512266B1 (en)

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030098489A1 (en) * 2001-11-29 2003-05-29 International Business Machines Corporation High temperature processing compatible metal gate electrode for pFETS and methods for fabrication
US20040198003A1 (en) * 2003-03-26 2004-10-07 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple-gate transistors with improved gate control
US20040217433A1 (en) * 2003-04-29 2004-11-04 Yee-Chia Yeo Doping of semiconductor fin devices
US20040266077A1 (en) * 2003-06-27 2004-12-30 Yee-Chia Yeo Structure and method for forming the gate electrode in a multiple-gate transistor
US20050026380A1 (en) * 2003-07-31 2005-02-03 Thorsten Kammler Technique for forming recessed sidewall spacers for a polysilicon line
US20050064635A1 (en) * 2003-09-22 2005-03-24 International Business Machines Corporation METHOD FOR AVOIDING OXIDE UNDERCUT DURING PRE-SILICIDE CLEAN FOR THIN SPACER FETs
WO2005047561A1 (en) * 2003-11-13 2005-05-26 International Business Machines Corporation Cvd tantalum compounds for fet gate electrodes
US20050121706A1 (en) * 2003-02-20 2005-06-09 Hao-Yu Chen Semiconductor nano-rod devices
US20050142828A1 (en) * 2003-12-30 2005-06-30 Thorsten Kammler Technique for forming a spacer for a line element by using an etch stop layer deposited by a highly directional deposition technique
US20050275010A1 (en) * 2004-06-10 2005-12-15 Hung-Wei Chen Semiconductor nano-wire devices and methods of fabrication
US20060094194A1 (en) * 2004-11-04 2006-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced disposable spacer process by low-temperature high-stress nitride film for sub-90NM CMOS technology
US7078285B1 (en) 2005-01-21 2006-07-18 Sony Corporation SiGe nickel barrier structure employed in a CMOS device to prevent excess diffusion of nickel used in the silicide material
US20070267678A1 (en) * 2006-05-16 2007-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with corner spacers
US20080230839A1 (en) * 2007-03-23 2008-09-25 Joern Regul Method of producing a semiconductor structure
US20080272438A1 (en) * 2007-05-02 2008-11-06 Doris Bruce B CMOS Circuits with High-K Gate Dielectric
CN100459075C (en) * 2005-03-22 2009-02-04 台湾积体电路制造股份有限公司 Semiconductor device and method for forming grid spacer
US20090286384A1 (en) * 2008-05-14 2009-11-19 Ming-Yuan Wu Dishing-free gap-filling with multiple CMPs
US20100022061A1 (en) * 2008-07-24 2010-01-28 Ming-Yuan Wu Spacer Shape Engineering for Void-Free Gap-Filling Process
FR3046290A1 (en) * 2015-12-23 2017-06-30 Commissariat Energie Atomique METHOD FOR PRODUCING SPACERS WITH LOW PERMITTIVITY
US20180190787A1 (en) * 2014-06-19 2018-07-05 Globalfoundries Inc. Method and structure for protecting gates during epitaxial growth
US10561812B2 (en) 2005-06-06 2020-02-18 ResMed Pty Ltd Mask system
DE102022104004A1 (en) 2021-12-08 2023-06-15 Taiwan Semiconductor Manufacturing Co., Ltd. SELF-FILLING SPACER STRUCTURE

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6610571B1 (en) * 2002-02-07 2003-08-26 Taiwan Semiconductor Manufacturing Company Approach to prevent spacer undercut by low temperature nitridation
JP2003258248A (en) * 2002-03-05 2003-09-12 Mitsubishi Electric Corp Method of manufacturing semiconductor device
KR100429007B1 (en) * 2002-07-25 2004-04-29 동부전자 주식회사 Method of manufacturing MOS Transistor
US6936512B2 (en) 2002-09-27 2005-08-30 International Business Machines Corporation Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric
JP2004127957A (en) * 2002-09-30 2004-04-22 Fujitsu Ltd Process for fabricating semiconductor device, and semiconductor device
US6734072B1 (en) * 2003-03-05 2004-05-11 Chartered Semiconductor Manufacturing Ltd. Method of fabricating a MOSFET device using a spike rapid thermal oxidation procedure
JP2004363443A (en) * 2003-06-06 2004-12-24 Toshiba Corp Non-volatile semiconductor storage device and its manufacturing method
US6812105B1 (en) * 2003-07-16 2004-11-02 International Business Machines Corporation Ultra-thin channel device with raised source and drain and solid source extension doping
US6975006B2 (en) * 2003-07-25 2005-12-13 Taiwan Semiconductor Manufacturing Company Semiconductor device with modified channel compressive stress
KR100562301B1 (en) * 2003-12-27 2006-03-22 동부아남반도체 주식회사 Gate structure of transistor and manufacturing method therefor
US20050164460A1 (en) * 2004-01-23 2005-07-28 Agency For Science, Technology And Research Salicide process for metal gate CMOS devices
JP2005277172A (en) * 2004-03-25 2005-10-06 Toshiba Corp Semiconductor device, and its manufacturing method
KR100618908B1 (en) * 2005-08-12 2006-09-05 삼성전자주식회사 Semiconductor device for improving resistance of gate and method of manufacturing the same
US7759206B2 (en) * 2005-11-29 2010-07-20 International Business Machines Corporation Methods of forming semiconductor devices using embedded L-shape spacers
US7411245B2 (en) * 2005-11-30 2008-08-12 Taiwan Semiconductor Manufacturing Co., Ltd. Spacer barrier structure to prevent spacer voids and method for forming the same
JP5076119B2 (en) * 2006-02-22 2012-11-21 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
US7446007B2 (en) * 2006-11-17 2008-11-04 International Business Machines Corporation Multi-layer spacer with inhibited recess/undercut and method for fabrication thereof
US7393738B1 (en) 2007-01-16 2008-07-01 International Business Machines Corporation Subground rule STI fill for hot structure
US8119470B2 (en) * 2007-03-21 2012-02-21 Texas Instruments Incorporated Mitigation of gate to contact capacitance in CMOS flow
US8809962B2 (en) * 2011-08-26 2014-08-19 Globalfoundries Inc. Transistor with reduced parasitic capacitance
CN102976264B (en) * 2012-12-13 2015-04-15 中国科学院物理研究所 Method for preparing self-supporting multilayer micro nano structure
US9614053B2 (en) * 2013-12-05 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Spacers with rectangular profile and methods of forming the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3714995B2 (en) 1995-07-05 2005-11-09 シャープ株式会社 Semiconductor device
US6010954A (en) 1997-07-11 2000-01-04 Chartered Semiconductor Manufacturing, Ltd. Cmos gate architecture for integration of salicide process in sub 0.1 . .muM devices
US6160299A (en) 1997-08-29 2000-12-12 Texas Instruments Incorporated Shallow-implant elevated source/drain doping from a sidewall dopant source
KR100236101B1 (en) * 1997-09-29 1999-12-15 김영환 Semiconductor device and method of manufacturing the same
US5936279A (en) * 1997-10-20 1999-08-10 United Microelectronics Corp. Method of fabricating self-align contact window with silicon nitride side wall
US6121100A (en) 1997-12-31 2000-09-19 Intel Corporation Method of fabricating a MOS transistor with a raised source/drain extension
US6087706A (en) 1998-04-07 2000-07-11 Advanced Micro Devices, Inc. Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls
US6034388A (en) 1998-05-15 2000-03-07 International Business Machines Corporation Depleted polysilicon circuit element and method for producing the same
US6127712A (en) * 1998-05-22 2000-10-03 Texas Instruments--Acer Incorporated Mosfet with buried contact and air-gap gate structure
US6153485A (en) 1998-11-09 2000-11-28 Chartered Semiconductor Manufacturing Ltd. Salicide formation on narrow poly lines by pulling back of spacer

Cited By (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030098489A1 (en) * 2001-11-29 2003-05-29 International Business Machines Corporation High temperature processing compatible metal gate electrode for pFETS and methods for fabrication
US7863083B2 (en) 2001-11-29 2011-01-04 International Business Machines Corporation High temperature processing compatible metal gate electrode for pFETS and methods for fabrication
US20080311745A1 (en) * 2001-11-29 2008-12-18 International Business Machines Corporation High Temperature Processing Compatible Metal Gate Electrode For pFETS and Methods For Fabrication
US20050121706A1 (en) * 2003-02-20 2005-06-09 Hao-Yu Chen Semiconductor nano-rod devices
US20040198003A1 (en) * 2003-03-26 2004-10-07 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple-gate transistors with improved gate control
US6844238B2 (en) * 2003-03-26 2005-01-18 Taiwan Semiconductor Manufacturing Co., Ltd Multiple-gate transistors with improved gate control
US20060234431A1 (en) * 2003-04-29 2006-10-19 Yee-Chia Yeo Doping of semiconductor fin devices
US7074656B2 (en) 2003-04-29 2006-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of semiconductor fin devices
US7701008B2 (en) 2003-04-29 2010-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of semiconductor fin devices
US20100176424A1 (en) * 2003-04-29 2010-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of Semiconductor Fin Devices
US20040217433A1 (en) * 2003-04-29 2004-11-04 Yee-Chia Yeo Doping of semiconductor fin devices
US20060220133A1 (en) * 2003-04-29 2006-10-05 Yee-Chia Yeo Doping of semiconductor fin devices
US8053839B2 (en) 2003-04-29 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of semiconductor fin devices
US8790970B2 (en) 2003-04-29 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of semiconductor fin devices
US7005330B2 (en) 2003-06-27 2006-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for forming the gate electrode in a multiple-gate transistor
US7276763B2 (en) 2003-06-27 2007-10-02 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for forming the gate electrode in a multiple-gate transistor
US20060091428A1 (en) * 2003-06-27 2006-05-04 Yee-Chia Yeo Structure and method for forming the gate electrode in a multiple-gate transistor
US20040266077A1 (en) * 2003-06-27 2004-12-30 Yee-Chia Yeo Structure and method for forming the gate electrode in a multiple-gate transistor
US7005358B2 (en) 2003-07-31 2006-02-28 Advanced Micro Devices, Inc. Technique for forming recessed sidewall spacers for a polysilicon line
DE10335100B4 (en) * 2003-07-31 2008-06-05 Advanced Micro Devices, Inc., Sunnyvale A method of fabricating truncated sidewall spacers for a polysilicon line and method of fabricating a field effect transistor
US20050026380A1 (en) * 2003-07-31 2005-02-03 Thorsten Kammler Technique for forming recessed sidewall spacers for a polysilicon line
US20050064635A1 (en) * 2003-09-22 2005-03-24 International Business Machines Corporation METHOD FOR AVOIDING OXIDE UNDERCUT DURING PRE-SILICIDE CLEAN FOR THIN SPACER FETs
US20060057797A1 (en) * 2003-09-22 2006-03-16 International Business Machines Corporation Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs
US6991979B2 (en) * 2003-09-22 2006-01-31 International Business Machines Corporation Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs
US7091128B2 (en) * 2003-09-22 2006-08-15 International Business Machines Corporation Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs
WO2005047561A1 (en) * 2003-11-13 2005-05-26 International Business Machines Corporation Cvd tantalum compounds for fet gate electrodes
US7109086B2 (en) 2003-12-30 2006-09-19 Advanced Micro Devices, Inc. Technique for forming a spacer for a line element by using an etch stop layer deposited by a highly directional deposition technique
DE10361635A1 (en) * 2003-12-30 2005-08-04 Advanced Micro Devices, Inc., Sunnyvale A technique of making a spacer for a conduit element by applying an etch stop layer applied by a high directional deposition technique
US20050142828A1 (en) * 2003-12-30 2005-06-30 Thorsten Kammler Technique for forming a spacer for a line element by using an etch stop layer deposited by a highly directional deposition technique
DE10361635B4 (en) * 2003-12-30 2010-05-06 Advanced Micro Devices, Inc., Sunnyvale A method of manufacturing a spacer element for a line element by applying an etch stop layer applied by a high directional deposition technique and a spacer transistor
US20050275010A1 (en) * 2004-06-10 2005-12-15 Hung-Wei Chen Semiconductor nano-wire devices and methods of fabrication
US7452778B2 (en) 2004-06-10 2008-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-wire devices and methods of fabrication
US20060094194A1 (en) * 2004-11-04 2006-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced disposable spacer process by low-temperature high-stress nitride film for sub-90NM CMOS technology
US7397091B2 (en) 2005-01-21 2008-07-08 Sony Corporation SiGe nickel barrier structure employed in a CMOS device to prevent excess diffusion of nickel used in the silicide material
US20060166422A1 (en) * 2005-01-21 2006-07-27 Jun Suenaga Sige nickel barrier structure employed in a cmos device to prevent excess diffusion of nickel used in the silicide material
US7078285B1 (en) 2005-01-21 2006-07-18 Sony Corporation SiGe nickel barrier structure employed in a CMOS device to prevent excess diffusion of nickel used in the silicide material
CN100459075C (en) * 2005-03-22 2009-02-04 台湾积体电路制造股份有限公司 Semiconductor device and method for forming grid spacer
US10864340B2 (en) 2005-06-06 2020-12-15 ResMed Pty Ltd Mask system
US10569041B2 (en) 2005-06-06 2020-02-25 ResMed Pty Ltd Mask system
US10561812B2 (en) 2005-06-06 2020-02-18 ResMed Pty Ltd Mask system
US7495280B2 (en) * 2006-05-16 2009-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with corner spacers
US7772051B2 (en) 2006-05-16 2010-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with corner spacers
US20070267678A1 (en) * 2006-05-16 2007-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with corner spacers
US20080230839A1 (en) * 2007-03-23 2008-09-25 Joern Regul Method of producing a semiconductor structure
WO2008135335A1 (en) * 2007-05-02 2008-11-13 International Business Machines Corporation Cmos circuits with high-k gate dielectric
US20080272438A1 (en) * 2007-05-02 2008-11-06 Doris Bruce B CMOS Circuits with High-K Gate Dielectric
US20090286384A1 (en) * 2008-05-14 2009-11-19 Ming-Yuan Wu Dishing-free gap-filling with multiple CMPs
US7955964B2 (en) 2008-05-14 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Dishing-free gap-filling with multiple CMPs
US20110227189A1 (en) * 2008-05-14 2011-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Dishing-Free Gap-Filling with Multiple CMPs
US8552522B2 (en) 2008-05-14 2013-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Dishing-free gap-filling with multiple CMPs
US8932951B2 (en) 2008-05-14 2015-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. Dishing-free gap-filling with multiple CMPs
US8461654B2 (en) 2008-07-24 2013-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Spacer shape engineering for void-free gap-filling process
US20100022061A1 (en) * 2008-07-24 2010-01-28 Ming-Yuan Wu Spacer Shape Engineering for Void-Free Gap-Filling Process
US8048752B2 (en) 2008-07-24 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Spacer shape engineering for void-free gap-filling process
US20180190787A1 (en) * 2014-06-19 2018-07-05 Globalfoundries Inc. Method and structure for protecting gates during epitaxial growth
US10446665B2 (en) * 2014-06-19 2019-10-15 Globalfoundries Inc. Method and structure for protecting gates during epitaxial growth
FR3046290A1 (en) * 2015-12-23 2017-06-30 Commissariat Energie Atomique METHOD FOR PRODUCING SPACERS WITH LOW PERMITTIVITY
US10658197B2 (en) 2015-12-23 2020-05-19 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for producing low-permittivity spacers
DE102022104004A1 (en) 2021-12-08 2023-06-15 Taiwan Semiconductor Manufacturing Co., Ltd. SELF-FILLING SPACER STRUCTURE

Also Published As

Publication number Publication date
US6512266B1 (en) 2003-01-28

Similar Documents

Publication Publication Date Title
US6512266B1 (en) Method of fabricating SiO2 spacers and annealing caps
US6720630B2 (en) Structure and method for MOSFET with metallic gate electrode
US6790733B1 (en) Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer
US7397091B2 (en) SiGe nickel barrier structure employed in a CMOS device to prevent excess diffusion of nickel used in the silicide material
US6271094B1 (en) Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance
US7041538B2 (en) Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOS
US7250658B2 (en) Hybrid planar and FinFET CMOS devices
US7091069B2 (en) Ultra thin body fully-depleted SOI MOSFETs
US6905941B2 (en) Structure and method to fabricate ultra-thin Si channel devices
US6806534B2 (en) Damascene method for improved MOS transistor
US6656824B1 (en) Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch
US20050164479A1 (en) Zirconium oxide and hafnium oxide etching using halogen containing chemicals
US6800530B2 (en) Triple layer hard mask for gate patterning to fabricate scaled CMOS transistors
US20040023478A1 (en) Capped dual metal gate transistors for CMOS process and method for making the same
US6440808B1 (en) Damascene-gate process for the fabrication of MOSFET devices with minimum poly-gate depletion, silicided source and drain junctions, and low sheet resistance gate-poly
US20030209765A1 (en) All-in-one disposable/permanent spacer elevated source/drain, self-aligned silicide CMOS
US20080237867A1 (en) Low contact resistance metal contact
WO2010020579A1 (en) Thin body silicon-on-insulator transistor with borderless self-aligned contacts
US7847356B2 (en) Metal gate high-K devices having a layer comprised of amorphous silicon
US5915181A (en) Method for forming a deep submicron MOSFET device using a silicidation process
US20090057755A1 (en) Spacer undercut filler, method of manufacture thereof and articles comprising the same
US20080299767A1 (en) Method for Forming a Semiconductor Device Having a Salicide Layer
US7833853B2 (en) Method of defining gate structure height for semiconductor devices
KR20080036289A (en) Method for manufacturing mos transistor

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DESHPANDE, SADANAND V.;DORIS, BRUCE B.;JAMMY, RAJARAO;AND OTHERS;REEL/FRAME:012007/0734;SIGNING DATES FROM 20010628 TO 20010706

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
FPAY Fee payment

Year of fee payment: 12

SULP Surcharge for late payment

Year of fee payment: 11

AS Assignment

Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001

Effective date: 20150629

AS Assignment

Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001

Effective date: 20150910

AS Assignment

Owner name: AURIGA INNOVATIONS, INC., CANADA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:041741/0358

Effective date: 20161207