US20020028555A1 - Mosfet with high dielectric constant gate insulator and minimum overlap capacitance - Google Patents
Mosfet with high dielectric constant gate insulator and minimum overlap capacitance Download PDFInfo
- Publication number
- US20020028555A1 US20020028555A1 US09/866,239 US86623901A US2002028555A1 US 20020028555 A1 US20020028555 A1 US 20020028555A1 US 86623901 A US86623901 A US 86623901A US 2002028555 A1 US2002028555 A1 US 2002028555A1
- Authority
- US
- United States
- Prior art keywords
- layer
- gate
- forming
- substrate
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000012212 insulator Substances 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 75
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 46
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 46
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000000126 substance Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 47
- 150000004767 nitrides Chemical class 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 22
- 229920005591 polysilicon Polymers 0.000 claims description 22
- 239000004020 conductor Substances 0.000 claims description 20
- 238000005137 deposition process Methods 0.000 claims description 20
- 238000002955 isolation Methods 0.000 claims description 18
- 239000003989 dielectric material Substances 0.000 claims description 15
- 238000005229 chemical vapour deposition Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 14
- 229910052681 coesite Inorganic materials 0.000 claims description 13
- 229910052906 cristobalite Inorganic materials 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 229910052682 stishovite Inorganic materials 0.000 claims description 13
- 229910052905 tridymite Inorganic materials 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 10
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 9
- 229910021332 silicide Inorganic materials 0.000 claims description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 8
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 6
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical group O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 6
- 238000001459 lithography Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 229910052454 barium strontium titanate Inorganic materials 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 claims description 3
- 229910002113 barium titanate Inorganic materials 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- 238000006731 degradation reaction Methods 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 6
- 230000000295 complement effect Effects 0.000 abstract description 2
- 230000005669 field effect Effects 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000001020 plasma etching Methods 0.000 description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 6
- 238000000137 annealing Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000004913 activation Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 2
- 238000000280 densification Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/512—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being parallel to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Definitions
- the present invention relates to semiconductor devices, and in particular to methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/ ⁇ m or below) and a channel length (sub-lithographic, e.g., 0.1 ⁇ m or less) that is shorter than the lithography-defined gate lengths.
- MOSFET metal oxide semiconductor field effect transistor
- CMOS Complementary Metal Oxide Semiconductor
- the activation anneal of the source/drain implants is typically performed after the gate insulator is formed. This limits the anneal temperature to less than 800° C. to prevent degradation of the properties of the high-k insulator. Such low temperature anneals result in partial activation of the source/drain junctions as well as in depletion of the polysilicon gate. Both of the above mentioned characteristics are undesirable since they oftentimes lead to device performance degradation.
- the source/drain extensions must overlap the gate region of the device. This overlap causes capacitance in the device. The greater the overlap of the source/drain extensions with the gate region, the greater the overlap capacitance is. Likewise, if the overlap of the source/drain extensions with the gate is too small, an unreliable MOSFET device may be fabricated.
- One object of the present invention is to provide a method of fabricating a highly reliable MOSFET device that contains a high-k dielectric material as the gate insulator of the device.
- a further object of the present invention is to provide a method of fabricating a highly reliable MOSFET device that contains a high-k dielectric gate insulator and a low overlap capacitance.
- Another object of the present invention is to provide a method of fabricating a highly reliable MOSFET device that has a high-k gate insulator, low overlap capacitance and a short channel length.
- a still further object of the present invention is to provide methods of fabricating a highly reliable MOSFET device having low overlap capacitance and a short channel length in which a high-k, low-temperature metal oxide or a high-k, high-temperature metal oxide is employed as the gate insulator of the device.
- high k is used in the present invention to denote a dielectric material that has a dielectric constant greater than Si 3 N 4 , i.e., greater than 7.0. More preferably, the term “high k” denotes a dielectric material having a dielectric constant of 15 or above.
- low overlap capacitance is used in the present invention to denote a capacitance of 0.35 fF/ ⁇ m or less.
- short channel length is employed in the present invention to denote a gate channel that lies beneath the gate region whose length is 0.1 ⁇ m or less, i.e., sub-lithographic.
- high-temperature metal oxide denotes a metal oxide that does not degrade when subjected to annealing at a temperature of about 950°-1050° C., preferably 1000° C., 10 seconds.
- metal oxides within this class include, but are not limited to: Al 2 O 3 and TiO 2 .
- low-temperature metal oxide denotes a metal oxide that is converted to a metal or it becomes leaky upon annealing at 950°-1050° C., preferably 1000° C., 10 seconds.
- metal oxides within this class include, but are not limited to: ZrO 2 , barium titanate, strontium titanate and barium strontium titanate.
- the processing steps of the present invention comprise:
- Step (h) includes forming activated source/drain extensions in said substrate beneath said gate conductor; forming spacers on exposed sidewalls of said high-k, high-temperature metal oxide; forming activated source/drain regions in said substrate; and forming silicide regions in portions of said pad oxide layer and in said gate conductor.
- the processing steps of the present invention comprise:
- step (xii) An optional planarization process may follow step (xii).
- MOSFET devices that are fabricated utilizing either of the above methods.
- the MOSFET devices of the present invention are characterized as having a low overlap capacitance and a short channel length.
- the MOSFET devices of the present invention comprise at least a gate region having a high-k gate insulator formed on at least a portion of a tapered pad oxide layer, wherein said gate region further includes a channel whose length is sublithographic, preferably 0.1 ⁇ m or less.
- FIGS. 1 A-G show a MOSFET device of the present invention through the various processing steps used in the first embodiment of the present invention, i.e., in situations in which a high-k, high-temperature metal oxide is employed.
- FIGS. 2 A-F shows a MOSFET device of the present invention through the various processing steps used in the second embodiment of the present invention, i.e., in situations in which a high-k, low-temperature metal oxide is employed.
- FIGS. 1 A- 1 G illustrate the basic processing steps that are employed in the first embodiment of the present invention.
- FIGS. 1 A- 1 G are cross-sectional views of one possible MOSFET device that can be formed utilizing the first method of the present invention.
- the first method is employed when a high-k, high-temperature metal oxide is used as the gate insulator.
- FIG. 1A shows an initial structure that is formed from step (a) of the present invention.
- the initial structure comprises a substrate 10 and a film stack 12 .
- the film stack includes a pad oxide layer 14 such as SiO 2 which is formed on the surface of substrate 10 and a nitride layer 16 such as Si 3 N 4 that is formed on the pad oxide layer.
- a pad oxide layer 14 such as SiO 2 which is formed on the surface of substrate 10
- a nitride layer 16 such as Si 3 N 4 that is formed on the pad oxide layer.
- nitride layer 16 is different from the nitride layer used in defining the isolation trench, therefore that layer will be removed by a subsequent etching step to expose the gate region of the structure—the pad oxide layer remains on portions of the substrate after removal of the nitride layer.
- Pad oxide layer 14 is formed on the surface of substrate 10 using a conventional thermal growing process, or alternatively, the pad oxide layer may be formed by a conventional deposition process such as, but not limited to: chemical vapor deposition (CVD), plasma-assisted CVD, sputtering, evaporation and other like deposition processes.
- CVD chemical vapor deposition
- CVD plasma-assisted CVD
- sputtering evaporation and other like deposition processes.
- the thickness of the pad oxide layer may vary, but it should be thicker than the corresponding gate insulator which will be formed in a subsequent processing step.
- the pad oxide layer has a thickness of from about 8 to about 20
- nitride layer 16 is concerned that layer is formed on the surface of pad oxide layer 14 utilizing conventional deposition processes well known in the art, including the same as mentioned hereinabove in forming the pad oxide layer.
- the thickness of the nitride layer may vary, but it should be thicker than the pad oxide in which it is formed thereon.
- nitride layer 16 of film stack 12 has a thickness of from about 50 to about 200 nm.
- the substrate employed in the present invention may be any conventional semiconductor substrate in which a semiconducting material such as silicon is present therein.
- a semiconducting material such as silicon
- examples of some substrates that may be employed in the present invention include, but are not limited to: Si, Ge, SiGe, GaP, InAs, InP and all other III/V compound semiconductors.
- the substrate may also be composed of a layered semiconductor such as Si/SiGe.
- the substrate may be of the n-type or p-type depending on the desired device to be fabricated.
- the substrate may contain various active and/or isolation regions either formed on the substrate or formed in the substrate using processing techniques that are well known in the art.
- a preferred substrate employed in the present invention is a Si wafer or chip.
- isolation trenches are formed in the substrate.
- the isolation trenches are formed through a previously deposited nitride layer (that is different from nitride layer 16 ), pad oxide layer 14 and a portion of substrate 10 .
- Isolation trenches are formed using conventional lithography and etching (reactive-ion etching (RIE), plasma etching, ion beam etching and other like dry etch processes).
- RIE reactive-ion etching
- plasma etching plasma etching
- ion beam etching ion beam etching and other like dry etch processes.
- the lithography step employs a conventional photoresist and optionally an anti-reflective coating, both of which are removed after the isolation trenches have been formed in the structure.
- An oxide liner e.g., SiO 2
- isolation trenches are formed in the isolation trenches so as to line the sidewalls and bottom of each trench and then the trench is filled with a trench dielectric material (In the drawings, isolation regions 18 are meant to include both the oxide liner as well as the trench dielectric material).
- An optional densification step and/or a planarization step may follow the trench fill.
- the structure which is formed after isolation trench fill, planarization and film stack 12 formation is shown in FIG. 1A. It should be noted that the oxide liner forms a continuous layer with the top surface of the pad oxide; therefore, the entire bottom portion of the isolation trench is isolated from substrate 10 .
- the oxide liner may be formed using any conventional deposition or thermal growing process including the same as mentioned hereinabove in forming pad oxide layer 14 .
- the thickness of the oxide liner may vary depending on the processing technique used in forming the same, but a typical thickness range of the oxide liner is from about 5 to about 20 nm.
- a trench dielectric material is formed on the surface of the previously formed nitride layer and in isolation trenches.
- the filling process employed in the present invention comprises any conventional deposition process including, but not limited to: CVD and plasma-assisted CVD.
- Suitable trench dielectric materials that may be employed in this step of the present invention include: any conventional dielectric material. Examples of some suitable trench dielectric materials that can be used in the present invention include, but are note limited to: tetraethylorthosilicate (TEOS), SiO 2 , flowable oxides and other like dielectric materials. When TEOS is used as the trench dielectric material, an optical densification step may be employed prior to planarization.
- the planarization process comprises any conventional planarization technique known to those skilled in the art including, but not limited to: chemical-mechanical polishing (CMP) and grinding.
- CMP chemical-mechanical polishing
- the nitride layer may be removed and a new nitride layer 16 is formed, or alternatively additional nitride material is deposited forming a new nitride layer 16 .
- the next step of the first method of the present invention includes the formation of gate hole 20 in nitride layer 16 stopping on pad oxide 14 , See FIG. 1B.
- the gate hole is formed utilizing conventional lithography and etching (reactive-ion etching (RIE), plasma-etching, ion beam etching and other like dry etching processes) providing the structure shown in FIG. 1B.
- RIE reactive-ion etching
- a conventional photoresist is employed in defining the gate hole and is removed after fabricating the same.
- an optional threshold adjust implant step may be performed utilizing conventional ion implantation and an activation anneal; both of these processes are well known to those skilled in the art.
- an oxide film 22 is formed on the nitride layer in gate hole 20 providing the structure shown in FIG. 1C.
- the oxide layer is formed by utilizing a deposition process such as CVD that is capable of forming a layer of oxide on the nitride layer within the gate hole.
- the oxide is composed of a conventional material such as TEOS.
- an opening 24 is formed in pad oxide layer 14 in the bottom of gate hole 20 so as to provide a tapered pad oxide layer in the gate hole.
- tape it is meant the sidewalls of the pad oxide are not vertical. Rather, the sidewalls of the pad oxide deviate significantly from 90°. Preferably, the sidewalls of the tapered pad oxide are about 45° or less.
- the tapering is provided in the present invention by utilizing a chemical oxide removal (COR) step which is highly selective in removing oxide. This step of the present invention exposes a portion of substrate 10 in the gate hole by tapering the pad oxide layer while completely removing the oxide layer that was previously formed on the nitride layer within the gate hole.
- the COR step is a vapor phase chemical oxide removal process wherein a vapor of HF and NH 3 is employed as the etchant and low pressures (6 millitorr or below) are used.
- a high-k, high-temperature metal oxide layer 26 (See FIG. 1E) is formed about the gate hole (including the tapered pad oxide layer and the exposed surface of the substrate).
- the high-k, high-temperature metal oxide is formed utilizing a conventional deposition process including, but not limited to: CVD, plasma-assisted CVD, atomic layer deposition, sputtering and other like deposition processes.
- the high-k, high-temperature material includes any metal oxide that does not degrade when it is annealed at 950°-1050° C., preferably at 1000° C., for 10 seconds. Examples of some high-k, high-temperature metal oxides that can be employed in the present invention include: Al 2 O 3 and TiO 2 .
- the thickness of the high-k, high-temperature dielectric material is not critical to the present invention, but typically the thickness of the high-k, high-temperature dielectric is from about 5 to about 30 ⁇ .
- the gate hole is filled with a gate conductor 28 utilizing conventional deposition processes well known to those skilled in the art such as CVD, plasma-assisted CVD, evaporation and sputtering.
- Suitable gate conductors that can be employed in the present invention include, but are not limited to: polysilicon, W, Ta, TiN and other like conductive materials.
- the structure including the gate conductor is also shown in FIG. 1E. If needed, a conventional planarization process is used after filling the gate hole with the gate conductor.
- nitride layer 16 is removed from the structure utilizing a conventional damascene etch back process.
- a chemical etchant such as hot phosphoric acid, that is highly selective in removing nitride as compared to the other surrounding materials layers is employed in the damascene etch back process; the damascene etch back process employed in the present invention stops on the pad oxide layer mentioned above.
- FIG. 1G is a blown up view about the MOSFET device region.
- FIG. 1G includes: source/drain extensions 30 , spacers 32 , source/drain regions 34 and silicide regions 36 .
- the source/drain extensions are formed utilizing conventional ion implantation and annealing.
- the annealing temperature sued in activating the source/drain extensions is typically about 950° C. or above, and the annealing time is typically about 5 seconds or below.
- Spacers 32 are composed of any conventional nitride (e.g., Si 3 N 4 ) or oxide (e.g., SiO 2 ) and are formed utilizing conventional deposition processes well known in the art and then they are etched by RIE or another like etch process.
- the thickness of spacers 32 may vary, but typically they have a thickness of from about 100 to about 150 nm.
- Source/drain regions 34 are formed by conventional ion implantation and annealing.
- the anneal temperature used in activating the source/drain regions is typically about 1000° C. or above, for a time period of about 5 seconds or less.
- silicide regions are formed in the structure utilizing conventional silicide processing steps that are well known to those skilled in the art. Since such processing steps are well known, a detailed description of the same is not provided herein.
- FIG. 1G may then be subjected to other conventional CMOS processing steps which are well known in the art and are described, for example, in R.Colclaser, “Miro Electronics processing and Device Design, Chapter 10, pages 266-269, John Wiley and Sons publisher, 1980.
- FIGS. 1 A- 1 G illustrate a method of the present invention wherein a high-k, high-temperature metal oxide is employed as the gate insulator.
- FIGS. 2 A- 2 F illustrate a method of the present invention when a high-k, low-temperature metal oxide is employed as the gate insulator. It is noted that the second embodiment shown in FIGS. 2 A- 2 F represents a preferred embodiment of the present invention.
- FIG. 2A The initial structure employed in this embodiment of the present invention is shown in FIG. 2A.
- FIG. 2A comprises substrate 10 , isolation trenches 18 and a dummy film stack 50 which comprises a pad oxide layer 14 , a polysilicon layer 52 and a SiO 2 layer 54 .
- the trenches and the pad oxide layer are formed utilizing the processing steps mentioned above in connection with the first embodiment of the present invention.
- the polysilicon layer of dummy film stack 50 is formed utilizing conventional deposition processes such as CVD, plasma-assisted CVD and sputtering, with a low pressure CVD process being highly preferred.
- the thickness of polysilicon layer 52 is not critical to the present invention, but typically the thickness of the polysilicon layer is from about 1000 to about 2000 ⁇ .
- the SiO 2 layer of dummy film stack 50 is formed utilizing ozone deposition of tetraethylorthosilicate (TEOS), or are formed utilizing the same processing techniques as mentioned hereinabove. It is noted that FIG. 2B illustrates a structure which includes a dummy gate region 58 which comprises polysilicon layer 52 . The use of the dummy gate region and the subsequent formation of regions 30 , 32 , 34 and 36 , allows one to be able to employ a high-k, low-temperature metal oxide as the gate insulator.
- TEOS tetraethylorthosilicate
- an insulator layer 60 is formed over the structure utilizing conventional deposition processes such as CVD, low pressure CVD, plasma-assisted CVD and other like deposition processes that are capable of forming a conformal layer over the structure.
- Any insulator material such as SiO 2 can be employed as layer 60 .
- the thickness of the insulator layer may vary depending upon the type of material used, but typically the thickness of the insulator layer is from about 2000 to about 3000 ⁇ .
- any conventional planarization process such as chemical-mechanical polishing or grinding may be employed. It is noted that the planarization process employed in this step of the present invention is stopped after the silicide region 36 formed on top of polysilicon layer 52 is removed. Thus, the planarization exposes polysilicon layer 52 of the dummy gate region.
- the structure formed after conducting the above planarization step is shown in FIG. 2D.
- polysilicon layer 52 is removed utilizing RIE or a chemical down stream etching process exposing pad oxide layer 14 .
- the exposed pad oxide is then etched utilizing the COR process mentioned above so that a tapper is formed in the pad oxide layer, See FIG. 2E.
- the combined etch steps form opening 24 in the structure, wherein said opening contains a tapered pad oxide layer.
- a high-k, low-temperature metal oxide layer 62 such as ZrO 2 , barium titanate, strontium titanate, barium strontium titanate and the like is formed in the opening utilizing a conventional deposition process as described previously herein in connection with the high-k, high-temperature metal oxide.
- the thickness of the high-k, low-temperature metal oxide is from about 5 to about 30 ⁇ .
- An optional barrier layer e.g., a nitride, may be formed in the opening prior to deposition of the high-k, low-temperature metal oxide.
- any conventional deposition process such as CVD may be used and the thickness may vary depending on the type of material used in forming the barrier layer.
- a rapid thermal anneal in N 2 at a temperature of about 950° or below and for about 30 seconds or less is employed.
- the rapid thermal anneal may be carried out utilizing a single ramp and soak cycle or multiple ramp and soak cycles may be employed.
- a conductive material 28 such as described above is then formed in the opening utilizing the processing steps mentioned hereinabove.
- the structure may then be planarized by conventional planarization processes, e.g., CMP, to provide the structure shown in FIG. 2F.
- FIGS. 1G and 2F there are shown MOSFET devices in which a high-k metal oxide is employed as the gate insulator. Moreover, the MOSFET devices shown in FIGS. 1G and 2F have a low overlap capacitance and a short channel length. The short channel length is a direct result of providing a taper to the pad oxide layer. By tapering the pad oxide layer in the manner described above, channel 38 is much smaller than that which can be obtained from lithographic processes.
Abstract
Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/μm or below) and a channel length (sub-lithographic, e.g., 0.1 μm or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.
Description
- The present invention relates to semiconductor devices, and in particular to methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/μm or below) and a channel length (sub-lithographic, e.g., 0.1 μm or less) that is shorter than the lithography-defined gate lengths.
- As MOSFET channel lengths are scaled down to sub-0.1 μm dimensions and as the gate oxide thickness is scaled down to below 1.5 nm, tunneling currents larger than 1 A/cm 2 will preclude the use of SiO2 as a gate dielectric layer. Therefore, the development of a Complementary Metal Oxide Semiconductor (CMOS) technology which utilizes a high-k gate insulator is a must for the continuing of CMOS scaling into the sub-0.1 μm regime.
- In conventional gate CMOS technologies wherein high-k gate insulators are employed, the activation anneal of the source/drain implants is typically performed after the gate insulator is formed. This limits the anneal temperature to less than 800° C. to prevent degradation of the properties of the high-k insulator. Such low temperature anneals result in partial activation of the source/drain junctions as well as in depletion of the polysilicon gate. Both of the above mentioned characteristics are undesirable since they oftentimes lead to device performance degradation.
- Moreover, in conventional gate CMOS technologies, the source/drain extensions must overlap the gate region of the device. This overlap causes capacitance in the device. The greater the overlap of the source/drain extensions with the gate region, the greater the overlap capacitance is. Likewise, if the overlap of the source/drain extensions with the gate is too small, an unreliable MOSFET device may be fabricated.
- Another problem associated with conventional gate-CMOS technologies is that the gate is fabricated utilizing sag lithography and etching. The use of lithography and etching in forming the gate region of the CMOS device ago provides a MOSFET device whose channel length is in the same order as the lithographic tool. That is, lithography-defined gate length preclude the formation of sub-lithographic devices.
- In view of the drawbacks with prior art gate CMOS technologies, there is a continued need to develop new and improved methods that will permit the fabrication of MOSFET devices that have a high-k gate insulator, low overlap capacitance and a sub-lithographic channel length.
- One object of the present invention is to provide a method of fabricating a highly reliable MOSFET device that contains a high-k dielectric material as the gate insulator of the device.
- A further object of the present invention is to provide a method of fabricating a highly reliable MOSFET device that contains a high-k dielectric gate insulator and a low overlap capacitance.
- Another object of the present invention is to provide a method of fabricating a highly reliable MOSFET device that has a high-k gate insulator, low overlap capacitance and a short channel length.
- A still further object of the present invention is to provide methods of fabricating a highly reliable MOSFET device having low overlap capacitance and a short channel length in which a high-k, low-temperature metal oxide or a high-k, high-temperature metal oxide is employed as the gate insulator of the device.
- The term “high k” is used in the present invention to denote a dielectric material that has a dielectric constant greater than Si 3N4, i.e., greater than 7.0. More preferably, the term “high k” denotes a dielectric material having a dielectric constant of 15 or above.
- The term “low overlap capacitance” is used in the present invention to denote a capacitance of 0.35 fF/μm or less.
- The term “short channel length” is employed in the present invention to denote a gate channel that lies beneath the gate region whose length is 0.1 μm or less, i.e., sub-lithographic.
- The term “high-temperature metal oxide” denotes a metal oxide that does not degrade when subjected to annealing at a temperature of about 950°-1050° C., preferably 1000° C., 10 seconds. Illustrative examples of metal oxides within this class include, but are not limited to: Al 2O3 and TiO2.
- The term “low-temperature metal oxide” denotes a metal oxide that is converted to a metal or it becomes leaky upon annealing at 950°-1050° C., preferably 1000° C., 10 seconds. Illustrative examples of metal oxides within this class include, but are not limited to: ZrO 2, barium titanate, strontium titanate and barium strontium titanate.
- These and other objects and advantages can be achieved in the present invention by utilizing a method which includes a damascene processing step for the formation of the gate electrode and a chemical oxide removal (COR) processing step for producing a large taper in the pad oxide layer. When these two processing steps are used in combination with a high-k dielectric material, a MOSFET device having a low overlap capacitance and a short channel length can be fabricated.
- In one embodiment of the present invention wherein a high-k, high-temperature metal oxide is employed as the gate insulator, the processing steps of the present invention comprise:
- (a) providing a semiconductor structure having a film stack formed on a surface of a substrate, said film stack comprising at least a pad oxide layer formed on said surface of said substrate and a nitride layer formed on said pad oxide layer;
- (b) forming a gate hole in said nitride layer stopping on said pad oxide layer;
- (c) forming an oxide film on the nitride layer in said gate hole;
- (d) etching said oxide film and a portion of said pad oxide layer so as to provide an opening in said gate hole exposing a portion of said substrate, wherein the pad oxide layer is tapered by said etching;
- (e) forming a high-k, high-temperature metal oxide layer about said gate hole and on said exposed substrate;
- (f) filling said gate hole with a gate conductor;
- (g) removing said nitride layer exposing portions of said high-k, high-temperature metal oxide; and
- (h) completing fabrication of said MOSFET device.
- Step (h) includes forming activated source/drain extensions in said substrate beneath said gate conductor; forming spacers on exposed sidewalls of said high-k, high-temperature metal oxide; forming activated source/drain regions in said substrate; and forming silicide regions in portions of said pad oxide layer and in said gate conductor.
- In another embodiment of the present invention, wherein a high-k, low-temperature metal oxide is employed as the gate insulator, the processing steps of the present invention comprise:
- (i) providing a semiconductor structure having a dummy film stack formed on a surface of a substrate, said dummy film stack comprising at least a pad oxide layer formed on said surface of said substrate, a polysilicon layer formed on said pad oxide layer, and a SiO 2 layer formed on said polysilicon layer;
- (ii) removing selective portions of said dummy film stack stopping on said pad oxide layer so as to provide a patterned dummy gate region;
- (iii) removing said SiO 2 layer from said patterned dummy gate region;
- (iv) forming activated source/drain extensions in said substrate beneath said dummy gate region;
- (v) forming spacers on sidewalls of said dummy gate region;
- (vi) forming activated source/drain regions in said substrate;
- (vii) forming silicide regions in portions of said pad oxide layer and in said polysilicon layer of said dummy gate region;
- (viii) forming an insulator layer surrounding said dummy gate region;
- (ix) planarizing said insulator layer stopping at said polysilicon layer in said dummy gate region;
- (x) forming an opening so as to expose a portion of said substrate, said opening being formed by removing said polysilicon layer of said dummy gate and by tapering a portion of said pad oxide layer of said dummy gate region;
- (xi) forming a high-k, low-temperature metal oxide in said opening; and
- (xii) filling said opening with a gate conductor, said gate conductor being formed at a low temperature.
- An optional planarization process may follow step (xii).
- Another aspect of the present invention relates to MOSFET devices that are fabricated utilizing either of the above methods. The MOSFET devices of the present invention are characterized as having a low overlap capacitance and a short channel length. Specifically, the MOSFET devices of the present invention comprise at least a gate region having a high-k gate insulator formed on at least a portion of a tapered pad oxide layer, wherein said gate region further includes a channel whose length is sublithographic, preferably 0.1 μm or less.
- FIGS. 1A-G show a MOSFET device of the present invention through the various processing steps used in the first embodiment of the present invention, i.e., in situations in which a high-k, high-temperature metal oxide is employed.
- FIGS. 2A-F shows a MOSFET device of the present invention through the various processing steps used in the second embodiment of the present invention, i.e., in situations in which a high-k, low-temperature metal oxide is employed.
- The present invention which provides methods of fabricating a MOSFET device having a high-k gate insulator, low overlap capacitance and a short channel length will now be described in greater detail by referring to the drawings that accompany the present invention. It should be noted that in the accompanying drawings like reference numerals are used for describing like and/or corresponding elements.
- Reference is made to FIGS. 1A-1G which illustrate the basic processing steps that are employed in the first embodiment of the present invention. Specifically, FIGS. 1A-1G are cross-sectional views of one possible MOSFET device that can be formed utilizing the first method of the present invention. As state above, the first method is employed when a high-k, high-temperature metal oxide is used as the gate insulator.
- FIG. 1A shows an initial structure that is formed from step (a) of the present invention. The initial structure comprises a
substrate 10 and afilm stack 12. The film stack includes apad oxide layer 14 such as SiO2 which is formed on the surface ofsubstrate 10 and anitride layer 16 such as Si3N4 that is formed on the pad oxide layer. Although the drawings of the present invention depict a film stack comprising two material layers, the film stack may also comprise additional material layers. In the embodiment in the drawings of the present invention,nitride layer 16 is different from the nitride layer used in defining the isolation trench, therefore that layer will be removed by a subsequent etching step to expose the gate region of the structure—the pad oxide layer remains on portions of the substrate after removal of the nitride layer. -
Pad oxide layer 14 is formed on the surface ofsubstrate 10 using a conventional thermal growing process, or alternatively, the pad oxide layer may be formed by a conventional deposition process such as, but not limited to: chemical vapor deposition (CVD), plasma-assisted CVD, sputtering, evaporation and other like deposition processes. The thickness of the pad oxide layer may vary, but it should be thicker than the corresponding gate insulator which will be formed in a subsequent processing step. Typically, the pad oxide layer has a thickness of from about 8 to about 20 - Insofar as
nitride layer 16 is concerned that layer is formed on the surface ofpad oxide layer 14 utilizing conventional deposition processes well known in the art, including the same as mentioned hereinabove in forming the pad oxide layer. The thickness of the nitride layer may vary, but it should be thicker than the pad oxide in which it is formed thereon. Typically, in the present invention,nitride layer 16 offilm stack 12 has a thickness of from about 50 to about 200 nm. - The substrate employed in the present invention may be any conventional semiconductor substrate in which a semiconducting material such as silicon is present therein. Examples of some substrates that may be employed in the present invention include, but are not limited to: Si, Ge, SiGe, GaP, InAs, InP and all other III/V compound semiconductors. The substrate may also be composed of a layered semiconductor such as Si/SiGe. The substrate may be of the n-type or p-type depending on the desired device to be fabricated. The substrate may contain various active and/or isolation regions either formed on the substrate or formed in the substrate using processing techniques that are well known in the art. A preferred substrate employed in the present invention is a Si wafer or chip.
- Prior to forming
film stack 12 onsubstrate 10, isolation trenches are formed in the substrate. The isolation trenches are formed through a previously deposited nitride layer (that is different from nitride layer 16),pad oxide layer 14 and a portion ofsubstrate 10. Isolation trenches are formed using conventional lithography and etching (reactive-ion etching (RIE), plasma etching, ion beam etching and other like dry etch processes). Although not shown in the drawings, the lithography step employs a conventional photoresist and optionally an anti-reflective coating, both of which are removed after the isolation trenches have been formed in the structure. - An oxide liner, e.g., SiO 2, is formed in the isolation trenches so as to line the sidewalls and bottom of each trench and then the trench is filled with a trench dielectric material (In the drawings,
isolation regions 18 are meant to include both the oxide liner as well as the trench dielectric material). An optional densification step and/or a planarization step may follow the trench fill. The structure which is formed after isolation trench fill, planarization andfilm stack 12 formation is shown in FIG. 1A. It should be noted that the oxide liner forms a continuous layer with the top surface of the pad oxide; therefore, the entire bottom portion of the isolation trench is isolated fromsubstrate 10. - The oxide liner may be formed using any conventional deposition or thermal growing process including the same as mentioned hereinabove in forming
pad oxide layer 14. The thickness of the oxide liner may vary depending on the processing technique used in forming the same, but a typical thickness range of the oxide liner is from about 5 to about 20 nm. - After the bottom portions of the isolation trenches have been lined with the oxide liner, a trench dielectric material is formed on the surface of the previously formed nitride layer and in isolation trenches. The filling process employed in the present invention comprises any conventional deposition process including, but not limited to: CVD and plasma-assisted CVD. Suitable trench dielectric materials that may be employed in this step of the present invention include: any conventional dielectric material. Examples of some suitable trench dielectric materials that can be used in the present invention include, but are note limited to: tetraethylorthosilicate (TEOS), SiO 2, flowable oxides and other like dielectric materials. When TEOS is used as the trench dielectric material, an optical densification step may be employed prior to planarization.
- The planarization process comprises any conventional planarization technique known to those skilled in the art including, but not limited to: chemical-mechanical polishing (CMP) and grinding. After forming the isolation regions, the nitride layer may be removed and a
new nitride layer 16 is formed, or alternatively additional nitride material is deposited forming anew nitride layer 16. - The next step of the first method of the present invention includes the formation of
gate hole 20 innitride layer 16 stopping onpad oxide 14, See FIG. 1B. Specifically, the gate hole is formed utilizing conventional lithography and etching (reactive-ion etching (RIE), plasma-etching, ion beam etching and other like dry etching processes) providing the structure shown in FIG. 1B. A conventional photoresist is employed in defining the gate hole and is removed after fabricating the same. Although the drawings depict the formation of only one gate hole in the structure, a plurality of gate holes are also contemplated herein. - Following gate hole formation, an optional threshold adjust implant step may be performed utilizing conventional ion implantation and an activation anneal; both of these processes are well known to those skilled in the art.
- After gate hole formation and optional threshold adjust implant formation, an
oxide film 22 is formed on the nitride layer ingate hole 20 providing the structure shown in FIG. 1C. The oxide layer is formed by utilizing a deposition process such as CVD that is capable of forming a layer of oxide on the nitride layer within the gate hole. The oxide is composed of a conventional material such as TEOS. - Next, as is shown in FIG. 1D, an
opening 24 is formed inpad oxide layer 14 in the bottom ofgate hole 20 so as to provide a tapered pad oxide layer in the gate hole. By “taper” it is meant the sidewalls of the pad oxide are not vertical. Rather, the sidewalls of the pad oxide deviate significantly from 90°. Preferably, the sidewalls of the tapered pad oxide are about 45° or less. The tapering is provided in the present invention by utilizing a chemical oxide removal (COR) step which is highly selective in removing oxide. This step of the present invention exposes a portion ofsubstrate 10 in the gate hole by tapering the pad oxide layer while completely removing the oxide layer that was previously formed on the nitride layer within the gate hole. The COR step is a vapor phase chemical oxide removal process wherein a vapor of HF and NH3 is employed as the etchant and low pressures (6 millitorr or below) are used. - After tapering the pad oxide layer in the gate hole, a high-k, high-temperature metal oxide layer 26 (See FIG. 1E) is formed about the gate hole (including the tapered pad oxide layer and the exposed surface of the substrate). The high-k, high-temperature metal oxide is formed utilizing a conventional deposition process including, but not limited to: CVD, plasma-assisted CVD, atomic layer deposition, sputtering and other like deposition processes. As stated above, the high-k, high-temperature material includes any metal oxide that does not degrade when it is annealed at 950°-1050° C., preferably at 1000° C., for 10 seconds. Examples of some high-k, high-temperature metal oxides that can be employed in the present invention include: Al2O3 and TiO2.
- The thickness of the high-k, high-temperature dielectric material is not critical to the present invention, but typically the thickness of the high-k, high-temperature dielectric is from about 5 to about 30 Å.
- Following formation of the high-k, high-temperature metal oxide, the gate hole is filled with a
gate conductor 28 utilizing conventional deposition processes well known to those skilled in the art such as CVD, plasma-assisted CVD, evaporation and sputtering. Suitable gate conductors that can be employed in the present invention include, but are not limited to: polysilicon, W, Ta, TiN and other like conductive materials. The structure including the gate conductor is also shown in FIG. 1E. If needed, a conventional planarization process is used after filling the gate hole with the gate conductor. - Next, as shown in FIG. 1F,
nitride layer 16 is removed from the structure utilizing a conventional damascene etch back process. Specifically, a chemical etchant, such as hot phosphoric acid, that is highly selective in removing nitride as compared to the other surrounding materials layers is employed in the damascene etch back process; the damascene etch back process employed in the present invention stops on the pad oxide layer mentioned above. - Following removal of
nitride layer 16, other regions that are typically present in MOSFET devices are fabricated utilizing techniques that are well known to those skilled in the art. One completed MOSFET device of the present invention is shown in FIG. 1G which is a blown up view about the MOSFET device region. Specifically, FIG. 1G includes: source/drain extensions 30,spacers 32, source/drain regions 34 andsilicide regions 36. The source/drain extensions are formed utilizing conventional ion implantation and annealing. The annealing temperature sued in activating the source/drain extensions is typically about 950° C. or above, and the annealing time is typically about 5 seconds or below. -
Spacers 32 are composed of any conventional nitride (e.g., Si3N4) or oxide (e.g., SiO2) and are formed utilizing conventional deposition processes well known in the art and then they are etched by RIE or another like etch process. The thickness ofspacers 32 may vary, but typically they have a thickness of from about 100 to about 150 nm. - Source/
drain regions 34 are formed by conventional ion implantation and annealing. The anneal temperature used in activating the source/drain regions is typically about 1000° C. or above, for a time period of about 5 seconds or less. - The silicide regions are formed in the structure utilizing conventional silicide processing steps that are well known to those skilled in the art. Since such processing steps are well known, a detailed description of the same is not provided herein.
- The structure shown in FIG. 1G may then be subjected to other conventional CMOS processing steps which are well known in the art and are described, for example, in R.Colclaser, “Miro Electronics processing and Device Design,
Chapter 10, pages 266-269, John Wiley and Sons publisher, 1980. - The above description and FIGS. 1A-1G illustrate a method of the present invention wherein a high-k, high-temperature metal oxide is employed as the gate insulator. The following description and FIGS. 2A-2F illustrate a method of the present invention when a high-k, low-temperature metal oxide is employed as the gate insulator. It is noted that the second embodiment shown in FIGS. 2A-2F represents a preferred embodiment of the present invention.
- The initial structure employed in this embodiment of the present invention is shown in FIG. 2A. Specifically, FIG. 2A comprises
substrate 10,isolation trenches 18 and adummy film stack 50 which comprises apad oxide layer 14, apolysilicon layer 52 and a SiO2 layer 54. The trenches and the pad oxide layer are formed utilizing the processing steps mentioned above in connection with the first embodiment of the present invention. The polysilicon layer ofdummy film stack 50 is formed utilizing conventional deposition processes such as CVD, plasma-assisted CVD and sputtering, with a low pressure CVD process being highly preferred. The thickness ofpolysilicon layer 52 is not critical to the present invention, but typically the thickness of the polysilicon layer is from about 1000 to about 2000 Å. - The SiO 2 layer of
dummy film stack 50 is formed utilizing ozone deposition of tetraethylorthosilicate (TEOS), or are formed utilizing the same processing techniques as mentioned hereinabove. It is noted that FIG. 2B illustrates a structure which includes adummy gate region 58 which comprisespolysilicon layer 52. The use of the dummy gate region and the subsequent formation ofregions - Next, as shown in FIG. 2C, an
insulator layer 60 is formed over the structure utilizing conventional deposition processes such as CVD, low pressure CVD, plasma-assisted CVD and other like deposition processes that are capable of forming a conformal layer over the structure. Any insulator material such as SiO2 can be employed aslayer 60. The thickness of the insulator layer may vary depending upon the type of material used, but typically the thickness of the insulator layer is from about 2000 to about 3000 Å. - After forming the insulator layer over the structure, any conventional planarization process such as chemical-mechanical polishing or grinding may be employed. It is noted that the planarization process employed in this step of the present invention is stopped after the
silicide region 36 formed on top ofpolysilicon layer 52 is removed. Thus, the planarization exposespolysilicon layer 52 of the dummy gate region. The structure formed after conducting the above planarization step is shown in FIG. 2D. - Next,
polysilicon layer 52 is removed utilizing RIE or a chemical down stream etching process exposingpad oxide layer 14. The exposed pad oxide is then etched utilizing the COR process mentioned above so that a tapper is formed in the pad oxide layer, See FIG. 2E. The combined etch steps form opening 24 in the structure, wherein said opening contains a tapered pad oxide layer. - After forming the taper in the pad oxide layer, a high-k, low-temperature
metal oxide layer 62 such as ZrO2, barium titanate, strontium titanate, barium strontium titanate and the like is formed in the opening utilizing a conventional deposition process as described previously herein in connection with the high-k, high-temperature metal oxide. The thickness of the high-k, low-temperature metal oxide is from about 5 to about 30 Å. - An optional barrier layer, e.g., a nitride, may be formed in the opening prior to deposition of the high-k, low-temperature metal oxide. When an optional barrier layer is formed in the structure, any conventional deposition process such as CVD may be used and the thickness may vary depending on the type of material used in forming the barrier layer.
- After forming the high-k, low-temperature metal oxide in the structure a rapid thermal anneal in N 2 at a temperature of about 950° or below and for about 30 seconds or less is employed. The rapid thermal anneal may be carried out utilizing a single ramp and soak cycle or multiple ramp and soak cycles may be employed.
- A
conductive material 28 such as described above is then formed in the opening utilizing the processing steps mentioned hereinabove. The structure may then be planarized by conventional planarization processes, e.g., CMP, to provide the structure shown in FIG. 2F. - In both FIGS. 1G and 2F, there are shown MOSFET devices in which a high-k metal oxide is employed as the gate insulator. Moreover, the MOSFET devices shown in FIGS. 1G and 2F have a low overlap capacitance and a short channel length. The short channel length is a direct result of providing a taper to the pad oxide layer. By tapering the pad oxide layer in the manner described above,
channel 38 is much smaller than that which can be obtained from lithographic processes. - While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
Claims (32)
1. A method of forming a MOSFET device having low overlap capacitance and a short channel length comprising the steps of:
(a) providing a semiconductor structure having a film stack formed on a surface of a substrate, said film stack comprising at least a pad oxide layer formed on said surface of said substrate and a nitride layer formed on said pad oxide layer;
(b) forming a gate hole in said nitride layer stopping on said pad oxide layer;
(c) forming an oxide layer on said nitride layer in said gate hole;
(d) etching said oxide layer and a portion of said pad oxide layer so as to provide an opening in said gate hole exposing said substrate, wherein the pad oxide layer is tapered by said etching;
(e) forming a high-k, high-temperature metal oxide layer about said gate hole and on said exposed substrate;
(f) filling said gate hole with gate conductor;
(g) removing said nitride layer exposing portions of said high k, high-temperature metal oxide; and
(h) completing fabrication of said MOSFET device.
2. The method of claim 1 wherein step (h) includes forming activated source/drain extensions in said substrate beneath said gate conductor; forming spacers on said exposed high-k, high-temperature metal oxide; forming activated source/drain regions in said substrate; and forming silicide regions in portions of said pad oxide and in said gate conductor.
3. The method of claim 1 wherein said substrate includes isolation regions formed therein.
4. The method of claim 3 wherein said isolation regions include an oxide liner and a trench dielectric material.
5. The method of claim 1 wherein said substrate is a semiconducting material selected from the group consisting of Si, Ge, SiGe, GaAs, InAs, InP and layered semiconductors.
6. The method of claim 1 wherein said gate hole is formed by lithography and etching.
7. The method of claim 1 wherein said oxide layer is formed by deposition of an oxide material.
8. The method of claim 1 wherein step (d) is conducted utilizing a chemical oxide removal process.
9. The method of claim 8 wherein said chemical oxide removal process is conducted in a vapor of HF and NH3.
10. The method of claim 8 wherein said chemical oxide removal process is carried out at a pressure of about 8 millitorr or below.
11. The method of claim 1 wherein said high-k, high-temperature metal oxide is Al2O3 or TiO2 or any other oxide that is capable of withstanding degradation using a 950°-1050° C., 10 second anneal.
12. The method of claim 1 wherein said high-k, high-temperature metal oxide is formed by a deposition process selected from the group consisting of chemical vapor deposition (CVD), plasma-assisted CVD, sputtering, atomic layer deposition and other like deposition processes.
13. The method of claim 1 wherein said high-k, high-temperature metal oxide has a thickness of from about 5 to about 30 Å.
14. The method of claim 1 wherein said gate conductor is polysilicon, W, Ta, TiN and other like conductors.
15. The method of claim 1 wherein step (g) comprises a damascene processing step, wherein a chemical etchant is employed.
16. A method of forming a MOSFET device having low overlap capacitance and a short channel length comprising the steps of:
(i) providing a semiconductor structure having a dummy film stack formed on a surface of a substrate, said dummy film stack comprising at least a pad oxide layer formed on said surface of said substrate, a polysilicon layer on said pad oxide layer, and a SiO2 layer formed on said polysilicon layer;
(ii) removing selective portions of said dummy film stack stopping on said pad oxide layer so as to provide a patterned dummy gate region;
(iii) removing said SiO2 layer from said patterned dummy gate region;
(iv) forming activated source/drain extensions in said substrate beneath said dummy gate region;
(v) forming spacers on sidewalls of said dummy gate region;
(vi) forming activated source/drain regions in said substrate;
(vii) forming silicide regions in portions of said pad oxide layer and in said polysilicon layer of said dummy gate region;
(viii) forming an insulator layer surrounding said dummy gate region;
(ix) planarizing said insulator layer stopping at said polysilicon layer in said dummy gate region;
(x) forming an opening so as to expose a portion of said substrate, said opening being formed by removing said polysilicon layer of said dummy gate and by tapering a portion of said pad oxide layer of said dummy gate;
(xi) forming a high-k, low-temperature metal oxide in said opening; and
(xii) filling said opening with a gate conductor deposited at low temperatures
17. The method of claim 16 wherein said substrate includes isolation regions formed therein.
18. The method of claim 17 wherein said isolation regions include an oxide liner and a trench dielectric material.
19. The method of claim 16 wherein said substrate is a semiconducting material selected from the group consisting of Si, Ge, SiGe, GaAs, InAs, InP and layered semiconductors.
20. The method of claim 16 wherein step (i) comprises providing a resist, patterning said resist and etching areas not including the patterned resist.
21. The method of claim 16 wherein said SiO2 layer is removed utilizing a chemical etchant.
22. The method of claim 16 wherein said insulator layer is formed by a deposition process selected from the group consisting of CVD, low pressure CVD, plasma-assisted CVD and other like deposition processes that are capable of forming a conformal layer.
23. The method of claim 16 wherein said planarizing is carried out by chemical-mechanical polishing or grinding.
24. The method of claim 16 wherein step (x) is conducted utilizing a chemical oxide removal process.
25. The method of claim 24 wherein said chemical oxide removal process is conducted in a vapor of HF and NH3.
26. The method of claim 24 wherein said chemical oxide removal process is carried out at a pressure of about 8 millitorr or below.
27. The method of claim 1 wherein said high-k, low-temperature metal oxide is ZrO2, barium titanate, strontium titanate and barium strontium titanate, or any other oxide that degrades when a 950°-1050° C., 10 second anneal is employed.
28. The method of claim 16 wherein said high-k, low-temperature metal oxide is formed by a deposition process selected from the group consisting of chemical vapor deposition (CVD), plasma-assisted CVD, sputtering, atomic layer deposition and other like deposition processes.
29. The method of claim 16 wherein said high-k, low-temperature metal oxide has a thickness of from about 5 to about 30 Å.
30. The method of claim 16 wherein said high-k, low-temperature oxide is annealed in N2 at a temperature of about 950° C. or below and for a time period of from about 30 seconds or less.
31. The method of claim 16 wherein said gate conductor is polysilicon, W, Ta, TiN and other like conductors.
32. A MOSFET device comprising at least one gate region formed on a semiconductor substrate, said gate region comprising a gate conductor, a gate insulator and spacers, said gate insulator is a high-k metal oxide having a dielectric constant of greater than 7.0, said gate region further comprising a sub-lithographic channel formed beneath said gate insulator, wherein said channel length is determined by forming a portion of said gate insulator on a tapered pad oxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/866,239 US6353249B1 (en) | 2000-02-14 | 2001-05-25 | MOSFET with high dielectric constant gate insulator and minimum overlap capacitance |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/503,926 US6271094B1 (en) | 2000-02-14 | 2000-02-14 | Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance |
| US09/866,239 US6353249B1 (en) | 2000-02-14 | 2001-05-25 | MOSFET with high dielectric constant gate insulator and minimum overlap capacitance |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US09/503,926 Division US6271094B1 (en) | 2000-02-14 | 2000-02-14 | Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| US6353249B1 US6353249B1 (en) | 2002-03-05 |
| US20020028555A1 true US20020028555A1 (en) | 2002-03-07 |
Family
ID=24004103
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US09/503,926 Expired - Lifetime US6271094B1 (en) | 2000-02-14 | 2000-02-14 | Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance |
| US09/866,239 Expired - Fee Related US6353249B1 (en) | 2000-02-14 | 2001-05-25 | MOSFET with high dielectric constant gate insulator and minimum overlap capacitance |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US09/503,926 Expired - Lifetime US6271094B1 (en) | 2000-02-14 | 2000-02-14 | Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US6271094B1 (en) |
| JP (1) | JP3529732B2 (en) |
| KR (1) | KR100354115B1 (en) |
| CN (1) | CN1177357C (en) |
| SG (1) | SG90231A1 (en) |
| TW (1) | TW478162B (en) |
Cited By (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6541351B1 (en) * | 2001-11-20 | 2003-04-01 | International Business Machines Corporation | Method for limiting divot formation in post shallow trench isolation processes |
| US6614081B2 (en) * | 2000-04-05 | 2003-09-02 | Nec Electronics Corporation | High-performance MOS transistor of LDD structure having a gate insulating film with a nitride central portion and oxide end portions |
| US20040185670A1 (en) * | 2003-03-17 | 2004-09-23 | Tokyo Electron Limited | Processing system and method for treating a substrate |
| US20040184792A1 (en) * | 2003-03-17 | 2004-09-23 | Tokyo Electron Limited | Processing system and method for thermally treating a substrate |
| US20040182417A1 (en) * | 2003-03-17 | 2004-09-23 | Tokyo Electron Limited | Processing system and method for chemically treating a substrate |
| US20040182324A1 (en) * | 2003-03-17 | 2004-09-23 | Tokyo Electron Limited | Method and apparatus for thermally insulating adjacent temperature controlled processing chambers |
| US20040191998A1 (en) * | 2003-03-28 | 2004-09-30 | International Business Machines Corporation | Preserving teos hard mask using cor for raised source-drain including removable/disposable spacer |
| US20040192018A1 (en) * | 2001-12-04 | 2004-09-30 | Intel Corporation | Polysilicon opening polish |
| US20040262697A1 (en) * | 2003-05-28 | 2004-12-30 | Infineon Technologies | Semiconductor gate structure and method for fabricating a semiconductor gate structure |
| US20050000794A1 (en) * | 2003-05-23 | 2005-01-06 | Demaray Richard E. | Transparent conductive oxides |
| US20050104095A1 (en) * | 2003-11-13 | 2005-05-19 | International Business Machines Corporation | Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance |
| US20060057304A1 (en) * | 2002-03-16 | 2006-03-16 | Symmorphix, Inc. | Biased pulse DC reactive sputtering of oxide films |
| US20070170711A1 (en) * | 2006-01-25 | 2007-07-26 | Bechtel Travis D | Power release and locking adjustable steering column apparatus and method |
| US20070298972A1 (en) * | 2006-06-22 | 2007-12-27 | Tokyo Electron Limited | A dry non-plasma treatment system and method of using |
| US20080048225A1 (en) * | 2006-08-25 | 2008-02-28 | Micron Technology, Inc. | Atomic layer deposited barium strontium titanium oxide films |
| US20080099845A1 (en) * | 2006-10-25 | 2008-05-01 | International Business Machines Corporation | Sub-lithographic gate length transistor using self-assembling polymers |
| US20080222644A1 (en) * | 2007-03-05 | 2008-09-11 | International Business Machines Corporation | Risk-modulated proactive data migration for maximizing utility in storage systems |
| US7435636B1 (en) | 2007-03-29 | 2008-10-14 | Micron Technology, Inc. | Fabrication of self-aligned gallium arsenide MOSFETs using damascene gate methods |
| US20090087974A1 (en) * | 2007-09-29 | 2009-04-02 | Andrew Waite | Method of forming high-k gate electrode structures after transistor fabrication |
| US20100025389A1 (en) * | 2008-07-31 | 2010-02-04 | Tokyo Electron Limited | Heater assembly for high throughput chemical treatment system |
| US20100025368A1 (en) * | 2008-07-31 | 2010-02-04 | Tokyo Electron Limited | High throughput thermal treatment system and method of operating |
| US20100025367A1 (en) * | 2008-07-31 | 2010-02-04 | Tokyo Electron Limited | High throughput chemical treatment system and method of operating |
| US20120178231A1 (en) * | 2011-01-12 | 2012-07-12 | Samsung Electronics Co., Ltd. | Methods for fabricating a metal silicide layer and semiconductor devices using the same |
| US8287688B2 (en) | 2008-07-31 | 2012-10-16 | Tokyo Electron Limited | Substrate support for high throughput chemical treatment system |
| US8303716B2 (en) | 2008-07-31 | 2012-11-06 | Tokyo Electron Limited | High throughput processing system for chemical treatment and thermal treatment and method of operating |
| US8343280B2 (en) | 2006-03-28 | 2013-01-01 | Tokyo Electron Limited | Multi-zone substrate temperature control system and method of operating |
| US8636876B2 (en) | 2004-12-08 | 2014-01-28 | R. Ernest Demaray | Deposition of LiCoO2 |
| US10319427B2 (en) | 2017-06-09 | 2019-06-11 | Samsung Electronics Co., Ltd. | Semiconductor device |
Families Citing this family (138)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6355580B1 (en) | 1998-09-03 | 2002-03-12 | Micron Technology, Inc. | Ion-assisted oxidation methods and the resulting structures |
| WO2000055897A1 (en) * | 1999-03-17 | 2000-09-21 | Koninklijke Philips Electronics N.V. | Method of manufacturing a mis field-effect transistor |
| US6273951B1 (en) | 1999-06-16 | 2001-08-14 | Micron Technology, Inc. | Precursor mixtures for use in preparing layers on substrates |
| FR2810157B1 (en) * | 2000-06-09 | 2002-08-16 | Commissariat Energie Atomique | METHOD FOR PRODUCING AN ELECTRONIC COMPONENT WITH SOURCE, DRAIN AND SELF-ALLOCATED GRID, IN DAMASCENE ARCHITECTURE |
| US6444512B1 (en) * | 2000-06-12 | 2002-09-03 | Motorola, Inc. | Dual metal gate transistors for CMOS process |
| JP2002110967A (en) * | 2000-09-26 | 2002-04-12 | Seiko Epson Corp | Method of manufacturing semiconductor device and the semiconductor device |
| JP2002110966A (en) | 2000-09-26 | 2002-04-12 | Seiko Epson Corp | Method of manufacturing semiconductor device and the semiconductor device |
| JP2002110965A (en) * | 2000-09-26 | 2002-04-12 | Seiko Epson Corp | Method of manufacturing semiconductor device and the semiconductor device |
| US6440808B1 (en) * | 2000-09-28 | 2002-08-27 | International Business Machines Corporation | Damascene-gate process for the fabrication of MOSFET devices with minimum poly-gate depletion, silicided source and drain junctions, and low sheet resistance gate-poly |
| US6589866B1 (en) * | 2000-10-19 | 2003-07-08 | Advanced Micro Devices, Inc. | Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process |
| JP3940565B2 (en) * | 2001-03-29 | 2007-07-04 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| US6448192B1 (en) * | 2001-04-16 | 2002-09-10 | Motorola, Inc. | Method for forming a high dielectric constant material |
| US6509612B2 (en) * | 2001-05-04 | 2003-01-21 | International Business Machines Corporation | High dielectric constant materials as gate dielectrics (insulators) |
| US6762463B2 (en) * | 2001-06-09 | 2004-07-13 | Advanced Micro Devices, Inc. | MOSFET with SiGe source/drain regions and epitaxial gate dielectric |
| US6900094B2 (en) * | 2001-06-14 | 2005-05-31 | Amberwave Systems Corporation | Method of selective removal of SiGe alloys |
| US6417056B1 (en) * | 2001-10-18 | 2002-07-09 | Chartered Semiconductor Manufacturing Ltd. | Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge |
| KR100442784B1 (en) * | 2001-12-26 | 2004-08-04 | 동부전자 주식회사 | Method of manufacturing short-channel transistor in semiconductor device |
| KR100449324B1 (en) * | 2001-12-26 | 2004-09-18 | 동부전자 주식회사 | Method of manufacturing short-channel transistor in semiconductor device |
| KR100449323B1 (en) * | 2001-12-26 | 2004-09-18 | 동부전자 주식회사 | Method of manufacturing short-channel transistor in semiconductor device |
| US6479403B1 (en) | 2002-02-28 | 2002-11-12 | Taiwan Semiconductor Manufacturing Company | Method to pattern polysilicon gates with high-k material gate dielectric |
| KR20030073338A (en) * | 2002-03-11 | 2003-09-19 | 주식회사 다산 씨.앤드.아이 | Semiconductor device applying high-k insulator as gate and Method for manufacturing the same |
| US7087480B1 (en) | 2002-04-18 | 2006-08-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process to make high-k transistor dielectrics |
| US6818553B1 (en) * | 2002-05-15 | 2004-11-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etching process for high-k gate dielectrics |
| US6541336B1 (en) | 2002-05-15 | 2003-04-01 | International Business Machines Corporation | Method of fabricating a bipolar transistor having a realigned emitter |
| KR100439034B1 (en) * | 2002-08-02 | 2004-07-03 | 삼성전자주식회사 | Bitline of semiconductor device with leakage current protection and method for forming the same |
| US6642117B1 (en) | 2002-08-05 | 2003-11-04 | Taiwan Semiconductor Manufacturing Co. Ltd | Method for forming composite dielectric layer |
| US6995081B2 (en) * | 2002-08-28 | 2006-02-07 | Micron Technology, Inc. | Systems and methods for forming tantalum silicide layers |
| US6967159B2 (en) * | 2002-08-28 | 2005-11-22 | Micron Technology, Inc. | Systems and methods for forming refractory metal nitride layers using organic amines |
| US8617312B2 (en) * | 2002-08-28 | 2013-12-31 | Micron Technology, Inc. | Systems and methods for forming layers that contain niobium and/or tantalum |
| US6730164B2 (en) * | 2002-08-28 | 2004-05-04 | Micron Technology, Inc. | Systems and methods for forming strontium- and/or barium-containing layers |
| US6794284B2 (en) * | 2002-08-28 | 2004-09-21 | Micron Technology, Inc. | Systems and methods for forming refractory metal nitride layers using disilazanes |
| KR100479231B1 (en) * | 2002-09-17 | 2005-03-25 | 동부아남반도체 주식회사 | Method for forming a silicide gate line in a semiconductor dual damascene structure |
| US6756284B2 (en) * | 2002-09-18 | 2004-06-29 | Silicon Storage Technology, Inc. | Method for forming a sublithographic opening in a semiconductor process |
| US6770536B2 (en) * | 2002-10-03 | 2004-08-03 | Agere Systems Inc. | Process for semiconductor device fabrication in which a insulating layer is formed on a semiconductor substrate |
| US6656824B1 (en) * | 2002-11-08 | 2003-12-02 | International Business Machines Corporation | Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch |
| US6762114B1 (en) | 2002-12-31 | 2004-07-13 | Texas Instruments Incorporated | Methods for transistor gate fabrication and for reducing high-k gate dielectric roughness |
| US6750126B1 (en) | 2003-01-08 | 2004-06-15 | Texas Instruments Incorporated | Methods for sputter deposition of high-k dielectric films |
| US6806517B2 (en) * | 2003-03-17 | 2004-10-19 | Samsung Electronics Co., Ltd. | Flash memory having local SONOS structure using notched gate and manufacturing method thereof |
| US7115528B2 (en) | 2003-04-29 | 2006-10-03 | Micron Technology, Inc. | Systems and method for forming silicon oxide layers |
| US6924517B2 (en) * | 2003-08-26 | 2005-08-02 | International Business Machines Corporation | Thin channel FET with recessed source/drains and extensions |
| US7041601B1 (en) * | 2003-09-03 | 2006-05-09 | Advanced Micro Devices, Inc. | Method of manufacturing metal gate MOSFET with strained channel |
| US7205185B2 (en) * | 2003-09-15 | 2007-04-17 | International Busniess Machines Corporation | Self-aligned planar double-gate process by self-aligned oxidation |
| US6838347B1 (en) * | 2003-09-23 | 2005-01-04 | International Business Machines Corporation | Method for reducing line edge roughness of oxide material using chemical oxide removal |
| US7049662B2 (en) * | 2003-11-26 | 2006-05-23 | International Business Machines Corporation | Structure and method to fabricate FinFET devices |
| KR100707169B1 (en) * | 2003-12-12 | 2007-04-13 | 삼성전자주식회사 | Memory Device and Manufacturing Method thereof |
| US7351994B2 (en) * | 2004-01-21 | 2008-04-01 | Taiwan Semiconductor Manufacturing Company | Noble high-k device |
| US20050242387A1 (en) * | 2004-04-29 | 2005-11-03 | Micron Technology, Inc. | Flash memory device having a graded composition, high dielectric constant gate insulator |
| US7148099B2 (en) * | 2004-06-24 | 2006-12-12 | Intel Corporation | Reducing the dielectric constant of a portion of a gate dielectric |
| KR100642898B1 (en) * | 2004-07-21 | 2006-11-03 | 에스티마이크로일렉트로닉스 엔.브이. | Transistor of semiconductor device and mathod for manufacturing the same |
| US7301185B2 (en) * | 2004-11-29 | 2007-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | High-voltage transistor device having an interlayer dielectric etch stop layer for preventing leakage and improving breakdown voltage |
| US7071047B1 (en) * | 2005-01-28 | 2006-07-04 | International Business Machines Corporation | Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions |
| US7745296B2 (en) * | 2005-06-08 | 2010-06-29 | Globalfoundries Inc. | Raised source and drain process with disposable spacers |
| US20070120199A1 (en) * | 2005-11-30 | 2007-05-31 | Advanced Micro Devices, Inc. | Low resistivity compound refractory metal silicides with high temperature stability |
| CN100435350C (en) * | 2006-01-25 | 2008-11-19 | 南京大学 | High-dielectric coefficient grid dielectric material titanium aluminate film and preparing method thereof |
| US20070224745A1 (en) * | 2006-03-21 | 2007-09-27 | Hui-Chen Chang | Semiconductor device and fabricating method thereof |
| US7368393B2 (en) * | 2006-04-20 | 2008-05-06 | International Business Machines Corporation | Chemical oxide removal of plasma damaged SiCOH low k dielectrics |
| US7407890B2 (en) * | 2006-04-21 | 2008-08-05 | International Business Machines Corporation | Patterning sub-lithographic features with variable widths |
| US20080079084A1 (en) * | 2006-09-28 | 2008-04-03 | Micron Technology, Inc. | Enhanced mobility MOSFET devices |
| WO2009012536A1 (en) * | 2007-07-20 | 2009-01-29 | Interuniversitair Microelektronica Centrum | Damascene contacts on iii-v cmos devices |
| US7812370B2 (en) * | 2007-07-25 | 2010-10-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tunnel field-effect transistor with narrow band-gap channel and strong gate coupling |
| US7674669B2 (en) * | 2007-09-07 | 2010-03-09 | Micron Technology, Inc. | FIN field effect transistor |
| US7745295B2 (en) * | 2007-11-26 | 2010-06-29 | Micron Technology, Inc. | Methods of forming memory cells |
| US7834345B2 (en) * | 2008-09-05 | 2010-11-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tunnel field-effect transistors with superlattice channels |
| US8587075B2 (en) * | 2008-11-18 | 2013-11-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tunnel field-effect transistor with metal source |
| JP2010245366A (en) * | 2009-04-08 | 2010-10-28 | Fujifilm Corp | Electronic device, method of manufacturing the same, and display device |
| US8093117B2 (en) * | 2010-01-14 | 2012-01-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a metal gate |
| US8535998B2 (en) * | 2010-03-09 | 2013-09-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a gate structure |
| CN101864556A (en) * | 2010-05-14 | 2010-10-20 | 南京大学 | High dielectric coefficient titanium-aluminum oxide film and preparation method and application thereof |
| CN102280375B (en) * | 2010-06-08 | 2013-10-16 | 中国科学院微电子研究所 | Manufacturing method of laminated metal gate structure in gate first process |
| CN102456558B (en) * | 2010-10-25 | 2013-10-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing high dielectric constant medium-metal gate |
| CN102569076B (en) * | 2010-12-08 | 2015-06-10 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN102800631B (en) * | 2011-05-26 | 2014-09-03 | 中芯国际集成电路制造(上海)有限公司 | Method for forming complementary metal oxide semiconductor (CMOS) transistor |
| CN102916038B (en) * | 2011-08-04 | 2015-12-16 | 北大方正集团有限公司 | A kind of field-effect transistor and manufacture method thereof |
| US8445345B2 (en) | 2011-09-08 | 2013-05-21 | International Business Machines Corporation | CMOS structure having multiple threshold voltage devices |
| KR20130127257A (en) * | 2012-05-14 | 2013-11-22 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the device |
| JP5955658B2 (en) * | 2012-06-15 | 2016-07-20 | 株式会社Ｓｃｒｅｅｎホールディングス | Heat treatment method and heat treatment apparatus |
| US8941177B2 (en) | 2012-06-27 | 2015-01-27 | International Business Machines Corporation | Semiconductor devices having different gate oxide thicknesses |
| US9385044B2 (en) * | 2012-12-31 | 2016-07-05 | Texas Instruments Incorporated | Replacement gate process |
| RU2531122C1 (en) * | 2013-04-18 | 2014-10-20 | Открытое Акционерное Общество "Воронежский Завод Полупроводниковых Приборов-Сборка" | Manufacturing method of semiconductor device |
| US9728623B2 (en) * | 2013-06-19 | 2017-08-08 | Varian Semiconductor Equipment Associates, Inc. | Replacement metal gate transistor |
| US10084060B2 (en) * | 2014-08-15 | 2018-09-25 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method of the same |
| US9812577B2 (en) * | 2014-09-05 | 2017-11-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure and fabricating method thereof |
| CN104465323A (en) * | 2014-11-28 | 2015-03-25 | 上海华力微电子有限公司 | Method for reducing key dimension of active region |
| US9276013B1 (en) * | 2015-01-21 | 2016-03-01 | International Business Machines Corporation | Integrated formation of Si and SiGe fins |
| US9656093B2 (en) | 2015-07-16 | 2017-05-23 | Boston Scientific Neuromodulation Corporation | Systems and methods for making and using connector contact arrays for electrical stimulation systems |
| US10232169B2 (en) | 2015-07-23 | 2019-03-19 | Boston Scientific Neuromodulation Corporation | Burr hole plugs for electrical stimulation systems and methods of making and using |
| US9956394B2 (en) | 2015-09-10 | 2018-05-01 | Boston Scientific Neuromodulation Corporation | Connectors for electrical stimulation systems and methods of making and using |
| US9986989B2 (en) | 2016-01-08 | 2018-06-05 | Boston Scientific Neuromodulation Corporation | Surgical retractor for implanting leads and methods of making and using |
| US10342983B2 (en) | 2016-01-14 | 2019-07-09 | Boston Scientific Neuromodulation Corporation | Systems and methods for making and using connector contact arrays for electrical stimulation systems |
| WO2017136346A1 (en) | 2016-02-05 | 2017-08-10 | Boston Scientfic Neuromodulation Corporation | Implantable optical stimulation lead |
| US10814127B2 (en) | 2016-02-05 | 2020-10-27 | Boston Scientific Neuromodulation Corporation | Slotted sleeve neurostimulation device |
| US10485969B2 (en) | 2016-02-19 | 2019-11-26 | Boston Scientific Neuromodulation Corporation | Electrical stimulation cuff devices and systems |
| WO2017151438A1 (en) | 2016-02-29 | 2017-09-08 | Boston Scientific Neuromodulation Corporation | Lead anchor for an electrical stimulation system |
| US10124161B2 (en) | 2016-03-31 | 2018-11-13 | Boston Scientific Neuromodulation Corporation | Neurostimulation lead with conductive elements and methods for making the same |
| EP3429679B1 (en) | 2016-05-17 | 2022-11-23 | Boston Scientific Neuromodulation Corporation | Systems for anchoring a lead for neurostimulation of a target anatomy |
| US10493269B2 (en) | 2016-06-02 | 2019-12-03 | Boston Scientific Neuromodulation Corporation | Leads for electrostimulation of peripheral nerves and other targets |
| US10201713B2 (en) | 2016-06-20 | 2019-02-12 | Boston Scientific Neuromodulation Corporation | Threaded connector assembly and methods of making and using the same |
| US10307602B2 (en) | 2016-07-08 | 2019-06-04 | Boston Scientific Neuromodulation Corporation | Threaded connector assembly and methods of making and using the same |
| US10709888B2 (en) | 2016-07-29 | 2020-07-14 | Boston Scientific Neuromodulation Corporation | Systems and methods for making and using an electrical stimulation system for peripheral nerve stimulation |
| WO2018022455A1 (en) | 2016-07-29 | 2018-02-01 | Boston Scientific Neuromodulation Corporation | Connector assembly with contact rings comprising biased ball-spring contacts |
| US10543374B2 (en) | 2016-09-30 | 2020-01-28 | Boston Scientific Neuromodulation Corporation | Connector assemblies with bending limiters for electrical stimulation systems and methods of making and using same |
| US10625072B2 (en) | 2016-10-21 | 2020-04-21 | Boston Scientific Neuromodulation Corporation | Electrical stimulation methods with optical observation and devices therefor |
| US10905883B2 (en) | 2016-12-02 | 2021-02-02 | Boston Scientific Neuromodulation Corporation | Methods and systems for selecting stimulation parameters for electrical stimulation devices |
| US10905871B2 (en) | 2017-01-27 | 2021-02-02 | Boston Scientific Neuromodulation Corporation | Lead assemblies with arrangements to confirm alignment between terminals and contacts |
| WO2018160495A1 (en) | 2017-02-28 | 2018-09-07 | Boston Scientific Neuromodulation Corporation | Toolless connector for latching stimulation leads and methods of making and using |
| US10709886B2 (en) | 2017-02-28 | 2020-07-14 | Boston Scientific Neuromodulation Corporation | Electrical stimulation leads and systems with elongate anchoring elements and methods of making and using |
| US10835739B2 (en) | 2017-03-24 | 2020-11-17 | Boston Scientific Neuromodulation Corporation | Electrical stimulation leads and systems with elongate anchoring elements and methods of making and using |
| US10603499B2 (en) | 2017-04-07 | 2020-03-31 | Boston Scientific Neuromodulation Corporation | Tapered implantable lead and connector interface and methods of making and using |
| WO2019005684A1 (en) | 2017-06-26 | 2019-01-03 | Boston Scientific Neuromodulation Corporation | Systems and methods for making and using implantable optical stimulation leads and assemblies |
| EP3645110B1 (en) | 2017-06-26 | 2022-07-13 | Boston Scientific Neuromodulation Corporation | Systems for visualizing and controlling optogenetic stimulation using optical stimulation systems |
| EP3658228A1 (en) | 2017-07-25 | 2020-06-03 | Boston Scientific Neuromodulation Corporation | Systems and methods for making and using an enhanced connector of an electrical stimulation system |
| US11045656B2 (en) | 2017-09-15 | 2021-06-29 | Boston Scientific Neuromodulation Corporation | Biased lead connector for operating room cable assembly and methods of making and using |
| US10639485B2 (en) | 2017-09-15 | 2020-05-05 | Boston Scientific Neuromodulation Corporation | Actuatable lead connector for an operating room cable assembly and methods of making and using |
| US11139603B2 (en) | 2017-10-03 | 2021-10-05 | Boston Scientific Neuromodulation Corporation | Connectors with spring contacts for electrical stimulation systems and methods of making and using same |
| JP2021502215A (en) | 2017-11-13 | 2021-01-28 | ボストン サイエンティフィック ニューロモデュレイション コーポレイション | Systems and methods for manufacturing and using flat control modules for electrical stimulation systems |
| US10229983B1 (en) * | 2017-11-16 | 2019-03-12 | International Business Machines Corporation | Methods and structures for forming field-effect transistors (FETs) with low-k spacers |
| EP3737464A1 (en) | 2018-01-11 | 2020-11-18 | Boston Scientific Neuromodulation Corporation | Methods and systems for stimulation for glial modulation |
| WO2019143574A1 (en) | 2018-01-16 | 2019-07-25 | Boston Scientific Neuromodulation Corporation | An electrical stimulation system with a case-neutral battery and a control module for such a system |
| US11103712B2 (en) | 2018-01-16 | 2021-08-31 | Boston Scientific Neuromodulation Corporation | Connector assemblies with novel spacers for electrical stimulation systems and methods of making and using same |
| US11058870B2 (en) | 2018-03-09 | 2021-07-13 | Boston Scientific Neuromodulation Corporation | Burr hole plugs for electrical stimulation systems and methods of making and using |
| US11013913B2 (en) | 2018-03-16 | 2021-05-25 | Boston Scientific Neuromodulation Corporation | Kits and methods for securing a burr hole plugs for stimulation systems |
| EP3768381B1 (en) | 2018-03-23 | 2023-03-08 | Boston Scientific Neuromodulation Corporation | An optical stimulation system with automated monitoring |
| WO2019183078A1 (en) | 2018-03-23 | 2019-09-26 | Boston Scientific Neuromodulation Corporation | Optical stimulation systems using therapy cycling and methods of using |
| WO2019183054A1 (en) | 2018-03-23 | 2019-09-26 | Boston Scientific Neuromodulation Corporation | Optical stimulation systems with calibration and methods of making and using |
| US11524174B2 (en) | 2018-03-23 | 2022-12-13 | Boston Scientific Neuromodulation Corporation | Optical stimulation system with on-demand monitoring and methods of making and using |
| US11052259B2 (en) | 2018-05-11 | 2021-07-06 | Boston Scientific Neuromodulation Corporation | Connector assembly for an electrical stimulation system and methods of making and using |
| WO2020014083A1 (en) | 2018-07-09 | 2020-01-16 | Boston Scientific Neuromodulation Corporation | Directional electrical stimulation leads and systems for spinal cord stimulation |
| US11224743B2 (en) | 2018-09-21 | 2022-01-18 | Boston Scientific Neuromodulation Corporation | Systems and methods for making and using modular leads for electrical stimulation systems |
| WO2020102039A1 (en) | 2018-11-16 | 2020-05-22 | Boston Scientific Neuromodulation Corporation | An optical stimulation system with on-demand monitoring and methods of making |
| US11152384B2 (en) * | 2019-01-15 | 2021-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Boundary structure for embedded memory |
| EP3883644A2 (en) | 2019-02-19 | 2021-09-29 | Boston Scientific Neuromodulation Corporation | Lead introducers and systems and methods including the lead introducers |
| US11357992B2 (en) | 2019-05-03 | 2022-06-14 | Boston Scientific Neuromodulation Corporation | Connector assembly for an electrical stimulation system and methods of making and using |
| EP4168110A1 (en) | 2020-09-04 | 2023-04-26 | Boston Scientific Neuromodulation Corporation | Stimulation systems with a lens arrangement for light coupling and methods of making and using |
| EP4240472A1 (en) | 2021-01-19 | 2023-09-13 | Boston Scientific Neuromodulation Corporation | Electrical stimulation cuff devices and systems with directional electrode configurations |
| EP4288145A1 (en) | 2021-04-08 | 2023-12-13 | Boston Scientific Neuromodulation Corporation | Photobiomodulation system and delivery device |
| AU2022277556A1 (en) | 2021-05-21 | 2023-11-02 | Boston Scientific Neuromodulation Corporation | Electrical stimulation cuff devices and systems with helical arrangement of electrodes |
| WO2024044050A1 (en) | 2022-08-22 | 2024-02-29 | Boston Scientific Neuromodulation Corporation | Implantable photobiomodulation systems employing thermal monitoring or control and methods of making and using |
| WO2024044048A1 (en) | 2022-08-22 | 2024-02-29 | Boston Scientific Neuromodulation Corporation | Photobiomodulation systems including an electrode disposed on or over a light emitter and methods of making and using |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100198674B1 (en) * | 1996-10-18 | 1999-06-15 | 구본준 | Manufacture of semiconductor device |
| US5872038A (en) * | 1997-01-08 | 1999-02-16 | Advanced Micro Devices | Semiconductor device having an elevated active region formed in an oxide trench and method of manufacture thereof |
| US6218276B1 (en) * | 1997-12-22 | 2001-04-17 | Lsi Logic Corporation | Silicide encapsulation of polysilicon gate and interconnect |
| TW454254B (en) * | 1998-05-20 | 2001-09-11 | Winbond Electronics Corp | Method to manufacture devices with elevated source/drain |
| US6140677A (en) * | 1998-06-26 | 2000-10-31 | Advanced Micro Devices, Inc. | Semiconductor topography for a high speed MOSFET having an ultra narrow gate |
| US6008095A (en) * | 1998-08-07 | 1999-12-28 | Advanced Micro Devices, Inc. | Process for formation of isolation trenches with high-K gate dielectrics |
| US6188110B1 (en) * | 1998-10-15 | 2001-02-13 | Advanced Micro Devices | Integration of isolation with epitaxial growth regions for enhanced device formation |
| US6087231A (en) * | 1999-08-05 | 2000-07-11 | Advanced Micro Devices, Inc. | Fabrication of dual gates of field transistors with prevention of reaction between the gate electrode and the gate dielectric with a high dielectric constant |
| US6300172B1 (en) * | 1999-10-01 | 2001-10-09 | Chartered Semiconductor Manufacturing Ltd. | Method of field isolation in silicon-on-insulator technology |
-
2000
- 2000-02-14 US US09/503,926 patent/US6271094B1/en not_active Expired - Lifetime
- 2000-10-25 TW TW089122492A patent/TW478162B/en not_active IP Right Cessation
-
2001
- 2001-01-25 JP JP2001017484A patent/JP3529732B2/en not_active Expired - Fee Related
- 2001-01-31 KR KR1020010004445A patent/KR100354115B1/en not_active IP Right Cessation
- 2001-02-01 SG SG200100583A patent/SG90231A1/en unknown
- 2001-02-13 CN CNB011029927A patent/CN1177357C/en not_active Expired - Lifetime
- 2001-05-25 US US09/866,239 patent/US6353249B1/en not_active Expired - Fee Related
Cited By (66)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6614081B2 (en) * | 2000-04-05 | 2003-09-02 | Nec Electronics Corporation | High-performance MOS transistor of LDD structure having a gate insulating film with a nitride central portion and oxide end portions |
| US20040026752A1 (en) * | 2000-04-05 | 2004-02-12 | Nec Electronics Corporation | High-performance MOS transistor of LDD structure having a gate insulating film with a nitride central portion and oxide end portions |
| US6794258B2 (en) | 2000-04-05 | 2004-09-21 | Nec Electronics Corporation | High-performance MOS transistor of LDD structure having a gate insulating film with a nitride central portion and oxide end portions |
| WO2003044833A3 (en) * | 2001-11-20 | 2003-11-27 | Ibm | Method for limiting divot formation in post shallow trench isolation processes |
| US6541351B1 (en) * | 2001-11-20 | 2003-04-01 | International Business Machines Corporation | Method for limiting divot formation in post shallow trench isolation processes |
| US20040192018A1 (en) * | 2001-12-04 | 2004-09-30 | Intel Corporation | Polysilicon opening polish |
| US7144816B2 (en) * | 2001-12-04 | 2006-12-05 | Intel Corporation | Polysilicon opening polish |
| US8105466B2 (en) | 2002-03-16 | 2012-01-31 | Springworks, Llc | Biased pulse DC reactive sputtering of oxide films |
| US20060057304A1 (en) * | 2002-03-16 | 2006-03-16 | Symmorphix, Inc. | Biased pulse DC reactive sputtering of oxide films |
| US7964058B2 (en) | 2003-03-17 | 2011-06-21 | Tokyo Electron Limited | Processing system and method for chemically treating a substrate |
| US7079760B2 (en) | 2003-03-17 | 2006-07-18 | Tokyo Electron Limited | Processing system and method for thermally treating a substrate |
| US20040184792A1 (en) * | 2003-03-17 | 2004-09-23 | Tokyo Electron Limited | Processing system and method for thermally treating a substrate |
| US20110204029A1 (en) * | 2003-03-17 | 2011-08-25 | Tokyo Electron Limited | Processing system and method for chemically treating a substrate |
| US20040185670A1 (en) * | 2003-03-17 | 2004-09-23 | Tokyo Electron Limited | Processing system and method for treating a substrate |
| US7214274B2 (en) | 2003-03-17 | 2007-05-08 | Tokyo Electron Limited | Method and apparatus for thermally insulating adjacent temperature controlled processing chambers |
| US20050211386A1 (en) * | 2003-03-17 | 2005-09-29 | Tokyo Electron Limited | Processing system and method for chemically treating a substrate |
| US6951821B2 (en) | 2003-03-17 | 2005-10-04 | Tokyo Electron Limited | Processing system and method for chemically treating a substrate |
| US20040182324A1 (en) * | 2003-03-17 | 2004-09-23 | Tokyo Electron Limited | Method and apparatus for thermally insulating adjacent temperature controlled processing chambers |
| US7029536B2 (en) | 2003-03-17 | 2006-04-18 | Tokyo Electron Limited | Processing system and method for treating a substrate |
| US20040182417A1 (en) * | 2003-03-17 | 2004-09-23 | Tokyo Electron Limited | Processing system and method for chemically treating a substrate |
| US7462564B2 (en) | 2003-03-17 | 2008-12-09 | Tokyo Electron Limited | Processing system and method for treating a substrate |
| US20060134919A1 (en) * | 2003-03-17 | 2006-06-22 | Tokyo Electron Limited | Processing system and method for treating a substrate |
| US20040191998A1 (en) * | 2003-03-28 | 2004-09-30 | International Business Machines Corporation | Preserving teos hard mask using cor for raised source-drain including removable/disposable spacer |
| US8728285B2 (en) | 2003-05-23 | 2014-05-20 | Demaray, Llc | Transparent conductive oxides |
| US20050000794A1 (en) * | 2003-05-23 | 2005-01-06 | Demaray Richard E. | Transparent conductive oxides |
| US7045422B2 (en) | 2003-05-28 | 2006-05-16 | Infineon Technologies Ag | Semiconductor gate structure and method for fabricating a semiconductor gate structure |
| DE10324448B3 (en) * | 2003-05-28 | 2005-02-03 | Infineon Technologies Ag | Method for producing a semiconductor gate structure |
| US20040262697A1 (en) * | 2003-05-28 | 2004-12-30 | Infineon Technologies | Semiconductor gate structure and method for fabricating a semiconductor gate structure |
| US20050104095A1 (en) * | 2003-11-13 | 2005-05-19 | International Business Machines Corporation | Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance |
| US7307323B2 (en) | 2003-11-13 | 2007-12-11 | International Business Machines Corporation | Structure to use an etch resistant liner on transistor gate structure to achieve high device performance |
| US20080036017A1 (en) * | 2003-11-13 | 2008-02-14 | Ng Hung Y | Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance |
| US7064027B2 (en) | 2003-11-13 | 2006-06-20 | International Business Machines Corporation | Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance |
| US8636876B2 (en) | 2004-12-08 | 2014-01-28 | R. Ernest Demaray | Deposition of LiCoO2 |
| US20070170711A1 (en) * | 2006-01-25 | 2007-07-26 | Bechtel Travis D | Power release and locking adjustable steering column apparatus and method |
| US8343280B2 (en) | 2006-03-28 | 2013-01-01 | Tokyo Electron Limited | Multi-zone substrate temperature control system and method of operating |
| US9115429B2 (en) | 2006-06-22 | 2015-08-25 | Tokyo Electron Limited | Dry non-plasma treatment system and method of using |
| US8828185B2 (en) | 2006-06-22 | 2014-09-09 | Tokyo Electron Limited | Dry non-plasma treatment system and method of using |
| US20070298972A1 (en) * | 2006-06-22 | 2007-12-27 | Tokyo Electron Limited | A dry non-plasma treatment system and method of using |
| US20100237046A1 (en) * | 2006-06-22 | 2010-09-23 | Tokyo Electron Limited | Dry non-plasma treatment system and method of using |
| US11745202B2 (en) | 2006-06-22 | 2023-09-05 | Tokyo Electron Limited | Dry non-plasma treatment system |
| US7718032B2 (en) | 2006-06-22 | 2010-05-18 | Tokyo Electron Limited | Dry non-plasma treatment system and method of using |
| US20090315089A1 (en) * | 2006-08-25 | 2009-12-24 | Ahn Kie Y | Atomic layer deposited barium strontium titanium oxide films |
| US9202686B2 (en) | 2006-08-25 | 2015-12-01 | Micron Technology, Inc. | Electronic devices including barium strontium titanium oxide films |
| US20080048225A1 (en) * | 2006-08-25 | 2008-02-28 | Micron Technology, Inc. | Atomic layer deposited barium strontium titanium oxide films |
| US8581352B2 (en) | 2006-08-25 | 2013-11-12 | Micron Technology, Inc. | Electronic devices including barium strontium titanium oxide films |
| US20080179667A1 (en) * | 2006-10-25 | 2008-07-31 | International Business Machines Corporation | Sub-lithographic gate length transistor using self-assembling polymers |
| US7786527B2 (en) | 2006-10-25 | 2010-08-31 | International Business Machines Corporation | Sub-lithographic gate length transistor using self-assembling polymers |
| US7384852B2 (en) * | 2006-10-25 | 2008-06-10 | International Business Machines Corporation | Sub-lithographic gate length transistor using self-assembling polymers |
| US20080099845A1 (en) * | 2006-10-25 | 2008-05-01 | International Business Machines Corporation | Sub-lithographic gate length transistor using self-assembling polymers |
| US20080222644A1 (en) * | 2007-03-05 | 2008-09-11 | International Business Machines Corporation | Risk-modulated proactive data migration for maximizing utility in storage systems |
| US20080222218A1 (en) * | 2007-03-05 | 2008-09-11 | Richards Elizabeth S | Risk-modulated proactive data migration for maximizing utility in storage systems |
| US20090011563A1 (en) * | 2007-03-29 | 2009-01-08 | Micron Technology, Inc. | Fabrication of Self-Aligned Gallium Arsenide Mosfets Using Damascene Gate Methods |
| US7955917B2 (en) | 2007-03-29 | 2011-06-07 | Micron Technology, Inc. | Fabrication of self-aligned gallium arsenide MOSFETS using damascene gate methods |
| US7435636B1 (en) | 2007-03-29 | 2008-10-14 | Micron Technology, Inc. | Fabrication of self-aligned gallium arsenide MOSFETs using damascene gate methods |
| DE102007046849B4 (en) * | 2007-09-29 | 2014-11-06 | Advanced Micro Devices, Inc. | Method of making large-gate-gate structures after transistor fabrication |
| US20090087974A1 (en) * | 2007-09-29 | 2009-04-02 | Andrew Waite | Method of forming high-k gate electrode structures after transistor fabrication |
| US8323410B2 (en) | 2008-07-31 | 2012-12-04 | Tokyo Electron Limited | High throughput chemical treatment system and method of operating |
| US8115140B2 (en) | 2008-07-31 | 2012-02-14 | Tokyo Electron Limited | Heater assembly for high throughput chemical treatment system |
| US8303715B2 (en) | 2008-07-31 | 2012-11-06 | Tokyo Electron Limited | High throughput thermal treatment system and method of operating |
| US20100025367A1 (en) * | 2008-07-31 | 2010-02-04 | Tokyo Electron Limited | High throughput chemical treatment system and method of operating |
| US20100025368A1 (en) * | 2008-07-31 | 2010-02-04 | Tokyo Electron Limited | High throughput thermal treatment system and method of operating |
| US8287688B2 (en) | 2008-07-31 | 2012-10-16 | Tokyo Electron Limited | Substrate support for high throughput chemical treatment system |
| US20100025389A1 (en) * | 2008-07-31 | 2010-02-04 | Tokyo Electron Limited | Heater assembly for high throughput chemical treatment system |
| US8303716B2 (en) | 2008-07-31 | 2012-11-06 | Tokyo Electron Limited | High throughput processing system for chemical treatment and thermal treatment and method of operating |
| US20120178231A1 (en) * | 2011-01-12 | 2012-07-12 | Samsung Electronics Co., Ltd. | Methods for fabricating a metal silicide layer and semiconductor devices using the same |
| US10319427B2 (en) | 2017-06-09 | 2019-06-11 | Samsung Electronics Co., Ltd. | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3529732B2 (en) | 2004-05-24 |
| KR20010082029A (en) | 2001-08-29 |
| US6271094B1 (en) | 2001-08-07 |
| JP2001267565A (en) | 2001-09-28 |
| CN1309419A (en) | 2001-08-22 |
| SG90231A1 (en) | 2002-07-23 |
| TW478162B (en) | 2002-03-01 |
| CN1177357C (en) | 2004-11-24 |
| KR100354115B1 (en) | 2002-09-28 |
| US6353249B1 (en) | 2002-03-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6271094B1 (en) | Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance | |
| US6905941B2 (en) | Structure and method to fabricate ultra-thin Si channel devices | |
| US6512266B1 (en) | Method of fabricating SiO2 spacers and annealing caps | |
| US8686535B2 (en) | Trench isolation implantation | |
| US7041538B2 (en) | Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOS | |
| US10943901B2 (en) | Semiconductor device and method | |
| US6440808B1 (en) | Damascene-gate process for the fabrication of MOSFET devices with minimum poly-gate depletion, silicided source and drain junctions, and low sheet resistance gate-poly | |
| US6245619B1 (en) | Disposable-spacer damascene-gate process for SUB 0.05 μm MOS devices | |
| US11164959B2 (en) | VFET devices with ILD protection | |
| US20110042729A1 (en) | Method for improving selectivity of epi process | |
| US10453741B2 (en) | Method for forming semiconductor device contact | |
| US7247569B2 (en) | Ultra-thin Si MOSFET device structure and method of manufacture | |
| US11515165B2 (en) | Semiconductor device and method | |
| US6335248B1 (en) | Dual workfunction MOSFETs with borderless diffusion contacts for high-performance embedded DRAM technology | |
| US6867084B1 (en) | Gate structure and method of forming the gate dielectric with mini-spacer | |
| US6664150B2 (en) | Active well schemes for SOI technology | |
| US6184114B1 (en) | MOS transistor formation | |
| TWI290370B (en) | Multiple gate field effect transistor structure | |
| US6544874B2 (en) | Method for forming junction on insulator (JOI) structure | |
| US6436746B1 (en) | Transistor having an improved gate structure and method of construction | |
| US11935920B2 (en) | Semiconductor device and method | |
| US20220231023A1 (en) | Finfet device and method | |
| JP2005093816A (en) | Semiconductor device manufacturing method and the semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Fee payment |
Year of fee payment: 4 |
|
| FPAY | Fee payment |
Year of fee payment: 8 |
|
| REMI | Maintenance fee reminder mailed | ||
| LAPS | Lapse for failure to pay maintenance fees | ||
| STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
| FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20140305 |
|
| AS | Assignment |
Owner name: ELPIS TECHNOLOGIES INC., CANADA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:052620/0961 Effective date: 20200306 |