US20010049186A1 - Method for establishing ultra-thin gate insulator using anneal in ammonia - Google Patents

Method for establishing ultra-thin gate insulator using anneal in ammonia Download PDF

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US20010049186A1
US20010049186A1 US09/479,506 US47950600A US2001049186A1 US 20010049186 A1 US20010049186 A1 US 20010049186A1 US 47950600 A US47950600 A US 47950600A US 2001049186 A1 US2001049186 A1 US 2001049186A1
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substrate
ammonia
base film
film
gate insulator
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US6444555B2 (en
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Effiong Ibok
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GlobalFoundries Inc
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Priority to US09/479,506 priority Critical patent/US6444555B2/en
Priority to TW089125288A priority patent/TW556273B/en
Priority to PCT/US2000/033071 priority patent/WO2001043177A1/en
Priority to CN00816802A priority patent/CN1423832A/en
Priority to JP2001543768A priority patent/JP2003516633A/en
Priority to EP00983955A priority patent/EP1236225A1/en
Priority to KR1020027007313A priority patent/KR100702694B1/en
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Publication of US6444555B2 publication Critical patent/US6444555B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Definitions

  • the present invention relates to the fabrication of semiconductor devices, and more particularly to establishing field effect transistor (FET) gate insulators.
  • FET field effect transistor
  • Semiconductor chips or wafers are used in many applications, including as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
  • a gate is formed on a semiconductor substrate, with the gate being insulated from the substrate by a very thin dielectric layer, referred to as the “gate oxide” or “gate insulator”. As the scale of semiconductor devices decreases, the thickness of the gate insulator layer likewise decreases.
  • the gate insulator can be become so thin that otherwise relatively small encroachments into the gate insulator layer by sub-oxides from the substrate and from adjacent polysilicon connector electrodes can reduce the insulating ability of the gate insulator layer. This poses severe problems because under these circumstances, even very minor defects in the substrate can create electron leakage paths through the gate insulator, leading to catastrophic failure of the transistor.
  • the present invention recognizes that it is desirable to provide a gate insulator layer that can be made very thin as appropriate for very small-scale transistors while retaining sufficient electrical insulation properties to adequately function as a gate insulator, and while retaining sufficient physical thickness to facilitate device integration, without degrading performance vis-a-vis oxide insulators.
  • a method for making a semiconductor device includes providing a semiconductor substrate, and establishing an oxide base film on the substrate.
  • the substrate is annealed, preferably in ammonia at temperatures up to eleven hundred degrees Celsius (1100° C.), after which FET gates are formed on portions of the film.
  • the preferred base film defines a thickness of no more than twenty four Angstroms (24 ⁇ ).
  • the electrical resistance of the base film is reduced to that of a conventional oxide film having a thickness of only 20 ⁇ , such that the electrical resistance of the film is advantageously reduced while the physical thickness remains sufficiently thick to inhibit undesired tunneling, resulting in a relatively lower standby current for a relatively higher drive current and capacitance.
  • FIG. 1 is a flow chart of the manufacturing process
  • FIG. 2 is a side view of the device after forming the base film on the substrate
  • FIG. 3 is a side view of the device after annealing the base film.
  • FIG. 4 is a side view of the device after forming the FET gate stacks on the nitride film.
  • a semiconductor substrate 12 such as Silicon is provided, and then at block 14 a thin Oxide base film 16 is grown on the substrate 12 in accordance with oxide film formation principles known in the art, in direct contact with the substrate 12 .
  • the thickness “t” of the base film 16 is no more than twenty four Angstroms (24 ⁇ ).
  • the substrate 12 with film 16 is annealed in situ in ammonia (NH 3 ) at a temperature of up to eleven hundred degrees Celsius (1100° C.) to establish a Nitrogen concentration in the base film 16 .
  • the Nitrogen is represented by the dots 19 .
  • the electrical resistance of the base film 16 is reduced to that of a conventional oxide film having a thickness of only 20 ⁇ , such that the electrical resistance of the film 16 advantageously is reduced while the physical thickness remains sufficiently thick to inhibit undesired tunneling, resulting in a relatively lower standby current for a relatively higher drive current and capacitance.
  • a polysilicon-based field effect transistor (FET) stack 28 is formed on the film 16 in accordance with FET gate stack deposition and patterning principles known in the art. After forming and patterning the FET stacks 28 , the process is completed by forming FET sources and drains 36 , 38 using conventional principles, and contacts, interconnects, and FET to FET insulation are likewise conventionally undertaken.
  • FET field effect transistor
  • the ammonia anneal of the base film reduces the equivalent electrical thickness of the base film.
  • the film advantageously behaves electrically like a film that is only 20 ⁇ thick. This in turn advantageously decreases subsequent electron tunneling resulting in a lower standby current for higher drive current and capacitance, compared to a film not annealed in ammonia.

Abstract

A method for fabricating a semiconductor device including a silicon substrate includes forming a thin Oxide base film on a substrate, and then annealing the substrate in ammonia. FET gates are then conventionally formed over the gate insulator. The resultant gate insulator is electrically insulative without degrading performance with respect to a conventional gate oxide insulator.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application claims the benefit of U.S. Provisional Application No. 60/169,540, filed on Dec. 7, 1999 and entitled “METHOD FOR ESTABLISHING ULTRA-THIN GATE INSULATOR USING ANNEAL IN AMMONIA”.[0001]
    • TECHNICAL FIELD
  • The present invention relates to the fabrication of semiconductor devices, and more particularly to establishing field effect transistor (FET) gate insulators. [0002]
    • BACKGROUND OF THE INVENTION
  • Semiconductor chips or wafers are used in many applications, including as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices. [0003]
  • It can readily be appreciated that it is important to electrically isolate various components of an integrated circuit from each other, to ensure proper circuit operation. As one example, in a transistor, a gate is formed on a semiconductor substrate, with the gate being insulated from the substrate by a very thin dielectric layer, referred to as the “gate oxide” or “gate insulator”. As the scale of semiconductor devices decreases, the thickness of the gate insulator layer likewise decreases. [0004]
  • As recognized herein, at very small scales, the gate insulator can be become so thin that otherwise relatively small encroachments into the gate insulator layer by sub-oxides from the substrate and from adjacent polysilicon connector electrodes can reduce the insulating ability of the gate insulator layer. This poses severe problems because under these circumstances, even very minor defects in the substrate can create electron leakage paths through the gate insulator, leading to catastrophic failure of the transistor. [0005]
  • To circumvent this problem, alternatives to traditional gate oxide materials, such as high-k dielectric materials including nitrides and oxynitrides that can be made very thin and still retain good insulating properties, have been proposed. Unfortunately, it is thought that these materials can degrade the performance of the transistor. Nitride, in particular, has been considered undesirable because it promotes unwanted leakage of electrons through the gate insulator layer. [0006]
  • Furthermore, as the gate insulator layer becomes very thin, e.g., on the order of nineteen Angstroms (19 Å), device integration becomes highly complicated. Specifically, it is necessary to etch portions of the polysilicon electrodes down to the substrate, but stopping the etch on a very thin, e.g., 19 Å gate insulator layer without pitting the substrate underneath becomes problematic. Accordingly, the present invention recognizes that it is desirable to provide a gate insulator layer that can be made very thin as appropriate for very small-scale transistors while retaining sufficient electrical insulation properties to adequately function as a gate insulator, and while retaining sufficient physical thickness to facilitate device integration, without degrading performance vis-a-vis oxide insulators. [0007]
    • BRIEF SUMMARY OF THE INVENTION
  • A method for making a semiconductor device includes providing a semiconductor substrate, and establishing an oxide base film on the substrate. The substrate is annealed, preferably in ammonia at temperatures up to eleven hundred degrees Celsius (1100° C.), after which FET gates are formed on portions of the film. The preferred base film defines a thickness of no more than twenty four Angstroms (24 Å). However, after annealing the electrical resistance of the base film is reduced to that of a conventional oxide film having a thickness of only 20 Å, such that the electrical resistance of the film is advantageously reduced while the physical thickness remains sufficiently thick to inhibit undesired tunneling, resulting in a relatively lower standby current for a relatively higher drive current and capacitance. [0008]
  • Other features of the present invention are disclosed or apparent in the section entitled “DETAILED DESCRIPTION OF THE INVENTION”. [0009]
    • BRIEF DESCRIPTION OF DRAWINGS
  • For understanding of the present invention, reference is made to the accompanying drawing in the following DETAILED DESCRIPTION OF THE INVENTION. In the drawings: [0010]
  • FIG. 1 is a flow chart of the manufacturing process; [0011]
  • FIG. 2 is a side view of the device after forming the base film on the substrate; [0012]
  • FIG. 3 is a side view of the device after annealing the base film; and [0013]
  • FIG. 4 is a side view of the device after forming the FET gate stacks on the nitride film.[0014]
    • DETAILED DESCRIPTION OF THE INVENTION
  • The principles of the present invention are equally applicable to a wide range of semiconductor and integrated circuit design and manufacture regimens, including but not necessarily limited to the production of non-volatile memory devices. All such implementations are specifically contemplated by the principles of the present intention. [0015]
  • Referring initially to FIGS. 1 and 2, at [0016] block 10 in FIG. 1 a semiconductor substrate 12 (FIG. 2) such as Silicon is provided, and then at block 14 a thin Oxide base film 16 is grown on the substrate 12 in accordance with oxide film formation principles known in the art, in direct contact with the substrate 12. The thickness “t” of the base film 16 is no more than twenty four Angstroms (24 Å).
  • Moving to block [0017] 18 of FIG. 1 and referring to FIG. 3, the substrate 12 with film 16 is annealed in situ in ammonia (NH3) at a temperature of up to eleven hundred degrees Celsius (1100° C.) to establish a Nitrogen concentration in the base film 16. The Nitrogen is represented by the dots 19. In accordance with present principles, after annealing the electrical resistance of the base film 16 is reduced to that of a conventional oxide film having a thickness of only 20 Å, such that the electrical resistance of the film 16 advantageously is reduced while the physical thickness remains sufficiently thick to inhibit undesired tunneling, resulting in a relatively lower standby current for a relatively higher drive current and capacitance.
  • Next, at [0018] block 20 in FIG. 2 and referring now to FIG. 4, a polysilicon-based field effect transistor (FET) stack 28 is formed on the film 16 in accordance with FET gate stack deposition and patterning principles known in the art. After forming and patterning the FET stacks 28, the process is completed by forming FET sources and drains 36, 38 using conventional principles, and contacts, interconnects, and FET to FET insulation are likewise conventionally undertaken.
  • With the above disclosure in mind, the ammonia anneal of the base film reduces the equivalent electrical thickness of the base film. In other words, for a film that is sufficiently thick for the above-mentioned structural considerations, e.g., 24 Å thick, after annealing the film advantageously behaves electrically like a film that is only 20 Å thick. This in turn advantageously decreases subsequent electron tunneling resulting in a lower standby current for higher drive current and capacitance, compared to a film not annealed in ammonia. [0019]
  • The present invention has been particularly shown and described with respect to certain preferred embodiments of features thereof. However, it should be readily apparent to those of ordinary skill in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims. In particular, the use of: alternate layer deposition or forming methodologies; etching technologies; masking methods; lithographic methods, passivation and nitridization techniques; as well as alternative semiconductor designs, as well as the application of the technology disclosed herein to alternate electronic components are all contemplated by the principles of the present invention. The invention disclosed herein may be practiced without any element which is not specifically disclosed herein. The use of the singular in the claims does not mean “only one”, but rather “one or more”, unless otherwise stated in the claims. [0020]

Claims (6)

What is claimed is:
1. A method for making a semiconductor device, comprising:
providing a semiconductor substrate;
establishing an oxide base film on the substrate; then
annealing the substrate in ammonia; then
forming FET gates on portions of the film.
2. The method of
claim 1
, wherein the base film defines a thickness of no more than twenty four Angstroms (24 Å).
3. The method of
claim 2
, wherein the electrical resistance of the base film is reduced as a result of the annealing act.
4. The method of
claim 1
, wherein the annealing act reduces the electrical thickness of the oxide base film.
5. The method of
claim 1
, wherein the annealing act is undertaken at temperatures up to eleven hundred degrees Celsius (1100° C.).
6. The method of
claim 4
, wherein the annealing act decreases subsequent electron tunneling resulting in a lower standby current for higher drive current and capacitance, compared to a film not annealed in ammonia.
US09/479,506 1999-12-07 2000-01-07 Method for establishing ultra-thin gate insulator using anneal in ammonia Expired - Lifetime US6444555B2 (en)

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US09/479,506 US6444555B2 (en) 1999-12-07 2000-01-07 Method for establishing ultra-thin gate insulator using anneal in ammonia
TW089125288A TW556273B (en) 1999-12-07 2000-11-29 Method for establishing ultra-thin gate insulator using anneal in ammonia
KR1020027007313A KR100702694B1 (en) 1999-12-07 2000-12-05 A method for making a semiconductor device having an ultra-thin insulator for inhibiting tunneling effects
CN00816802A CN1423832A (en) 1999-12-07 2000-12-05 Method for establishing ultra-thin gate insulator using anneal in ammonia
JP2001543768A JP2003516633A (en) 1999-12-07 2000-12-05 A method for establishing ultra-thin gate insulators using annealing in ammonia
EP00983955A EP1236225A1 (en) 1999-12-07 2000-12-05 Method for establishing ultra-thin gate insulator using anneal in ammonia
PCT/US2000/033071 WO2001043177A1 (en) 1999-12-07 2000-12-05 Method for establishing ultra-thin gate insulator using anneal in ammonia

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US16954099P 1999-12-07 1999-12-07
US09/479,506 US6444555B2 (en) 1999-12-07 2000-01-07 Method for establishing ultra-thin gate insulator using anneal in ammonia

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EP (1) EP1236225A1 (en)
JP (1) JP2003516633A (en)
KR (1) KR100702694B1 (en)
CN (1) CN1423832A (en)
TW (1) TW556273B (en)
WO (1) WO2001043177A1 (en)

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TW556273B (en) 2003-10-01
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