US20010013629A1 - Multi-layer gate dielectric - Google Patents

Multi-layer gate dielectric Download PDF

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Publication number
US20010013629A1
US20010013629A1 US09/109,261 US10926198A US2001013629A1 US 20010013629 A1 US20010013629 A1 US 20010013629A1 US 10926198 A US10926198 A US 10926198A US 2001013629 A1 US2001013629 A1 US 2001013629A1
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dielectric
gate
thickness
gate dielectric
dielectric constant
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US09/109,261
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Gang Bai
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Intel Corp
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Intel Corp
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Publication of US20010013629A1 publication Critical patent/US20010013629A1/en
Priority to US12/615,938 priority patent/US8193593B2/en
Priority to US12/976,211 priority patent/US8581353B2/en
Priority to US14/054,778 priority patent/US9412860B2/en
Priority to US15/225,785 priority patent/US20160343824A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the invention relates to integrated circuit devices and more particularly to enhancing dielectric material in those device.
  • the scale of a transistor device requires consideration of the desired performance of the device. For example, one goal may be to increase the current flow in the semiconductor material of the transistor.
  • the current flow is proportional to the voltage applied to the gate electrode and the capacitance seen at the gate:
  • Q is one measure of the current flow
  • C is capacitance
  • V is the voltage applied to the gate electrode
  • V th is the threshold voltage of the device.
  • the capacitance is related to the gate dielectric by the following formula:
  • k ox is the dielectric constant of silicon dioxide (SiO 2 ) and telectrical is the electrical thickness of the gate dielectric.
  • the electrical thickness of the gate dielectric is greater than the actual thickness of the dielectric in most semiconductor devices.
  • the insulative region acts like an extension of the gate dielectric by essentially extending the dielectric into a portion of the channel.
  • the second cause of increase gate dielectric thickness attributable to telectrical is experienced by a similar phenomenon happening in the gate electrode itself.
  • a gate electrode of polysilicon for example, will generally experience a depletion of carriers in the area of the polysilicon near the gate dielectric. Accordingly, the gate dielectric appears to extend into the polysilicon gate electrode.
  • the result of the quantum effect in the channel and a depletion in the polysilicon gate electrode is an electrical thickness (telectrical) of the gate dielectric greater than the actual thickness of the gate dielectric.
  • the magnitude of the channel quantum effect and polysilicon depletion may be estimated or determined for a given technology. Accordingly, the electrical thickness (t electrical ) for a SiO 2 may be calculated and scaled for a given technology.
  • the gate dielectric cannot be too thin as a thin gate dielectric will allow a leakage current from the channel through the gate electrode.
  • the gate dielectric cannot be too thick because such a gate structure may produce an undesirable fringe electric field.
  • the desired electric field at the gate is typically perpendicular to the surface of the semiconductor substrate. Beyond a certain gate dielectric thickness, generally thought to be beyond one-third the lateral width of the gate electrode for a SiO 2 gate dielectric, the electrical field deviates from a perpendicular course and sprays about the gate electrode leading to an undesirable fringe electric field.
  • a transistor gate dielectric is disclosed.
  • the transistor gate dielectric includes a first dielectric material having a first dielectric constant and a second dielectric material having a second dielectric constant different from the first dielectric constant.
  • FIG. 1 is a schematic illustration of a side view of a transistor dielectric having a gate dielectric of a first dielectric material and a second dielectric material.
  • the invention relates to a transistor gate dielectric made up of at least two different dielectric materials.
  • a gate dielectric made up of two different dielectric materials each with its own dielectric constant.
  • the dielectric material nearest the substrate e.g., a semiconductor substrate will have a modest dielectric constant that produces a defect-free interface with the substrate and is stable against oxide formation.
  • the second dielectric material will have a relatively high dielectric constant and be stable in contact with the desired gate material.
  • a gate dielectric can be formed that is scalable for different technology generations, has a low leakage current, and maintains an electric field of the gate perpendicular to the surface of the semiconductor.
  • a transistor gate utilizing the multi-layer gate dielectric is also disclosed.
  • FIG. 1 illustrates an embodiment of the multi-layer gate dielectric of the invention.
  • FIG. 1 shows transistor 100 consisting of gate electrode 110 overlying gate dielectric 140 .
  • Gate electrode 110 and gate dielectric 140 overlie semiconductor substrate 105 such as, for example, a silicon semiconductor substrate. Formed in substrate 105 adjacent transistor gate electrode 110 are diffusion or junction regions 160 .
  • the transistor is isolated from other devices, in this example, by shallow trench isolation structures 150 .
  • Gate dielectric 140 is made up of, in this example, a bi-layer gate dielectric stack.
  • the gate dielectric material is deposited by conventional techniques such as chemical vapor deposition or other deposition techniques according to the specifics of the material.
  • the individual dielectric materials that make up the gate dielectric stack are patterned using conventional techniques such as masking and etching.
  • the bottom dielectric layer 130 is selected to have a modest dielectric constant, k 1 , that forms a generally defect-free interface with substrate 105 .
  • a generally defect-free interface is one that has a sufficiently high (e.g., >8 MV/cm) dielectric breakdown strength implying that the dielectric layer is pin-hole free and contains a negligible number of defects that would lead to breakdown of the dielectric layer at lower electric fields.
  • Bottom dielectric layer 130 should also be stable on silicon and stable against oxide formation.
  • bottom dielectric layer 130 materials are chosen that have a heat of formation greater than the heat of formation of SiO 2 . The chemistry in terms of stability of bottom layer 130 is important to achieve the low defect interface.
  • suitable bottom dielectric layer 130 include, but are not limited to, hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), barium oxide (BaO), lanthanum oxide (La 2 O 3 ), and yttrium oxide (Y 2 O 3 ).
  • top dielectric layer 120 is selected to have a relatively high dielectric constant, k 2 , and is a material that is stable in contact with gate electrode 110 .
  • suitable top dielectric layers are BaSrTiO 3 (BST) and PbZrTiO 3 (PZT).
  • BST BaSrTiO 3
  • PZT PbZrTiO 3
  • One function of top dielectric layer 120 is to block any leakage current through bottom dielectric layer 130 , without adding to the equivalent thickness of gate dielectric 140 (i.e., equivalent thickness of an SiO 2 gate dielectric) and contributing to the production of a fringe electric field.
  • One guideline to select the appropriate dielectric layer thickness t 1 for bottom dielectric layer 130 , and t 2 for top dielectric layer 120 is the following.
  • a total thickness, t, of gate dielectric 140 should be less than one-third of the gate length of gate electrode 110 .
  • the effective dielectric constant, k may then be determined by the following relationship:
  • k ox is the dielectric constant of SiO 2 which is typically represented as 4.0.
  • the total thickness of dielectric layer 140 may be calculated:
  • Equation (4) is then solved for a thickness of bottom dielectric layer 130 having a known dielectric constant, k 1 , and top dielectric layer 120 also having a known dielectric constant, k 2 .
  • Table I shows the individual thicknesses of first dielectric layer 130 (t 1 ) and second dielectric layer 120 (t 2 ) for various technologies scaled by the Morse rule starting with a gate electrode length of 150 nanometers, for a k 1 of 30 and a k 2 of 300.
  • Table I demonstrates that a multi-layer dielectric gate stack, in this case, a bi-layer dielectric gate stack, is scalable for a given technology. For example, for each technology, given a first dielectric layer 130 having a dielectric constant k 1 of 30 and a second dielectric layer 120 having a dielectric constant k 2 of 300, a total gate dielectric layer thickness less than one-third of the individual gate lengths is maintained. Further, the choice of second gate dielectric layer 120 of material to block the leakage current maintains the performance of the device. Finally, by manipulating the gate dielectric materials, the capacitance of the device may be appropriately increased for the given technology.
  • a third dielectric layer may be utilized to act as a barrier layer to prevent interaction between top dielectric layer 120 materials having high dielectric constants and the polysilicon gate material.
  • Suitable third dielectric materials include, but are not limited to, HfO 2 , ZrO 2 , BaO, La 2 O 3 , and Y 2 O 3 (notably the same materials suitable as bottom dielectric layer 130 ).
  • gate electrode 110 being a polysilicon. It is to be appreciated that the same principles may be applied to gate electrodes of different materials, such as, for example, metal gates. In the case of a metal gate electrode, the electrical thickness (telectrical) may be reduced since, in general, metal gate electrodes do not experience the depletion seen by polysilicon. Table I also shows the scaling of the bi-layer dielectric materials discussed above using metal gate technology.

Abstract

A transistor gate dielectric including a first dielectric material having a first dielectric constant and a second dielectric material having a second dielectric constant different from the first dielectric constant.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The invention relates to integrated circuit devices and more particularly to enhancing dielectric material in those device. [0002]
  • 2. Description of Related Art [0003]
  • One way to improve integrated circuit performance is through scaling the individual devices that comprise the integrated circuit. Thus, each subsequent generation of integrated circuit generally involves reducing the size of the individual devices on, for example, a semiconductor chip. The Morse rule is a common benchmark in the integrated circuit technology and provides that devices will be scaled down or reduced in size by one-third for each new generation. [0004]
  • The scale of a transistor device requires consideration of the desired performance of the device. For example, one goal may be to increase the current flow in the semiconductor material of the transistor. The current flow is proportional to the voltage applied to the gate electrode and the capacitance seen at the gate: [0005]
  • Q ∝C (V−V th)
  • where Q is one measure of the current flow, C is capacitance, V is the voltage applied to the gate electrode, and V[0006] th is the threshold voltage of the device.
  • To increase the voltage applied to a device requires an increase in power, P (P∝V[0007] 2). However, at the same time as increasing the charge in the transistor, subsequent generations also seek to reduce the power required to run the device, since, importantly, a reduction of power reduces the heat generated by the device. Thus, to increase the current flow through the device without increasing the power requires an increase in the capacitance in the gate.
  • One way to increase the capacitance is by adjusting the thickness of the gate dielectric. In general, the capacitance is related to the gate dielectric by the following formula: [0008]
  • C=k ox /t electrical
  • where k[0009] ox is the dielectric constant of silicon dioxide (SiO2) and telectrical is the electrical thickness of the gate dielectric. The electrical thickness of the gate dielectric is greater than the actual thickness of the dielectric in most semiconductor devices. In general, as carriers flow through the channel of a semiconductor-based transistor device there is a quantum effect experienced in the channel which causes an area directly below the gate to become insulative. The insulative region acts like an extension of the gate dielectric by essentially extending the dielectric into a portion of the channel. The second cause of increase gate dielectric thickness attributable to telectrical is experienced by a similar phenomenon happening in the gate electrode itself. At inversion, a gate electrode of polysilicon, for example, will generally experience a depletion of carriers in the area of the polysilicon near the gate dielectric. Accordingly, the gate dielectric appears to extend into the polysilicon gate electrode.
  • The result of the quantum effect in the channel and a depletion in the polysilicon gate electrode is an electrical thickness (telectrical) of the gate dielectric greater than the actual thickness of the gate dielectric. The magnitude of the channel quantum effect and polysilicon depletion may be estimated or determined for a given technology. Accordingly, the electrical thickness (t[0010] electrical) for a SiO2 may be calculated and scaled for a given technology.
  • In considering the capacitance effects of the gate dielectric, a consideration of the thickness of gate dielectric is important for other reasons. First, the gate dielectric cannot be too thin as a thin gate dielectric will allow a leakage current from the channel through the gate electrode. At the same time, the gate dielectric cannot be too thick because such a gate structure may produce an undesirable fringe electric field. The desired electric field at the gate is typically perpendicular to the surface of the semiconductor substrate. Beyond a certain gate dielectric thickness, generally thought to be beyond one-third the lateral width of the gate electrode for a SiO[0011] 2 gate dielectric, the electrical field deviates from a perpendicular course and sprays about the gate electrode leading to an undesirable fringe electric field.
  • What is needed is a way to increase the capacitance of a gate dielectric without decreasing the performance of the device. It is preferable if the increased capacitance is consistent with scaling techniques and may be used in multiple generation technologies. [0012]
    • SUMMARY OF THE INVENTION
  • A transistor gate dielectric is disclosed. The transistor gate dielectric includes a first dielectric material having a first dielectric constant and a second dielectric material having a second dielectric constant different from the first dielectric constant. [0013]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic illustration of a side view of a transistor dielectric having a gate dielectric of a first dielectric material and a second dielectric material. [0014]
    • DETAILED DESCRIPTION OF THE INVENTION
  • The invention relates to a transistor gate dielectric made up of at least two different dielectric materials. For example, one embodiment contemplates a gate dielectric made up of two different dielectric materials each with its own dielectric constant. The dielectric material nearest the substrate, e.g., a semiconductor substrate will have a modest dielectric constant that produces a defect-free interface with the substrate and is stable against oxide formation. The second dielectric material will have a relatively high dielectric constant and be stable in contact with the desired gate material. By varying the thickness of the material, a gate dielectric can be formed that is scalable for different technology generations, has a low leakage current, and maintains an electric field of the gate perpendicular to the surface of the semiconductor. A transistor gate utilizing the multi-layer gate dielectric is also disclosed. [0015]
  • FIG. 1 illustrates an embodiment of the multi-layer gate dielectric of the invention. FIG. 1 shows [0016] transistor 100 consisting of gate electrode 110 overlying gate dielectric 140. Gate electrode 110 and gate dielectric 140 overlie semiconductor substrate 105 such as, for example, a silicon semiconductor substrate. Formed in substrate 105 adjacent transistor gate electrode 110 are diffusion or junction regions 160. The transistor is isolated from other devices, in this example, by shallow trench isolation structures 150.
  • Gate dielectric [0017] 140 is made up of, in this example, a bi-layer gate dielectric stack. The gate dielectric material is deposited by conventional techniques such as chemical vapor deposition or other deposition techniques according to the specifics of the material. The individual dielectric materials that make up the gate dielectric stack are patterned using conventional techniques such as masking and etching.
  • In one embodiment, the bottom [0018] dielectric layer 130 is selected to have a modest dielectric constant, k1, that forms a generally defect-free interface with substrate 105. A generally defect-free interface is one that has a sufficiently high (e.g., >8 MV/cm) dielectric breakdown strength implying that the dielectric layer is pin-hole free and contains a negligible number of defects that would lead to breakdown of the dielectric layer at lower electric fields. Bottom dielectric layer 130 should also be stable on silicon and stable against oxide formation. In one embodiment, bottom dielectric layer 130 materials are chosen that have a heat of formation greater than the heat of formation of SiO2. The chemistry in terms of stability of bottom layer 130 is important to achieve the low defect interface. Examples of suitable bottom dielectric layer 130 include, but are not limited to, hafnium oxide (HfO2), zirconium oxide (ZrO2), barium oxide (BaO), lanthanum oxide (La2O3), and yttrium oxide (Y2O3).
  • In this embodiment, top [0019] dielectric layer 120 is selected to have a relatively high dielectric constant, k2, and is a material that is stable in contact with gate electrode 110. Examples of suitable top dielectric layers are BaSrTiO3 (BST) and PbZrTiO3 (PZT). One function of top dielectric layer 120 is to block any leakage current through bottom dielectric layer 130, without adding to the equivalent thickness of gate dielectric 140 (i.e., equivalent thickness of an SiO2 gate dielectric) and contributing to the production of a fringe electric field.
  • One guideline to select the appropriate dielectric layer thickness t[0020] 1 for bottom dielectric layer 130, and t2 for top dielectric layer 120, is the following. For a given technology generation (i.e., a given gate length of gate electrode 110 and equivalent oxide thickness of a SiO2 gate dielectric, tox), a total thickness, t, of gate dielectric 140 should be less than one-third of the gate length of gate electrode 110. The effective dielectric constant, k, may then be determined by the following relationship:
  • k=k ox(t/t ox)   (1)
  • wherein k[0021] ox is the dielectric constant of SiO2 which is typically represented as 4.0.
  • Combining the above relationship with a relationship for calculating the effective dielectric constant of [0022] gate dielectric 140 of the following:
  • k=t/(t 1 /k 1 +t 2 /k 2),   (2)
  • the total thickness of [0023] dielectric layer 140 may be calculated:
  • t=t 1 +t 2.   (3)
  • Combining equations (1), (2), and (3) yields the following: [0024]
  • t 1 /k 1 +t 2 /k 2 =t ox /k ox .   (4)
  • Equation (4) is then solved for a thickness of [0025] bottom dielectric layer 130 having a known dielectric constant, k1, and top dielectric layer 120 also having a known dielectric constant, k2. Table I shows the individual thicknesses of first dielectric layer 130 (t1) and second dielectric layer 120 (t2) for various technologies scaled by the Morse rule starting with a gate electrode length of 150 nanometers, for a k1 of 30 and a k2 of 300.
  • Table I demonstrates that a multi-layer dielectric gate stack, in this case, a bi-layer dielectric gate stack, is scalable for a given technology. For example, for each technology, given a first [0026] dielectric layer 130 having a dielectric constant k1 of 30 and a second dielectric layer 120 having a dielectric constant k2 of 300, a total gate dielectric layer thickness less than one-third of the individual gate lengths is maintained. Further, the choice of second gate dielectric layer 120 of material to block the leakage current maintains the performance of the device. Finally, by manipulating the gate dielectric materials, the capacitance of the device may be appropriately increased for the given technology.
  • For a [0027] gate electrode 110 that is polysilicon, a third dielectric layer may be utilized to act as a barrier layer to prevent interaction between top dielectric layer 120 materials having high dielectric constants and the polysilicon gate material. Suitable third dielectric materials include, but are not limited to, HfO2, ZrO2, BaO, La2O3, and Y2O3 (notably the same materials suitable as bottom dielectric layer 130).
  • The above example is described with respect to [0028] gate electrode 110 being a polysilicon. It is to be appreciated that the same principles may be applied to gate electrodes of different materials, such as, for example, metal gates. In the case of a metal gate electrode, the electrical thickness (telectrical) may be reduced since, in general, metal gate electrodes do not experience the depletion seen by polysilicon. Table I also shows the scaling of the bi-layer dielectric materials discussed above using metal gate technology.
    TABLE I
    Technology Generation 1 2 3 4 5 6
    Lgate (nm) 150 100 70 50 35 25
    t_electrical (Å) 30 21 15 10 7 5
    t_ox (Å): metal gate 26 17 11 6 3 1
    t (Å): total stack thick 300 210 147 103 72 50
    t1 (Å), k1 = 30 183 118 75 39 17 3
    t2 (Å), k2 = 300 117 92 72 64 55 48
  • In the preceding detailed description, the invention is described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. [0029]

Claims (14)

What is claimed:
1. A transistor gate dielectric comprising:
a first dielectric material having a first dielectric constant; and
a second dielectric material having a second dielectric constant different from the first dielectric constant.
2. The transistor gate dielectric of
claim 1
, wherein the second dielectric constant is greater than the first dielectric constant.
3. The transistor gate dielectric of
claim 1
, wherein the first material has a first thickness and the second material has a second thickness, the combination of the first thickness and the second thickness defining a total thickness less than one- third of the length of a transistor gate adapted to overly the gate dielectric.
4. The gate dielectric of
claim 3
, wherein the first material thickness and the second material thickness are determined by the relationship
t 1 /k 1 +t 2 /k 2 =t ox /k ox
wherein
t1 is the first material thickness,
t2 is the second material thickness,
tox is the minimum thickness for a gate dielectric of silicon dioxide for a chosen gate length,
k1 is the dielectric constant for the first dielectric material,
k2 is the dielectric constant for the second dielectric material, and
kox is the dielectric constant of silicon dioxide.
5. The gate dielectric of
claim 1
, wherein the first gate dielectric material is selected from one of silicon nitride, HfO2, BaO, La2O3, Y2O3, and ZrO2.
6. The gate dielectric of
claim 1
, wherein the second dielectric material is selected from one of BST and PZT.
7. The gate dielectric of
claim 1
, further comprising a third dielectric material having a third dielectric constant.
8. A transistor having a gate electrode overlying a gate dielectric comprising:
a first dielectric material having a first dielectric constant; and
a second dielectric material having a second dielectric constant different from the first dielectric constant.
9. The transistor of
claim 8
, wherein the second dielectric of the gate dielectric has a dielectric constant greater than the first dielectric constant.
10. The transistor of
claim 8
, wherein the first material of the gate dielectric has a first thickness and the second material of the gate dielectric has a second thickness, the combination of the first thickness and the second thickness defining a total thickness less than one-third of a length of the transistor gate electrode.
11. The transistor of
claim 8
, wherein the first material thickness and the second material thickness are determined by the relationship
t 1 /k 1 +t 2 /k 2 =t ox /k ox
wherein
t1 is the first material thickness,
t2 is the second material thickness,
tox is the minimum thickness for a gate dielectric of silicon dioxide for a chosen gate electrode length,
k1 is the dielectric constant for the first dielectric material,
k2 is the dielectric constant for the second dielectric material, and
kox is the dielectric constant of silicon dioxide.
12. The transistor of
claim 8
, wherein the first gate dielectric material is selected from one of silicon nitride, HfO2,BaO, La2O3, Y2O3, and ZrO2.
13. The gate dielectric of
claim 8
, wherein the second dielectric material is selected from one of BST and PZT.
14. The gate dielectric of
claim 8
, further comprising a third dielectric material having a third dielectric constant.
US09/109,261 1998-06-30 1998-06-30 Multi-layer gate dielectric Abandoned US20010013629A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US09/109,261 US20010013629A1 (en) 1998-06-30 1998-06-30 Multi-layer gate dielectric
US12/615,938 US8193593B2 (en) 1998-06-30 2009-11-10 Multi-layer gate dielectric
US12/976,211 US8581353B2 (en) 1998-06-30 2010-12-22 Multi-layer gate dielectric
US14/054,778 US9412860B2 (en) 1998-06-30 2013-10-15 Multi-layer gate dielectric
US15/225,785 US20160343824A1 (en) 1998-06-30 2016-08-01 Multi-layer gate dielectric

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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6348386B1 (en) * 2001-04-16 2002-02-19 Motorola, Inc. Method for making a hafnium-based insulating film
US20020192974A1 (en) * 2001-06-13 2002-12-19 Ahn Kie Y. Dielectric layer forming method and devices formed therewith
US6563183B1 (en) * 2001-12-31 2003-05-13 Advanced Micro Devices, Inc. Gate array with multiple dielectric properties and method for forming same
US20030176049A1 (en) * 2002-03-15 2003-09-18 Hegde Rama I. Gate dielectric and method therefor
US20030178674A1 (en) * 2002-03-22 2003-09-25 Shigeru Fujita Semiconductor device and its manufacturing method
KR100415538B1 (en) * 2001-09-14 2004-01-24 주식회사 하이닉스반도체 Capacitor with double dielectric layer and method for fabricating the same
US20050023628A1 (en) * 2001-01-26 2005-02-03 Yoshihide Senzaki Multilayer high k dielectric films and method of making the same
US20050087791A1 (en) * 2002-08-16 2005-04-28 Samsung Electronics Co., Ltd. Capacitor of semiconductor memory device that has composite A12O3/HfO2 dielectric layer and method of manufacturing the same
US20070096226A1 (en) * 2005-10-31 2007-05-03 Chun-Li Liu MOSFET dielectric including a diffusion barrier
US20070170502A1 (en) * 2003-03-24 2007-07-26 Tominaga Koji Semiconductor device and method for manufacturing the same
JP2014523131A (en) * 2011-06-27 2014-09-08 クリー インコーポレイテッド Wet chemistry process for manufacturing semiconductor devices with increased channel mobility
US20170025515A1 (en) * 2013-03-28 2017-01-26 Toyoda Gosei Co., Ltd. Semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9490335B1 (en) 2015-12-30 2016-11-08 International Business Machines Corporation Extra gate device for nanosheet
KR102317203B1 (en) * 2017-02-28 2021-10-26 한국전자통신연구원 Semiconductor devices comprising metal-insulator transition materials

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4015281A (en) * 1970-03-30 1977-03-29 Hitachi, Ltd. MIS-FETs isolated on common substrate
US5621681A (en) * 1995-03-22 1997-04-15 Samsung Electronics Co., Ltd. Device and manufacturing method for a ferroelectric memory
US5990516A (en) * 1994-09-13 1999-11-23 Kabushiki Kaisha Toshiba MOSFET with a thin gate insulating film

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6148956A (en) * 1984-08-16 1986-03-10 Toshiba Corp Manufacture of semiconductor device
US5292673A (en) * 1989-08-16 1994-03-08 Hitachi, Ltd Method of manufacturing a semiconductor device
US5258645A (en) 1990-03-09 1993-11-02 Fujitsu Limited Semiconductor device having MOS transistor and a sidewall with a double insulator layer structure
JPH0629549A (en) 1992-07-13 1994-02-04 Oki Electric Ind Co Ltd Field-effect transistor
JP2760709B2 (en) 1992-07-15 1998-06-04 株式会社東芝 Semiconductor device having LDD structure with high breakdown voltage and method of manufacturing the same
JP2643833B2 (en) * 1994-05-30 1997-08-20 日本電気株式会社 Semiconductor memory device and method of manufacturing the same
JP2901493B2 (en) 1994-06-27 1999-06-07 日本電気株式会社 Semiconductor memory device and method of manufacturing the same
US5963810A (en) 1997-12-18 1999-10-05 Advanced Micro Devices Semiconductor device having nitrogen enhanced high permittivity gate insulating layer and fabrication thereof
US6121094A (en) 1998-07-21 2000-09-19 Advanced Micro Devices, Inc. Method of making a semiconductor device with a multi-level gate structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4015281A (en) * 1970-03-30 1977-03-29 Hitachi, Ltd. MIS-FETs isolated on common substrate
US5990516A (en) * 1994-09-13 1999-11-23 Kabushiki Kaisha Toshiba MOSFET with a thin gate insulating film
US5621681A (en) * 1995-03-22 1997-04-15 Samsung Electronics Co., Ltd. Device and manufacturing method for a ferroelectric memory

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050023628A1 (en) * 2001-01-26 2005-02-03 Yoshihide Senzaki Multilayer high k dielectric films and method of making the same
US6348386B1 (en) * 2001-04-16 2002-02-19 Motorola, Inc. Method for making a hafnium-based insulating film
US6787413B2 (en) * 2001-06-13 2004-09-07 Micron Technology, Inc. Capacitor structure forming methods
US7465982B2 (en) 2001-06-13 2008-12-16 Micron Technology, Inc. Capacitor structures
US7420239B2 (en) * 2001-06-13 2008-09-02 Micron Technology, Inc. Dielectric layer forming method and devices formed therewith
US20020192975A1 (en) * 2001-06-13 2002-12-19 Ahn Kie Y. Dielectric layer forming method and devices formed therewith
US7235448B2 (en) 2001-06-13 2007-06-26 Micron Technology, Inc. Dielectric layer forming method and devices formed therewith
US20020192974A1 (en) * 2001-06-13 2002-12-19 Ahn Kie Y. Dielectric layer forming method and devices formed therewith
US20050037563A1 (en) * 2001-06-13 2005-02-17 Ahn Kie Y. Capacitor structures
US7037862B2 (en) * 2001-06-13 2006-05-02 Micron Technology, Inc. Dielectric layer forming method and devices formed therewith
KR100415538B1 (en) * 2001-09-14 2004-01-24 주식회사 하이닉스반도체 Capacitor with double dielectric layer and method for fabricating the same
US20050106798A1 (en) * 2001-09-14 2005-05-19 Hynix Semiconductor Inc. Semiconductor device and method for fabricating the same
US6563183B1 (en) * 2001-12-31 2003-05-13 Advanced Micro Devices, Inc. Gate array with multiple dielectric properties and method for forming same
WO2003079451A1 (en) * 2002-03-15 2003-09-25 Motorola, Inc., A Corporation Of The State Of Delaware Gate dielectric and method therefor
US6717226B2 (en) * 2002-03-15 2004-04-06 Motorola, Inc. Transistor with layered high-K gate dielectric and method therefor
US20030176049A1 (en) * 2002-03-15 2003-09-18 Hegde Rama I. Gate dielectric and method therefor
US20030178674A1 (en) * 2002-03-22 2003-09-25 Shigeru Fujita Semiconductor device and its manufacturing method
US20050087791A1 (en) * 2002-08-16 2005-04-28 Samsung Electronics Co., Ltd. Capacitor of semiconductor memory device that has composite A12O3/HfO2 dielectric layer and method of manufacturing the same
US20070170502A1 (en) * 2003-03-24 2007-07-26 Tominaga Koji Semiconductor device and method for manufacturing the same
US8044452B2 (en) * 2003-03-24 2011-10-25 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
US20070096226A1 (en) * 2005-10-31 2007-05-03 Chun-Li Liu MOSFET dielectric including a diffusion barrier
JP2014523131A (en) * 2011-06-27 2014-09-08 クリー インコーポレイテッド Wet chemistry process for manufacturing semiconductor devices with increased channel mobility
US20170025515A1 (en) * 2013-03-28 2017-01-26 Toyoda Gosei Co., Ltd. Semiconductor device
US10074728B2 (en) * 2013-03-28 2018-09-11 Toyoda Gosei Co., Ltd. Semiconductor device

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US8193593B2 (en) 2012-06-05
US8581353B2 (en) 2013-11-12
US20100052078A1 (en) 2010-03-04
US20140042560A1 (en) 2014-02-13
US20110089502A1 (en) 2011-04-21
US20160343824A1 (en) 2016-11-24

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