EP0361143A2 - Circuitry for the on-chip interleaved access to dynamic RAM modules - Google Patents
Circuitry for the on-chip interleaved access to dynamic RAM modules Download PDFInfo
- Publication number
- EP0361143A2 EP0361143A2 EP89116380A EP89116380A EP0361143A2 EP 0361143 A2 EP0361143 A2 EP 0361143A2 EP 89116380 A EP89116380 A EP 89116380A EP 89116380 A EP89116380 A EP 89116380A EP 0361143 A2 EP0361143 A2 EP 0361143A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- chip
- logic
- address bus
- conflict
- blocks
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0607—Interleaved addressing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
Definitions
- the present invention relates to a circuit arrangement for performing an on-chip interleaving of access to dynamic RAM components (DRAMs) in a data processing device.
- DRAMs dynamic RAM components
- the invention has for its object to provide a circuit arrangement of the type mentioned, which has a simple structure and can be implemented in space and inexpensively together with the relevant dynamic RAM modules on a chip.
- the memory field of a chip is divided into 2 n blocks A, B (n> 0) with upstream registers.
- a common on-chip address bus supplies each of these blocks A, B.
- the block addresses are transmitted over this bus in time division multiplex. The maximum degree of entanglement is limited by the ratio of the total cycle time to the duration of an address transfer. An increased number of blocks reduces the likelihood of a conflict.
- the individual blocks A, B are selected via the n least significant bits of the address codes.
- Logic which causes addressing and data output to be time-linked, places the read data on the common, external data bus. If there is an address stream with non-sequential addresses, conflicts can arise when accessing blocks that are still occupied. Conflicts result in delayed access.
- An on-chip logic conflict detection detects these conflicts and communicates them to the "outside world" via signals (WAIT).
- the so-called RAS and CAS time control is also carried out by a suitable internal logic (control).
- Fig. 2 shows the temporal assignment of the processes on the address bus and the data bus.
- the circuit arrangement according to the invention brings about a shortening of the average access time of dynamic RAM chips (DRAMs) in the case of rapidly successive memory requests by means of an interleaving technique.
- DRAMs dynamic RAM chips
Abstract
Description
Die vorliegende Erfindung betrifft eine Schaltungsanordnung zum Durchführen eines On-Chip-Zeitverschachtelns (Interleaving) des Zugriffs auf dynamische RAM-Bausteine (DRAMs) in einer Datenverarbeitungseinrichtung.The present invention relates to a circuit arrangement for performing an on-chip interleaving of access to dynamic RAM components (DRAMs) in a data processing device.
Bisher wird ein Zeitverschachteln (Interleaving) auf Baustein-Ebene angewandt. Die derzeitige DRAM-Architektur läßt zeitverschachtelte oder verschränkte Zugriffe nur dann zu, wenn ungleiche Bausteine angesprochen werden. Dabei steuert eine zusätzlich erforderliche externe Logik die Bausteinzugriffe und erkennt Konfliktfälle. Diese bekannte Technik ist aufwendig und hat u. a. den Nachteil eines höheren Platzbedarfs und höherer Kosten gegenüber einer Technik, wie sie erfindungsgemäß vorgesehen ist.So far, time interleaving has been used at the block level. The current DRAM architecture only permits time-interleaved or restricted access if unequal blocks are addressed. An additional required external logic controls the block access and detects conflict cases. This known technique is complex and has u. a. the disadvantage of a higher space requirement and higher costs compared to a technology as it is provided according to the invention.
Der Erfindung liegt die Aufgabe zugrunde, eine Schaltungsanordnung der eingangs genannten Art zu schaffen, die einen einfachen Aufbau hat und platz- und kostengünstig gemeinsam mit den betreffenden dynamischen RAM-Bausteinen auf einen Chip realisiert werden kann.The invention has for its object to provide a circuit arrangement of the type mentioned, which has a simple structure and can be implemented in space and inexpensively together with the relevant dynamic RAM modules on a chip.
Zur Lösung der Aufgabe wird eine Schaltungsanordnung gemäß dem Oberbegriff des Patentanspruchs vorgeschlagen, die durch die in dem kennzeichnenden Teil des Patentanspruchs angegebenen Merkmale charakterisiert ist.To achieve the object, a circuit arrangement according to the preamble of the patent claim is proposed, which is characterized by the features specified in the characterizing part of the patent claim.
Im folgenden wird die Erfindung anhand mehrerer Figuren im einzelnen beschrieben.
- Fig. 1 zeigt ein Blockschaltbild der erfindungsgemäßen Schaltungsanordnung.
- Fig. 2 zeigt eine diagrammartige Darstellung des zeitlichen Ablaufs von Vorgängen auf dem Adreßbus und dem Datenbus der Schaltungsanordnung bei konfliktfreiem Zugriff auf die dynamischen RAM-Bausteine.
- 1 shows a block diagram of the circuit arrangement according to the invention.
- FIG. 2 shows a diagrammatic representation of the chronological sequence of events on the address bus and the data bus of the circuit arrangement with conflict-free access to the dynamic RAM modules.
Wie Fig. 1 zeigt, ist das Speicherfeld eines Chips in 2n Blöcke A, B (n>0) mit vorgeschalteten Registern unterteilt. Ein gemeinsamer On-Chip-Adreßbus versorgt jeden dieser Blöcke A, B. Die Blockadressen werden über diesen Bus im Zeitmultiplex übertragen. Der maximale Verschränkungsgrad ist vom Verhältnis der Gesamtzyklusdauer zur Dauer einer Adreßübertragung begrenzt. Eine erhöhte Blockanzahl verringert die Wahrscheinlichkeit eines Konflikts. Die einzelnen Blöcke A, B werden über die n niederwertigsten Bits der Adreßcodes ausgewählt. Eine das zeitliche Verschränken von Adressierung und Datenausgabe bewirkende Logik legt die ausgelesenen Daten auf den gemeinsamen, nach außen geführten Datenbus. Liegt ein Adreßstrom mit nichtsequentiellen Adressen vor, können Konflikte auftreten, wenn auf Blöcke zugegriffen wird, die noch belegt sind. Konflikte haben verzögerte Zugriffe zur Folge. Eine On-Chip-Logik Konflikterkennung erkennt diese Konflikte und teilt sie über Signale (WAIT) der "Außenwelt" mit. Ebenso wird die sog. RAS- und CAS-Zeitsteuerung von einer geeigneten internen Logik (Steuerung) durchgeführt.1 shows, the memory field of a chip is divided into 2 n blocks A, B (n> 0) with upstream registers. A common on-chip address bus supplies each of these blocks A, B. The block addresses are transmitted over this bus in time division multiplex. The maximum degree of entanglement is limited by the ratio of the total cycle time to the duration of an address transfer. An increased number of blocks reduces the likelihood of a conflict. The individual blocks A, B are selected via the n least significant bits of the address codes. Logic, which causes addressing and data output to be time-linked, places the read data on the common, external data bus. If there is an address stream with non-sequential addresses, conflicts can arise when accessing blocks that are still occupied. Conflicts result in delayed access. An on-chip logic conflict detection detects these conflicts and communicates them to the "outside world" via signals (WAIT). The so-called RAS and CAS time control is also carried out by a suitable internal logic (control).
Fig. 2 zeigt die zeitliche Zuordnung der Vorgänge auf dem Adreßbus und dem Datenbus.Fig. 2 shows the temporal assignment of the processes on the address bus and the data bus.
Die erfindungsgemäße Schaltungsanordnung bewirkt eine Verkürzung der mittleren Zugriffszeit dynamischer RAM-Bausteine (DRAMs) bei schnell aufeinanderfolgenden Speicheranforderungen durch eine sog. Interleaving-Technik.The circuit arrangement according to the invention brings about a shortening of the average access time of dynamic RAM chips (DRAMs) in the case of rapidly successive memory requests by means of an interleaving technique.
Claims (1)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE3833095 | 1988-09-29 | ||
DE3833095 | 1988-09-29 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0361143A2 true EP0361143A2 (en) | 1990-04-04 |
EP0361143A3 EP0361143A3 (en) | 1990-11-28 |
EP0361143B1 EP0361143B1 (en) | 1995-08-30 |
Family
ID=6363988
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP89116380A Expired - Lifetime EP0361143B1 (en) | 1988-09-29 | 1989-09-05 | Circuitry for the on-chip interleaved access to dynamic RAM modules |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0361143B1 (en) |
AT (1) | ATE127254T1 (en) |
DE (1) | DE58909408D1 (en) |
HK (1) | HK90897A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0513451A1 (en) * | 1991-05-16 | 1992-11-19 | International Business Machines Corporation | Memory device |
EP1293905A1 (en) * | 2001-09-17 | 2003-03-19 | STMicroelectronics S.r.l. | A pointer circuit |
US6810449B1 (en) | 1995-10-19 | 2004-10-26 | Rambus, Inc. | Protocol for communication with dynamic memory |
US6931467B2 (en) | 1995-10-19 | 2005-08-16 | Rambus Inc. | Memory integrated circuit device which samples data upon detection of a strobe signal |
CN100464317C (en) * | 2007-06-27 | 2009-02-25 | 北京中星微电子有限公司 | Bus access collision detection method and system |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3727688A1 (en) * | 1986-08-19 | 1988-02-25 | Toshiba Kawasaki Kk | SEMICONDUCTOR STORAGE SYSTEM |
-
1989
- 1989-09-05 EP EP89116380A patent/EP0361143B1/en not_active Expired - Lifetime
- 1989-09-05 DE DE58909408T patent/DE58909408D1/en not_active Expired - Fee Related
- 1989-09-05 AT AT89116380T patent/ATE127254T1/en not_active IP Right Cessation
-
1997
- 1997-06-26 HK HK90897A patent/HK90897A/en not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3727688A1 (en) * | 1986-08-19 | 1988-02-25 | Toshiba Kawasaki Kk | SEMICONDUCTOR STORAGE SYSTEM |
Non-Patent Citations (2)
Title |
---|
ELECTRONIC ENGINEERING, Band 58, Nr. 710, Februar 1986, Seiten 87-92, London, GB; P. BAGNALL et al.: "A hierarchical RAM with multi-level access path - part 2" * |
IBM TECHNICAL DISCLOSURE BULLETIN, Band 25, Nr. 6, November 1982, Seiten 3042-3044, New York, US; J.C. LEININGER: "Microprocessor interleave instruction" * |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0513451A1 (en) * | 1991-05-16 | 1992-11-19 | International Business Machines Corporation | Memory device |
US5450367A (en) * | 1991-05-16 | 1995-09-12 | International Business Machines Corporation | Split SAM with independent SAM access |
US6810449B1 (en) | 1995-10-19 | 2004-10-26 | Rambus, Inc. | Protocol for communication with dynamic memory |
US6931467B2 (en) | 1995-10-19 | 2005-08-16 | Rambus Inc. | Memory integrated circuit device which samples data upon detection of a strobe signal |
EP1293905A1 (en) * | 2001-09-17 | 2003-03-19 | STMicroelectronics S.r.l. | A pointer circuit |
US7181592B2 (en) | 2001-09-17 | 2007-02-20 | Stmicroelectronics S.R.L. | Pointer circuit |
CN100464317C (en) * | 2007-06-27 | 2009-02-25 | 北京中星微电子有限公司 | Bus access collision detection method and system |
Also Published As
Publication number | Publication date |
---|---|
EP0361143A3 (en) | 1990-11-28 |
EP0361143B1 (en) | 1995-08-30 |
DE58909408D1 (en) | 1995-10-05 |
HK90897A (en) | 1997-08-01 |
ATE127254T1 (en) | 1995-09-15 |
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