EP0361143A2 - Circuitry for the on-chip interleaved access to dynamic RAM modules - Google Patents

Circuitry for the on-chip interleaved access to dynamic RAM modules Download PDF

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Publication number
EP0361143A2
EP0361143A2 EP89116380A EP89116380A EP0361143A2 EP 0361143 A2 EP0361143 A2 EP 0361143A2 EP 89116380 A EP89116380 A EP 89116380A EP 89116380 A EP89116380 A EP 89116380A EP 0361143 A2 EP0361143 A2 EP 0361143A2
Authority
EP
European Patent Office
Prior art keywords
chip
logic
address bus
conflict
blocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP89116380A
Other languages
German (de)
French (fr)
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EP0361143A3 (en
EP0361143B1 (en
Inventor
Christoph Dipl.-Ing. Legutko
Thomas Dipl.-Ing. Niedermeier
Doris Dipl.-Math. Rauh
Eberhard Dipl.-Ing. Schäfer
Erwin Dipl.-Ing. Thurner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
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Siemens AG
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Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0361143A2 publication Critical patent/EP0361143A2/en
Publication of EP0361143A3 publication Critical patent/EP0361143A3/en
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Publication of EP0361143B1 publication Critical patent/EP0361143B1/en
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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607Interleaved addressing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4096Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Definitions

  • the present invention relates to a circuit arrangement for performing an on-chip interleaving of access to dynamic RAM components (DRAMs) in a data processing device.
  • DRAMs dynamic RAM components
  • the invention has for its object to provide a circuit arrangement of the type mentioned, which has a simple structure and can be implemented in space and inexpensively together with the relevant dynamic RAM modules on a chip.
  • the memory field of a chip is divided into 2 n blocks A, B (n> 0) with upstream registers.
  • a common on-chip address bus supplies each of these blocks A, B.
  • the block addresses are transmitted over this bus in time division multiplex. The maximum degree of entanglement is limited by the ratio of the total cycle time to the duration of an address transfer. An increased number of blocks reduces the likelihood of a conflict.
  • the individual blocks A, B are selected via the n least significant bits of the address codes.
  • Logic which causes addressing and data output to be time-linked, places the read data on the common, external data bus. If there is an address stream with non-sequential addresses, conflicts can arise when accessing blocks that are still occupied. Conflicts result in delayed access.
  • An on-chip logic conflict detection detects these conflicts and communicates them to the "outside world" via signals (WAIT).
  • the so-called RAS and CAS time control is also carried out by a suitable internal logic (control).
  • Fig. 2 shows the temporal assignment of the processes on the address bus and the data bus.
  • the circuit arrangement according to the invention brings about a shortening of the average access time of dynamic RAM chips (DRAMs) in the case of rapidly successive memory requests by means of an interleaving technique.
  • DRAMs dynamic RAM chips

Abstract

Circuitry for the on-chip interleaved access to dynamic RAM modules (DRAMs) of a data processing device, in which it is provided that the memory field of a DRAM chip is subdivided into 2<n> blocks (A, B), in which n>0 and each block (A, B) has a register connected upstream of it which is connected on the input side to an address bus and on the output side to the block (A, B) assigned to it, that the blocks (A, B) are connected on the output side to individual inputs of a data output logic which effects a time restriction on the addressing and data output, the outputs of which logic are connected to a data bus, that a conflict detection logic is connected to the address bus which in the case of an access conflict on the address bus transmits a conflict signal (WAIT) to the chip environment, that a RAS/CAS control logic is provided, to which a request signal (REQUEST) can be fed and which transmits the RAS and CAS time control signals, and that the entire arrangement is constructed on one common chip. <IMAGE>

Description

Die vorliegende Erfindung betrifft eine Schaltungsanordnung zum Durchführen eines On-Chip-Zeitverschachtelns (Interleaving) des Zugriffs auf dynamische RAM-Bausteine (DRAMs) in einer Daten­verarbeitungseinrichtung.The present invention relates to a circuit arrangement for performing an on-chip interleaving of access to dynamic RAM components (DRAMs) in a data processing device.

Bisher wird ein Zeitverschachteln (Interleaving) auf Baustein-­Ebene angewandt. Die derzeitige DRAM-Architektur läßt zeit­verschachtelte oder verschränkte Zugriffe nur dann zu, wenn ungleiche Bausteine angesprochen werden. Dabei steuert eine zu­sätzlich erforderliche externe Logik die Bausteinzugriffe und erkennt Konfliktfälle. Diese bekannte Technik ist aufwendig und hat u. a. den Nachteil eines höheren Platzbedarfs und höherer Kosten gegenüber einer Technik, wie sie erfindungsgemäß vorge­sehen ist.So far, time interleaving has been used at the block level. The current DRAM architecture only permits time-interleaved or restricted access if unequal blocks are addressed. An additional required external logic controls the block access and detects conflict cases. This known technique is complex and has u. a. the disadvantage of a higher space requirement and higher costs compared to a technology as it is provided according to the invention.

Der Erfindung liegt die Aufgabe zugrunde, eine Schaltungsan­ordnung der eingangs genannten Art zu schaffen, die einen einfachen Aufbau hat und platz- und kostengünstig gemeinsam mit den betreffenden dynamischen RAM-Bausteinen auf einen Chip realisiert werden kann.The invention has for its object to provide a circuit arrangement of the type mentioned, which has a simple structure and can be implemented in space and inexpensively together with the relevant dynamic RAM modules on a chip.

Zur Lösung der Aufgabe wird eine Schaltungsanordnung gemäß dem Oberbegriff des Patentanspruchs vorgeschlagen, die durch die in dem kennzeichnenden Teil des Patentanspruchs angegebenen Merkmale charakterisiert ist.To achieve the object, a circuit arrangement according to the preamble of the patent claim is proposed, which is characterized by the features specified in the characterizing part of the patent claim.

Im folgenden wird die Erfindung anhand mehrerer Figuren im einzelnen beschrieben.

  • Fig. 1 zeigt ein Blockschaltbild der erfindungsgemäßen Schaltungs­anordnung.
  • Fig. 2 zeigt eine diagrammartige Darstellung des zeitlichen Ablaufs von Vorgängen auf dem Adreßbus und dem Datenbus der Schaltungsanordnung bei konfliktfreiem Zugriff auf die dynamischen RAM-Bausteine.
The invention is described in detail below with reference to several figures.
  • 1 shows a block diagram of the circuit arrangement according to the invention.
  • FIG. 2 shows a diagrammatic representation of the chronological sequence of events on the address bus and the data bus of the circuit arrangement with conflict-free access to the dynamic RAM modules.

Wie Fig. 1 zeigt, ist das Speicherfeld eines Chips in 2n Blöcke A, B (n>0) mit vorgeschalteten Registern unterteilt. Ein gemeinsamer On-Chip-Adreßbus versorgt jeden dieser Blöcke A, B. Die Blockadressen werden über diesen Bus im Zeitmultiplex über­tragen. Der maximale Verschränkungsgrad ist vom Verhältnis der Gesamtzyklusdauer zur Dauer einer Adreßübertragung begrenzt. Eine erhöhte Blockanzahl verringert die Wahrscheinlichkeit eines Konflikts. Die einzelnen Blöcke A, B werden über die n niederwertigsten Bits der Adreßcodes ausgewählt. Eine das zeit­liche Verschränken von Adressierung und Datenausgabe bewirkende Logik legt die ausgelesenen Daten auf den gemeinsamen, nach außen geführten Datenbus. Liegt ein Adreßstrom mit nicht­sequentiellen Adressen vor, können Konflikte auftreten, wenn auf Blöcke zugegriffen wird, die noch belegt sind. Konflikte haben verzögerte Zugriffe zur Folge. Eine On-Chip-Logik Konflikt­erkennung erkennt diese Konflikte und teilt sie über Signale (WAIT) der "Außenwelt" mit. Ebenso wird die sog. RAS- und CAS-­Zeitsteuerung von einer geeigneten internen Logik (Steuerung) durchgeführt.1 shows, the memory field of a chip is divided into 2 n blocks A, B (n> 0) with upstream registers. A common on-chip address bus supplies each of these blocks A, B. The block addresses are transmitted over this bus in time division multiplex. The maximum degree of entanglement is limited by the ratio of the total cycle time to the duration of an address transfer. An increased number of blocks reduces the likelihood of a conflict. The individual blocks A, B are selected via the n least significant bits of the address codes. Logic, which causes addressing and data output to be time-linked, places the read data on the common, external data bus. If there is an address stream with non-sequential addresses, conflicts can arise when accessing blocks that are still occupied. Conflicts result in delayed access. An on-chip logic conflict detection detects these conflicts and communicates them to the "outside world" via signals (WAIT). The so-called RAS and CAS time control is also carried out by a suitable internal logic (control).

Fig. 2 zeigt die zeitliche Zuordnung der Vorgänge auf dem Adreßbus und dem Datenbus.Fig. 2 shows the temporal assignment of the processes on the address bus and the data bus.

Die erfindungsgemäße Schaltungsanordnung bewirkt eine Ver­kürzung der mittleren Zugriffszeit dynamischer RAM-Bausteine (DRAMs) bei schnell aufeinanderfolgenden Speicheranforderungen durch eine sog. Interleaving-Technik.The circuit arrangement according to the invention brings about a shortening of the average access time of dynamic RAM chips (DRAMs) in the case of rapidly successive memory requests by means of an interleaving technique.

Claims (1)

Schaltungsanordnung zum Durchführen eines On-Chip-Zeitver­schachtelns (Interleaving) des Zugriffs auf dynamische RAM-Bau­steine (DRAMs) einer Datenverarbeitungseinrichtung, dadurch gekennzeichnet, daß das Speicherfeld eines DRAM-Chips in 2n Blöcke (A,B) unterteilt ist, wobei n>0 ist und wobei jedem Block (A,B) ein Register vorge­schaltet ist, das eingangsseitig an einen Adreßbus geschaltet ist und ausgangsseitig mit dem ihm zugeordneten Block (A,B) ver­bunden ist, daß die Blöcke (A,B) ausgangsseitig mit individuellen Eingängen einer eine zeitliche Verschränkung von Adressierung und Datenausgabe bewirkenden Datenausgabe-Logik verbunden sind, deren Ausgang an einen Datenbus geführt ist, daß eine Konflikt­erkennungslogik mit dem Adreßbus verbunden ist, die im Falle eines Zugriffskonflikts auf dem Adreßbus ein Konfliktsignal (WAIT) an die Chip-Umgebung ausgibt, daß eine RAS/CAS-Steuer­logik vorgesehen ist, der ein Anforderungssignal (REQUEST) zuführbar ist und die RAS- und CAS-Zeitsteuersignale ausgibt, und daß die Gesamtanordnung auf einem gemeinsamen Chip ausge­bildet ist.Circuit arrangement for performing an on-chip interleaving of the access to dynamic RAM modules (DRAMs) of a data processing device, characterized in that the memory field of a DRAM chip is divided into 2 n blocks (A, B), where n> Is 0 and each block (A, B) is preceded by a register which is connected on the input side to an address bus and is connected on the output side to the block (A, B) assigned to it, that the blocks (A, B) have individual inputs on the output side a time interleaving of addressing and data output data output logic are connected, the output of which is led to a data bus, that a conflict detection logic is connected to the address bus, which in the event of an access conflict on the address bus, a conflict signal (WAIT) to the chip environment outputs that a RAS / CAS control logic is provided, to which a request signal (REQUEST) can be fed and the RAS and CAS time outputs control signals, and that the overall arrangement is formed on a common chip.
EP89116380A 1988-09-29 1989-09-05 Circuitry for the on-chip interleaved access to dynamic RAM modules Expired - Lifetime EP0361143B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3833095 1988-09-29
DE3833095 1988-09-29

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EP0361143A2 true EP0361143A2 (en) 1990-04-04
EP0361143A3 EP0361143A3 (en) 1990-11-28
EP0361143B1 EP0361143B1 (en) 1995-08-30

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AT (1) ATE127254T1 (en)
DE (1) DE58909408D1 (en)
HK (1) HK90897A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0513451A1 (en) * 1991-05-16 1992-11-19 International Business Machines Corporation Memory device
EP1293905A1 (en) * 2001-09-17 2003-03-19 STMicroelectronics S.r.l. A pointer circuit
US6810449B1 (en) 1995-10-19 2004-10-26 Rambus, Inc. Protocol for communication with dynamic memory
US6931467B2 (en) 1995-10-19 2005-08-16 Rambus Inc. Memory integrated circuit device which samples data upon detection of a strobe signal
CN100464317C (en) * 2007-06-27 2009-02-25 北京中星微电子有限公司 Bus access collision detection method and system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3727688A1 (en) * 1986-08-19 1988-02-25 Toshiba Kawasaki Kk SEMICONDUCTOR STORAGE SYSTEM

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3727688A1 (en) * 1986-08-19 1988-02-25 Toshiba Kawasaki Kk SEMICONDUCTOR STORAGE SYSTEM

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ELECTRONIC ENGINEERING, Band 58, Nr. 710, Februar 1986, Seiten 87-92, London, GB; P. BAGNALL et al.: "A hierarchical RAM with multi-level access path - part 2" *
IBM TECHNICAL DISCLOSURE BULLETIN, Band 25, Nr. 6, November 1982, Seiten 3042-3044, New York, US; J.C. LEININGER: "Microprocessor interleave instruction" *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0513451A1 (en) * 1991-05-16 1992-11-19 International Business Machines Corporation Memory device
US5450367A (en) * 1991-05-16 1995-09-12 International Business Machines Corporation Split SAM with independent SAM access
US6810449B1 (en) 1995-10-19 2004-10-26 Rambus, Inc. Protocol for communication with dynamic memory
US6931467B2 (en) 1995-10-19 2005-08-16 Rambus Inc. Memory integrated circuit device which samples data upon detection of a strobe signal
EP1293905A1 (en) * 2001-09-17 2003-03-19 STMicroelectronics S.r.l. A pointer circuit
US7181592B2 (en) 2001-09-17 2007-02-20 Stmicroelectronics S.R.L. Pointer circuit
CN100464317C (en) * 2007-06-27 2009-02-25 北京中星微电子有限公司 Bus access collision detection method and system

Also Published As

Publication number Publication date
EP0361143A3 (en) 1990-11-28
EP0361143B1 (en) 1995-08-30
DE58909408D1 (en) 1995-10-05
HK90897A (en) 1997-08-01
ATE127254T1 (en) 1995-09-15

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