DE69939895D1 - Herstellungsverfahren für ein halbleiterbauelement - Google Patents
Herstellungsverfahren für ein halbleiterbauelementInfo
- Publication number
- DE69939895D1 DE69939895D1 DE69939895T DE69939895T DE69939895D1 DE 69939895 D1 DE69939895 D1 DE 69939895D1 DE 69939895 T DE69939895 T DE 69939895T DE 69939895 T DE69939895 T DE 69939895T DE 69939895 D1 DE69939895 D1 DE 69939895D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing
- semiconductor component
- semiconductor
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/46—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with an inter-gate dielectric layer also being used as part of the peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98204342 | 1998-12-18 | ||
PCT/EP1999/009356 WO2000038237A1 (en) | 1998-12-18 | 1999-12-01 | A method of manufacturing a semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69939895D1 true DE69939895D1 (de) | 2008-12-24 |
Family
ID=8234496
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69939895T Expired - Lifetime DE69939895D1 (de) | 1998-12-18 | 1999-12-01 | Herstellungsverfahren für ein halbleiterbauelement |
Country Status (7)
Country | Link |
---|---|
US (1) | US6251729B1 (de) |
EP (1) | EP1057218B1 (de) |
JP (1) | JP2002533931A (de) |
KR (1) | KR100665416B1 (de) |
DE (1) | DE69939895D1 (de) |
TW (1) | TW449919B (de) |
WO (1) | WO2000038237A1 (de) |
Families Citing this family (63)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3257513B2 (ja) * | 1998-07-10 | 2002-02-18 | 日本電気株式会社 | 半導体装置及び半導体装置の製造方法 |
JP3264264B2 (ja) * | 1999-03-01 | 2002-03-11 | 日本電気株式会社 | 相補型集積回路とその製造方法 |
WO2000055896A1 (en) * | 1999-03-17 | 2000-09-21 | Koninklijke Philips Electronics N.V. | Method of manufacturing a floating gate field-effect transistor |
US6391724B1 (en) * | 1999-12-24 | 2002-05-21 | Hyundai Electronics Industries Co., Ltd. | Method for manufacturing a gate structure incorporating aluminum oxide as a gate dielectric |
KR100313547B1 (ko) * | 2000-02-29 | 2001-11-07 | 박종섭 | 반도체 소자의 제조방법 |
FR2810157B1 (fr) * | 2000-06-09 | 2002-08-16 | Commissariat Energie Atomique | Procede de realisation d'un composant electronique a source, drain et grille auto-allignes, en architecture damascene |
KR100372643B1 (ko) * | 2000-06-30 | 2003-02-17 | 주식회사 하이닉스반도체 | 다마신 공정을 이용한 반도체 소자의 제조방법 |
US6495419B1 (en) * | 2000-09-27 | 2002-12-17 | Lsi Logic Corporation | Nonvolatile memory in CMOS process flow |
JP4096507B2 (ja) * | 2000-09-29 | 2008-06-04 | 富士通株式会社 | 半導体装置の製造方法 |
US6338992B1 (en) * | 2000-11-29 | 2002-01-15 | Lsi Logic Corporation | Programmable read only memory in CMOS process flow |
US6406956B1 (en) * | 2001-04-30 | 2002-06-18 | Taiwan Semiconductor Manufacturing Company | Poly resistor structure for damascene metal gate |
JP4439142B2 (ja) | 2001-06-26 | 2010-03-24 | 株式会社東芝 | 不揮発性半導体メモリの製造方法 |
FR2826777B1 (fr) * | 2001-06-29 | 2003-12-12 | St Microelectronics Sa | Procede de fabrication d'un transistor mos a extension de drain et transistor correspondant |
US6583043B2 (en) | 2001-07-27 | 2003-06-24 | Motorola, Inc. | Dielectric between metal structures and method therefor |
US6566205B1 (en) | 2002-01-11 | 2003-05-20 | Taiwan Semiconductor Manufacturing Company | Method to neutralize fixed charges in high K dielectric |
EP1363324A1 (de) | 2002-05-16 | 2003-11-19 | STMicroelectronics S.r.l. | Herstellungsverfahren von Festwertspeicherbauelement |
US6475863B1 (en) * | 2002-05-17 | 2002-11-05 | Advanced Micro Devices, Inc. | Method for fabricating self-aligned gate of flash memory cell |
KR100467357B1 (ko) * | 2002-09-24 | 2005-01-24 | 삼성전자주식회사 | 모오스 트랜지스터 제조 방법 |
JP2006519491A (ja) | 2003-02-26 | 2006-08-24 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | ラテラルセレクトゲートを有する不揮発性メモリ・セルの製造方法 |
JP4282359B2 (ja) | 2003-04-11 | 2009-06-17 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
US6909151B2 (en) * | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
US7456476B2 (en) | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US20050189598A1 (en) * | 2004-02-27 | 2005-09-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Logic embedded-memory integrated circuits |
US7154118B2 (en) | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
US7279735B1 (en) | 2004-05-05 | 2007-10-09 | Spansion Llc | Flash memory device |
US7579280B2 (en) | 2004-06-01 | 2009-08-25 | Intel Corporation | Method of patterning a film |
US7042009B2 (en) | 2004-06-30 | 2006-05-09 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
US7348284B2 (en) | 2004-08-10 | 2008-03-25 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
US7422946B2 (en) | 2004-09-29 | 2008-09-09 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
US7332439B2 (en) * | 2004-09-29 | 2008-02-19 | Intel Corporation | Metal gate transistors with epitaxial source and drain regions |
US7361958B2 (en) * | 2004-09-30 | 2008-04-22 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
US20060086977A1 (en) | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
KR100620233B1 (ko) * | 2004-12-31 | 2006-09-08 | 동부일렉트로닉스 주식회사 | 플래시 메모리 소자의 제조 방법 |
US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US20060202266A1 (en) | 2005-03-14 | 2006-09-14 | Marko Radosavljevic | Field effect transistor with metal source/drain regions |
US7563701B2 (en) * | 2005-03-31 | 2009-07-21 | Intel Corporation | Self-aligned contacts for transistors |
US7858481B2 (en) | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
US7279375B2 (en) | 2005-06-30 | 2007-10-09 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
US7402875B2 (en) | 2005-08-17 | 2008-07-22 | Intel Corporation | Lateral undercut of metal gate in SOI device |
US20070090416A1 (en) | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
US7479421B2 (en) | 2005-09-28 | 2009-01-20 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
US7485503B2 (en) | 2005-11-30 | 2009-02-03 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
KR100661217B1 (ko) * | 2005-12-29 | 2006-12-22 | 동부일렉트로닉스 주식회사 | 반도체 소자의 제조 방법 |
US8143646B2 (en) | 2006-08-02 | 2012-03-27 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
US8043951B2 (en) | 2007-08-01 | 2011-10-25 | Freescale Semiconductor, Inc. | Method of manufacturing a semiconductor device and semiconductor device obtainable therewith |
DE102007041207B4 (de) * | 2007-08-31 | 2015-05-21 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | CMOS-Bauelement mit Gateisolationsschichten mit unterschiedlicher Art und Dicke und Verfahren zur Herstellung |
US20090087973A1 (en) * | 2007-10-02 | 2009-04-02 | Walker Andrew J | Retention improvement in dual-gate memory |
US7745295B2 (en) * | 2007-11-26 | 2010-06-29 | Micron Technology, Inc. | Methods of forming memory cells |
EP2070533B1 (de) * | 2007-12-11 | 2014-05-07 | Apoteknos Para La Piel, s.l. | Verwendung einer aus P-Hydroxyphenyl-Propionsäure entwickelten Verbindung zur Behandlung von Psoriasis |
JP2009170841A (ja) * | 2008-01-21 | 2009-07-30 | Toshiba Corp | 半導体装置の製造方法 |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
KR101448154B1 (ko) * | 2008-06-30 | 2014-10-08 | 삼성전자주식회사 | 반도체 소자의 게이트 전극의 형성 방법 |
US8294216B2 (en) * | 2008-08-14 | 2012-10-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrating the formation of I/O and core MOS devices with MOS capacitors and resistors |
US20100163952A1 (en) * | 2008-12-31 | 2010-07-01 | Chia-Hong Jan | Flash Cell with Integrated High-K Dielectric and Metal-Based Control Gate |
US8278203B2 (en) | 2010-07-28 | 2012-10-02 | Sandisk Technologies Inc. | Metal control gate formation in non-volatile storage |
US8772165B2 (en) * | 2011-07-14 | 2014-07-08 | Samsung Electronics Co., Ltd. | Methods of manufacturing gates for preventing shorts between the gates and self-aligned contacts and semiconductor devices having the same |
US8722493B2 (en) * | 2012-04-09 | 2014-05-13 | Freescale Semiconductor, Inc. | Logic transistor and non-volatile memory cell integration |
US9147738B2 (en) | 2012-11-30 | 2015-09-29 | Samsung Electronics Co., Ltd. | High electron mobility transistor including plurality of gate electrodes |
JP2014165457A (ja) * | 2013-02-27 | 2014-09-08 | Toshiba Corp | 不揮発性半導体記憶装置の製造方法 |
US9059208B2 (en) * | 2013-04-10 | 2015-06-16 | International Business Machines Corporation | Replacement gate integration scheme employing multiple types of disposable gate structures |
CN105244276B (zh) * | 2014-06-12 | 2018-08-21 | 中芯国际集成电路制造(上海)有限公司 | 一种FinFET及其制造方法、电子装置 |
US20170200729A1 (en) * | 2016-01-12 | 2017-07-13 | United Microelectronics Corp. | Integrated circuit and process thereof |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6362272A (ja) * | 1986-09-02 | 1988-03-18 | Seiko Instr & Electronics Ltd | 半導体装置の製造方法 |
JP2664685B2 (ja) * | 1987-07-31 | 1997-10-15 | 株式会社東芝 | 半導体装置の製造方法 |
US5512505A (en) * | 1990-12-18 | 1996-04-30 | Sandisk Corporation | Method of making dense vertical programmable read only memory cell structure |
US5340764A (en) | 1993-02-19 | 1994-08-23 | Atmel Corporation | Integration of high performance submicron CMOS and dual-poly non-volatile memory devices using a third polysilicon layer |
US5474947A (en) * | 1993-12-27 | 1995-12-12 | Motorola Inc. | Nonvolatile memory process |
KR0136995B1 (ko) * | 1994-09-08 | 1998-04-24 | 김주용 | 비휘발성메모리셀의제조방법 |
JPH09205154A (ja) * | 1996-01-25 | 1997-08-05 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
EP0811983A1 (de) * | 1996-06-06 | 1997-12-10 | STMicroelectronics S.r.l. | Flash-Speicherzelle, elektronische Vorrichtung mit einer solchen Zelle und Herstellungsverfahren |
US5756384A (en) * | 1997-05-20 | 1998-05-26 | Vanguard International Semiconductor Corporation | Method of fabricating an EPROM cell with a high coupling ratio |
US5972752A (en) * | 1997-12-29 | 1999-10-26 | United Semiconductor Corp. | Method of manufacturing a flash memory cell having a tunnel oxide with a long narrow top profile |
TW390028B (en) * | 1998-06-08 | 2000-05-11 | United Microelectronics Corp | A flash memory structure and its manufacturing |
US6093945A (en) * | 1998-07-09 | 2000-07-25 | Windbond Electronics Corp. | Split gate flash memory with minimum over-erase problem |
JP2000232173A (ja) * | 1998-12-09 | 2000-08-22 | Matsushita Electronics Industry Corp | 半導体記憶装置およびその製造方法 |
US6168995B1 (en) * | 1999-01-12 | 2001-01-02 | Lucent Technologies Inc. | Method of fabricating a split gate memory cell |
TW479364B (en) * | 1999-04-28 | 2002-03-11 | Koninkl Philips Electronics Nv | Method of manufacturing a semiconductor device comprising a field effect transistor |
-
1999
- 1999-06-21 TW TW088110316A patent/TW449919B/zh not_active IP Right Cessation
- 1999-12-01 EP EP99962194A patent/EP1057218B1/de not_active Expired - Lifetime
- 1999-12-01 DE DE69939895T patent/DE69939895D1/de not_active Expired - Lifetime
- 1999-12-01 JP JP2000590216A patent/JP2002533931A/ja not_active Withdrawn
- 1999-12-01 KR KR1020007009057A patent/KR100665416B1/ko not_active IP Right Cessation
- 1999-12-01 WO PCT/EP1999/009356 patent/WO2000038237A1/en active IP Right Grant
- 1999-12-15 US US09/464,004 patent/US6251729B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2002533931A (ja) | 2002-10-08 |
EP1057218A1 (de) | 2000-12-06 |
KR20010041025A (ko) | 2001-05-15 |
EP1057218B1 (de) | 2008-11-12 |
US6251729B1 (en) | 2001-06-26 |
WO2000038237A1 (en) | 2000-06-29 |
TW449919B (en) | 2001-08-11 |
KR100665416B1 (ko) | 2007-01-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |