DE69939895D1 - Herstellungsverfahren für ein halbleiterbauelement - Google Patents

Herstellungsverfahren für ein halbleiterbauelement

Info

Publication number
DE69939895D1
DE69939895D1 DE69939895T DE69939895T DE69939895D1 DE 69939895 D1 DE69939895 D1 DE 69939895D1 DE 69939895 T DE69939895 T DE 69939895T DE 69939895 T DE69939895 T DE 69939895T DE 69939895 D1 DE69939895 D1 DE 69939895D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor component
semiconductor
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69939895T
Other languages
English (en)
Inventor
Andreas H Montree
Jurriaan Schmitz
Pierre H Woerlee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Application granted granted Critical
Publication of DE69939895D1 publication Critical patent/DE69939895D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42Simultaneous manufacture of periphery and memory cells
    • H10B41/43Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/46Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with an inter-gate dielectric layer also being used as part of the peripheral transistor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
DE69939895T 1998-12-18 1999-12-01 Herstellungsverfahren für ein halbleiterbauelement Expired - Lifetime DE69939895D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP98204342 1998-12-18
PCT/EP1999/009356 WO2000038237A1 (en) 1998-12-18 1999-12-01 A method of manufacturing a semiconductor device

Publications (1)

Publication Number Publication Date
DE69939895D1 true DE69939895D1 (de) 2008-12-24

Family

ID=8234496

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69939895T Expired - Lifetime DE69939895D1 (de) 1998-12-18 1999-12-01 Herstellungsverfahren für ein halbleiterbauelement

Country Status (7)

Country Link
US (1) US6251729B1 (de)
EP (1) EP1057218B1 (de)
JP (1) JP2002533931A (de)
KR (1) KR100665416B1 (de)
DE (1) DE69939895D1 (de)
TW (1) TW449919B (de)
WO (1) WO2000038237A1 (de)

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US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
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US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7332439B2 (en) * 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7361958B2 (en) * 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
KR100620233B1 (ko) * 2004-12-31 2006-09-08 동부일렉트로닉스 주식회사 플래시 메모리 소자의 제조 방법
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20060202266A1 (en) 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
US7563701B2 (en) * 2005-03-31 2009-07-21 Intel Corporation Self-aligned contacts for transistors
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7402875B2 (en) 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
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US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
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DE102007041207B4 (de) * 2007-08-31 2015-05-21 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg CMOS-Bauelement mit Gateisolationsschichten mit unterschiedlicher Art und Dicke und Verfahren zur Herstellung
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KR101448154B1 (ko) * 2008-06-30 2014-10-08 삼성전자주식회사 반도체 소자의 게이트 전극의 형성 방법
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Also Published As

Publication number Publication date
JP2002533931A (ja) 2002-10-08
EP1057218A1 (de) 2000-12-06
KR20010041025A (ko) 2001-05-15
EP1057218B1 (de) 2008-11-12
US6251729B1 (en) 2001-06-26
WO2000038237A1 (en) 2000-06-29
TW449919B (en) 2001-08-11
KR100665416B1 (ko) 2007-01-04

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