DE602004015592D1 - Methode zur herstellung von finfets mit mehreren höhen - Google Patents
Methode zur herstellung von finfets mit mehreren höhenInfo
- Publication number
- DE602004015592D1 DE602004015592D1 DE602004015592T DE602004015592T DE602004015592D1 DE 602004015592 D1 DE602004015592 D1 DE 602004015592D1 DE 602004015592 T DE602004015592 T DE 602004015592T DE 602004015592 T DE602004015592 T DE 602004015592T DE 602004015592 D1 DE602004015592 D1 DE 602004015592D1
- Authority
- DE
- Germany
- Prior art keywords
- fin
- fins
- ratio
- channel region
- finfets
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004020 conductor Substances 0.000 abstract 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/249,738 US6909147B2 (en) | 2003-05-05 | 2003-05-05 | Multi-height FinFETS |
| PCT/US2004/002647 WO2004100290A2 (en) | 2003-05-05 | 2004-01-30 | Multi-height finfets |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE602004015592D1 true DE602004015592D1 (de) | 2008-09-18 |
Family
ID=33415537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE602004015592T Expired - Lifetime DE602004015592D1 (de) | 2003-05-05 | 2004-01-30 | Methode zur herstellung von finfets mit mehreren höhen |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US6909147B2 (de) |
| EP (1) | EP1620891B1 (de) |
| KR (1) | KR100690559B1 (de) |
| CN (1) | CN100466229C (de) |
| AT (1) | ATE403937T1 (de) |
| DE (1) | DE602004015592D1 (de) |
| TW (1) | TWI289354B (de) |
| WO (1) | WO2004100290A2 (de) |
Families Citing this family (106)
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| US6894326B2 (en) * | 2003-06-25 | 2005-05-17 | International Business Machines Corporation | High-density finFET integration scheme |
| US6909151B2 (en) | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
| US7456476B2 (en) | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
| US7095065B2 (en) * | 2003-08-05 | 2006-08-22 | Advanced Micro Devices, Inc. | Varying carrier mobility in semiconductor devices to achieve overall design goals |
| JP2005086024A (ja) * | 2003-09-09 | 2005-03-31 | Toshiba Corp | 半導体装置及びその製造方法 |
| US6970373B2 (en) * | 2003-10-02 | 2005-11-29 | Intel Corporation | Method and apparatus for improving stability of a 6T CMOS SRAM cell |
| JPWO2005091374A1 (ja) * | 2004-03-19 | 2008-02-07 | 日本電気株式会社 | 半導体装置及びその製造方法 |
| KR100576361B1 (ko) * | 2004-03-23 | 2006-05-03 | 삼성전자주식회사 | 3차원 시모스 전계효과 트랜지스터 및 그것을 제조하는 방법 |
| DE102004020593A1 (de) * | 2004-04-27 | 2005-11-24 | Infineon Technologies Ag | Fin-Feldeffekttransistor-Anordnung und Verfahren zum Herstellen einer Fin-Feldeffektransistor-Anordnung |
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| US20060086977A1 (en) | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
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| JP4044276B2 (ja) * | 2000-09-28 | 2008-02-06 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US6562665B1 (en) * | 2000-10-16 | 2003-05-13 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology |
| US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
| US6657259B2 (en) * | 2001-12-04 | 2003-12-02 | International Business Machines Corporation | Multiple-plane FinFET CMOS |
| US6706571B1 (en) * | 2002-10-22 | 2004-03-16 | Advanced Micro Devices, Inc. | Method for forming multiple structures in a semiconductor device |
| US6864519B2 (en) * | 2002-11-26 | 2005-03-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | CMOS SRAM cell configured using multiple-gate transistors |
| US6645797B1 (en) * | 2002-12-06 | 2003-11-11 | Advanced Micro Devices, Inc. | Method for forming fins in a FinFET device using sacrificial carbon layer |
| US7214991B2 (en) * | 2002-12-06 | 2007-05-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | CMOS inverters configured using multiple-gate transistors |
| US6762448B1 (en) * | 2003-04-03 | 2004-07-13 | Advanced Micro Devices, Inc. | FinFET device with multiple fin structures |
-
2003
- 2003-05-05 US US10/249,738 patent/US6909147B2/en not_active Expired - Lifetime
-
2004
- 2004-01-30 DE DE602004015592T patent/DE602004015592D1/de not_active Expired - Lifetime
- 2004-01-30 AT AT04707026T patent/ATE403937T1/de not_active IP Right Cessation
- 2004-01-30 EP EP04707026A patent/EP1620891B1/de not_active Expired - Lifetime
- 2004-01-30 WO PCT/US2004/002647 patent/WO2004100290A2/en active Search and Examination
- 2004-01-30 CN CNB2004800120281A patent/CN100466229C/zh not_active Expired - Fee Related
- 2004-01-30 KR KR1020057018446A patent/KR100690559B1/ko active IP Right Grant
- 2004-05-03 TW TW093112418A patent/TWI289354B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR100690559B1 (ko) | 2007-03-12 |
| US20040222477A1 (en) | 2004-11-11 |
| KR20060004659A (ko) | 2006-01-12 |
| WO2004100290A3 (en) | 2005-02-24 |
| TWI289354B (en) | 2007-11-01 |
| EP1620891A2 (de) | 2006-02-01 |
| CN1784782A (zh) | 2006-06-07 |
| ATE403937T1 (de) | 2008-08-15 |
| WO2004100290A2 (en) | 2004-11-18 |
| EP1620891A4 (de) | 2007-03-28 |
| US6909147B2 (en) | 2005-06-21 |
| TW200507265A (en) | 2005-02-16 |
| EP1620891B1 (de) | 2008-08-06 |
| CN100466229C (zh) | 2009-03-04 |
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