DE502006004698D1 - Verfahren zur Herstellung von sublithographischen Strukturen - Google Patents

Verfahren zur Herstellung von sublithographischen Strukturen

Info

Publication number
DE502006004698D1
DE502006004698D1 DE502006004698T DE502006004698T DE502006004698D1 DE 502006004698 D1 DE502006004698 D1 DE 502006004698D1 DE 502006004698 T DE502006004698 T DE 502006004698T DE 502006004698 T DE502006004698 T DE 502006004698T DE 502006004698 D1 DE502006004698 D1 DE 502006004698D1
Authority
DE
Germany
Prior art keywords
preparation
sublithographic structures
sublithographic
structures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE502006004698T
Other languages
English (en)
Inventor
Martin Gutsche
Harald Seidl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE502006004698D1 publication Critical patent/DE502006004698D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
DE502006004698T 2005-02-24 2006-02-03 Verfahren zur Herstellung von sublithographischen Strukturen Active DE502006004698D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102005008478A DE102005008478B3 (de) 2005-02-24 2005-02-24 Verfahren zur Herstellung von sublithographischen Strukturen

Publications (1)

Publication Number Publication Date
DE502006004698D1 true DE502006004698D1 (de) 2009-10-15

Family

ID=36579679

Family Applications (2)

Application Number Title Priority Date Filing Date
DE102005008478A Expired - Fee Related DE102005008478B3 (de) 2005-02-24 2005-02-24 Verfahren zur Herstellung von sublithographischen Strukturen
DE502006004698T Active DE502006004698D1 (de) 2005-02-24 2006-02-03 Verfahren zur Herstellung von sublithographischen Strukturen

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE102005008478A Expired - Fee Related DE102005008478B3 (de) 2005-02-24 2005-02-24 Verfahren zur Herstellung von sublithographischen Strukturen

Country Status (5)

Country Link
US (2) US7605090B2 (de)
EP (1) EP1696477B1 (de)
KR (1) KR100715051B1 (de)
DE (2) DE102005008478B3 (de)
TW (1) TWI304151B (de)

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US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7547945B2 (en) * 2004-09-01 2009-06-16 Micron Technology, Inc. Transistor devices, transistor structures and semiconductor constructions
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) * 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7282401B2 (en) 2005-07-08 2007-10-16 Micron Technology, Inc. Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
US7867851B2 (en) 2005-08-30 2011-01-11 Micron Technology, Inc. Methods of forming field effect transistors on substrates
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US7700441B2 (en) 2006-02-02 2010-04-20 Micron Technology, Inc. Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
US7602001B2 (en) 2006-07-17 2009-10-13 Micron Technology, Inc. Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US7772632B2 (en) 2006-08-21 2010-08-10 Micron Technology, Inc. Memory arrays and methods of fabricating memory arrays
US7589995B2 (en) 2006-09-07 2009-09-15 Micron Technology, Inc. One-transistor memory cell with bias gate
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US8119528B2 (en) * 2008-08-19 2012-02-21 International Business Machines Corporation Nanoscale electrodes for phase change memory devices
US9171929B2 (en) 2012-04-25 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Strained structure of semiconductor device and method of making the strained structure
US9293345B2 (en) 2013-08-16 2016-03-22 Globalfoundries Inc. Sidewall image transfer with a spin-on hardmask
US11129962B2 (en) 2013-11-26 2021-09-28 Biosense Webster (Israel) Ltd. Robotic assister for catheter insertion
WO2018109857A1 (ja) 2016-12-14 2018-06-21 三菱電機株式会社 光半導体装置の製造方法

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US4354896A (en) * 1980-08-05 1982-10-19 Texas Instruments Incorporated Formation of submicron substrate element
US4631113A (en) * 1985-12-23 1986-12-23 Signetics Corporation Method for manufacturing a narrow line of photosensitive material
US5328810A (en) * 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
JPH0450943A (ja) * 1990-06-15 1992-02-19 Mitsubishi Electric Corp マスクパターンとその製造方法
US5431770A (en) 1993-10-13 1995-07-11 At&T Corp. Transistor gate formation
KR0122315B1 (ko) * 1993-12-27 1997-11-26 김주용 고집적 반도체 소자의 미세패턴 형성방법
US5795830A (en) * 1995-06-06 1998-08-18 International Business Machines Corporation Reducing pitch with continuously adjustable line and space dimensions
DE19526011C1 (de) 1995-07-17 1996-11-28 Siemens Ag Verfahren zur Herstellung von sublithographischen Ätzmasken
US5714039A (en) * 1995-10-04 1998-02-03 International Business Machines Corporation Method for making sub-lithographic images by etching the intersection of two spacers
JP3080036B2 (ja) * 1997-06-20 2000-08-21 日本電気株式会社 マスク形成方法及び該方法により形成したマスク
US6296974B1 (en) * 1999-09-08 2001-10-02 Benjamin Szu-Min Lin Method of forming a multi-layer photo mask
US6926843B2 (en) * 2000-11-30 2005-08-09 International Business Machines Corporation Etching of hard masks
DE10217875B4 (de) * 2002-04-22 2004-04-29 Infineon Technologies Ag Verfahren zur Herstellung einer sublithographischen Maske
US6673714B2 (en) 2002-04-25 2004-01-06 Hewlett-Packard Development Company, L.P. Method of fabricating a sub-lithographic sized via
US6749997B2 (en) 2002-05-14 2004-06-15 Sandia National Laboratories Method for providing an arbitrary three-dimensional microstructure in silicon using an anisotropic deep etch
US6913871B2 (en) 2002-07-23 2005-07-05 Intel Corporation Fabricating sub-resolution structures in planar lightwave devices
US7186649B2 (en) * 2003-04-08 2007-03-06 Dongbu Electronics Co. Ltd. Submicron semiconductor device and a fabricating method thereof
US6858485B2 (en) * 2003-05-07 2005-02-22 International Business Machines Corporation Method for creation of a very narrow emitter feature
US7585614B2 (en) * 2004-09-20 2009-09-08 International Business Machines Corporation Sub-lithographic imaging techniques and processes
US7285499B1 (en) * 2005-05-12 2007-10-23 Advanced Micro Devices, Inc. Polymer spacers for creating sub-lithographic spaces
US6982221B1 (en) * 2005-06-10 2006-01-03 Sharp Laboratories Of America, Inc. Method of forming 2/3F pitch high density line array

Also Published As

Publication number Publication date
EP1696477B1 (de) 2009-09-02
TWI304151B (en) 2008-12-11
KR20060094481A (ko) 2006-08-29
US8084190B2 (en) 2011-12-27
US20100006983A1 (en) 2010-01-14
EP1696477A2 (de) 2006-08-30
EP1696477A3 (de) 2008-05-07
US20060204898A1 (en) 2006-09-14
DE102005008478B3 (de) 2006-10-26
KR100715051B1 (ko) 2007-05-04
TW200643607A (en) 2006-12-16
US7605090B2 (en) 2009-10-20

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